1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: class/cla084.finn 31 // 32 33 #include "nv_vgpu_types.h" 34 #include "cla084_notification.h" 35 36 #define NVA084_KERNEL_HOST_VGPU_DEVICE (0xa084U) /* finn: Evaluated from "NVA084_ALLOC_PARAMETERS_MESSAGE_ID" */ 37 38 #define NVA084_MAX_VMMU_SEGMENTS 384 39 40 /* 41 * NVA084_ALLOC_PARAMETERS 42 * 43 * This structure represents vGPU host device KERNEL object allocation parameters. 44 * dbdf -> domain (31:16), bus (15:8), device (7:3), function (2:0) 45 * gfid -> Used only when SRIOV is enabled otherwise set to 0. 46 * swizzId [IN] -> Used only when MIG mode is enabled otherwise set 47 * to NV2080_CTRL_GPU_PARTITION_ID_INVALID. 48 * numChannels -> Used only when SRIOV is enabled. Must be a power of 2. 49 * bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition 50 * save/restore will not be done in host-RM 51 * vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used 52 * for supporting multiple vGPUs per VM. 53 * hPluginClient -> handle to the plugin client 54 * numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient 55 * guestFbHandleList -> handle list to guest memory 56 * hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient 57 * hMigRmHeapMemory -> MIG-RM heap memory handle 58 * bDeviceProfilingEnabled -> If set to true, profiling is allowed 59 */ 60 #define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U) 61 62 typedef struct NVA084_ALLOC_PARAMETERS { 63 NvU32 dbdf; 64 NvU32 gfid; 65 NvU32 swizzId; 66 NvU32 vgpuType; 67 NvU32 vmPid; 68 NvU32 numChannels; 69 NvU32 numPluginChannels; 70 VM_ID_TYPE vmIdType; 71 NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); 72 NvBool bDisableDefaultSmcExecPartRestore; 73 NvU32 vgpuDeviceInstanceId; 74 NvHandle hPluginClient; 75 NvU32 numGuestFbHandles; 76 NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS]; 77 NvHandle hPluginHeapMemory; 78 NvHandle hMigRmHeapMemory; 79 NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); 80 NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8); 81 NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8); 82 NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8); 83 NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8); 84 NvBool bDeviceProfilingEnabled; 85 } NVA084_ALLOC_PARAMETERS; 86