1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #pragma once 24 25 #include <nvtypes.h> 26 27 // 28 // This file was generated with FINN, an NVIDIA coding tool. 29 // Source file: ctrl/ctrl0000/ctrl0000system.finn 30 // 31 32 #include "ctrl/ctrlxxxx.h" 33 #include "ctrl/ctrl0000/ctrl0000base.h" 34 35 /* NV01_ROOT (client) system control commands and parameters */ 36 37 /* 38 * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES 39 * 40 * This command returns a mask of supported features for the SYSTEM category 41 * of the 0000 class. 42 * 43 * Valid features include: 44 * 45 * NV0000_CTRL_GET_FEATURES_SLI 46 * When this bit is set, SLI is supported. 47 * NV0000_CTRL_GET_FEATURES_UEFI 48 * When this bit is set, it is a UEFI system. 49 * NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 50 * When this bit is set, EFI has initialized core channel 51 * 52 * Possible status values returned are: 53 * NV_OK 54 * NV_ERR_INVALID_STATE 55 */ 56 #define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ 57 58 #define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) 59 60 typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { 61 NvU32 featuresMask; 62 } NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS; 63 64 65 66 /* Valid feature values */ 67 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 68 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) 69 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) 70 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1 71 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U) 72 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U) 73 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 74 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) 75 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) 76 /* 77 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION 78 * 79 * This command returns the current driver information. 80 * The first time this is called the size of strings is 81 * set with the greater of NV_BUILD_BRANCH_VERSION and 82 * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory 83 * of size sizeOfStrings for pVersionBuffer and pTitleBuffer 84 * and calls the command again to receive driver info. 85 * 86 * sizeOfStrings 87 * This field returns the size in bytes of the pVersionBuffer and 88 * pTitleBuffer strings. 89 * pDriverVersionBuffer 90 * This field returns the version (NV_VERSION_STRING). 91 * pVersionBuffer 92 * This field returns the version (NV_BUILD_BRANCH_VERSION). 93 * pTitleBuffer 94 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 95 * changelistNumber 96 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 97 * officialChangelistNumber 98 * This field returns the last official changelist value 99 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 100 * 101 * Possible status values returned are: 102 * NV_OK 103 * NV_ERR_INVALID_PARAM_STRUCT 104 */ 105 106 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ 107 108 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) 109 110 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { 111 NvU32 sizeOfStrings; 112 NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8); 113 NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8); 114 NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8); 115 NvU32 changelistNumber; 116 NvU32 officialChangelistNumber; 117 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS; 118 119 /* 120 * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO 121 * 122 * This command returns system CPU information. 123 * 124 * type 125 * This field returns the processor type. 126 * Legal processor types include: 127 * Intel processors: 128 * P55 : P55C - MMX 129 * P6 : PPro 130 * P2 : PentiumII 131 * P2XC : Xeon & Celeron 132 * CELA : Celeron-A 133 * P3 : Pentium-III 134 * P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K) 135 * P4 : Pentium 4 136 * CORE2 : Core2 Duo Conroe 137 * AMD processors 138 * K62 : K6-2 w/ 3DNow 139 * IDT/Centaur processors 140 * C6 : WinChip C6 141 * C62 : WinChip 2 w/ 3DNow 142 * Cyrix processors 143 * GX : MediaGX 144 * M1 : 6x86 145 * M2 : M2 146 * MGX : MediaGX w/ MMX 147 * Transmeta processors 148 * TM_CRUSOE : Transmeta Crusoe(tm) 149 * PowerPC processors 150 * PPC603 : PowerPC 603 151 * PPC604 : PowerPC 604 152 * PPC750 : PowerPC 750 153 * 154 * capabilities 155 * This field returns the capabilities of the processor. 156 * Legal processor capabilities include: 157 * MMX : supports MMX 158 * SSE : supports SSE 159 * 3DNOW : supports 3DNow 160 * SSE2 : supports SSE2 161 * SFENCE : supports SFENCE 162 * WRITE_COMBINING : supports write-combining 163 * ALTIVEC : supports ALTIVEC 164 * PUT_NEEDS_IO : requires OUT inst w/PUT updates 165 * NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug 166 * 3DNOW_EXT : supports 3DNow Extensions 167 * MMX_EXT : supports MMX Extensions 168 * CMOV : supports CMOV 169 * CLFLUSH : supports CLFLUSH 170 * SSE3 : supports SSE3 171 * NEEDS_WAR_124888 : requires write to GPU while spinning on 172 * : GPU value 173 * HT : support hyper-threading 174 * clock 175 * This field returns the processor speed in MHz. 176 * L1DataCacheSize 177 * This field returns the level 1 data (or unified) cache size 178 * in kilobytes. 179 * L2DataCacheSize 180 * This field returns the level 2 data (or unified) cache size 181 * in kilobytes. 182 * dataCacheLineSize 183 * This field returns the bytes per line in the level 1 data cache. 184 * numLogicalCpus 185 * This field returns the number of logical processors. On Intel x86 186 * systems that support it, this value will incorporate the current state 187 * of HyperThreading. 188 * numPhysicalCpus 189 * This field returns the number of physical processors. 190 * name 191 * This field returns the CPU name in ASCII string format. 192 * family 193 * Vendor defined Family and Extended Family combined 194 * model 195 * Vendor defined Model and Extended Model combined 196 * stepping 197 * Silicon stepping 198 * bSEVEnabled 199 * Secure Encrypted Virtualization enabled/disabled state 200 * 201 * Possible status values returned are: 202 * NV_OK 203 * NV_ERR_INVALID_PARAM_STRUCT 204 */ 205 #define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ 206 207 #define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) 208 209 typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { 210 NvU32 type; /* processor type */ 211 NvU32 capabilities; /* processor caps */ 212 NvU32 clock; /* processor speed (MHz) */ 213 NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ 214 NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ 215 NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ 216 NvU32 numLogicalCpus; /* logial processor cnt */ 217 NvU32 numPhysicalCpus; /* physical processor cnt*/ 218 NvU8 name[52]; /* embedded cpu name */ 219 NvU32 family; /* Vendor defined Family and Extended Family combined */ 220 NvU32 model; /* Vendor defined Model and Extended Model combined */ 221 NvU8 stepping; /* Silicon stepping */ 222 NvU32 coresOnDie; /* cpu cores per die */ 223 NvBool bSEVEnabled; /* SEV enabled on cpu */ 224 } NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; 225 226 // Macros for CPU family information 227 #define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 228 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 229 230 // Macros for CPU model information 231 #define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 232 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 233 234 // Macros for AMD CPU information 235 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF 236 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA 237 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 238 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 239 240 // Macros for Intel CPU information 241 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 242 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 243 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 244 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA 245 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 246 247 /* processor type values */ 248 #define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) 249 /* Intel types */ 250 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) 251 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) 252 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) 253 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) 254 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) 255 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) 256 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) 257 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) 258 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) 259 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) 260 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) 261 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) 262 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) 263 /* AMD types */ 264 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) 265 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) 266 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) 267 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) 268 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) 269 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) 270 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) 271 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) 272 #define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) 273 /* IDT/Centaur types */ 274 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) 275 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) 276 /* Cyrix types */ 277 #define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) 278 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) 279 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) 280 #define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) 281 /* Transmeta types */ 282 #define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) 283 /* IBM types */ 284 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) 285 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) 286 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) 287 #define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) 288 /* Unknown ARM architecture CPU type */ 289 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) 290 /* ARM Ltd types */ 291 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) 292 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) 293 /* NVIDIA types */ 294 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) 295 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) 296 297 /* Generic types */ 298 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) 299 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) 300 301 /* processor capabilities */ 302 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) 303 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) 304 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) 305 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) 306 #define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) 307 #define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) 308 #define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) 309 #define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) 310 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) 311 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) 312 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) 313 #define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) 314 #define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) 315 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ 316 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) 317 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) 318 #define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) 319 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) 320 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) 321 #define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) 322 #define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) 323 324 /* feature mask (as opposed to bugs, requirements, etc.) */ 325 #define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */ 326 327 /* 328 * NV0000_CTRL_CMD_SYSTEM_GET_CAPS 329 * 330 * This command returns the set of system capabilities in the 331 * form of an array of unsigned bytes. System capabilities include 332 * supported features and required workarounds for the system, 333 * each represented by a byte offset into the table and a bit 334 * position within that byte. 335 * 336 * capsTblSize 337 * This parameter specifies the size in bytes of the caps table. 338 * This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE. 339 * capsTbl 340 * This parameter specifies a pointer to the client's caps table buffer 341 * into which the system caps bits will be transferred by the RM. 342 * The caps table is an array of unsigned bytes. 343 * 344 * Possible status values returned are: 345 * NV_OK 346 * NV_ERR_INVALID_PARAM_STRUCT 347 * NV_ERR_INVALID_ARGUMENT 348 */ 349 #define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */ 350 351 typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { 352 NvU32 capsTblSize; 353 NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); 354 } NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS; 355 356 /* extract cap bit setting from tbl */ 357 #define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) 358 359 /* caps format is byte_index:bit_mask */ 360 #define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01 361 362 /* size in bytes of system caps table */ 363 #define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U 364 365 /* 366 * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO 367 * 368 * This command returns system chipset information. 369 * 370 * vendorId 371 * This parameter returns the vendor identification for the chipset. 372 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 373 * cannot be identified. 374 * deviceId 375 * This parameter returns the device identification for the chipset. 376 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 377 * cannot be identified. 378 * subSysVendorId 379 * This parameter returns the subsystem vendor identification for the 380 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 381 * chipset cannot be identified. 382 * subSysDeviceId 383 * This parameter returns the subsystem device identification for the 384 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 385 * chipset cannot be identified. 386 * HBvendorId 387 * This parameter returns the vendor identification for the chipset's 388 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 389 * the chipset's host bridge cannot be identified. 390 * HBdeviceId 391 * This parameter returns the device identification for the chipset's 392 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 393 * the chipset's host bridge cannot be identified. 394 * HBsubSysVendorId 395 * This parameter returns the subsystem vendor identification for the 396 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 397 * indicates the chipset's host bridge cannot be identified. 398 * HBsubSysDeviceId 399 * This parameter returns the subsystem device identification for the 400 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 401 * indicates the chipset's host bridge cannot be identified. 402 * sliBondId 403 * This parameter returns the SLI bond identification for the chipset. 404 * vendorNameString 405 * This parameter returns the vendor name string. 406 * chipsetNameString 407 * This parameter returns the vendor name string. 408 * sliBondNameString 409 * This parameter returns the SLI bond name string. 410 * flag 411 * This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags: 412 * _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1 413 * should be disabled - bug 3440153 414 * 415 * Possible status values returned are: 416 * NV_OK 417 * NV_ERR_INVALID_PARAM_STRUCT 418 * NV_ERR_INVALID_ARGUMENT 419 * NV_ERR_OPERATING_SYSTEM 420 */ 421 #define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ 422 423 /* maximum name string length */ 424 #define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) 425 426 /* invalid id */ 427 #define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) 428 429 #define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) 430 431 typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { 432 NvU16 vendorId; 433 NvU16 deviceId; 434 NvU16 subSysVendorId; 435 NvU16 subSysDeviceId; 436 NvU16 HBvendorId; 437 NvU16 HBdeviceId; 438 NvU16 HBsubSysVendorId; 439 NvU16 HBsubSysDeviceId; 440 NvU32 sliBondId; 441 NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 442 NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 443 NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 444 NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 445 NvU32 flags; 446 } NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; 447 448 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 449 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) 450 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) 451 452 453 454 /* 455 * NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE 456 * 457 * This command is used to set the system memory size in pages. 458 * 459 * memorySize 460 * This parameter specifies the system memory size in pages. All values 461 * are considered legal. 462 * 463 * 464 * Possible status values returned are: 465 * NV_OK 466 * NV_ERR_INVALID_PARAM_STRUCT 467 */ 468 #define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */ 469 470 #define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U) 471 472 typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS { 473 NvU32 memorySize; 474 } NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS; 475 476 /* 477 * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST 478 * 479 * This command is used to retrieve the set of system-level classes 480 * supported by the platform. 481 * 482 * numClasses 483 * This parameter returns the number of valid entries in the returned 484 * classes[] list. This parameter will not exceed 485 * Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE. 486 * classes 487 * This parameter returns the list of supported classes 488 * 489 * Possible status values returned are: 490 * NV_OK 491 * NV_ERR_INVALID_PARAM_STRUCT 492 */ 493 494 #define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ 495 496 /* maximum number of classes returned in classes[] array */ 497 #define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) 498 499 #define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) 500 501 typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { 502 NvU32 numClasses; 503 NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE]; 504 } NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS; 505 506 /* 507 * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT 508 * 509 * This command is used to send triggered mobile related system events 510 * to the RM. 511 * 512 * eventType 513 * This parameter indicates the triggered event type. This parameter 514 * should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value. 515 * eventData 516 * This parameter specifies the type-dependent event data associated 517 * with EventType. This parameter should specify a valid 518 * NV0000_CTRL_SYSTEM_EVENT_DATA value. 519 * bEventDataForced 520 * This parameter specifies what we have to do, Whether trust current 521 * Lid/Dock state or not. This parameter should specify a valid 522 * NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value. 523 524 * Possible status values returned are: 525 * NV_OK 526 * NV_ERR_INVALID_PARAM_STRUCT 527 * NV_ERR_INVALID_ARGUMENT 528 * 529 * Sync this up (#defines) with one in nvapi.spec! 530 * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) 531 */ 532 #define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ 533 534 #define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) 535 536 typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { 537 NvU32 eventType; 538 NvU32 eventData; 539 NvBool bEventDataForced; 540 } NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; 541 542 /* valid eventType values */ 543 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) 544 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) 545 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) 546 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) 547 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) 548 549 /* valid eventData values */ 550 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) 551 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) 552 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) 553 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) 554 #define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) 555 #define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) 556 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) 557 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) 558 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) 559 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) 560 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) 561 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ 562 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) 563 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) 564 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) 565 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) 566 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) 567 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ 568 569 /* valid bEventDataForced values */ 570 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) 571 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) 572 573 /* 574 * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE 575 * 576 * This command is used to query the platform type. 577 * 578 * systemType 579 * This parameter returns the type of the system. 580 * Legal values for this parameter include: 581 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 582 * The system is a desktop platform. 583 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC 584 * The system is a mobile (non-Toshiba) platform. 585 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 586 * The system is a mobile Toshiba platform. 587 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC 588 * The system is a system-on-a-chip (SOC) platform. 589 * 590 591 * Possible status values returned are: 592 * NV_OK 593 * NV_ERR_INVALID_PARAM_STRUCT 594 * NV_ERR_INVALID_ARGUMENT 595 */ 596 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ 597 598 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) 599 600 typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { 601 NvU32 systemType; 602 } NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; 603 604 /* valid systemType values */ 605 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) 606 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) 607 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) 608 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) 609 610 611 612 613 /* 614 * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL 615 * 616 * This command controls the current RmMsg filters. 617 * 618 * It is only supported if RmMsg is enabled (e.g. debug builds). 619 * 620 * cmd 621 * GET - Gets the current RmMsg filter string. 622 * SET - Sets the current RmMsg filter string. 623 * 624 * count 625 * The length of the RmMsg filter string. 626 * 627 * data 628 * The RmMsg filter string. 629 * 630 * Possible status values returned are: 631 * NV_OK 632 * NV_ERR_INVALID_ARGUMENT 633 * NV_ERR_NOT_SUPPORTED 634 */ 635 #define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ 636 637 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U 638 639 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) 640 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) 641 642 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) 643 644 typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS { 645 NvU32 cmd; 646 NvU32 count; 647 NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE]; 648 } NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS; 649 650 /* 651 * NV0000_CTRL_SYSTEM_HWBC_INFO 652 * 653 * This structure contains information about the HWBC (BR04) specified by 654 * hwbcId. 655 * 656 * hwbcId 657 * This field specifies the HWBC ID. 658 * firmwareVersion 659 * This field returns the version of the firmware on the HWBC (BR04), if 660 * present. This is a packed binary number of the form 0x12345678, which 661 * corresponds to a firmware version of 12.34.56.78. 662 * subordinateBus 663 * This field returns the subordinate bus number of the HWBC (BR04). 664 * secondaryBus 665 * This field returns the secondary bus number of the HWBC (BR04). 666 * 667 * Possible status values returned are: 668 * NV_OK 669 * NV_ERR_INVALID_ARGUMENT 670 */ 671 672 typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { 673 NvU32 hwbcId; 674 NvU32 firmwareVersion; 675 NvU32 subordinateBus; 676 NvU32 secondaryBus; 677 } NV0000_CTRL_SYSTEM_HWBC_INFO; 678 679 #define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU) 680 681 /* 682 * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO 683 * 684 * This command returns information about all Hardware Broadcast (HWBC) 685 * devices present in the system that are BR04s. To get the complete 686 * list of HWBCs in the system, all GPUs present in the system must be 687 * initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to 688 * accomplish this. 689 * 690 * hwbcInfo 691 * This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into 692 * which HWBC information is placed. There is one entry for each HWBC 693 * present in the system. Valid entries are contiguous, invalid entries 694 * have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC 695 * is present in the system, all the entries would be marked invalid, but 696 * the return value would still be SUCCESS. 697 * 698 * Possible status values returned are: 699 * NV_OK 700 * NV_ERR_INVALID_ARGUMENT 701 */ 702 #define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ 703 704 #define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U) 705 706 #define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U) 707 708 typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { 709 NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS]; 710 } NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS; 711 712 /* 713 * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL 714 * 715 * This command is used to control GPS functionality. It allows control of 716 * GPU Performance Scaling (GPS), changing its operational parameters and read 717 * most GPS dynamic parameters. 718 * 719 * command 720 * This parameter specifies the command to execute. Invalid commands 721 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 722 * locale 723 * This parameter indicates the specific locale to which the command 724 * 'command' is to be applied. 725 * Supported range of CPU/GPU {i = 0, ..., 255} 726 * data 727 * This parameter contains a command-specific data payload. It can 728 * be used to input data as well as output data. 729 * 730 * Possible status values returned are: 731 * NV_OK 732 * NV_ERR_INVALID_COMMAND 733 * NV_ERR_INVALID_STATE 734 * NV_ERR_INVALID_DATA 735 * NV_ERR_INVALID_REQUEST 736 * NV_ERR_NOT_SUPPORTED 737 */ 738 #define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ 739 740 #define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) 741 742 typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { 743 NvU16 command; 744 NvU16 locale; 745 NvU32 data; 746 } NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; 747 748 /* 749 * Valid command values : 750 * 751 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT 752 * Is used to check if GPS was correctly initialized. 753 * Possible return (OUT) values are: 754 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO 755 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES 756 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC 757 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC 758 * Are used to stop/start GPS functionality and to get current status. 759 * Possible IN/OUT values are: 760 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP 761 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START 762 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS 763 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS 764 * Are used to control execution of GPS actions and to get current status. 765 * Possible IN/OUT values are: 766 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF 767 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON 768 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC 769 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC 770 * Are used to switch current GPS logic and to retrieve current logic. 771 * Possible IN/OUT values are: 772 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF 773 * Will cause that all GPS actions will be NULL. 774 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY 775 * Fuzzy logic will determine GPS actions based on current ruleset. 776 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC 777 * Deterministic logic will define GPS actions based on current ruleset. 778 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE 779 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE 780 * Are used to set/retrieve system control preference. 781 * Possible IN/OUT values are: 782 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU 783 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU 784 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH 785 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT 786 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT 787 * Are used to set/retrieve GPU2CPU pstate limits. 788 * IN/OUT values are four bytes packed into a 32-bit data field. 789 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 790 * index for the GPU pstate 3 is in the highest byte, etc. One 791 * special value is to disable the override to the GPU2CPU map: 792 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE 793 * Is used to stop/start GPS PMU functionality. 794 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE 795 * Is used to get the current status of PMU GPS. 796 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE 797 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER 798 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER 799 * Are used to set/retrieve max power [mW] that system can provide. 800 * This is hardcoded GPS safety feature and logic/rules does not apply 801 * to this threshold. 802 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET 803 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET 804 * Are used to set/retrieve current system cooling budget [mW]. 805 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD 806 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD 807 * Are used to set/retrieve integration interval [sec]. 808 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET 809 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET 810 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT 811 * Are used to set/retrieve used ruleset [#]. Value is checked 812 * against MAX number of rules for currently used GPS logic. Also COUNT 813 * provides a way to find out how many rules exist for the current control 814 * system. 815 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST 816 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST 817 * Is used to set/get a delay relative to now during which to allow unbound 818 * CPU performance. Units are seconds. 819 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE 820 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE 821 * Is used to override/get the actual power supply mode (AC/Battery). 822 * Possible IN/OUT values are: 823 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL 824 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC 825 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT 826 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO 827 * Is used to get the Ventura system information for VCT tool 828 * Returned 32bit value should be treated as bitmask and decoded in 829 * following way: 830 * Encoding details are defined in objgps.h refer to 831 * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. 832 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION 833 * Is used to get the supported sub-functions defined in SBIOS. Returned 834 * value is a bitmask where each bit corresponds to different function: 835 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT 836 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS 837 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS 838 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC 839 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC 840 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB 841 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS 842 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER 843 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA 844 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE 845 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG 846 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL 847 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN 848 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE 849 * Are used to retrieve appropriate power measurements and their derivatives 850 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 851 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 852 * index. 853 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS 854 * Is used to retrieve parameters when adjusting raw sensor power reading. 855 * The values may come from SBIOS, VBIOS, registry or driver default. 856 * Possible IN value is the index of interested parameter. 857 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP 858 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA 859 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE 860 * Are used to retrieve appropriate temperature measurements and their 861 * derivatives in [1/1000 Celsius]. 862 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE 863 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP 864 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN 865 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX 866 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 867 * Not applicable to _LOCALE_SYSTEM. 868 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION 869 * Is used to retrieve last GPS action for given domain. 870 * Not applicable to _LOCALE_SYSTEM. 871 * Possible return (OUT) values are: 872 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 873 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 874 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING 875 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT 876 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 877 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 878 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM 879 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM 880 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE 881 * Is used to set the power sensor simulator state. 882 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE 883 * Is used to get the power simulator sensor simulator state. 884 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA 885 * Is used to set power sensor simulator data 886 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA 887 * Is used to get power sensor simulator data 888 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK 889 * Is used to respond to the ACPI event triggered by SBIOS. RM will 890 * request value for budget and status, validate them, apply them 891 * and send ACK back to SBIOS. 892 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT 893 * Is a test cmd that should notify SBIOS to send ACPI event requesting 894 * budget and status change. 895 */ 896 #define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) 897 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) 898 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) 899 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) 900 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) 901 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) 902 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) 903 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) 904 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) 905 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) 906 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) 907 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) 908 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) 909 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) 910 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) 911 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) 912 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) 913 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) 914 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) 915 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) 916 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) 917 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) 918 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) 919 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) 920 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) 921 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 922 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 923 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 924 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 925 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) 926 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) 927 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) 928 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) 929 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) 930 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) 931 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) 932 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) 933 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) 934 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) 935 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) 936 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) 937 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) 938 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) 939 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) 940 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) 941 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 942 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) 943 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) 944 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) 945 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) 946 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 947 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 948 949 /* valid LOCALE values */ 950 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) 951 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) 952 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) 953 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) 954 955 /* valid data values for enums */ 956 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) 957 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) 958 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) 959 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) 960 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) 961 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) 962 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) 963 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) 964 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) 965 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 966 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) 967 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) 968 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 969 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 970 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) 971 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) 972 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 973 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 974 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 975 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) 976 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 977 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) 978 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) 979 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) 980 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) 981 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 982 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 983 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 984 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 985 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 986 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 987 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 988 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 989 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 990 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 991 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 992 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 993 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 994 995 /* 996 * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL 997 * 998 * This command allows execution of multiple GpsControl commands within one 999 * RmControl call. For practical reasons # of commands is limited to 16. 1000 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. 1001 * 1002 * cmdCount 1003 * Number of commands that should be executed. 1004 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 1005 * 1006 * succeeded 1007 * Number of commands that were succesully executed. 1008 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 1009 * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID 1010 * in their data field. 1011 * 1012 * cmdData 1013 * Array of commands with following structure: 1014 * command 1015 * This parameter specifies the command to execute. 1016 * Invalid commands result in the return of an 1017 * NV_ERR_INVALID_ARGUMENT status. 1018 * locale 1019 * This parameter indicates the specific locale to which 1020 * the command 'command' is to be applied. 1021 * Supported range of CPU/GPU {i = 0, ..., 255} 1022 * data 1023 * This parameter contains a command-specific data payload. 1024 * It is used both to input data as well as to output data. 1025 * 1026 * Possible status values returned are: 1027 * NV_OK 1028 * NV_ERR_INVALID_REQUEST 1029 * NV_ERR_NOT_SUPPORTED 1030 */ 1031 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 1032 1033 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) 1034 #define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) 1035 1036 typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { 1037 NvU32 cmdCount; 1038 NvU32 succeeded; 1039 1040 struct { 1041 NvU16 command; 1042 NvU16 locale; 1043 NvU32 data; 1044 } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; 1045 } NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; 1046 1047 1048 /* 1049 * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. 1050 */ 1051 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 1052 1053 /* 1054 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of 1055 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues. 1056 * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups 1057 * allowed for batched P2P caps queries provided by the RM control 1058 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. 1059 */ 1060 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U 1061 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U 1062 #define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U 1063 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU 1064 1065 /* P2P capabilities status index values */ 1066 #define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U 1067 #define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U 1068 #define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U 1069 #define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U 1070 #define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U 1071 #define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U 1072 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U 1073 #define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U 1074 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U 1075 1076 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U 1077 1078 1079 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) 1080 1081 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { 1082 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1083 NvU32 gpuCount; 1084 NvU32 p2pCaps; 1085 NvU32 p2pOptimalReadCEs; 1086 NvU32 p2pOptimalWriteCEs; 1087 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1088 NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); 1089 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; 1090 1091 /* valid p2pCaps values */ 1092 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 1093 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) 1094 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) 1095 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 1096 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) 1097 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) 1098 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 1099 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) 1100 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) 1101 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 1102 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) 1103 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) 1104 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 1105 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1106 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1107 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 1108 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) 1109 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) 1110 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 1111 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) 1112 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) 1113 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 1114 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) 1115 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) 1116 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 1117 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) 1118 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) 1119 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 1120 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1121 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1122 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 1123 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) 1124 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) 1125 1126 1127 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 1128 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) 1129 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) 1130 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 1131 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) 1132 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) 1133 1134 /* P2P status codes */ 1135 #define NV0000_P2P_CAPS_STATUS_OK (0x00U) 1136 #define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) 1137 #define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) 1138 #define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) 1139 #define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) 1140 #define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) 1141 1142 /* 1143 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 1144 * 1145 * This command returns peer to peer capabilities present between GPUs. 1146 * Valid requests must present a list of GPU Ids. 1147 * 1148 * [in] gpuIds 1149 * This member contains the array of GPU IDs for which we query the P2P 1150 * capabilities. Valid entries are contiguous, beginning with the first 1151 * entry in the list. 1152 * [in] gpuCount 1153 * This member contains the number of GPU IDs stored in the gpuIds[] array. 1154 * [out] p2pCaps 1155 * This member returns the peer to peer capabilities discovered between the 1156 * GPUs. Valid p2pCaps values include: 1157 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1158 * When this bit is set, peer to peer writes between subdevices owned 1159 * by this device are supported. 1160 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1161 * When this bit is set, peer to peer reads between subdevices owned 1162 * by this device are supported. 1163 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1164 * When this bit is set, peer to peer PROP between subdevices owned 1165 * by this device are supported. This is enabled by default 1166 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1167 * When this bit is set, PCI is supported for all P2P between subdevices 1168 * owned by this device. 1169 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1170 * When this bit is set, NVLINK is supported for all P2P between subdevices 1171 * owned by this device. 1172 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1173 * When this bit is set, peer to peer atomics between subdevices owned 1174 * by this device are supported. 1175 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1176 * When this bit is set, peer to peer loopback is supported for subdevices 1177 * owned by this device. 1178 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1179 * When this bit is set, indirect peer to peer writes between subdevices 1180 * owned by this device are supported. 1181 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1182 * When this bit is set, indirect peer to peer reads between subdevices 1183 * owned by this device are supported. 1184 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1185 * When this bit is set, indirect peer to peer atomics between 1186 * subdevices owned by this device are supported. 1187 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1188 * When this bit is set, indirect NVLINK is supported for subdevices 1189 * owned by this device. 1190 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 1191 * When this bit is set, C2C P2P is supported between the GPUs 1192 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED 1193 * When this bit is set, BAR1 P2P is supported between the GPUs 1194 * mentioned in @ref gpuIds 1195 * [out] p2pOptimalReadCEs 1196 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1197 * [out] p2pOptimalWriteCEs 1198 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1199 * [out] p2pCapsStatus 1200 * This member returns status of all supported p2p capabilities. Valid 1201 * status values include: 1202 * NV0000_P2P_CAPS_STATUS_OK 1203 * P2P capability is supported. 1204 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 1205 * Chipset doesn't support p2p capability. 1206 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 1207 * GPU doesn't support p2p capability. 1208 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 1209 * IOH topology isn't supported. For e.g. root ports are on different 1210 * IOH. 1211 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 1212 * P2P Capability is disabled by a regkey. 1213 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 1214 * P2P Capability is not supported. 1215 * NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED 1216 * Indicates that NvLink P2P link setup failed. 1217 * [out] busPeerIds 1218 * Peer ID matrix. It is a one-dimentional array. 1219 * busPeerIds[X * gpuCount + Y] maps from index X to index Y in 1220 * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] 1221 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 1222 * 1223 * Possible status values returned are: 1224 * NV_OK 1225 * NV_ERR_INVALID_ARGUMENT 1226 * NV_ERR_INVALID_PARAM_STRUCT 1227 */ 1228 1229 1230 1231 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ 1232 1233 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) 1234 1235 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { 1236 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1237 NvU32 gpuCount; 1238 NvU32 p2pCaps; 1239 NvU32 p2pOptimalReadCEs; 1240 NvU32 p2pOptimalWriteCEs; 1241 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1242 NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; 1243 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; 1244 1245 /* 1246 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX 1247 * 1248 * This command returns peer to peer capabilities present between all pairs of 1249 * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to 1250 * collect all P2P capabilities in the system - see the SRT: 1251 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST 1252 * for a demonstration. 1253 * 1254 * The call will query for all pairs between set A and set B, and returns 1255 * results in both link directions. The results are two-dimensional arrays where 1256 * the first dimension is the index within the set-A array of one GPU ID under 1257 * consideration, and the second dimension is the index within the set-B array 1258 * of the other GPU ID under consideration. 1259 * 1260 * That is, the result arrays are *ALWAYS* to be indexed first with the set-A 1261 * index, then with the set-B index. The B-to-A direction of results are put in 1262 * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query 1263 * twice, since the usual use case requires both directions. 1264 * 1265 * If a set is being compared against itself (by setting grpBCount to 0), then 1266 * the result matrices are symmetric - it doesn't matter which index is first. 1267 * However, the choice of indices is effectively a choice of which ID is "B" and 1268 * which is "A" for the "a2b" and "b2a" directional results. 1269 * 1270 * [in] grpACount 1271 * This member contains the number of GPU IDs stored in the gpuIdGrpA[] 1272 * array. Must be >= 0. 1273 * [in] grpBCount 1274 * This member contains the number of GPU IDs stored in the gpuIdGrpB[] 1275 * array. Can be == 0 to specify a check of group A against itself. 1276 * [in] gpuIdGrpA 1277 * This member contains the array of GPU IDs in "group A", each of which 1278 * will have its P2P capabilities returned with respect to each GPU ID in 1279 * "group B". Valid entries are contiguous, beginning with the first entry 1280 * in the list. 1281 * [in] gpuIdGrpB 1282 * This member contains the array of GPU IDs in "group B", each of which 1283 * will have its P2P capabilities returned with respect to each GPU ID in 1284 * "group A". Valid entries are contiguous, beginning with the first entry 1285 * in the list. May be equal to gpuIdGrpA, but best performance requires 1286 * that the caller specifies grpBCount = 0 in this case, and ignores this. 1287 * [out] p2pCaps 1288 * This member returns the peer to peer capabilities discovered between the 1289 * pairs of input GPUs between the groups, indexed by [A_index][B_index]. 1290 * Valid p2pCaps values include: 1291 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1292 * When this bit is set, peer to peer writes between subdevices owned 1293 * by this device are supported. 1294 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1295 * When this bit is set, peer to peer reads between subdevices owned 1296 * by this device are supported. 1297 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1298 * When this bit is set, peer to peer PROP between subdevices owned 1299 * by this device are supported. This is enabled by default 1300 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1301 * When this bit is set, PCI is supported for all P2P between subdevices 1302 * owned by this device. 1303 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1304 * When this bit is set, NVLINK is supported for all P2P between subdevices 1305 * owned by this device. 1306 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1307 * When this bit is set, peer to peer atomics between subdevices owned 1308 * by this device are supported. 1309 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1310 * When this bit is set, peer to peer loopback is supported for subdevices 1311 * owned by this device. 1312 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1313 * When this bit is set, indirect peer to peer writes between subdevices 1314 * owned by this device are supported. 1315 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1316 * When this bit is set, indirect peer to peer reads between subdevices 1317 * owned by this device are supported. 1318 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1319 * When this bit is set, indirect peer to peer atomics between 1320 * subdevices owned by this device are supported. 1321 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1322 * When this bit is set, indirect NVLINK is supported for subdevices 1323 * owned by this device. 1324 * [out] a2bOptimalReadCes 1325 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1326 * in the A-to-B direction. 1327 * [out] a2bOptimalWriteCes 1328 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1329 * in the A-to-B direction. 1330 * [out] b2aOptimalReadCes 1331 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1332 * in the B-to-A direction. 1333 * [out] b2aOptimalWriteCes 1334 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1335 * in the B-to-A direction. 1336 * 1337 * Possible status values returned are: 1338 * NV_OK 1339 * NV_ERR_INVALID_ARGUMENT 1340 * NV_ERR_INVALID_PARAM_STRUCT 1341 */ 1342 1343 1344 1345 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ 1346 1347 typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1348 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) 1349 1350 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { 1351 NvU32 grpACount; 1352 NvU32 grpBCount; 1353 NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1354 NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1355 NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1356 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1357 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1358 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1359 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1360 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; 1361 1362 /* 1363 * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL 1364 * 1365 * This command is used to execute general GPS Functions, most dealing with 1366 * calling SBIOS, or retrieving cached sensor and GPS state data. 1367 * 1368 * version 1369 * This parameter specifies the version of the interface. Legal values 1370 * for this parameter are 1. 1371 * cmd 1372 * This parameter specifies the GPS API to be invoked. 1373 * Valid values for this parameter are: 1374 * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT 1375 * This command gets the temperature limit for thermal controller. When 1376 * this command is specified the input parameter contains ???. 1377 * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT 1378 * This command set the temperature limit for thermal controller. When 1379 * this command is specified the input parameter contains ???. 1380 * input 1381 * This parameter specifies the cmd-specific input value. 1382 * result 1383 * This parameter returns the cmd-specific output value. 1384 * 1385 * Possible status values returned are: 1386 * NV_OK 1387 * NV_ERR_INVALID_PARAM_STRUCT 1388 * NV_ERR_INVALID_ARGUMENT 1389 */ 1390 1391 #define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ 1392 1393 #define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) 1394 1395 typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { 1396 NvU32 cmd; 1397 NvS32 input[2]; 1398 NvS32 result[4]; 1399 } NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; 1400 1401 /* valid version values */ 1402 #define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 1403 1404 /* valid cmd values */ 1405 #define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 1406 #define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) 1407 #define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) 1408 #define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) 1409 #define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) 1410 #define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) 1411 1412 #define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 1413 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1414 #define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) 1415 1416 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 1417 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1418 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 1419 1420 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 1421 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1422 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 1423 1424 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 1425 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1426 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 1427 1428 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 1429 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1430 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 1431 1432 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 1433 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1434 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 1435 1436 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 1437 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1438 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 1439 1440 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 1441 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1442 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 1443 1444 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 1445 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1446 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 1447 1448 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 1449 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1450 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1451 1452 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 1453 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1454 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1455 1456 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 1457 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) 1458 1459 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 1460 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) 1461 1462 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 1463 #define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 1464 1465 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 1466 #define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 1467 1468 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 1469 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1470 #define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 1471 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) 1472 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 1473 1474 #define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) 1475 #define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) 1476 #define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) 1477 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) 1478 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) 1479 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 1480 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 1481 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 1482 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) 1483 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 1484 1485 #define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 1486 #define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) 1487 1488 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 1489 #define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) 1490 1491 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 1492 #define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) 1493 1494 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 1495 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) 1496 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 1497 1498 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 1499 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) 1500 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 1501 1502 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 1503 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1504 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1505 1506 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 1507 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1508 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1509 1510 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 1511 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1512 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1513 1514 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 1515 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1516 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1517 1518 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 1519 #define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) 1520 1521 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 1522 #define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) 1523 1524 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 1525 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1526 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 1527 1528 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 1529 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1530 1531 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 1532 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1533 1534 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 1535 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1536 1537 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) 1538 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) 1539 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 1540 1541 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) 1542 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) 1543 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 1544 1545 #define NV0000_CTRL_GPS_PPM_INDEX 7:0 1546 #define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) 1547 #define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) 1548 #define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) 1549 #define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) 1550 #define NV0000_CTRL_GPS_PPM_MASK 15:8 1551 #define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) 1552 1553 /* valid PS_STATUS result values */ 1554 #define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) 1555 #define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) 1556 1557 1558 /* 1559 * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS 1560 * 1561 * This command allows privileged users to update the values of 1562 * security settings governing RM behavior. 1563 * 1564 * Possible status values returned are: 1565 * NV_OK 1566 * NV_ERR_INVALID_ARGUMENT, 1567 * NV_ERR_INVALID_OBJECT_HANDLE 1568 * NV_ERR_NOT_SUPPORTED 1569 * NV_ERR_INSUFFICIENT_PERMISSIONS 1570 * 1571 * Please note: as implied above, administrator privileges are 1572 * required to modify security settings. 1573 */ 1574 #define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */ 1575 1576 #define GPS_MAX_COUNTERS_PER_BLOCK 32U 1577 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { 1578 NvU32 objHndl; 1579 NvU32 blockId; 1580 NvU32 nextExpectedSampleTimems; 1581 NvU32 countersReq; 1582 NvU32 countersReturned; 1583 NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; 1584 } NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; 1585 1586 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */ 1587 1588 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */ 1589 1590 /* 1591 * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI 1592 * 1593 * This command allows users to call GPS ACPI commands for testing purposes. 1594 * 1595 * cmd 1596 * This parameter specifies the GPS ACPI command to execute. 1597 * 1598 * input 1599 * This parameter specified the cmd-dependent input value. 1600 * 1601 * resultSz 1602 * This parameter returns the size (in bytes) of the valid data 1603 * returned in the result parameter. 1604 * 1605 * result 1606 * This parameter returns the results of the specified cmd. 1607 * The maximum size (in bytes) of this returned data will 1608 * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1609 * 1610 * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1611 * The size of buffer (result) in unit of NvU32. 1612 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 1613 * Since the prior one is 24 bytes, and the later one is 48, 1614 * this value cannot be smaller than 288. 1615 * 1616 * Possible status values returned are: 1617 * NV_OK 1618 * NV_ERR_INVALID_ARGUMENT, 1619 * NV_ERR_INVALID_OBJECT_HANDLE 1620 * NV_ERR_NOT_SUPPORTED 1621 * NV_ERR_INSUFFICIENT_PERMISSIONS 1622 * 1623 */ 1624 #define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 1625 #define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) 1626 1627 typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { 1628 NvU32 cmd; 1629 NvU32 input; 1630 NvU32 resultSz; 1631 NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 1632 } NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; 1633 1634 #define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ 1635 1636 /* 1637 * NV0000_CTRL_SYSTEM_PARAM_* 1638 * 1639 * The following is a list of system-level parameters (often sensors) that the 1640 * driver can be made aware of. They are primarily intended to be used by system 1641 * power-balancing algorithms that require system-wide visibility in order to 1642 * function. The names and values used here are established and specified in 1643 * several different NVIDIA documents that are made externally available. Thus, 1644 * updates to this list must be made with great caution. The only permissible 1645 * change is to append new parameters. Reordering is strictly prohibited. 1646 * 1647 * Brief Parameter Summary: 1648 * TGPU - GPU temperature (NvTemp) 1649 * PDTS - CPU package temperature (NvTemp) 1650 * SFAN - System fan speed (% of maximum fan speed) 1651 * SKNT - Skin temperature (NvTemp) 1652 * CPUE - CPU energy counter (NvU32) 1653 * TMP1 - Additional temperature sensor 1 (NvTemp) 1654 * TMP2 - Additional temperature sensor 2 (NvTemp) 1655 * CTGP - Mode 2 power limit offset (NvU32) 1656 * PPMD - Power mode data (NvU32) 1657 */ 1658 #define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) 1659 #define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) 1660 #define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) 1661 #define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) 1662 #define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) 1663 #define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) 1664 #define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) 1665 #define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) 1666 #define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) 1667 #define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) 1668 1669 /* 1670 * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD 1671 * 1672 * This command is used to execute general ACPI methods. 1673 * 1674 * method 1675 * This parameter identifies the MXM ACPI API to be invoked. 1676 * Valid values for this parameter are: 1677 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS 1678 * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS 1679 * API is to be invoked. 1680 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG 1681 * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG 1682 * API is to be invoked. This API will set a Flag in sbios to Indicate 1683 * that HD Audio Controller is disable/Enabled from GPU Config space. 1684 * This flag will be used by sbios to restore Audio state after resuming 1685 * from s3/s4. 1686 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS 1687 * This value specifies that the DSM JT subfunction FUNC_CAPS is to 1688 * to be invoked to get the SBIOS capabilities 1689 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY 1690 * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is 1691 * to be invoked to set and get the various platform policies for JT. 1692 * Refer to the JT spec in more detail on various policies. 1693 * inData 1694 * This parameter specifies the method-specific input buffer. Data is 1695 * passed to the specified API using this buffer. 1696 * inDataSize 1697 * This parameter specifies the size of the inData buffer in bytes. 1698 * outStatus 1699 * This parameter returns the status code from the associated ACPI call. 1700 * outData 1701 * This parameter specifies the method-specific output buffer. Data 1702 * is returned by the specified API using this buffer. 1703 * outDataSize 1704 * This parameter specifies the size of the outData buffer in bytes. 1705 * 1706 * Possible status values returned are: 1707 * NV_OK 1708 * NV_ERR_INVALID_PARAM_STRUCT 1709 * NV_ERR_INVALID_ARGUMENT 1710 */ 1711 1712 #define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ 1713 1714 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) 1715 1716 typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { 1717 NvU32 method; 1718 NV_DECLARE_ALIGNED(NvP64 inData, 8); 1719 NvU16 inDataSize; 1720 NvU32 outStatus; 1721 NV_DECLARE_ALIGNED(NvP64 outData, 8); 1722 NvU16 outDataSize; 1723 } NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; 1724 1725 /* valid method parameter values */ 1726 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) 1727 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) 1728 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) 1729 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) 1730 /* 1731 * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS 1732 * 1733 * This command can be used to instruct the RM to enable/disable specific module 1734 * of ETW events. 1735 * 1736 * moduleMask 1737 * This parameter specifies the module of events we would like to 1738 * enable/disable. 1739 * 1740 * Possible status values returned are: 1741 * NV_OK 1742 */ 1743 #define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ 1744 1745 #define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) 1746 1747 typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { 1748 NvU32 moduleMask; 1749 } NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; 1750 1751 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) 1752 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) 1753 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) 1754 1755 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) 1756 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) 1757 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) 1758 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) 1759 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) 1760 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) 1761 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) 1762 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) 1763 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) 1764 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) 1765 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) 1766 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) 1767 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) 1768 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) 1769 1770 /* 1771 * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA 1772 * 1773 * This command is used to read FRL data based on need. 1774 * 1775 * nextSampleNumber 1776 * This parameter returns the counter of next sample which is being filled. 1777 * samples 1778 * This parameter returns the frame time, render time, target time, client ID 1779 * with one reserve bit for future use. 1780 * 1781 * Possible status values returned are: 1782 * NV_OK 1783 * NV_ERR_NOT_SUPPORTED 1784 */ 1785 1786 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1787 1788 #define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U 1789 1790 typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { 1791 NvU16 frameTime; 1792 NvU16 renderTime; 1793 NvU16 targetTime; 1794 NvU8 sleepTime; 1795 NvU8 sampleNumber; 1796 } NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; 1797 1798 #define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) 1799 1800 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { 1801 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; 1802 NvU8 nextSampleNumber; 1803 } NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; 1804 1805 /* 1806 * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA 1807 * 1808 * This command is used to write FRM data based on need. 1809 * 1810 * frameTime 1811 * This parameter contains the frame time of current frame. 1812 * renderTime 1813 * This parameter contains the render time of current frame. 1814 * targetTime 1815 * This parameter contains the target time of current frame. 1816 * sleepTime 1817 * This parameter contains the sleep duration inserted by FRL for the latest frame. 1818 * 1819 * Possible status values returned are: 1820 * NV_OK 1821 * NV_ERR_NOT_SUPPORTED 1822 */ 1823 1824 #define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1825 1826 #define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) 1827 1828 typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { 1829 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; 1830 } NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; 1831 1832 /* 1833 * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO 1834 * 1835 * This command returns the current host driver, host OS and 1836 * plugin information. It is only valid when VGX is setup. 1837 * szHostDriverVersionBuffer 1838 * This field returns the host driver version (NV_VERSION_STRING). 1839 * szHostVersionBuffer 1840 * This field returns the host driver version (NV_BUILD_BRANCH_VERSION). 1841 * szHostTitleBuffer 1842 * This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE). 1843 * szPluginTitleBuffer 1844 * This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE). 1845 * szHostUnameBuffer 1846 * This field returns the call of 'uname' on the host OS. 1847 * iHostChangelistNumber 1848 * This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM). 1849 * iPluginChangelistNumber 1850 * This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM). 1851 * 1852 * Possible status values returned are: 1853 * NV_OK 1854 * NV_ERR_INVALID_PARAM_STRUCT 1855 */ 1856 1857 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U 1858 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ 1859 1860 #define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) 1861 1862 typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { 1863 char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1864 char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1865 char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1866 char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1867 char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1868 NvU32 iHostChangelistNumber; 1869 NvU32 iPluginChangelistNumber; 1870 } NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; 1871 1872 /* 1873 * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS 1874 * 1875 * This command returns the power status of the GPUs in the system, successfully attached or not because of 1876 * insufficient power. It is supported on Kepler and up only. 1877 * gpuCount 1878 * This field returns the count into the following arrays. 1879 * busNumber 1880 * This field returns the busNumber of a GPU. 1881 * gpuExternalPowerStatus 1882 * This field returns the corresponding external power status: 1883 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 1884 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1885 * 1886 * Possible status values returned are: 1887 * NV_OK 1888 * NV_ERR_INVALID_PARAM_STRUCT 1889 * NV_ERR_NOT_SUPPORTED 1890 */ 1891 1892 #define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ 1893 1894 #define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) 1895 1896 typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { 1897 NvU8 gpuCount; 1898 NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1899 NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1900 } NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; 1901 1902 /* Valid gpuExternalPowerStatus values */ 1903 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U 1904 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U 1905 1906 /* 1907 * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS 1908 * 1909 * This command returns the caller's API access privileges using 1910 * this client handle. 1911 * 1912 * privStatus 1913 * This parameter returns a mask of possible access privileges: 1914 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG 1915 * The caller is running with elevated privileges 1916 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG 1917 * Client is of NV01_ROOT class. 1918 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG 1919 * Client has PRIV bit set. 1920 * 1921 * Possible status values returned are: 1922 * NV_OK 1923 * NV_ERR_INVALID_PARAM_STRUCT 1924 */ 1925 1926 1927 #define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ 1928 1929 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) 1930 1931 typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { 1932 NvU8 privStatusFlags; 1933 } NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS; 1934 1935 1936 /* Valid privStatus values */ 1937 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) 1938 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) 1939 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) 1940 1941 /* 1942 * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS 1943 * 1944 * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to 1945 * peer (P2P) use or still initializing the fabric. This command allows clients 1946 * to query fabric status to allow P2P operations. 1947 * 1948 * Note, on systems where FM isn't used, RM just returns _SKIP. 1949 * 1950 * fabricStatus 1951 * This parameter returns current fabric status: 1952 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP 1953 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED 1954 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS 1955 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED 1956 * 1957 * Possible status values returned are: 1958 * NV_OK 1959 * NV_ERR_INVALID_ARGUMENT 1960 * NV_ERR_INVALID_OBJECT_HANDLE 1961 * NV_ERR_NOT_SUPPORTED 1962 * NV_ERR_INSUFFICIENT_PERMISSIONS 1963 * NV_ERR_INVALID_PARAM_STRUCT 1964 */ 1965 1966 typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { 1967 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1, 1968 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2, 1969 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3, 1970 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, 1971 } NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; 1972 1973 #define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ 1974 1975 #define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) 1976 1977 typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { 1978 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; 1979 } NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; 1980 1981 /* 1982 * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO 1983 * 1984 * This command is used to query the range of VGX version supported. 1985 * 1986 * host_min_supported_version 1987 * The minimum vGPU version supported by host driver 1988 * host_max_supported_version 1989 * The maximum vGPU version supported by host driver 1990 * user_min_supported_version 1991 * The minimum vGPU version set by user for vGPU support 1992 * user_max_supported_version 1993 * The maximum vGPU version set by user for vGPU support 1994 * 1995 * Possible status values returned are: 1996 * NV_OK 1997 * NV_ERR_INVALID_REQUEST 1998 */ 1999 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 2000 2001 /* 2002 * NV0000_CTRL_VGPU_GET_VGPU_VERSION 2003 */ 2004 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) 2005 2006 typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { 2007 NvU32 host_min_supported_version; 2008 NvU32 host_max_supported_version; 2009 NvU32 user_min_supported_version; 2010 NvU32 user_max_supported_version; 2011 } NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; 2012 2013 /* 2014 * NV0000_CTRL_VGPU_SET_VGPU_VERSION 2015 * 2016 * This command is used to query whether pGPU is live migration capable or not. 2017 * 2018 * min_version 2019 * The minimum vGPU version to be supported being set 2020 * max_version 2021 * The maximum vGPU version to be supported being set 2022 * 2023 * Possible status values returned are: 2024 * NV_OK 2025 * NV_ERR_INVALID_REQUEST 2026 */ 2027 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 2028 2029 /* 2030 * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS 2031 */ 2032 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) 2033 2034 typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { 2035 NvU32 min_version; 2036 NvU32 max_version; 2037 } NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; 2038 2039 /* 2040 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID 2041 * 2042 * This command is used to get a unique identifier for the instance of RM. 2043 * The returned value will only change when the driver is reloaded. A previous 2044 * value will never be reused on a given machine. 2045 * 2046 * rm_instance_id; 2047 * The instance ID of the current RM instance 2048 * 2049 * Possible status values returned are: 2050 * NV_OK 2051 */ 2052 #define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ 2053 2054 /* 2055 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS 2056 */ 2057 #define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U) 2058 2059 typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { 2060 NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); 2061 } NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; 2062 2063 /* 2064 * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO 2065 * 2066 * This API is used to get the TPP(total processing power) and 2067 * the rated TGP(total GPU power) from SBIOS. 2068 * 2069 * NVPCF is an acronym for Nvidia Platform Controllers and Framework 2070 * which implements platform level policies. NVPCF is implemented in 2071 * a kernel driver on windows. It is implemented in a user mode app 2072 * called nvidia-powerd on Linux. 2073 * 2074 * Valid subFunc ids for NVPCF 1x include : 2075 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED 2076 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS 2077 * 2078 * Valid subFunc ids for NVPCF 2x include : 2079 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED 2080 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS 2081 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES 2082 * 2083 * Possible status values returned are: 2084 * NV_OK 2085 * NV_ERR_INVALID_REQUEST 2086 * NV_ERR_NOT_SUPPORTED 2087 */ 2088 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ 2089 2090 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) 2091 2092 typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { 2093 /* GPU ID */ 2094 NvU32 gpuId; 2095 2096 /* Total processing power including CPU and GPU */ 2097 NvU32 tpp; 2098 2099 /* Rated total GPU Power */ 2100 NvU32 ratedTgp; 2101 2102 /* NVPCF subfunction id */ 2103 NvU32 subFunc; 2104 2105 /* Configurable TGP offset, in mW */ 2106 NvU32 ctgpOffsetmW; 2107 2108 /* TPP, as offset in mW */ 2109 NvU32 targetTppOffsetmW; 2110 2111 /* Maximum allowed output, as offset in mW */ 2112 NvU32 maxOutputOffsetmW; 2113 2114 /* Minimum allowed output, as offset in mW */ 2115 NvU32 minOutputOffsetmW; 2116 2117 /* The System Controller Table Version */ 2118 NvU8 version; 2119 2120 /* Base sampling period */ 2121 NvU16 samplingPeriodmS; 2122 2123 /* Sampling Multiplier */ 2124 NvU16 samplingMulti; 2125 2126 /* Fitler function type */ 2127 NvU8 filterType; 2128 2129 union { 2130 2131 /* weight */ 2132 NvU8 weight; 2133 2134 /* windowSize */ 2135 NvU8 windowSize; 2136 } filterParam; 2137 2138 /* Reserved */ 2139 NvU16 filterReserved; 2140 2141 /* Controller Type Dynamic Boost Controller */ 2142 NvBool bIsBoostController; 2143 2144 /* Increase power limit ratio */ 2145 NvU16 incRatio; 2146 2147 /* Decrease power limit ratio */ 2148 NvU16 decRatio; 2149 2150 /* Dynamic Boost Controller DC Support */ 2151 NvBool bSupportBatt; 2152 2153 /* CPU type(Intel/AMD) */ 2154 NvU8 cpuType; 2155 2156 /* GPU type(Nvidia) */ 2157 NvU8 gpuType; 2158 } NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; 2159 2160 /* Define the filter types */ 2161 #define CONTROLLER_FILTER_TYPE_EMWA 0U 2162 #define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U 2163 2164 /* Valid NVPCF subfunction case */ 2165 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U 2166 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE 1U 2167 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U 2168 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U 2169 2170 /* NVPCF subfunction to get the static data tables */ 2171 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE 4U 2172 2173 /* Valid NVPCF subfunction ids */ 2174 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) 2175 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2176 2177 /* 2178 * Defines for get supported sub functions bit fields 2179 */ 2180 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 2181 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 2182 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 2183 2184 /*! 2185 * Config DSM 2x version specific defines 2186 */ 2187 #define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) 2188 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) 2189 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES (0x00000001) 2190 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2191 2192 /*! 2193 * Defines the max buffer size for config 2194 */ 2195 #define NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX (255) 2196 2197 /* 2198 * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT 2199 * 2200 * This API is used to sync the external fabric management status with 2201 * GSP-RM 2202 * 2203 * bExternalFabricMgmt 2204 * Whether fabric is externally managed 2205 * 2206 * Possible status values returned are: 2207 * NV_OK 2208 */ 2209 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ 2210 2211 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) 2212 2213 typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { 2214 NvBool bExternalFabricMgmt; 2215 } NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS; 2216 2217 /* 2218 * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO 2219 * 2220 * This API is used to get information about the RM client 2221 * database. 2222 * 2223 * clientCount [OUT] 2224 * This field indicates the number of clients currently allocated. 2225 * 2226 * resourceCount [OUT] 2227 * This field indicates the number of resources currently allocated 2228 * across all clients. 2229 * 2230 */ 2231 #define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ 2232 2233 #define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) 2234 2235 typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { 2236 NvU32 clientCount; 2237 NV_DECLARE_ALIGNED(NvU64 resourceCount, 8); 2238 } NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS; 2239 2240 /* 2241 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 2242 * 2243 * This command returns the current driver information in 2244 * statically sized character arrays. 2245 * 2246 * driverVersionBuffer 2247 * This field returns the version (NV_VERSION_STRING). 2248 * versionBuffer 2249 * This field returns the version (NV_BUILD_BRANCH_VERSION). 2250 * titleBuffer 2251 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 2252 * changelistNumber 2253 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 2254 * officialChangelistNumber 2255 * This field returns the last official changelist value 2256 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 2257 * 2258 * Possible status values returned are: 2259 * NV_OK 2260 */ 2261 2262 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U 2263 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ 2264 2265 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) 2266 2267 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { 2268 char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2269 char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2270 char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2271 NvU32 changelistNumber; 2272 NvU32 officialChangelistNumber; 2273 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; 2274 2275 /* 2276 * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL 2277 * 2278 * This API is used to get/set RMCTRL cache mode 2279 * 2280 * cmd [IN] 2281 * GET - Gets RMCTRL cache mode 2282 * SET - Sets RMCTRL cache mode 2283 * 2284 * mode [IN/OUT] 2285 * On GET, this field is the output of current RMCTRL cache mode 2286 * On SET, this field indicates the mode to set RMCTRL cache to 2287 * Valid values for this parameter are: 2288 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE 2289 * No get/set action to cache. 2290 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE 2291 * Try to get from cache at the beginning of the control. 2292 * Set cache after control finished if the control has not been cached. 2293 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY 2294 * Do not get from cache. Set cache when control call finished. 2295 * When setting the cache, verify the value in the cache is the same 2296 * with the current control value if the control is already cached. 2297 * 2298 * Possible status values returned are: 2299 * NV_OK 2300 * NV_ERR_INVALID_ARGUMENT 2301 */ 2302 #define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ 2303 2304 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) 2305 2306 typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { 2307 NvU32 cmd; 2308 NvU32 mode; 2309 } NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; 2310 2311 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) 2312 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) 2313 2314 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) 2315 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) 2316 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) 2317 2318 /* 2319 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL 2320 * 2321 * This command is used to control PFM_REQ_HNDLR functionality. It allows control of 2322 * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read 2323 * most PFM_REQ_HNDLR dynamic parameters. 2324 * 2325 * command 2326 * This parameter specifies the command to execute. Invalid commands 2327 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 2328 * locale 2329 * This parameter indicates the specific locale to which the command 2330 * 'command' is to be applied. 2331 * Supported range of CPU/GPU {i = 0, ..., 255} 2332 * data 2333 * This parameter contains a command-specific data payload. It can 2334 * be used to input data as well as output data. 2335 * 2336 * Possible status values returned are: 2337 * NV_OK 2338 * NV_ERR_INVALID_COMMAND 2339 * NV_ERR_INVALID_STATE 2340 * NV_ERR_INVALID_DATA 2341 * NV_ERR_INVALID_REQUEST 2342 * NV_ERR_NOT_SUPPORTED 2343 */ 2344 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ 2345 2346 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) 2347 2348 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { 2349 NvU16 command; 2350 NvU16 locale; 2351 NvU32 data; 2352 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; 2353 2354 /* 2355 * Valid command values : 2356 * 2357 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT 2358 * Is used to check if PFM_REQ_HNDLR was correctly initialized. 2359 * Possible return (OUT) values are: 2360 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO 2361 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES 2362 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC 2363 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC 2364 * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. 2365 * Possible IN/OUT values are: 2366 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP 2367 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START 2368 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS 2369 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS 2370 * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. 2371 * Possible IN/OUT values are: 2372 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF 2373 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON 2374 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC 2375 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC 2376 * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. 2377 * Possible IN/OUT values are: 2378 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF 2379 * Will cause that all PFM_REQ_HNDLR actions will be NULL. 2380 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY 2381 * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. 2382 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC 2383 * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. 2384 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE 2385 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE 2386 * Are used to set/retrieve system control preference. 2387 * Possible IN/OUT values are: 2388 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU 2389 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU 2390 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH 2391 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT 2392 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT 2393 * Are used to set/retrieve GPU2CPU pstate limits. 2394 * IN/OUT values are four bytes packed into a 32-bit data field. 2395 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 2396 * index for the GPU pstate 3 is in the highest byte, etc. One 2397 * special value is to disable the override to the GPU2CPU map: 2398 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE 2399 * Is used to stop/start PFM_REQ_HNDLR PMU functionality. 2400 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE 2401 * Is used to get the current status of PMU PFM_REQ_HNDLR. 2402 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE 2403 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER 2404 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER 2405 * Are used to set/retrieve max power [mW] that system can provide. 2406 * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply 2407 * to this threshold. 2408 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET 2409 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET 2410 * Are used to set/retrieve current system cooling budget [mW]. 2411 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD 2412 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD 2413 * Are used to set/retrieve integration interval [sec]. 2414 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET 2415 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET 2416 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT 2417 * Are used to set/retrieve used ruleset [#]. Value is checked 2418 * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT 2419 * provides a way to find out how many rules exist for the current control 2420 * system. 2421 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST 2422 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST 2423 * Is used to set/get a delay relative to now during which to allow unbound 2424 * CPU performance. Units are seconds. 2425 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE 2426 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE 2427 * Is used to override/get the actual power supply mode (AC/Battery). 2428 * Possible IN/OUT values are: 2429 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL 2430 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC 2431 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT 2432 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO 2433 * Is used to get the Ventura system information for VCT tool 2434 * Returned 32bit value should be treated as bitmask and decoded in 2435 * following way: 2436 * Encoding details are defined in objPFM_REQ_HNDLR.h refer to 2437 * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. 2438 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION 2439 * Is used to get the supported sub-functions defined in SBIOS. Returned 2440 * value is a bitmask where each bit corresponds to different function: 2441 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT 2442 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS 2443 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS 2444 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC 2445 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC 2446 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB 2447 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS 2448 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER 2449 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA 2450 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE 2451 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG 2452 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL 2453 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN 2454 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE 2455 * Are used to retrieve appropriate power measurements and their derivatives 2456 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 2457 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 2458 * index. 2459 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS 2460 * Is used to retrieve parameters when adjusting raw sensor power reading. 2461 * The values may come from SBIOS, VBIOS, registry or driver default. 2462 * Possible IN value is the index of interested parameter. 2463 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP 2464 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA 2465 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE 2466 * Are used to retrieve appropriate temperature measurements and their 2467 * derivatives in [1/1000 Celsius]. 2468 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE 2469 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP 2470 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN 2471 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX 2472 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 2473 * Not applicable to _LOCALE_SYSTEM. 2474 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION 2475 * Is used to retrieve last PFM_REQ_HNDLR action for given domain. 2476 * Not applicable to _LOCALE_SYSTEM. 2477 * Possible return (OUT) values are: 2478 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 2479 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 2480 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING 2481 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT 2482 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 2483 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 2484 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM 2485 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM 2486 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE 2487 * Is used to set the power sensor simulator state. 2488 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE 2489 * Is used to get the power simulator sensor simulator state. 2490 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA 2491 * Is used to set power sensor simulator data 2492 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA 2493 * Is used to get power sensor simulator data 2494 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK 2495 * Is used to respond to the ACPI event triggered by SBIOS. RM will 2496 * request value for budget and status, validate them, apply them 2497 * and send ACK back to SBIOS. 2498 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT 2499 * Is a test cmd that should notify SBIOS to send ACPI event requesting 2500 * budget and status change. 2501 */ 2502 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) 2503 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) 2504 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) 2505 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) 2506 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) 2507 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) 2508 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) 2509 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) 2510 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) 2511 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) 2512 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) 2513 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) 2514 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) 2515 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) 2516 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) 2517 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) 2518 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) 2519 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) 2520 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) 2521 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) 2522 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) 2523 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) 2524 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) 2525 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) 2526 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) 2527 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 2528 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 2529 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 2530 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 2531 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) 2532 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) 2533 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) 2534 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) 2535 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) 2536 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) 2537 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) 2538 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) 2539 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) 2540 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) 2541 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) 2542 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) 2543 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) 2544 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) 2545 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) 2546 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) 2547 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 2548 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) 2549 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) 2550 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) 2551 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) 2552 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 2553 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 2554 2555 /* valid LOCALE values */ 2556 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) 2557 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) 2558 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) 2559 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) 2560 2561 /* valid data values for enums */ 2562 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) 2563 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) 2564 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) 2565 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) 2566 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) 2567 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) 2568 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) 2569 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) 2570 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) 2571 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 2572 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) 2573 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) 2574 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 2575 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 2576 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) 2577 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) 2578 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 2579 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 2580 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 2581 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) 2582 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 2583 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) 2584 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) 2585 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) 2586 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) 2587 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 2588 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 2589 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 2590 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 2591 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 2592 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 2593 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 2594 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 2595 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 2596 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 2597 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 2598 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 2599 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 2600 2601 /* 2602 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL 2603 * 2604 * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one 2605 * RmControl call. For practical reasons # of commands is limited to 16. 2606 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. 2607 * 2608 * cmdCount 2609 * Number of commands that should be executed. 2610 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2611 * 2612 * succeeded 2613 * Number of commands that were succesully executed. 2614 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2615 * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID 2616 * in their data field. 2617 * 2618 * cmdData 2619 * Array of commands with following structure: 2620 * command 2621 * This parameter specifies the command to execute. 2622 * Invalid commands result in the return of an 2623 * NV_ERR_INVALID_ARGUMENT status. 2624 * locale 2625 * This parameter indicates the specific locale to which 2626 * the command 'command' is to be applied. 2627 * Supported range of CPU/GPU {i = 0, ..., 255} 2628 * data 2629 * This parameter contains a command-specific data payload. 2630 * It is used both to input data as well as to output data. 2631 * 2632 * Possible status values returned are: 2633 * NV_OK 2634 * NV_ERR_INVALID_REQUEST 2635 * NV_ERR_NOT_SUPPORTED 2636 */ 2637 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 2638 2639 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) 2640 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) 2641 2642 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { 2643 NvU32 cmdCount; 2644 NvU32 succeeded; 2645 2646 struct { 2647 NvU16 command; 2648 NvU16 locale; 2649 NvU32 data; 2650 } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; 2651 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; 2652 2653 /* 2654 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL 2655 * 2656 * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with 2657 * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. 2658 * 2659 * version 2660 * This parameter specifies the version of the interface. Legal values 2661 * for this parameter are 1. 2662 * cmd 2663 * This parameter specifies the PFM_REQ_HNDLR API to be invoked. 2664 * Valid values for this parameter are: 2665 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT 2666 * This command gets the temperature limit for thermal controller. When 2667 * this command is specified the input parameter contains ???. 2668 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT 2669 * This command set the temperature limit for thermal controller. When 2670 * this command is specified the input parameter contains ???. 2671 * input 2672 * This parameter specifies the cmd-specific input value. 2673 * result 2674 * This parameter returns the cmd-specific output value. 2675 * 2676 * Possible status values returned are: 2677 * NV_OK 2678 * NV_ERR_INVALID_PARAM_STRUCT 2679 * NV_ERR_INVALID_ARGUMENT 2680 */ 2681 2682 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ 2683 2684 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) 2685 2686 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { 2687 NvU32 cmd; 2688 NvS32 input[2]; 2689 NvS32 result[4]; 2690 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; 2691 2692 /* valid version values */ 2693 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 2694 2695 /* valid cmd values */ 2696 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 2697 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) 2698 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) 2699 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) 2700 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) 2701 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) 2702 2703 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 2704 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2705 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) 2706 2707 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 2708 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2709 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 2710 2711 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 2712 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2713 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 2714 2715 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 2716 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2717 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 2718 2719 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 2720 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2721 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 2722 2723 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 2724 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2725 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 2726 2727 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 2728 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2729 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 2730 2731 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 2732 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2733 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 2734 2735 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 2736 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2737 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 2738 2739 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 2740 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2741 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2742 2743 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 2744 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2745 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2746 2747 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 2748 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) 2749 2750 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 2751 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) 2752 2753 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 2754 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 2755 2756 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 2757 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 2758 2759 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 2760 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2761 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 2762 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) 2763 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 2764 2765 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) 2766 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) 2767 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) 2768 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) 2769 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) 2770 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 2771 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 2772 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 2773 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) 2774 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 2775 2776 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 2777 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) 2778 2779 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 2780 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) 2781 2782 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 2783 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) 2784 2785 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 2786 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) 2787 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 2788 2789 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 2790 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) 2791 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 2792 2793 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 2794 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2795 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2796 2797 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 2798 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2799 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2800 2801 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 2802 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2803 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2804 2805 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 2806 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2807 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2808 2809 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 2810 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) 2811 2812 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 2813 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) 2814 2815 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 2816 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2817 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 2818 2819 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 2820 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2821 2822 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 2823 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2824 2825 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 2826 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2827 2828 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) 2829 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) 2830 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 2831 2832 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) 2833 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) 2834 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 2835 2836 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 2837 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) 2838 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) 2839 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) 2840 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) 2841 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 2842 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) 2843 2844 /* valid PS_STATUS result values */ 2845 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) 2846 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) 2847 2848 #define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U 2849 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { 2850 NvU32 objHndl; 2851 NvU32 blockId; 2852 NvU32 nextExpectedSampleTimems; 2853 NvU32 countersReq; 2854 NvU32 countersReturned; 2855 NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; 2856 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; 2857 2858 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x46" */ 2859 2860 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x47" */ 2861 2862 /* 2863 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI 2864 * 2865 * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. 2866 * 2867 * cmd 2868 * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. 2869 * 2870 * input 2871 * This parameter specified the cmd-dependent input value. 2872 * 2873 * resultSz 2874 * This parameter returns the size (in bytes) of the valid data 2875 * returned in the result parameter. 2876 * 2877 * result 2878 * This parameter returns the results of the specified cmd. 2879 * The maximum size (in bytes) of this returned data will 2880 * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 2881 * 2882 * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 2883 * The size of buffer (result) in unit of NvU32. 2884 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 2885 * Since the prior one is 24 bytes, and the later one is 48, 2886 * this value cannot be smaller than 288. 2887 * 2888 * Possible status values returned are: 2889 * NV_OK 2890 * NV_ERR_INVALID_ARGUMENT, 2891 * NV_ERR_INVALID_OBJECT_HANDLE 2892 * NV_ERR_NOT_SUPPORTED 2893 * NV_ERR_INSUFFICIENT_PERMISSIONS 2894 * 2895 */ 2896 #define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 2897 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) 2898 2899 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { 2900 NvU32 cmd; 2901 NvU32 input; 2902 NvU32 resultSz; 2903 NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 2904 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; 2905 2906 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ 2907 2908 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) 2909 2910 /* 2911 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA 2912 * 2913 * This command is used to read FRL data based on need. 2914 * 2915 * nextSampleNumber 2916 * This parameter returns the counter of next sample which is being filled. 2917 * samples 2918 * This parameter returns the frame time, render time, target time, client ID 2919 * with one reserve bit for future use. 2920 * 2921 * Possible status values returned are: 2922 * NV_OK 2923 * NV_ERR_NOT_SUPPORTED 2924 */ 2925 2926 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 2927 2928 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U 2929 2930 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { 2931 NvU16 frameTime; 2932 NvU16 renderTime; 2933 NvU16 targetTime; 2934 NvU8 sleepTime; 2935 NvU8 sampleNumber; 2936 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; 2937 2938 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) 2939 2940 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { 2941 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; 2942 NvU8 nextSampleNumber; 2943 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; 2944 2945 /* 2946 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA 2947 * 2948 * This command is used to write FRM data based on need. 2949 * 2950 * frameTime 2951 * This parameter contains the frame time of current frame. 2952 * renderTime 2953 * This parameter contains the render time of current frame. 2954 * targetTime 2955 * This parameter contains the target time of current frame. 2956 * sleepTime 2957 * This parameter contains the sleep duration inserted by FRL for the latest frame. 2958 * 2959 * Possible status values returned are: 2960 * NV_OK 2961 * NV_ERR_NOT_SUPPORTED 2962 */ 2963 2964 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 2965 2966 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) 2967 2968 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { 2969 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; 2970 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; 2971 2972 /* _ctrl0000system_h_ */ 2973