1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #pragma once 24 25 #include <nvtypes.h> 26 27 // 28 // This file was generated with FINN, an NVIDIA coding tool. 29 // Source file: ctrl/ctrl0000/ctrl0000system.finn 30 // 31 32 #include "ctrl/ctrlxxxx.h" 33 #include "ctrl/ctrl0000/ctrl0000base.h" 34 35 /* NV01_ROOT (client) system control commands and parameters */ 36 37 /* 38 * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES 39 * 40 * This command returns a mask of supported features for the SYSTEM category 41 * of the 0000 class. 42 * 43 * Valid features include: 44 * 45 * NV0000_CTRL_GET_FEATURES_SLI 46 * When this bit is set, SLI is supported. 47 * NV0000_CTRL_GET_FEATURES_UEFI 48 * When this bit is set, it is a UEFI system. 49 * NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 50 * When this bit is set, EFI has initialized core channel 51 * 52 * Possible status values returned are: 53 * NV_OK 54 * NV_ERR_INVALID_STATE 55 */ 56 #define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ 57 58 #define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) 59 60 typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { 61 NvU32 featuresMask; 62 } NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS; 63 64 65 66 /* Valid feature values */ 67 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 68 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) 69 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) 70 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1 71 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U) 72 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U) 73 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 74 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) 75 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) 76 /* 77 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION 78 * 79 * This command returns the current driver information. 80 * The first time this is called the size of strings is 81 * set with the greater of NV_BUILD_BRANCH_VERSION and 82 * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory 83 * of size sizeOfStrings for pVersionBuffer and pTitleBuffer 84 * and calls the command again to receive driver info. 85 * 86 * sizeOfStrings 87 * This field returns the size in bytes of the pVersionBuffer and 88 * pTitleBuffer strings. 89 * pDriverVersionBuffer 90 * This field returns the version (NV_VERSION_STRING). 91 * pVersionBuffer 92 * This field returns the version (NV_BUILD_BRANCH_VERSION). 93 * pTitleBuffer 94 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 95 * changelistNumber 96 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 97 * officialChangelistNumber 98 * This field returns the last official changelist value 99 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 100 * 101 * Possible status values returned are: 102 * NV_OK 103 * NV_ERR_INVALID_PARAM_STRUCT 104 */ 105 106 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ 107 108 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) 109 110 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { 111 NvU32 sizeOfStrings; 112 NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8); 113 NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8); 114 NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8); 115 NvU32 changelistNumber; 116 NvU32 officialChangelistNumber; 117 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS; 118 119 /* 120 * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO 121 * 122 * This command returns system CPU information. 123 * 124 * type 125 * This field returns the processor type. 126 * Legal processor types include: 127 * Intel processors: 128 * P55 : P55C - MMX 129 * P6 : PPro 130 * P2 : PentiumII 131 * P2XC : Xeon & Celeron 132 * CELA : Celeron-A 133 * P3 : Pentium-III 134 * P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K) 135 * P4 : Pentium 4 136 * CORE2 : Core2 Duo Conroe 137 * AMD processors 138 * K62 : K6-2 w/ 3DNow 139 * IDT/Centaur processors 140 * C6 : WinChip C6 141 * C62 : WinChip 2 w/ 3DNow 142 * Cyrix processors 143 * GX : MediaGX 144 * M1 : 6x86 145 * M2 : M2 146 * MGX : MediaGX w/ MMX 147 * Transmeta processors 148 * TM_CRUSOE : Transmeta Crusoe(tm) 149 * PowerPC processors 150 * PPC603 : PowerPC 603 151 * PPC604 : PowerPC 604 152 * PPC750 : PowerPC 750 153 * 154 * capabilities 155 * This field returns the capabilities of the processor. 156 * Legal processor capabilities include: 157 * MMX : supports MMX 158 * SSE : supports SSE 159 * 3DNOW : supports 3DNow 160 * SSE2 : supports SSE2 161 * SFENCE : supports SFENCE 162 * WRITE_COMBINING : supports write-combining 163 * ALTIVEC : supports ALTIVEC 164 * PUT_NEEDS_IO : requires OUT inst w/PUT updates 165 * NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug 166 * 3DNOW_EXT : supports 3DNow Extensions 167 * MMX_EXT : supports MMX Extensions 168 * CMOV : supports CMOV 169 * CLFLUSH : supports CLFLUSH 170 * SSE3 : supports SSE3 171 * NEEDS_WAR_124888 : requires write to GPU while spinning on 172 * : GPU value 173 * HT : support hyper-threading 174 * clock 175 * This field returns the processor speed in MHz. 176 * L1DataCacheSize 177 * This field returns the level 1 data (or unified) cache size 178 * in kilobytes. 179 * L2DataCacheSize 180 * This field returns the level 2 data (or unified) cache size 181 * in kilobytes. 182 * dataCacheLineSize 183 * This field returns the bytes per line in the level 1 data cache. 184 * numLogicalCpus 185 * This field returns the number of logical processors. On Intel x86 186 * systems that support it, this value will incorporate the current state 187 * of HyperThreading. 188 * numPhysicalCpus 189 * This field returns the number of physical processors. 190 * name 191 * This field returns the CPU name in ASCII string format. 192 * family 193 * Vendor defined Family and Extended Family combined 194 * model 195 * Vendor defined Model and Extended Model combined 196 * stepping 197 * Silicon stepping 198 * bSEVEnabled 199 * Secure Encrypted Virtualization enabled/disabled state 200 * 201 * Possible status values returned are: 202 * NV_OK 203 * NV_ERR_INVALID_PARAM_STRUCT 204 */ 205 #define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ 206 207 #define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) 208 209 typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { 210 NvU32 type; /* processor type */ 211 NvU32 capabilities; /* processor caps */ 212 NvU32 clock; /* processor speed (MHz) */ 213 NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ 214 NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ 215 NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ 216 NvU32 numLogicalCpus; /* logial processor cnt */ 217 NvU32 numPhysicalCpus; /* physical processor cnt*/ 218 NvU8 name[52]; /* embedded cpu name */ 219 NvU32 family; /* Vendor defined Family and Extended Family combined */ 220 NvU32 model; /* Vendor defined Model and Extended Model combined */ 221 NvU8 stepping; /* Silicon stepping */ 222 NvU32 coresOnDie; /* cpu cores per die */ 223 NvBool bSEVEnabled; /* SEV enabled on cpu */ 224 } NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; 225 226 // Macros for CPU family information 227 #define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 228 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 229 230 // Macros for CPU model information 231 #define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 232 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 233 234 // Macros for AMD CPU information 235 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF 236 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA 237 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 238 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 239 240 // Macros for Intel CPU information 241 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 242 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 243 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 244 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA 245 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 246 247 /* processor type values */ 248 #define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) 249 /* Intel types */ 250 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) 251 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) 252 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) 253 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) 254 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) 255 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) 256 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) 257 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) 258 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) 259 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) 260 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) 261 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) 262 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) 263 /* AMD types */ 264 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) 265 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) 266 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) 267 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) 268 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) 269 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) 270 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) 271 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) 272 #define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) 273 /* IDT/Centaur types */ 274 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) 275 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) 276 /* Cyrix types */ 277 #define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) 278 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) 279 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) 280 #define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) 281 /* Transmeta types */ 282 #define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) 283 /* IBM types */ 284 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) 285 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) 286 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) 287 #define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) 288 /* Unknown ARM architecture CPU type */ 289 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) 290 /* ARM Ltd types */ 291 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) 292 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) 293 /* NVIDIA types */ 294 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) 295 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) 296 297 /* Generic types */ 298 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) 299 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) 300 301 /* processor capabilities */ 302 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) 303 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) 304 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) 305 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) 306 #define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) 307 #define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) 308 #define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) 309 #define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) 310 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) 311 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) 312 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) 313 #define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) 314 #define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) 315 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ 316 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) 317 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) 318 #define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) 319 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) 320 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) 321 #define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) 322 #define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) 323 324 /* 325 * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO 326 * 327 * This command returns system chipset information. 328 * 329 * vendorId 330 * This parameter returns the vendor identification for the chipset. 331 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 332 * cannot be identified. 333 * deviceId 334 * This parameter returns the device identification for the chipset. 335 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 336 * cannot be identified. 337 * subSysVendorId 338 * This parameter returns the subsystem vendor identification for the 339 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 340 * chipset cannot be identified. 341 * subSysDeviceId 342 * This parameter returns the subsystem device identification for the 343 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 344 * chipset cannot be identified. 345 * HBvendorId 346 * This parameter returns the vendor identification for the chipset's 347 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 348 * the chipset's host bridge cannot be identified. 349 * HBdeviceId 350 * This parameter returns the device identification for the chipset's 351 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 352 * the chipset's host bridge cannot be identified. 353 * HBsubSysVendorId 354 * This parameter returns the subsystem vendor identification for the 355 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 356 * indicates the chipset's host bridge cannot be identified. 357 * HBsubSysDeviceId 358 * This parameter returns the subsystem device identification for the 359 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 360 * indicates the chipset's host bridge cannot be identified. 361 * sliBondId 362 * This parameter returns the SLI bond identification for the chipset. 363 * vendorNameString 364 * This parameter returns the vendor name string. 365 * chipsetNameString 366 * This parameter returns the vendor name string. 367 * sliBondNameString 368 * This parameter returns the SLI bond name string. 369 * flag 370 * This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags: 371 * _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1 372 * should be disabled - bug 3440153 373 * 374 * Possible status values returned are: 375 * NV_OK 376 * NV_ERR_INVALID_PARAM_STRUCT 377 * NV_ERR_INVALID_ARGUMENT 378 * NV_ERR_OPERATING_SYSTEM 379 */ 380 #define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ 381 382 /* maximum name string length */ 383 #define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) 384 385 /* invalid id */ 386 #define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) 387 388 #define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) 389 390 typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { 391 NvU16 vendorId; 392 NvU16 deviceId; 393 NvU16 subSysVendorId; 394 NvU16 subSysDeviceId; 395 NvU16 HBvendorId; 396 NvU16 HBdeviceId; 397 NvU16 HBsubSysVendorId; 398 NvU16 HBsubSysDeviceId; 399 NvU32 sliBondId; 400 NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 401 NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 402 NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 403 NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 404 NvU32 flags; 405 } NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; 406 407 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 408 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) 409 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) 410 411 412 413 /* 414 * NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE 415 * 416 * This command is used to set the system memory size in pages. 417 * 418 * memorySize 419 * This parameter specifies the system memory size in pages. All values 420 * are considered legal. 421 * 422 * 423 * Possible status values returned are: 424 * NV_OK 425 * NV_ERR_INVALID_PARAM_STRUCT 426 */ 427 #define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */ 428 429 #define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U) 430 431 typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS { 432 NvU32 memorySize; 433 } NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS; 434 435 /* 436 * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST 437 * 438 * This command is used to retrieve the set of system-level classes 439 * supported by the platform. 440 * 441 * numClasses 442 * This parameter returns the number of valid entries in the returned 443 * classes[] list. This parameter will not exceed 444 * Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE. 445 * classes 446 * This parameter returns the list of supported classes 447 * 448 * Possible status values returned are: 449 * NV_OK 450 * NV_ERR_INVALID_PARAM_STRUCT 451 */ 452 453 #define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ 454 455 /* maximum number of classes returned in classes[] array */ 456 #define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) 457 458 #define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) 459 460 typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { 461 NvU32 numClasses; 462 NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE]; 463 } NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS; 464 465 /* 466 * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT 467 * 468 * This command is used to send triggered mobile related system events 469 * to the RM. 470 * 471 * eventType 472 * This parameter indicates the triggered event type. This parameter 473 * should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value. 474 * eventData 475 * This parameter specifies the type-dependent event data associated 476 * with EventType. This parameter should specify a valid 477 * NV0000_CTRL_SYSTEM_EVENT_DATA value. 478 * bEventDataForced 479 * This parameter specifies what we have to do, Whether trust current 480 * Lid/Dock state or not. This parameter should specify a valid 481 * NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value. 482 483 * Possible status values returned are: 484 * NV_OK 485 * NV_ERR_INVALID_PARAM_STRUCT 486 * NV_ERR_INVALID_ARGUMENT 487 * 488 * Sync this up (#defines) with one in nvapi.spec! 489 * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) 490 */ 491 #define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ 492 493 #define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) 494 495 typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { 496 NvU32 eventType; 497 NvU32 eventData; 498 NvBool bEventDataForced; 499 } NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; 500 501 /* valid eventType values */ 502 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) 503 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) 504 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) 505 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) 506 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) 507 508 /* valid eventData values */ 509 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) 510 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) 511 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) 512 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) 513 #define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) 514 #define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) 515 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) 516 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) 517 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) 518 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) 519 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) 520 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ 521 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) 522 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) 523 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) 524 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) 525 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) 526 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ 527 528 /* valid bEventDataForced values */ 529 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) 530 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) 531 532 /* 533 * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE 534 * 535 * This command is used to query the platform type. 536 * 537 * systemType 538 * This parameter returns the type of the system. 539 * Legal values for this parameter include: 540 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 541 * The system is a desktop platform. 542 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC 543 * The system is a mobile (non-Toshiba) platform. 544 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 545 * The system is a mobile Toshiba platform. 546 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC 547 * The system is a system-on-a-chip (SOC) platform. 548 * 549 550 * Possible status values returned are: 551 * NV_OK 552 * NV_ERR_INVALID_PARAM_STRUCT 553 * NV_ERR_INVALID_ARGUMENT 554 */ 555 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ 556 557 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) 558 559 typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { 560 NvU32 systemType; 561 } NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; 562 563 /* valid systemType values */ 564 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) 565 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) 566 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) 567 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) 568 569 570 571 572 /* 573 * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL 574 * 575 * This command controls the current RmMsg filters. 576 * 577 * It is only supported if RmMsg is enabled (e.g. debug builds). 578 * 579 * cmd 580 * GET - Gets the current RmMsg filter string. 581 * SET - Sets the current RmMsg filter string. 582 * 583 * count 584 * The length of the RmMsg filter string. 585 * 586 * data 587 * The RmMsg filter string. 588 * 589 * Possible status values returned are: 590 * NV_OK 591 * NV_ERR_INVALID_ARGUMENT 592 * NV_ERR_NOT_SUPPORTED 593 */ 594 #define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ 595 596 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U 597 598 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) 599 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) 600 601 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) 602 603 typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS { 604 NvU32 cmd; 605 NvU32 count; 606 NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE]; 607 } NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS; 608 609 /* 610 * NV0000_CTRL_SYSTEM_HWBC_INFO 611 * 612 * This structure contains information about the HWBC (BR04) specified by 613 * hwbcId. 614 * 615 * hwbcId 616 * This field specifies the HWBC ID. 617 * firmwareVersion 618 * This field returns the version of the firmware on the HWBC (BR04), if 619 * present. This is a packed binary number of the form 0x12345678, which 620 * corresponds to a firmware version of 12.34.56.78. 621 * subordinateBus 622 * This field returns the subordinate bus number of the HWBC (BR04). 623 * secondaryBus 624 * This field returns the secondary bus number of the HWBC (BR04). 625 * 626 * Possible status values returned are: 627 * NV_OK 628 * NV_ERR_INVALID_ARGUMENT 629 */ 630 631 typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { 632 NvU32 hwbcId; 633 NvU32 firmwareVersion; 634 NvU32 subordinateBus; 635 NvU32 secondaryBus; 636 } NV0000_CTRL_SYSTEM_HWBC_INFO; 637 638 #define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU) 639 640 /* 641 * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO 642 * 643 * This command returns information about all Hardware Broadcast (HWBC) 644 * devices present in the system that are BR04s. To get the complete 645 * list of HWBCs in the system, all GPUs present in the system must be 646 * initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to 647 * accomplish this. 648 * 649 * hwbcInfo 650 * This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into 651 * which HWBC information is placed. There is one entry for each HWBC 652 * present in the system. Valid entries are contiguous, invalid entries 653 * have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC 654 * is present in the system, all the entries would be marked invalid, but 655 * the return value would still be SUCCESS. 656 * 657 * Possible status values returned are: 658 * NV_OK 659 * NV_ERR_INVALID_ARGUMENT 660 */ 661 #define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ 662 663 #define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U) 664 665 #define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U) 666 667 typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { 668 NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS]; 669 } NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS; 670 671 /* 672 * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL 673 * 674 * This command is used to control GPS functionality. It allows control of 675 * GPU Performance Scaling (GPS), changing its operational parameters and read 676 * most GPS dynamic parameters. 677 * 678 * command 679 * This parameter specifies the command to execute. Invalid commands 680 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 681 * locale 682 * This parameter indicates the specific locale to which the command 683 * 'command' is to be applied. 684 * Supported range of CPU/GPU {i = 0, ..., 255} 685 * data 686 * This parameter contains a command-specific data payload. It can 687 * be used to input data as well as output data. 688 * 689 * Possible status values returned are: 690 * NV_OK 691 * NV_ERR_INVALID_COMMAND 692 * NV_ERR_INVALID_STATE 693 * NV_ERR_INVALID_DATA 694 * NV_ERR_INVALID_REQUEST 695 * NV_ERR_NOT_SUPPORTED 696 */ 697 #define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ 698 699 #define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) 700 701 typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { 702 NvU16 command; 703 NvU16 locale; 704 NvU32 data; 705 } NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; 706 707 /* 708 * Valid command values : 709 * 710 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT 711 * Is used to check if GPS was correctly initialized. 712 * Possible return (OUT) values are: 713 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO 714 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES 715 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC 716 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC 717 * Are used to stop/start GPS functionality and to get current status. 718 * Possible IN/OUT values are: 719 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP 720 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START 721 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS 722 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS 723 * Are used to control execution of GPS actions and to get current status. 724 * Possible IN/OUT values are: 725 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF 726 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON 727 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC 728 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC 729 * Are used to switch current GPS logic and to retrieve current logic. 730 * Possible IN/OUT values are: 731 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF 732 * Will cause that all GPS actions will be NULL. 733 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY 734 * Fuzzy logic will determine GPS actions based on current ruleset. 735 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC 736 * Deterministic logic will define GPS actions based on current ruleset. 737 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE 738 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE 739 * Are used to set/retrieve system control preference. 740 * Possible IN/OUT values are: 741 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU 742 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU 743 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH 744 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT 745 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT 746 * Are used to set/retrieve GPU2CPU pstate limits. 747 * IN/OUT values are four bytes packed into a 32-bit data field. 748 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 749 * index for the GPU pstate 3 is in the highest byte, etc. One 750 * special value is to disable the override to the GPU2CPU map: 751 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE 752 * Is used to stop/start GPS PMU functionality. 753 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE 754 * Is used to get the current status of PMU GPS. 755 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE 756 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER 757 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER 758 * Are used to set/retrieve max power [mW] that system can provide. 759 * This is hardcoded GPS safety feature and logic/rules does not apply 760 * to this threshold. 761 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET 762 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET 763 * Are used to set/retrieve current system cooling budget [mW]. 764 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD 765 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD 766 * Are used to set/retrieve integration interval [sec]. 767 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET 768 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET 769 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT 770 * Are used to set/retrieve used ruleset [#]. Value is checked 771 * against MAX number of rules for currently used GPS logic. Also COUNT 772 * provides a way to find out how many rules exist for the current control 773 * system. 774 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST 775 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST 776 * Is used to set/get a delay relative to now during which to allow unbound 777 * CPU performance. Units are seconds. 778 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE 779 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE 780 * Is used to override/get the actual power supply mode (AC/Battery). 781 * Possible IN/OUT values are: 782 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL 783 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC 784 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT 785 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO 786 * Is used to get the Ventura system information for VCT tool 787 * Returned 32bit value should be treated as bitmask and decoded in 788 * following way: 789 * Encoding details are defined in objgps.h refer to 790 * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. 791 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION 792 * Is used to get the supported sub-functions defined in SBIOS. Returned 793 * value is a bitmask where each bit corresponds to different function: 794 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT 795 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS 796 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS 797 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC 798 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC 799 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB 800 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS 801 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER 802 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA 803 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE 804 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG 805 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL 806 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN 807 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE 808 * Are used to retrieve appropriate power measurements and their derivatives 809 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 810 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 811 * index. 812 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS 813 * Is used to retrieve parameters when adjusting raw sensor power reading. 814 * The values may come from SBIOS, VBIOS, registry or driver default. 815 * Possible IN value is the index of interested parameter. 816 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP 817 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA 818 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE 819 * Are used to retrieve appropriate temperature measurements and their 820 * derivatives in [1/1000 Celsius]. 821 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE 822 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP 823 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN 824 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX 825 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 826 * Not applicable to _LOCALE_SYSTEM. 827 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION 828 * Is used to retrieve last GPS action for given domain. 829 * Not applicable to _LOCALE_SYSTEM. 830 * Possible return (OUT) values are: 831 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 832 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 833 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING 834 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT 835 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 836 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 837 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM 838 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM 839 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE 840 * Is used to set the power sensor simulator state. 841 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE 842 * Is used to get the power simulator sensor simulator state. 843 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA 844 * Is used to set power sensor simulator data 845 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA 846 * Is used to get power sensor simulator data 847 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK 848 * Is used to respond to the ACPI event triggered by SBIOS. RM will 849 * request value for budget and status, validate them, apply them 850 * and send ACK back to SBIOS. 851 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT 852 * Is a test cmd that should notify SBIOS to send ACPI event requesting 853 * budget and status change. 854 */ 855 #define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) 856 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) 857 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) 858 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) 859 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) 860 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) 861 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) 862 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) 863 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) 864 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) 865 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) 866 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) 867 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) 868 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) 869 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) 870 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) 871 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) 872 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) 873 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) 874 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) 875 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) 876 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) 877 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) 878 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) 879 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) 880 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 881 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 882 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 883 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 884 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) 885 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) 886 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) 887 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) 888 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) 889 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) 890 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) 891 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) 892 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) 893 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) 894 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) 895 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) 896 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) 897 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) 898 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) 899 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) 900 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 901 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) 902 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) 903 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) 904 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) 905 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 906 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 907 908 /* valid LOCALE values */ 909 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) 910 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) 911 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) 912 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) 913 914 /* valid data values for enums */ 915 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) 916 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) 917 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) 918 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) 919 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) 920 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) 921 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) 922 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) 923 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) 924 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 925 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) 926 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) 927 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 928 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 929 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) 930 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) 931 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 932 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 933 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 934 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) 935 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 936 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) 937 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) 938 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) 939 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) 940 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 941 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 942 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 943 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 944 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 945 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 946 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 947 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 948 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 949 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 950 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 951 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 952 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 953 954 /* 955 * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL 956 * 957 * This command allows execution of multiple GpsControl commands within one 958 * RmControl call. For practical reasons # of commands is limited to 16. 959 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. 960 * 961 * cmdCount 962 * Number of commands that should be executed. 963 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 964 * 965 * succeeded 966 * Number of commands that were succesully executed. 967 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 968 * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID 969 * in their data field. 970 * 971 * cmdData 972 * Array of commands with following structure: 973 * command 974 * This parameter specifies the command to execute. 975 * Invalid commands result in the return of an 976 * NV_ERR_INVALID_ARGUMENT status. 977 * locale 978 * This parameter indicates the specific locale to which 979 * the command 'command' is to be applied. 980 * Supported range of CPU/GPU {i = 0, ..., 255} 981 * data 982 * This parameter contains a command-specific data payload. 983 * It is used both to input data as well as to output data. 984 * 985 * Possible status values returned are: 986 * NV_OK 987 * NV_ERR_INVALID_REQUEST 988 * NV_ERR_NOT_SUPPORTED 989 */ 990 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 991 992 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) 993 #define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) 994 995 typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { 996 NvU32 cmdCount; 997 NvU32 succeeded; 998 999 struct { 1000 NvU16 command; 1001 NvU16 locale; 1002 NvU32 data; 1003 } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; 1004 } NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; 1005 1006 1007 /* 1008 * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. 1009 */ 1010 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 1011 1012 /* 1013 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of 1014 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues. 1015 * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups 1016 * allowed for batched P2P caps queries provided by the RM control 1017 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. 1018 */ 1019 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U 1020 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U 1021 #define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U 1022 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU 1023 1024 /* P2P capabilities status index values */ 1025 #define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U 1026 #define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U 1027 #define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U 1028 #define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U 1029 #define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U 1030 #define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U 1031 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U 1032 #define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U 1033 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U 1034 1035 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U 1036 1037 1038 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) 1039 1040 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { 1041 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1042 NvU32 gpuCount; 1043 NvU32 p2pCaps; 1044 NvU32 p2pOptimalReadCEs; 1045 NvU32 p2pOptimalWriteCEs; 1046 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1047 NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); 1048 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; 1049 1050 /* valid p2pCaps values */ 1051 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 1052 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) 1053 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) 1054 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 1055 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) 1056 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) 1057 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 1058 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) 1059 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) 1060 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 1061 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) 1062 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) 1063 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 1064 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1065 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1066 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 1067 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) 1068 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) 1069 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 1070 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) 1071 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) 1072 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 1073 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) 1074 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) 1075 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 1076 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) 1077 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) 1078 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 1079 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1080 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1081 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 1082 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) 1083 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) 1084 1085 1086 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 1087 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) 1088 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) 1089 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 1090 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) 1091 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) 1092 1093 /* P2P status codes */ 1094 #define NV0000_P2P_CAPS_STATUS_OK (0x00U) 1095 #define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) 1096 #define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) 1097 #define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) 1098 #define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) 1099 #define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) 1100 1101 /* 1102 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 1103 * 1104 * This command returns peer to peer capabilities present between GPUs. 1105 * Valid requests must present a list of GPU Ids. 1106 * 1107 * [in] gpuIds 1108 * This member contains the array of GPU IDs for which we query the P2P 1109 * capabilities. Valid entries are contiguous, beginning with the first 1110 * entry in the list. 1111 * [in] gpuCount 1112 * This member contains the number of GPU IDs stored in the gpuIds[] array. 1113 * [out] p2pCaps 1114 * This member returns the peer to peer capabilities discovered between the 1115 * GPUs. Valid p2pCaps values include: 1116 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1117 * When this bit is set, peer to peer writes between subdevices owned 1118 * by this device are supported. 1119 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1120 * When this bit is set, peer to peer reads between subdevices owned 1121 * by this device are supported. 1122 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1123 * When this bit is set, peer to peer PROP between subdevices owned 1124 * by this device are supported. This is enabled by default 1125 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1126 * When this bit is set, PCI is supported for all P2P between subdevices 1127 * owned by this device. 1128 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1129 * When this bit is set, NVLINK is supported for all P2P between subdevices 1130 * owned by this device. 1131 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1132 * When this bit is set, peer to peer atomics between subdevices owned 1133 * by this device are supported. 1134 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1135 * When this bit is set, peer to peer loopback is supported for subdevices 1136 * owned by this device. 1137 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1138 * When this bit is set, indirect peer to peer writes between subdevices 1139 * owned by this device are supported. 1140 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1141 * When this bit is set, indirect peer to peer reads between subdevices 1142 * owned by this device are supported. 1143 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1144 * When this bit is set, indirect peer to peer atomics between 1145 * subdevices owned by this device are supported. 1146 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1147 * When this bit is set, indirect NVLINK is supported for subdevices 1148 * owned by this device. 1149 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 1150 * When this bit is set, C2C P2P is supported between the GPUs 1151 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED 1152 * When this bit is set, BAR1 P2P is supported between the GPUs 1153 * mentioned in @ref gpuIds 1154 * [out] p2pOptimalReadCEs 1155 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1156 * [out] p2pOptimalWriteCEs 1157 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1158 * [out] p2pCapsStatus 1159 * This member returns status of all supported p2p capabilities. Valid 1160 * status values include: 1161 * NV0000_P2P_CAPS_STATUS_OK 1162 * P2P capability is supported. 1163 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 1164 * Chipset doesn't support p2p capability. 1165 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 1166 * GPU doesn't support p2p capability. 1167 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 1168 * IOH topology isn't supported. For e.g. root ports are on different 1169 * IOH. 1170 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 1171 * P2P Capability is disabled by a regkey. 1172 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 1173 * P2P Capability is not supported. 1174 * NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED 1175 * Indicates that NvLink P2P link setup failed. 1176 * [out] busPeerIds 1177 * Peer ID matrix. It is a one-dimentional array. 1178 * busPeerIds[X * gpuCount + Y] maps from index X to index Y in 1179 * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] 1180 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 1181 * 1182 * Possible status values returned are: 1183 * NV_OK 1184 * NV_ERR_INVALID_ARGUMENT 1185 * NV_ERR_INVALID_PARAM_STRUCT 1186 */ 1187 1188 1189 1190 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ 1191 1192 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) 1193 1194 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { 1195 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1196 NvU32 gpuCount; 1197 NvU32 p2pCaps; 1198 NvU32 p2pOptimalReadCEs; 1199 NvU32 p2pOptimalWriteCEs; 1200 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1201 NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; 1202 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; 1203 1204 /* 1205 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX 1206 * 1207 * This command returns peer to peer capabilities present between all pairs of 1208 * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to 1209 * collect all P2P capabilities in the system - see the SRT: 1210 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST 1211 * for a demonstration. 1212 * 1213 * The call will query for all pairs between set A and set B, and returns 1214 * results in both link directions. The results are two-dimensional arrays where 1215 * the first dimension is the index within the set-A array of one GPU ID under 1216 * consideration, and the second dimension is the index within the set-B array 1217 * of the other GPU ID under consideration. 1218 * 1219 * That is, the result arrays are *ALWAYS* to be indexed first with the set-A 1220 * index, then with the set-B index. The B-to-A direction of results are put in 1221 * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query 1222 * twice, since the usual use case requires both directions. 1223 * 1224 * If a set is being compared against itself (by setting grpBCount to 0), then 1225 * the result matrices are symmetric - it doesn't matter which index is first. 1226 * However, the choice of indices is effectively a choice of which ID is "B" and 1227 * which is "A" for the "a2b" and "b2a" directional results. 1228 * 1229 * [in] grpACount 1230 * This member contains the number of GPU IDs stored in the gpuIdGrpA[] 1231 * array. Must be >= 0. 1232 * [in] grpBCount 1233 * This member contains the number of GPU IDs stored in the gpuIdGrpB[] 1234 * array. Can be == 0 to specify a check of group A against itself. 1235 * [in] gpuIdGrpA 1236 * This member contains the array of GPU IDs in "group A", each of which 1237 * will have its P2P capabilities returned with respect to each GPU ID in 1238 * "group B". Valid entries are contiguous, beginning with the first entry 1239 * in the list. 1240 * [in] gpuIdGrpB 1241 * This member contains the array of GPU IDs in "group B", each of which 1242 * will have its P2P capabilities returned with respect to each GPU ID in 1243 * "group A". Valid entries are contiguous, beginning with the first entry 1244 * in the list. May be equal to gpuIdGrpA, but best performance requires 1245 * that the caller specifies grpBCount = 0 in this case, and ignores this. 1246 * [out] p2pCaps 1247 * This member returns the peer to peer capabilities discovered between the 1248 * pairs of input GPUs between the groups, indexed by [A_index][B_index]. 1249 * Valid p2pCaps values include: 1250 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1251 * When this bit is set, peer to peer writes between subdevices owned 1252 * by this device are supported. 1253 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1254 * When this bit is set, peer to peer reads between subdevices owned 1255 * by this device are supported. 1256 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1257 * When this bit is set, peer to peer PROP between subdevices owned 1258 * by this device are supported. This is enabled by default 1259 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1260 * When this bit is set, PCI is supported for all P2P between subdevices 1261 * owned by this device. 1262 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1263 * When this bit is set, NVLINK is supported for all P2P between subdevices 1264 * owned by this device. 1265 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1266 * When this bit is set, peer to peer atomics between subdevices owned 1267 * by this device are supported. 1268 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1269 * When this bit is set, peer to peer loopback is supported for subdevices 1270 * owned by this device. 1271 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1272 * When this bit is set, indirect peer to peer writes between subdevices 1273 * owned by this device are supported. 1274 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1275 * When this bit is set, indirect peer to peer reads between subdevices 1276 * owned by this device are supported. 1277 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1278 * When this bit is set, indirect peer to peer atomics between 1279 * subdevices owned by this device are supported. 1280 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1281 * When this bit is set, indirect NVLINK is supported for subdevices 1282 * owned by this device. 1283 * [out] a2bOptimalReadCes 1284 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1285 * in the A-to-B direction. 1286 * [out] a2bOptimalWriteCes 1287 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1288 * in the A-to-B direction. 1289 * [out] b2aOptimalReadCes 1290 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1291 * in the B-to-A direction. 1292 * [out] b2aOptimalWriteCes 1293 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1294 * in the B-to-A direction. 1295 * 1296 * Possible status values returned are: 1297 * NV_OK 1298 * NV_ERR_INVALID_ARGUMENT 1299 * NV_ERR_INVALID_PARAM_STRUCT 1300 */ 1301 1302 1303 1304 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ 1305 1306 typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1307 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) 1308 1309 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { 1310 NvU32 grpACount; 1311 NvU32 grpBCount; 1312 NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1313 NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1314 NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1315 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1316 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1317 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1318 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1319 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; 1320 1321 /* 1322 * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL 1323 * 1324 * This command is used to execute general GPS Functions, most dealing with 1325 * calling SBIOS, or retrieving cached sensor and GPS state data. 1326 * 1327 * version 1328 * This parameter specifies the version of the interface. Legal values 1329 * for this parameter are 1. 1330 * cmd 1331 * This parameter specifies the GPS API to be invoked. 1332 * Valid values for this parameter are: 1333 * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT 1334 * This command gets the temperature limit for thermal controller. When 1335 * this command is specified the input parameter contains ???. 1336 * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT 1337 * This command set the temperature limit for thermal controller. When 1338 * this command is specified the input parameter contains ???. 1339 * input 1340 * This parameter specifies the cmd-specific input value. 1341 * result 1342 * This parameter returns the cmd-specific output value. 1343 * 1344 * Possible status values returned are: 1345 * NV_OK 1346 * NV_ERR_INVALID_PARAM_STRUCT 1347 * NV_ERR_INVALID_ARGUMENT 1348 */ 1349 1350 #define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ 1351 1352 #define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) 1353 1354 typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { 1355 NvU32 cmd; 1356 NvS32 input[2]; 1357 NvS32 result[4]; 1358 } NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; 1359 1360 /* valid version values */ 1361 #define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 1362 1363 /* valid cmd values */ 1364 #define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 1365 #define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) 1366 #define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) 1367 #define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) 1368 #define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) 1369 #define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) 1370 1371 #define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 1372 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1373 #define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) 1374 1375 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 1376 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1377 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 1378 1379 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 1380 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1381 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 1382 1383 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 1384 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1385 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 1386 1387 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 1388 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1389 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 1390 1391 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 1392 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1393 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 1394 1395 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 1396 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1397 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 1398 1399 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 1400 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1401 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 1402 1403 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 1404 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1405 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 1406 1407 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 1408 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1409 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1410 1411 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 1412 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1413 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1414 1415 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 1416 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) 1417 1418 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 1419 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) 1420 1421 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 1422 #define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 1423 1424 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 1425 #define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 1426 1427 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 1428 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1429 #define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 1430 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) 1431 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 1432 1433 #define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) 1434 #define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) 1435 #define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) 1436 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) 1437 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) 1438 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 1439 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 1440 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 1441 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) 1442 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 1443 1444 #define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 1445 #define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) 1446 1447 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 1448 #define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) 1449 1450 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 1451 #define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) 1452 1453 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 1454 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) 1455 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 1456 1457 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 1458 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) 1459 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 1460 1461 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 1462 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1463 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1464 1465 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 1466 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1467 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1468 1469 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 1470 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1471 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1472 1473 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 1474 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1475 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1476 1477 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 1478 #define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) 1479 1480 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 1481 #define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) 1482 1483 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 1484 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1485 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 1486 1487 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 1488 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1489 1490 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 1491 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1492 1493 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 1494 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1495 1496 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) 1497 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) 1498 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 1499 1500 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) 1501 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) 1502 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 1503 1504 #define NV0000_CTRL_GPS_PPM_INDEX 7:0 1505 #define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) 1506 #define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) 1507 #define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) 1508 #define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) 1509 #define NV0000_CTRL_GPS_PPM_MASK 15:8 1510 #define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) 1511 1512 /* valid PS_STATUS result values */ 1513 #define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) 1514 #define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) 1515 1516 1517 /* 1518 * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS 1519 * 1520 * This command allows privileged users to update the values of 1521 * security settings governing RM behavior. 1522 * 1523 * Possible status values returned are: 1524 * NV_OK 1525 * NV_ERR_INVALID_ARGUMENT, 1526 * NV_ERR_INVALID_OBJECT_HANDLE 1527 * NV_ERR_NOT_SUPPORTED 1528 * NV_ERR_INSUFFICIENT_PERMISSIONS 1529 * 1530 * Please note: as implied above, administrator privileges are 1531 * required to modify security settings. 1532 */ 1533 #define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */ 1534 1535 #define GPS_MAX_COUNTERS_PER_BLOCK 32U 1536 #define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U) 1537 1538 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { 1539 NvU32 objHndl; 1540 NvU32 blockId; 1541 NvU32 nextExpectedSampleTimems; 1542 NvU32 countersReq; 1543 NvU32 countersReturned; 1544 NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; 1545 } NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; 1546 1547 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 1548 1549 #define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2CU) 1550 1551 typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS; 1552 1553 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 1554 1555 #define NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2EU) 1556 1557 typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS; 1558 1559 /* 1560 * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI 1561 * 1562 * This command allows users to call GPS ACPI commands for testing purposes. 1563 * 1564 * cmd 1565 * This parameter specifies the GPS ACPI command to execute. 1566 * 1567 * input 1568 * This parameter specified the cmd-dependent input value. 1569 * 1570 * resultSz 1571 * This parameter returns the size (in bytes) of the valid data 1572 * returned in the result parameter. 1573 * 1574 * result 1575 * This parameter returns the results of the specified cmd. 1576 * The maximum size (in bytes) of this returned data will 1577 * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1578 * 1579 * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1580 * The size of buffer (result) in unit of NvU32. 1581 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 1582 * Since the prior one is 24 bytes, and the later one is 48, 1583 * this value cannot be smaller than 288. 1584 * 1585 * Possible status values returned are: 1586 * NV_OK 1587 * NV_ERR_INVALID_ARGUMENT, 1588 * NV_ERR_INVALID_OBJECT_HANDLE 1589 * NV_ERR_NOT_SUPPORTED 1590 * NV_ERR_INSUFFICIENT_PERMISSIONS 1591 * 1592 */ 1593 #define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 1594 #define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) 1595 1596 typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { 1597 NvU32 cmd; 1598 NvU32 input; 1599 NvU32 resultSz; 1600 NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 1601 } NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; 1602 1603 #define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ 1604 1605 /* 1606 * NV0000_CTRL_SYSTEM_PARAM_* 1607 * 1608 * The following is a list of system-level parameters (often sensors) that the 1609 * driver can be made aware of. They are primarily intended to be used by system 1610 * power-balancing algorithms that require system-wide visibility in order to 1611 * function. The names and values used here are established and specified in 1612 * several different NVIDIA documents that are made externally available. Thus, 1613 * updates to this list must be made with great caution. The only permissible 1614 * change is to append new parameters. Reordering is strictly prohibited. 1615 * 1616 * Brief Parameter Summary: 1617 * TGPU - GPU temperature (NvTemp) 1618 * PDTS - CPU package temperature (NvTemp) 1619 * SFAN - System fan speed (% of maximum fan speed) 1620 * SKNT - Skin temperature (NvTemp) 1621 * CPUE - CPU energy counter (NvU32) 1622 * TMP1 - Additional temperature sensor 1 (NvTemp) 1623 * TMP2 - Additional temperature sensor 2 (NvTemp) 1624 * CTGP - Mode 2 power limit offset (NvU32) 1625 * PPMD - Power mode data (NvU32) 1626 */ 1627 #define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) 1628 #define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) 1629 #define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) 1630 #define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) 1631 #define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) 1632 #define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) 1633 #define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) 1634 #define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) 1635 #define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) 1636 #define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) 1637 1638 /* 1639 * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD 1640 * 1641 * This command is used to execute general ACPI methods. 1642 * 1643 * method 1644 * This parameter identifies the MXM ACPI API to be invoked. 1645 * Valid values for this parameter are: 1646 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS 1647 * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS 1648 * API is to be invoked. 1649 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG 1650 * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG 1651 * API is to be invoked. This API will set a Flag in sbios to Indicate 1652 * that HD Audio Controller is disable/Enabled from GPU Config space. 1653 * This flag will be used by sbios to restore Audio state after resuming 1654 * from s3/s4. 1655 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS 1656 * This value specifies that the DSM JT subfunction FUNC_CAPS is to 1657 * to be invoked to get the SBIOS capabilities 1658 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY 1659 * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is 1660 * to be invoked to set and get the various platform policies for JT. 1661 * Refer to the JT spec in more detail on various policies. 1662 * inData 1663 * This parameter specifies the method-specific input buffer. Data is 1664 * passed to the specified API using this buffer. 1665 * inDataSize 1666 * This parameter specifies the size of the inData buffer in bytes. 1667 * outStatus 1668 * This parameter returns the status code from the associated ACPI call. 1669 * outData 1670 * This parameter specifies the method-specific output buffer. Data 1671 * is returned by the specified API using this buffer. 1672 * outDataSize 1673 * This parameter specifies the size of the outData buffer in bytes. 1674 * 1675 * Possible status values returned are: 1676 * NV_OK 1677 * NV_ERR_INVALID_PARAM_STRUCT 1678 * NV_ERR_INVALID_ARGUMENT 1679 */ 1680 1681 #define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ 1682 1683 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) 1684 1685 typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { 1686 NvU32 method; 1687 NV_DECLARE_ALIGNED(NvP64 inData, 8); 1688 NvU16 inDataSize; 1689 NvU32 outStatus; 1690 NV_DECLARE_ALIGNED(NvP64 outData, 8); 1691 NvU16 outDataSize; 1692 } NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; 1693 1694 /* valid method parameter values */ 1695 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) 1696 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) 1697 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) 1698 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) 1699 /* 1700 * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS 1701 * 1702 * This command can be used to instruct the RM to enable/disable specific module 1703 * of ETW events. 1704 * 1705 * moduleMask 1706 * This parameter specifies the module of events we would like to 1707 * enable/disable. 1708 * 1709 * Possible status values returned are: 1710 * NV_OK 1711 */ 1712 #define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ 1713 1714 #define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) 1715 1716 typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { 1717 NvU32 moduleMask; 1718 } NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; 1719 1720 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) 1721 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) 1722 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) 1723 1724 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) 1725 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) 1726 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) 1727 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) 1728 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) 1729 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) 1730 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) 1731 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) 1732 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) 1733 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) 1734 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) 1735 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) 1736 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) 1737 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) 1738 1739 /* 1740 * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA 1741 * 1742 * This command is used to read FRL data based on need. 1743 * 1744 * nextSampleNumber 1745 * This parameter returns the counter of next sample which is being filled. 1746 * samples 1747 * This parameter returns the frame time, render time, target time, client ID 1748 * with one reserve bit for future use. 1749 * 1750 * Possible status values returned are: 1751 * NV_OK 1752 * NV_ERR_NOT_SUPPORTED 1753 */ 1754 1755 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1756 1757 #define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U 1758 1759 typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { 1760 NvU16 frameTime; 1761 NvU16 renderTime; 1762 NvU16 targetTime; 1763 NvU8 sleepTime; 1764 NvU8 sampleNumber; 1765 } NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; 1766 1767 #define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) 1768 1769 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { 1770 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; 1771 NvU8 nextSampleNumber; 1772 } NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; 1773 1774 /* 1775 * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA 1776 * 1777 * This command is used to write FRM data based on need. 1778 * 1779 * frameTime 1780 * This parameter contains the frame time of current frame. 1781 * renderTime 1782 * This parameter contains the render time of current frame. 1783 * targetTime 1784 * This parameter contains the target time of current frame. 1785 * sleepTime 1786 * This parameter contains the sleep duration inserted by FRL for the latest frame. 1787 * 1788 * Possible status values returned are: 1789 * NV_OK 1790 * NV_ERR_NOT_SUPPORTED 1791 */ 1792 1793 #define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1794 1795 #define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) 1796 1797 typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { 1798 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; 1799 } NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; 1800 1801 /* 1802 * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO 1803 * 1804 * This command returns the current host driver, host OS and 1805 * plugin information. It is only valid when VGX is setup. 1806 * szHostDriverVersionBuffer 1807 * This field returns the host driver version (NV_VERSION_STRING). 1808 * szHostVersionBuffer 1809 * This field returns the host driver version (NV_BUILD_BRANCH_VERSION). 1810 * szHostTitleBuffer 1811 * This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE). 1812 * szPluginTitleBuffer 1813 * This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE). 1814 * szHostUnameBuffer 1815 * This field returns the call of 'uname' on the host OS. 1816 * iHostChangelistNumber 1817 * This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM). 1818 * iPluginChangelistNumber 1819 * This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM). 1820 * 1821 * Possible status values returned are: 1822 * NV_OK 1823 * NV_ERR_INVALID_PARAM_STRUCT 1824 */ 1825 1826 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U 1827 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ 1828 1829 #define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) 1830 1831 typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { 1832 char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1833 char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1834 char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1835 char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1836 char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1837 NvU32 iHostChangelistNumber; 1838 NvU32 iPluginChangelistNumber; 1839 } NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; 1840 1841 /* 1842 * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS 1843 * 1844 * This command returns the power status of the GPUs in the system, successfully attached or not because of 1845 * insufficient power. It is supported on Kepler and up only. 1846 * gpuCount 1847 * This field returns the count into the following arrays. 1848 * busNumber 1849 * This field returns the busNumber of a GPU. 1850 * gpuExternalPowerStatus 1851 * This field returns the corresponding external power status: 1852 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 1853 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1854 * 1855 * Possible status values returned are: 1856 * NV_OK 1857 * NV_ERR_INVALID_PARAM_STRUCT 1858 * NV_ERR_NOT_SUPPORTED 1859 */ 1860 1861 #define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ 1862 1863 #define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) 1864 1865 typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { 1866 NvU8 gpuCount; 1867 NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1868 NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1869 } NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; 1870 1871 /* Valid gpuExternalPowerStatus values */ 1872 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U 1873 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U 1874 1875 /* 1876 * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS 1877 * 1878 * This command returns the caller's API access privileges using 1879 * this client handle. 1880 * 1881 * privStatus 1882 * This parameter returns a mask of possible access privileges: 1883 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG 1884 * The caller is running with elevated privileges 1885 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG 1886 * Client is of NV01_ROOT class. 1887 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG 1888 * Client has PRIV bit set. 1889 * 1890 * Possible status values returned are: 1891 * NV_OK 1892 * NV_ERR_INVALID_PARAM_STRUCT 1893 */ 1894 1895 1896 #define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ 1897 1898 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) 1899 1900 typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { 1901 NvU8 privStatusFlags; 1902 } NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS; 1903 1904 1905 /* Valid privStatus values */ 1906 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) 1907 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) 1908 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) 1909 1910 /* 1911 * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS 1912 * 1913 * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to 1914 * peer (P2P) use or still initializing the fabric. This command allows clients 1915 * to query fabric status to allow P2P operations. 1916 * 1917 * Note, on systems where FM isn't used, RM just returns _SKIP. 1918 * 1919 * fabricStatus 1920 * This parameter returns current fabric status: 1921 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP 1922 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED 1923 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS 1924 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED 1925 * 1926 * Possible status values returned are: 1927 * NV_OK 1928 * NV_ERR_INVALID_ARGUMENT 1929 * NV_ERR_INVALID_OBJECT_HANDLE 1930 * NV_ERR_NOT_SUPPORTED 1931 * NV_ERR_INSUFFICIENT_PERMISSIONS 1932 * NV_ERR_INVALID_PARAM_STRUCT 1933 */ 1934 1935 typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { 1936 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1, 1937 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2, 1938 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3, 1939 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, 1940 } NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; 1941 1942 #define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ 1943 1944 #define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) 1945 1946 typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { 1947 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; 1948 } NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; 1949 1950 /* 1951 * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO 1952 * 1953 * This command is used to query the range of VGX version supported. 1954 * 1955 * host_min_supported_version 1956 * The minimum vGPU version supported by host driver 1957 * host_max_supported_version 1958 * The maximum vGPU version supported by host driver 1959 * user_min_supported_version 1960 * The minimum vGPU version set by user for vGPU support 1961 * user_max_supported_version 1962 * The maximum vGPU version set by user for vGPU support 1963 * 1964 * Possible status values returned are: 1965 * NV_OK 1966 * NV_ERR_INVALID_REQUEST 1967 */ 1968 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 1969 1970 /* 1971 * NV0000_CTRL_VGPU_GET_VGPU_VERSION 1972 */ 1973 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) 1974 1975 typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { 1976 NvU32 host_min_supported_version; 1977 NvU32 host_max_supported_version; 1978 NvU32 user_min_supported_version; 1979 NvU32 user_max_supported_version; 1980 } NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; 1981 1982 /* 1983 * NV0000_CTRL_VGPU_SET_VGPU_VERSION 1984 * 1985 * This command is used to query whether pGPU is live migration capable or not. 1986 * 1987 * min_version 1988 * The minimum vGPU version to be supported being set 1989 * max_version 1990 * The maximum vGPU version to be supported being set 1991 * 1992 * Possible status values returned are: 1993 * NV_OK 1994 * NV_ERR_INVALID_REQUEST 1995 */ 1996 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 1997 1998 /* 1999 * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS 2000 */ 2001 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) 2002 2003 typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { 2004 NvU32 min_version; 2005 NvU32 max_version; 2006 } NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; 2007 2008 /* 2009 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID 2010 * 2011 * This command is used to get a unique identifier for the instance of RM. 2012 * The returned value will only change when the driver is reloaded. A previous 2013 * value will never be reused on a given machine. 2014 * 2015 * rm_instance_id; 2016 * The instance ID of the current RM instance 2017 * 2018 * Possible status values returned are: 2019 * NV_OK 2020 */ 2021 #define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ 2022 2023 /* 2024 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS 2025 */ 2026 #define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U) 2027 2028 typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { 2029 NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); 2030 } NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; 2031 2032 /* 2033 * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO 2034 * 2035 * This API is used to get the TPP(total processing power) and 2036 * the rated TGP(total GPU power) from SBIOS. 2037 * 2038 * NVPCF is an acronym for Nvidia Platform Controllers and Framework 2039 * which implements platform level policies. NVPCF is implemented in 2040 * a kernel driver on windows. It is implemented in a user mode app 2041 * called nvidia-powerd on Linux. 2042 * 2043 * Valid subFunc ids for NVPCF 1x include : 2044 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED 2045 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS 2046 * 2047 * Valid subFunc ids for NVPCF 2x include : 2048 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED 2049 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS 2050 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES 2051 * 2052 * Possible status values returned are: 2053 * NV_OK 2054 * NV_ERR_INVALID_REQUEST 2055 * NV_ERR_NOT_SUPPORTED 2056 */ 2057 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ 2058 2059 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) 2060 2061 typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { 2062 /* GPU ID */ 2063 NvU32 gpuId; 2064 2065 /* Total processing power including CPU and GPU */ 2066 NvU32 tpp; 2067 2068 /* Rated total GPU Power */ 2069 NvU32 ratedTgp; 2070 2071 /* NVPCF subfunction id */ 2072 NvU32 subFunc; 2073 2074 /* Configurable TGP offset, in mW */ 2075 NvU32 ctgpOffsetmW; 2076 2077 /* TPP, as offset in mW */ 2078 NvU32 targetTppOffsetmW; 2079 2080 /* Maximum allowed output, as offset in mW */ 2081 NvU32 maxOutputOffsetmW; 2082 2083 /* Minimum allowed output, as offset in mW */ 2084 NvU32 minOutputOffsetmW; 2085 2086 /* The System Controller Table Version */ 2087 NvU8 version; 2088 2089 /* Base sampling period */ 2090 NvU16 samplingPeriodmS; 2091 2092 /* Sampling Multiplier */ 2093 NvU16 samplingMulti; 2094 2095 /* Fitler function type */ 2096 NvU8 filterType; 2097 2098 union { 2099 2100 /* weight */ 2101 NvU8 weight; 2102 2103 /* windowSize */ 2104 NvU8 windowSize; 2105 } filterParam; 2106 2107 /* Reserved */ 2108 NvU16 filterReserved; 2109 2110 /* Controller Type Dynamic Boost Controller */ 2111 NvBool bIsBoostController; 2112 2113 /* Increase power limit ratio */ 2114 NvU16 incRatio; 2115 2116 /* Decrease power limit ratio */ 2117 NvU16 decRatio; 2118 2119 /* Dynamic Boost Controller DC Support */ 2120 NvBool bSupportBatt; 2121 2122 /* CPU type(Intel/AMD) */ 2123 NvU8 cpuType; 2124 2125 /* GPU type(Nvidia) */ 2126 NvU8 gpuType; 2127 } NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; 2128 2129 /* Define the filter types */ 2130 #define CONTROLLER_FILTER_TYPE_EMWA 0U 2131 #define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U 2132 2133 /* Valid NVPCF subfunction case */ 2134 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U 2135 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE 1U 2136 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U 2137 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U 2138 2139 /* NVPCF subfunction to get the static data tables */ 2140 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE 4U 2141 2142 /* Valid NVPCF subfunction ids */ 2143 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) 2144 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2145 2146 /* 2147 * Defines for get supported sub functions bit fields 2148 */ 2149 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 2150 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 2151 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 2152 2153 /*! 2154 * Config DSM 2x version specific defines 2155 */ 2156 #define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) 2157 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) 2158 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES (0x00000001) 2159 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2160 2161 /*! 2162 * Defines the max buffer size for config 2163 */ 2164 #define NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX (255) 2165 2166 /* 2167 * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT 2168 * 2169 * This API is used to sync the external fabric management status with 2170 * GSP-RM 2171 * 2172 * bExternalFabricMgmt 2173 * Whether fabric is externally managed 2174 * 2175 * Possible status values returned are: 2176 * NV_OK 2177 */ 2178 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ 2179 2180 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) 2181 2182 typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { 2183 NvBool bExternalFabricMgmt; 2184 } NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS; 2185 2186 /* 2187 * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO 2188 * 2189 * This API is used to get information about the RM client 2190 * database. 2191 * 2192 * clientCount [OUT] 2193 * This field indicates the number of clients currently allocated. 2194 * 2195 * resourceCount [OUT] 2196 * This field indicates the number of resources currently allocated 2197 * across all clients. 2198 * 2199 */ 2200 #define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ 2201 2202 #define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) 2203 2204 typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { 2205 NvU32 clientCount; 2206 NV_DECLARE_ALIGNED(NvU64 resourceCount, 8); 2207 } NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS; 2208 2209 /* 2210 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 2211 * 2212 * This command returns the current driver information in 2213 * statically sized character arrays. 2214 * 2215 * driverVersionBuffer 2216 * This field returns the version (NV_VERSION_STRING). 2217 * versionBuffer 2218 * This field returns the version (NV_BUILD_BRANCH_VERSION). 2219 * titleBuffer 2220 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 2221 * changelistNumber 2222 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 2223 * officialChangelistNumber 2224 * This field returns the last official changelist value 2225 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 2226 * 2227 * Possible status values returned are: 2228 * NV_OK 2229 */ 2230 2231 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U 2232 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ 2233 2234 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) 2235 2236 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { 2237 char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2238 char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2239 char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2240 NvU32 changelistNumber; 2241 NvU32 officialChangelistNumber; 2242 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; 2243 2244 /* 2245 * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL 2246 * 2247 * This API is used to get/set RMCTRL cache mode 2248 * 2249 * cmd [IN] 2250 * GET - Gets RMCTRL cache mode 2251 * SET - Sets RMCTRL cache mode 2252 * 2253 * mode [IN/OUT] 2254 * On GET, this field is the output of current RMCTRL cache mode 2255 * On SET, this field indicates the mode to set RMCTRL cache to 2256 * Valid values for this parameter are: 2257 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE 2258 * No get/set action to cache. 2259 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE 2260 * Try to get from cache at the beginning of the control. 2261 * Set cache after control finished if the control has not been cached. 2262 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY 2263 * Do not get from cache. Set cache when control call finished. 2264 * When setting the cache, verify the value in the cache is the same 2265 * with the current control value if the control is already cached. 2266 * 2267 * Possible status values returned are: 2268 * NV_OK 2269 * NV_ERR_INVALID_ARGUMENT 2270 */ 2271 #define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ 2272 2273 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) 2274 2275 typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { 2276 NvU32 cmd; 2277 NvU32 mode; 2278 } NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; 2279 2280 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) 2281 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) 2282 2283 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) 2284 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) 2285 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) 2286 2287 /* 2288 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL 2289 * 2290 * This command is used to control PFM_REQ_HNDLR functionality. It allows control of 2291 * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read 2292 * most PFM_REQ_HNDLR dynamic parameters. 2293 * 2294 * command 2295 * This parameter specifies the command to execute. Invalid commands 2296 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 2297 * locale 2298 * This parameter indicates the specific locale to which the command 2299 * 'command' is to be applied. 2300 * Supported range of CPU/GPU {i = 0, ..., 255} 2301 * data 2302 * This parameter contains a command-specific data payload. It can 2303 * be used to input data as well as output data. 2304 * 2305 * Possible status values returned are: 2306 * NV_OK 2307 * NV_ERR_INVALID_COMMAND 2308 * NV_ERR_INVALID_STATE 2309 * NV_ERR_INVALID_DATA 2310 * NV_ERR_INVALID_REQUEST 2311 * NV_ERR_NOT_SUPPORTED 2312 */ 2313 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ 2314 2315 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) 2316 2317 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { 2318 NvU16 command; 2319 NvU16 locale; 2320 NvU32 data; 2321 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; 2322 2323 /* 2324 * Valid command values : 2325 * 2326 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT 2327 * Is used to check if PFM_REQ_HNDLR was correctly initialized. 2328 * Possible return (OUT) values are: 2329 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO 2330 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES 2331 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC 2332 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC 2333 * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. 2334 * Possible IN/OUT values are: 2335 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP 2336 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START 2337 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS 2338 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS 2339 * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. 2340 * Possible IN/OUT values are: 2341 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF 2342 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON 2343 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC 2344 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC 2345 * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. 2346 * Possible IN/OUT values are: 2347 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF 2348 * Will cause that all PFM_REQ_HNDLR actions will be NULL. 2349 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY 2350 * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. 2351 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC 2352 * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. 2353 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE 2354 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE 2355 * Are used to set/retrieve system control preference. 2356 * Possible IN/OUT values are: 2357 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU 2358 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU 2359 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH 2360 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT 2361 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT 2362 * Are used to set/retrieve GPU2CPU pstate limits. 2363 * IN/OUT values are four bytes packed into a 32-bit data field. 2364 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 2365 * index for the GPU pstate 3 is in the highest byte, etc. One 2366 * special value is to disable the override to the GPU2CPU map: 2367 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE 2368 * Is used to stop/start PFM_REQ_HNDLR PMU functionality. 2369 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE 2370 * Is used to get the current status of PMU PFM_REQ_HNDLR. 2371 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE 2372 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER 2373 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER 2374 * Are used to set/retrieve max power [mW] that system can provide. 2375 * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply 2376 * to this threshold. 2377 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET 2378 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET 2379 * Are used to set/retrieve current system cooling budget [mW]. 2380 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD 2381 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD 2382 * Are used to set/retrieve integration interval [sec]. 2383 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET 2384 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET 2385 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT 2386 * Are used to set/retrieve used ruleset [#]. Value is checked 2387 * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT 2388 * provides a way to find out how many rules exist for the current control 2389 * system. 2390 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST 2391 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST 2392 * Is used to set/get a delay relative to now during which to allow unbound 2393 * CPU performance. Units are seconds. 2394 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE 2395 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE 2396 * Is used to override/get the actual power supply mode (AC/Battery). 2397 * Possible IN/OUT values are: 2398 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL 2399 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC 2400 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT 2401 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO 2402 * Is used to get the Ventura system information for VCT tool 2403 * Returned 32bit value should be treated as bitmask and decoded in 2404 * following way: 2405 * Encoding details are defined in objPFM_REQ_HNDLR.h refer to 2406 * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. 2407 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION 2408 * Is used to get the supported sub-functions defined in SBIOS. Returned 2409 * value is a bitmask where each bit corresponds to different function: 2410 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT 2411 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS 2412 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS 2413 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC 2414 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC 2415 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB 2416 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS 2417 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER 2418 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA 2419 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE 2420 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG 2421 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL 2422 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN 2423 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE 2424 * Are used to retrieve appropriate power measurements and their derivatives 2425 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 2426 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 2427 * index. 2428 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS 2429 * Is used to retrieve parameters when adjusting raw sensor power reading. 2430 * The values may come from SBIOS, VBIOS, registry or driver default. 2431 * Possible IN value is the index of interested parameter. 2432 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP 2433 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA 2434 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE 2435 * Are used to retrieve appropriate temperature measurements and their 2436 * derivatives in [1/1000 Celsius]. 2437 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE 2438 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP 2439 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN 2440 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX 2441 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 2442 * Not applicable to _LOCALE_SYSTEM. 2443 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION 2444 * Is used to retrieve last PFM_REQ_HNDLR action for given domain. 2445 * Not applicable to _LOCALE_SYSTEM. 2446 * Possible return (OUT) values are: 2447 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 2448 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 2449 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING 2450 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT 2451 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 2452 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 2453 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM 2454 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM 2455 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE 2456 * Is used to set the power sensor simulator state. 2457 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE 2458 * Is used to get the power simulator sensor simulator state. 2459 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA 2460 * Is used to set power sensor simulator data 2461 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA 2462 * Is used to get power sensor simulator data 2463 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK 2464 * Is used to respond to the ACPI event triggered by SBIOS. RM will 2465 * request value for budget and status, validate them, apply them 2466 * and send ACK back to SBIOS. 2467 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT 2468 * Is a test cmd that should notify SBIOS to send ACPI event requesting 2469 * budget and status change. 2470 */ 2471 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) 2472 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) 2473 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) 2474 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) 2475 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) 2476 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) 2477 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) 2478 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) 2479 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) 2480 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) 2481 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) 2482 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) 2483 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) 2484 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) 2485 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) 2486 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) 2487 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) 2488 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) 2489 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) 2490 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) 2491 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) 2492 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) 2493 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) 2494 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) 2495 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) 2496 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 2497 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 2498 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 2499 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 2500 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) 2501 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) 2502 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) 2503 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) 2504 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) 2505 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) 2506 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) 2507 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) 2508 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) 2509 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) 2510 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) 2511 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) 2512 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) 2513 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) 2514 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) 2515 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) 2516 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 2517 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) 2518 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) 2519 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) 2520 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) 2521 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 2522 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 2523 2524 /* valid LOCALE values */ 2525 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) 2526 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) 2527 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) 2528 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) 2529 2530 /* valid data values for enums */ 2531 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) 2532 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) 2533 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) 2534 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) 2535 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) 2536 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) 2537 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) 2538 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) 2539 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) 2540 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 2541 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) 2542 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) 2543 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 2544 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 2545 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) 2546 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) 2547 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 2548 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 2549 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 2550 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) 2551 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 2552 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) 2553 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) 2554 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) 2555 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) 2556 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 2557 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 2558 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 2559 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 2560 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 2561 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 2562 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 2563 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 2564 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 2565 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 2566 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 2567 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 2568 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 2569 2570 /* 2571 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL 2572 * 2573 * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one 2574 * RmControl call. For practical reasons # of commands is limited to 16. 2575 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. 2576 * 2577 * cmdCount 2578 * Number of commands that should be executed. 2579 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2580 * 2581 * succeeded 2582 * Number of commands that were succesully executed. 2583 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2584 * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID 2585 * in their data field. 2586 * 2587 * cmdData 2588 * Array of commands with following structure: 2589 * command 2590 * This parameter specifies the command to execute. 2591 * Invalid commands result in the return of an 2592 * NV_ERR_INVALID_ARGUMENT status. 2593 * locale 2594 * This parameter indicates the specific locale to which 2595 * the command 'command' is to be applied. 2596 * Supported range of CPU/GPU {i = 0, ..., 255} 2597 * data 2598 * This parameter contains a command-specific data payload. 2599 * It is used both to input data as well as to output data. 2600 * 2601 * Possible status values returned are: 2602 * NV_OK 2603 * NV_ERR_INVALID_REQUEST 2604 * NV_ERR_NOT_SUPPORTED 2605 */ 2606 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 2607 2608 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) 2609 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) 2610 2611 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { 2612 NvU32 cmdCount; 2613 NvU32 succeeded; 2614 2615 struct { 2616 NvU16 command; 2617 NvU16 locale; 2618 NvU32 data; 2619 } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; 2620 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; 2621 2622 /* 2623 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL 2624 * 2625 * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with 2626 * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. 2627 * 2628 * version 2629 * This parameter specifies the version of the interface. Legal values 2630 * for this parameter are 1. 2631 * cmd 2632 * This parameter specifies the PFM_REQ_HNDLR API to be invoked. 2633 * Valid values for this parameter are: 2634 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT 2635 * This command gets the temperature limit for thermal controller. When 2636 * this command is specified the input parameter contains ???. 2637 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT 2638 * This command set the temperature limit for thermal controller. When 2639 * this command is specified the input parameter contains ???. 2640 * input 2641 * This parameter specifies the cmd-specific input value. 2642 * result 2643 * This parameter returns the cmd-specific output value. 2644 * 2645 * Possible status values returned are: 2646 * NV_OK 2647 * NV_ERR_INVALID_PARAM_STRUCT 2648 * NV_ERR_INVALID_ARGUMENT 2649 */ 2650 2651 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ 2652 2653 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) 2654 2655 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { 2656 NvU32 cmd; 2657 NvS32 input[2]; 2658 NvS32 result[4]; 2659 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; 2660 2661 /* valid version values */ 2662 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 2663 2664 /* valid cmd values */ 2665 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 2666 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) 2667 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) 2668 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) 2669 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) 2670 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) 2671 2672 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 2673 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2674 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) 2675 2676 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 2677 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2678 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 2679 2680 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 2681 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2682 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 2683 2684 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 2685 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2686 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 2687 2688 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 2689 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2690 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 2691 2692 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 2693 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2694 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 2695 2696 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 2697 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2698 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 2699 2700 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 2701 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2702 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 2703 2704 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 2705 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2706 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 2707 2708 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 2709 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2710 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2711 2712 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 2713 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2714 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2715 2716 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 2717 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) 2718 2719 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 2720 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) 2721 2722 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 2723 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 2724 2725 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 2726 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 2727 2728 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 2729 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2730 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 2731 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) 2732 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 2733 2734 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) 2735 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) 2736 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) 2737 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) 2738 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) 2739 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 2740 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 2741 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 2742 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) 2743 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 2744 2745 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 2746 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) 2747 2748 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 2749 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) 2750 2751 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 2752 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) 2753 2754 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 2755 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) 2756 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 2757 2758 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 2759 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) 2760 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 2761 2762 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 2763 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2764 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2765 2766 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 2767 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2768 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2769 2770 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 2771 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2772 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2773 2774 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 2775 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2776 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2777 2778 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 2779 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) 2780 2781 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 2782 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) 2783 2784 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 2785 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2786 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 2787 2788 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 2789 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2790 2791 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 2792 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2793 2794 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 2795 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2796 2797 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) 2798 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) 2799 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 2800 2801 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) 2802 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) 2803 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 2804 2805 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 2806 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) 2807 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) 2808 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) 2809 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) 2810 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 2811 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) 2812 2813 /* valid PS_STATUS result values */ 2814 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) 2815 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) 2816 2817 #define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U 2818 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { 2819 NvU32 objHndl; 2820 NvU32 blockId; 2821 NvU32 nextExpectedSampleTimems; 2822 NvU32 countersReq; 2823 NvU32 countersReturned; 2824 NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; 2825 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; 2826 2827 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 2828 2829 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x46U) 2830 2831 typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS; 2832 2833 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 2834 2835 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x47U) 2836 2837 typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS; 2838 2839 /* 2840 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI 2841 * 2842 * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. 2843 * 2844 * cmd 2845 * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. 2846 * 2847 * input 2848 * This parameter specified the cmd-dependent input value. 2849 * 2850 * resultSz 2851 * This parameter returns the size (in bytes) of the valid data 2852 * returned in the result parameter. 2853 * 2854 * result 2855 * This parameter returns the results of the specified cmd. 2856 * The maximum size (in bytes) of this returned data will 2857 * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 2858 * 2859 * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 2860 * The size of buffer (result) in unit of NvU32. 2861 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 2862 * Since the prior one is 24 bytes, and the later one is 48, 2863 * this value cannot be smaller than 288. 2864 * 2865 * Possible status values returned are: 2866 * NV_OK 2867 * NV_ERR_INVALID_ARGUMENT, 2868 * NV_ERR_INVALID_OBJECT_HANDLE 2869 * NV_ERR_NOT_SUPPORTED 2870 * NV_ERR_INSUFFICIENT_PERMISSIONS 2871 * 2872 */ 2873 #define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 2874 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) 2875 2876 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { 2877 NvU32 cmd; 2878 NvU32 input; 2879 NvU32 resultSz; 2880 NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 2881 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; 2882 2883 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ 2884 2885 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) 2886 2887 /* 2888 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA 2889 * 2890 * This command is used to read FRL data based on need. 2891 * 2892 * nextSampleNumber 2893 * This parameter returns the counter of next sample which is being filled. 2894 * samples 2895 * This parameter returns the frame time, render time, target time, client ID 2896 * with one reserve bit for future use. 2897 * 2898 * Possible status values returned are: 2899 * NV_OK 2900 * NV_ERR_NOT_SUPPORTED 2901 */ 2902 2903 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 2904 2905 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U 2906 2907 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { 2908 NvU16 frameTime; 2909 NvU16 renderTime; 2910 NvU16 targetTime; 2911 NvU8 sleepTime; 2912 NvU8 sampleNumber; 2913 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; 2914 2915 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) 2916 2917 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { 2918 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; 2919 NvU8 nextSampleNumber; 2920 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; 2921 2922 /* 2923 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA 2924 * 2925 * This command is used to write FRM data based on need. 2926 * 2927 * frameTime 2928 * This parameter contains the frame time of current frame. 2929 * renderTime 2930 * This parameter contains the render time of current frame. 2931 * targetTime 2932 * This parameter contains the target time of current frame. 2933 * sleepTime 2934 * This parameter contains the sleep duration inserted by FRL for the latest frame. 2935 * 2936 * Possible status values returned are: 2937 * NV_OK 2938 * NV_ERR_NOT_SUPPORTED 2939 */ 2940 2941 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 2942 2943 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) 2944 2945 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { 2946 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; 2947 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; 2948 2949 /* _ctrl0000system_h_ */ 2950