1 /*
2  * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3  * SPDX-License-Identifier: MIT
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #pragma once
25 
26 #include <nvtypes.h>
27 
28 //
29 // This file was generated with FINN, an NVIDIA coding tool.
30 // Source file:      ctrl/ctrl0073/ctrl0073common.finn
31 //
32 
33 
34 
35 /*
36  *   DSC caps -
37  *      bDscSupported
38  *          If GPU supports DSC or not
39  *
40  *      encoderColorFormatMask
41  *          Mask of all color formats for which DSC
42  *          encoding is supported by GPU
43  *
44  *      lineBufferSizeKB
45  *          Size of line buffer.
46  *
47  *      rateBufferSizeKB
48  *          Size of rate buffer per slice.
49  *
50  *      bitsPerPixelPrecision
51  *          Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp
52  *
53  *      maxNumHztSlices
54  *          Maximum number of horizontal slices supported by DSC encoder
55  *
56  *      lineBufferBitDepth
57  *          Bit depth used by the GPU to store the reconstructed pixels within
58  *          the line buffer
59  */
60 #define NV0073_CTRL_CMD_DSC_CAP_PARAMS_MESSAGE_ID (0x1U)
61 
62 typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS {
63     NvBool bDscSupported;
64     NvU32  encoderColorFormatMask;
65     NvU32  lineBufferSizeKB;
66     NvU32  rateBufferSizeKB;
67     NvU32  bitsPerPixelPrecision;
68     NvU32  maxNumHztSlices;
69     NvU32  lineBufferBitDepth;
70 } NV0073_CTRL_CMD_DSC_CAP_PARAMS;
71 
72 /*
73  * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD
74  *
75  *   subDeviceInstance
76  *     This parameter specifies the subdevice instance within the
77  *     NV04_DISPLAY_COMMON parent device to which the operation should be
78  *     directed. This parameter must specify a value between zero and the
79  *     total number of subdevices within the parent device.  This parameter
80  *     should be set to zero for default behavior
81  *   cmd
82  *     This parameter is an input to this command.
83  *     Here are the current defined fields:
84  *       NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER
85  *         Set to specify what operation to run.
86  *           NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP
87  *             Request to power up pad.
88  *           NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN
89  *             Request to power down the pad.
90  *   linkBw
91  *     This parameter is used to pass in the link bandwidth required to run the
92  *     power up sequence. Refer enum DM_FRL_LINK_RATE_GBPS for valid values.
93  *   laneCount
94  *     This parameter is used to pass the lanecount.
95  *   sorIndex
96  *     This parameter is used to pass the SOR index.
97  *   padlinkIndex
98  *     This parameter is used to pass the padlink index for primary link.
99  *     Please refer enum DFPPADLINK for valid index values for Link A~F.
100  */
101 
102 #define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD (0x730502U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID << 8) | NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */
103 
104 #define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x2U)
105 
106 typedef struct NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS {
107     NvU32 subDeviceInstance;
108     NvU32 cmd;
109     NvU32 linkBw;
110     NvU32 laneCount;
111     NvU32 sorIndex;
112     NvU32 padlinkIndex;
113 } NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS;
114 
115 #define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER                        0:0
116 #define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP   (0x00000000U)
117 #define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN (0x00000001U)
118 
119 /* _ctrl0073common_h_ */
120