1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl0073/ctrl0073dfp.finn 31 // 32 33 #include "ctrl/ctrl0073/ctrl0073base.h" 34 35 /* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ 36 37 /* 38 * NV0073_CTRL_CMD_DFP_GET_INFO 39 * 40 * This command can be used to determine the associated display type for 41 * the specified displayId. 42 * 43 * subDeviceInstance 44 * This parameter specifies the subdevice instance within the 45 * NV04_DISPLAY_COMMON parent device to which the operation should be 46 * directed. This parameter must specify a value between zero and the 47 * total number of subdevices within the parent device. This parameter 48 * should be set to zero for default behavior. 49 * displayId 50 * This parameter specifies the ID of the display for which the dfp 51 * caps should be returned. The display ID must be a dfp display 52 * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. 53 * If more than one displayId bit is set or the displayId is not a dfp, 54 * this call will return NV_ERR_INVALID_ARGUMENT. 55 * flags 56 * This parameter returns the information specific to this dfp. Here are 57 * the possible fields: 58 * NV0073_CTRL_DFP_FLAGS_SIGNAL 59 * This specifies the type of signal used for this dfp. 60 * NV0073_CTRL_DFP_FLAGS_LANES 61 * This specifies whether the board supports 1, 2, or 4 lanes 62 * for DISPLAYPORT signals. 63 * NV0073_CTRL_DFP_FLAGS_LIMIT 64 * Some GPUs were not qualified to run internal TMDS except at 60 HZ 65 * refresh rates. So, if LIMIT_60HZ_RR is set, then the client must 66 * make sure to only allow 60 HZ refresh rate modes to the OS/User. 67 * NV0073_CTRL_DFP_FLAGS_SLI_SCALER 68 * While running in SLI, if SLI_SCALER_DISABLE is set, the GPU cannot 69 * scale any resolutions. So, the output timing must match the 70 * memory footprint. 71 * NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 72 * This specifies whether the DFP displayId is capable of 73 * transmitting HDMI. 74 * NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 75 * This specifies whether the displayId is capable of sending a 76 * limited color range out from the board. 77 * NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 78 * This specifies whether the displayId is capable of auto-configuring 79 * the color range. 80 * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 81 * This specifies whether the displayId is capable of sending the 82 * YCBCR422 color format out from the board. 83 * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 84 * This specifies whether the displayId is capable of sending 85 * YCBCR444 color format out from the board. 86 * NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH 87 * This specifies whether the displayId is capable of doing high 88 * bit-rate (2.7Gbps) or low bit-rate (1.62Gbps) if the DFP is 89 * display port. 90 * NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 91 * This specifies whether the DFP displayId is allowed to transmit HDMI 92 * based on the VBIOS settings. 93 * NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 94 * This specifies whether the DFP displayId is actually an embedded display 95 * port based on VBIOS connector information AND ASSR cap. 96 * NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 97 * This specifies whether the DFP displayId must be trained to RBR mode 98 * (if it is using DP protocol) whenever possible. 99 * NV0073_CTRL_DFP_FLAGS_LINK 100 * This specifies whether the board supports single or dual links 101 * for TMDS, LVDS, and SDI signals. 102 * NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 103 * This specifies if PostCursor2 is disabled in the VBIOS 104 * NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 105 * This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode). 106 * NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 107 * This indicates whether this DFP supports Dynamic MUX 108 * 109 * Possible status values returned are: 110 * NV_OK 111 * NV_ERR_INVALID_PARAM_STRUCT 112 * NV_ERR_INVALID_ARGUMENT 113 */ 114 #define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */ 115 116 #define NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID (0x40U) 117 118 typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { 119 NvU32 subDeviceInstance; 120 NvU32 displayId; 121 NvU32 flags; 122 } NV0073_CTRL_DFP_GET_INFO_PARAMS; 123 124 /* valid display types */ 125 #define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 126 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) 127 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) 128 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) 129 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) 130 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) 131 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) 132 #define NV0073_CTRL_DFP_FLAGS_LANE 5:3 133 #define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) 134 #define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) 135 #define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) 136 #define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) 137 #define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) 138 #define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 139 #define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) 140 #define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) 141 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 142 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) 143 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) 144 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 145 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) 146 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) 147 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 148 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) 149 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) 150 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 151 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) 152 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) 153 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 154 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) 155 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) 156 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 157 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) 158 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) 159 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 160 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) 161 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) 162 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 163 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) 164 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) 165 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 166 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) 167 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) 168 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 169 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) 170 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) 171 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) 172 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) 173 #define NV0073_CTRL_DFP_FLAGS_LINK 21:20 174 #define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) 175 #define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) 176 #define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) 177 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 178 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) 179 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) 180 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 181 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) 182 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) 183 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) 184 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) 185 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 186 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) 187 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) 188 #define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 189 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 190 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) 191 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) 192 193 194 195 /* 196 * NV0073_CTRL_CMD_DFP_GET_DP2TMDS_DONGLE_INFO 197 * 198 * This command can be used to determine information about dongles attached 199 * to a displayport connection. 200 * 201 * subDeviceInstance 202 * This parameter specifies the subdevice instance within the 203 * NV04_DISPLAY_COMMON parent device to which the operation should be 204 * directed. This parameter must specify a value between zero and the 205 * total number of subdevices within the parent device. This parameter 206 * should be set to zero for default behavior. 207 * displayId 208 * This parameter specifies the ID of the dfp display which owns the 209 * panel power to adjust. The display ID must be a dfp display 210 * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. 211 * If more than one displayId bit is set or the displayId is not a dfp, 212 * this call will return NV_ERR_INVALID_ARGUMENT. 213 * flags 214 * This parameter provide state information about the dongle attachments. 215 * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_CAPABLE 216 * Specifies if the connection is capable of a dongle. This field 217 * returns false in all cases of signal types except for those capable 218 * of outputting TMDS. Even then the if a gpio is not defined, the 219 * the a statement of false will also be returned. 220 * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_ATTACHED 221 * When attached, this value specifies that a dongle is detected and 222 * attached. The client should read the _TYPE field to determine 223 * if it is a dp2hdmi or dp2dvi dongle. 224 * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_TYPE 225 * _DP2DVI: no response to i2cAddr 0x80 per DP interop guidelines. 226 * clients MUST avoid outputting HDMI even if capable. 227 * _DP2HDMI: dongle responds to i2cAddr 0x80 per DP interop guidelines. 228 * client is allowed to output HDMI when possible. 229 * _LFH_DVI: DMS59-DVI breakout dongle is in use. 230 * _LFH_VGA: DMS59-VGA breakout dongle is in use. 231 * NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE 232 * _1: Max TMDS Clock rate is 165 MHz for both DVI and HDMI. 233 * _2: Max TMDS Clock rate will be specified in the dongle 234 * address space at device address 0x80. 235 * DVI is up to 165 MHz 236 * HDMI is up to 300 MHz 237 * There are type 2 devices that support beyond 600 MHz 238 * though not defined in the spec. 239 * maxTmdsClkRateHz 240 * This defines the max TMDS clock rate for dual mode adaptor in Hz. 241 */ 242 #define NV0073_CTRL_CMD_DFP_GET_DISPLAYPORT_DONGLE_INFO (0x731142U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID" */ 243 244 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID (0x42U) 245 246 typedef struct NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS { 247 NvU32 subDeviceInstance; 248 NvU32 displayId; 249 NvU32 flags; 250 NvU32 maxTmdsClkRateHz; 251 } NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS; 252 253 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE 0:0 254 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_FALSE (0x00000000U) 255 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_TRUE (0x00000001U) 256 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED 1:1 257 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_FALSE (0x00000000U) 258 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_TRUE (0x00000001U) 259 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE 7:4 260 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2DVI (0x00000000U) 261 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2HDMI (0x00000001U) 262 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_DVI (0x00000002U) 263 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_VGA (0x00000003U) 264 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE 8:8 265 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_1 (0x00000000U) 266 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_2 (0x00000001U) 267 268 269 270 /* 271 * NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS 272 * 273 * This command is used to inform hardware the receiver's audio capabilities 274 * using the new EDID Like Data (ELD) memory structure. The ELD memory 275 * structure is read by the audio driver by issuing the ELD Data command verb. 276 * This mechanism is used for passing sink device' audio EDID information 277 * from graphics software to audio software. ELD contents will contain a 278 * subset of the sink device's EDID information. 279 * The client should inform hardware at initial boot, a modeset, and whenever 280 * a hotplug event occurs. 281 * 282 * displayId 283 * This parameter indicates the digital display device's 284 * mask. This comes as input to this command. 285 * subDeviceInstance 286 * This parameter specifies the subdevice instance within the 287 * NV04_DISPLAY_COMMON parent device to which the operation should be directed. 288 * This parameter must specify a value between zero and the total number 289 * of subdevices within the parent device. This parameter should be set 290 * to zero for default behavior. 291 * numELDSize 292 * This parameter specifies how many bytes of data RM should write to the 293 * ELD buffer. Section 7.3.3.36 of the ECN specifies that the ELD buffer 294 * size of zero based. HDAudio driver will then use this information to 295 * determine how many bytes of the ELD buffer the HDAudio should read. 296 * The maximum size of the buffer is 96 bytes. 297 * bufferELD 298 * This buffer contains data as defined in the ECR HDMI ELD memory structure. 299 * Refer to the ELD Memory Structure Specification for more details. 300 * The format should be: 301 * - Header block is fixed at 4 bytes 302 * The header block contains the ELD version and baseline ELD len as 303 * well as some reserved fields. 304 * - Baseline block for audio descriptors is 76 bytes 305 * (15 SAD; each SAD=3 bytes requiring 45 bytes with 31 bytes to spare) 306 * As well as some other bits used to denote the CEA version, 307 * the speaker allocation data, monitor name, connector type, and 308 * hdcp capabilities. 309 * - Vendor specific block of 16 bytes 310 * maxFreqSupported 311 * Supply the maximum frequency supported for the overall audio caps. 312 * This value should match CEA861-X defines for sample freq. 313 * ctrl: 314 * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_PD: 315 * Specifies the presence detect of the receiver. On a hotplug 316 * or modeset client should set this bit to TRUE. 317 * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_ELDV: 318 * Specifies whether the ELD buffer contents are valid. 319 * An intrinsic unsolicited response (UR) is generated whenever 320 * the ELDV bit changes in value and the PD=1. When _PD=1(hotplug), 321 * RM will set the ELDV bit after ELD buffer contents are written. 322 * If _ELDV bit is set to false such as during a unplug, then the 323 * contents of the ELD buffer will be cleared. 324 * deviceEntry: 325 * The deviceEntry number from which the SF should accept packets. 326 * _NONE if disabling audio. 327 * Possible status values returned are: 328 * NV_OK 329 * NV_ERR_INVALID_PARAM_STRUCT 330 * NV_ERR_INVALID_ARGUMENT 331 */ 332 #define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */ 333 334 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U 335 336 #define NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID (0x44U) 337 338 typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS { 339 NvU32 subDeviceInstance; 340 NvU32 displayId; 341 NvU32 numELDSize; 342 NvU8 bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; 343 NvU32 maxFreqSupported; 344 NvU32 ctrl; 345 NvU32 deviceEntry; 346 } NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS; 347 348 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0320KHZ (0x00000001U) 349 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0441KHZ (0x00000002U) 350 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0480KHZ (0x00000003U) 351 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0882KHZ (0x00000004U) 352 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0960KHZ (0x00000005U) 353 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1764KHZ (0x00000006U) 354 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1920KHZ (0x00000007U) 355 356 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD 0:0 357 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE (0x00000000U) 358 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE (0x00000001U) 359 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV 1:1 360 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE (0x00000000U) 361 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE (0x00000001U) 362 363 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_0 (0x00000000U) 364 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_1 (0x00000001U) 365 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_2 (0x00000002U) 366 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 (0x00000003U) 367 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_NONE (0x00000007U) 368 369 370 371 /* 372 * NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM_STATUS 373 * 374 * This command is used to get spread spectrum status for a display device. 375 * 376 * displayId 377 * Display ID for which the spread spectrum status is needed. 378 * checkRMSsState 379 * Default is to check in Vbios. This flag lets this control call to check in register. 380 * status 381 * Return status value. 382 */ 383 384 #define NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM (0x73114cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID" */ 385 386 #define NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID (0x4CU) 387 388 typedef struct NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS { 389 NvU32 displayId; 390 NvBool enabled; 391 } NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS; 392 393 /* 394 * NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE 395 * 396 * Update the Dynamic DFP with Bcaps read from remote display. 397 * Also updates hdcpFlags, gpu hdcp capable flags in DFP. 398 * If bResetDfp is true, all the flags are reset before making changes. 399 * 400 * Possible status values returned are: 401 * NV_OK 402 * NV_ERR_INVALID_ARGUMENT 403 * NV_ERR_NOT_SUPPORTED 404 */ 405 406 #define NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE (0x73114eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID" */ 407 408 #define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID (0x4EU) 409 410 typedef struct NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS { 411 NvU32 subDeviceInstance; 412 NvU32 headIndex; 413 NvU8 bcaps; 414 NvU8 bksv[5]; 415 NvU32 hdcpFlags; 416 NvBool bHdcpCapable; 417 NvBool bResetDfp; 418 NvU8 updateMask; 419 } NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS; 420 421 #define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BCAPS 0x01U 422 #define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BKSV 0x02U 423 #define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_FLAGS 0x03U 424 425 /* 426 * NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE 427 * 428 * This command sets the audio enable state of the DFP. When disabled, 429 * no audio stream packets or audio timestamp packets will be sent. 430 * 431 * subDeviceInstance 432 * This parameter specifies the subdevice instance within the 433 * NV04_DISPLAY_COMMON parent device to which the operation should be 434 * directed. This parameter must specify a value between zero and the 435 * total number of subdevices within the parent device. This parameter 436 * should be set to zero for default behavior. 437 * displayId 438 * This parameter specifies the ID of the display for which the dfp 439 * audio should be enabled or disabled. The display ID must be a dfp display. 440 * If the displayId is not a dfp, this call will return 441 * NV_ERR_INVALID_ARGUMENT. 442 * enable 443 * This parameter specifies whether to enable (NV_TRUE) or disable (NV_FALSE) 444 * audio to the display. 445 * 446 * Possible status values returned are: 447 * NV_OK 448 * NV_ERR_INVALID_PARAM_STRUCT 449 * NV_ERR_INVALID_ARGUMENT 450 * 451 * 452 */ 453 #define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */ 454 455 #define NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID (0x50U) 456 457 typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { 458 NvU32 subDeviceInstance; 459 NvU32 displayId; 460 NvBool enable; 461 } NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS; 462 463 464 465 /* 466 * NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG 467 * 468 * This variable specifies default/primary/secondary sor sublinks to be configured. 469 * These access modes are: 470 * 471 * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE 472 * Default link config 473 * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK 474 * Primary sor sublink to be configured 475 * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK 476 * Secondary sor sublink to be configured 477 */ 478 typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; 479 480 #define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE (0x0U) 481 #define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK (0x1U) 482 #define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK (0x2U) 483 484 /* 485 * NV0073_CTRL_DFP_ASSIGN_SOR_INFO 486 * 487 * This structure describes info about assigned SOR 488 * 489 * displayMask 490 * The displayMask for the SOR corresponding to its HW routings 491 * sorType 492 * This parameter specifies the SOR type 493 * Here are the current defined fields: 494 * NV0073_CTRL_DFP_SOR_TYPE_NONE 495 * Unallocated SOR 496 * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY 497 * Primary SOR for 2H1OR stream 498 * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY 499 * Secondary SOR for 2H1OR stream 500 * NV0073_CTRL_DFP_SOR_TYPE_SINGLE 501 * Default Single SOR 502 * Note - sorType should only be referred to identify 2H1OR Primary and Secondary SOR 503 * 504 */ 505 506 typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO { 507 NvU32 displayMask; 508 NvU32 sorType; 509 } NV0073_CTRL_DFP_ASSIGN_SOR_INFO; 510 511 #define NV0073_CTRL_DFP_SOR_TYPE_NONE (0x00000000U) 512 #define NV0073_CTRL_DFP_SOR_TYPE_SINGLE (0x00000001U) 513 #define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY (0x00000002U) 514 #define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY (0x00000003U) 515 516 /* 517 * NV0073_CTRL_CMD_DFP_ASSIGN_SOR 518 * 519 * This command is used by the clients to assign SOR to DFP for CROSS-BAR 520 * when the default SOR-DFP routing that comes from vbios is not considered. 521 * SOR shall be assigned to a DFP at the runtime. This call should be called 522 * before a modeset is done on any dfp display and also before LinkTraining for DP displays. 523 * 524 * subDeviceInstance 525 * This parameter specifies the subdevice instance within the 526 * NV04_DISPLAY_COMMON parent device to which the operation should be 527 * directed. This parameter must specify a value between zero and the 528 * total number of subdevices within the parent device. This parameter 529 * should be set to zero for default behavior. 530 * displayId 531 * DisplayId of the primary display for which SOR is to be assigned. However, if 532 * displayId is 0 then RM shall return the XBAR config it has stored in it's structures. 533 * sorExcludeMask 534 * sorMask of the SORs which should not be used for assignment. If this is 0, 535 * then SW is free to allocate any available SOR. 536 * slaveDisplayId 537 * displayId of the slave device in case of dualSST mode. This ctrl call will 538 * allocate SORs to both slave and the master if slaveDisplayId is set. 539 * forceSublinkConfig 540 * forces RM to configure primary or secondary sor sublink on the given diaplayId. 541 * If not set, then RM will do the default configurations. 542 * bIs2Head1Or 543 * Specifies that SOR allocation is required for 2 head 1 OR. This will allocate 544 * 2 SOR for same displayId - one Master and one Slave. Slave SOR would be disconnected 545 * from any padlink and get feedback clock from Master SOR's padlink. 546 * sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] 547 * returns the displayMask for all SORs corresponding to their HW routings. 548 * sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] 549 * returns the displayMask for all SORs corresponding to their HW routings along with 550 * SOR type to identify 2H1OR Primary and Secondary SORs. SOR type would be identified by 551 * NV0073_CTRL_DFP_SOR_TYPE. sorAssignList would look as below - 552 * sorAssignListWithTag[] = { DisplayMask, SOR Type 553 * {0x100, SECONDARY_SOR} 554 * {0x200, SINGLE_SOR} 555 * {0x100, PRIMARY_SOR} 556 * {0, NONE}} 557 * } 558 * Here, for display id = 0x100, SOR2 is Primary and SOR0 is Secondary. 559 * Note - sorAssignList parameter would be removed after Bug 200749158 is resolved 560 * reservedSorMask 561 * returns the sorMask reserved for the internal panels. 562 * flags 563 * Other detail settings. 564 * _AUDIO_OPTIMAL: Client requests trying to get audio SOR if possible. 565 * If there's no audio capable SOR and OD is HDMI/DP, 566 * RM will fail the control call. 567 * _AUDIO_DEFAULT: RM does not check audio-capability of SOR. 568 * 569 * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable. 570 * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'. 571 * 572 * Possible status values returned are: 573 * NV_OK 574 * NV_ERR_INVALID_ARGUMENT 575 * NV_ERR_NOT_SUPPORTED 576 */ 577 578 579 #define NV0073_CTRL_CMD_DFP_ASSIGN_SOR (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */ 580 581 #define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS 4U 582 583 #define NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID (0x52U) 584 585 typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS { 586 NvU32 subDeviceInstance; 587 NvU32 displayId; 588 NvU8 sorExcludeMask; 589 NvU32 slaveDisplayId; 590 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig; 591 NvBool bIs2Head1Or; 592 NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; 593 NV0073_CTRL_DFP_ASSIGN_SOR_INFO sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; 594 NvU8 reservedSorMask; 595 NvU32 flags; 596 } NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS; 597 598 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO 0:0 599 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL (0x00000001U) 600 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT (0x00000000U) 601 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE 1:1 602 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO (0x00000000U) 603 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U) 604 605 /* 606 * NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK 607 * 608 * This command will only be used by chipTB tests to get the padlinks corresponding 609 * to the given displayId. RM gets this information from vbios. This control call is 610 * only for verif purpose. 611 * 612 * subDeviceInstance 613 * This parameter specifies the subdevice instance within the 614 * NV04_DISPLAY_COMMON parent device to which the operation should be 615 * directed. This parameter must specify a value between zero and the 616 * total number of subdevices within the parent device. This parameter 617 * should be set to zero for default behavior. 618 * displayId 619 * DisplayId of the display for which the client needs analog link Mask 620 * padlinkMask 621 * analogLinkMask for the given displayId. This value returned is 0xffffffff if 622 * the given displayId is invalid else RM returns the corresponding padlinkMask. 623 * NV_OK 624 * NV_ERR_INVALID_ARGUMENT 625 * NV_ERR_NOT_SUPPORTED 626 */ 627 628 629 #define NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK (0x731153U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID" */ 630 631 #define NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID (0x53U) 632 633 typedef struct NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS { 634 NvU32 subDeviceInstance; 635 NvU32 displayId; 636 NvU32 padlinkMask; 637 } NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS; 638 639 /* 640 * NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE 641 * This enum defines the functions that are supported for which a 642 * corresponding GPIO pin number could be retrieved 643 * Values copied from objgpio.h GPIO_FUNC_TYPE_LCD_*. Please keep the 644 * values in sync between the 2 files 645 */ 646 647 typedef enum NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE { 648 // GPIO types of LCD GPIO functions common to all internal panels 649 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BACKLIGHT = 268435456, 650 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER = 285212672, 651 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER_OK = 301989888, 652 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_SELF_TEST = 318767104, 653 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_LAMP_STATUS = 335544320, 654 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BRIGHTNESS = 352321536, 655 } NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE; 656 657 /* 658 * NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM 659 * 660 * This command can be used to get the GPIO pin number that corresponds to one 661 * of the LCD functions 662 * 663 * subDeviceInstance 664 * This parameter specifies the subdevice instance within the 665 * NV04_DISPLAY_COMMON parent device to which the operation should be 666 * directed. This parameter must specify a value between zero and the 667 * total number of subdevices within the parent device. This parameter 668 * should be set to zero for default behavior. 669 * displayId 670 * This parameter specifies the ID of the dfp display. 671 * If more than one displayId bit is set or the displayId is not a dfp, 672 * this call will return NVOS_STATUS_ERROR_INVALID_ARGUMENT. 673 * funcType 674 * The LDC function for which the GPIO pin number is needed 675 * lcdGpioPinNum 676 * The GPIO pin number that corresponds to the LCD function. 677 * 678 */ 679 #define NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM (0x731154U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID" */ 680 681 #define NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID (0x54U) 682 683 typedef struct NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS { 684 NvU32 subDeviceInstance; 685 NvU32 displayId; 686 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE funcType; 687 NvU32 lcdGpioPinNum; 688 } NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS; 689 690 691 692 /* 693 * NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR 694 * 695 * This command is used for configuration of 2 head 1 OR. 696 * 697 * subDeviceInstance 698 * This parameter specifies the subdevice instance within the 699 * NV04_DISPLAY_COMMON parent device to which the operation should be 700 * directed. This parameter must specify a value between zero and the 701 * total number of subdevices within the parent device. This parameter 702 * should be set to zero for default behavior. 703 * displayId 704 * Display Id of the panel for which Two Head One OR is going to be used 705 * bEnable 706 * Enable/Disable 2 Head 1 OR 707 * masterSorIdx 708 * Master SOR Index which will send pixels to panel 709 * slaveSorIdx 710 * Slave SOR Index which will take feedback clock from Master SOR's 711 * padlink 712 * Possible status values returned are: 713 * NVOS_STATUS_SUCCESS 714 * NVOS_STATUS_ERROR_INVALID_ARGUMENT 715 * NVOS_STATUS_ERROR_NOT_SUPPORTED 716 */ 717 718 719 #define NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR (0x731156U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID" */ 720 721 #define NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID (0x56U) 722 723 typedef struct NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS { 724 NvU32 subDeviceInstance; 725 NvU32 displayId; 726 NvBool bEnable; 727 NvU32 masterSorIdx; 728 NvU32 slaveSorIdx; 729 } NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS; 730 731 /* 732 * NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL 733 * 734 * This command is used to enable/disable CRC on the GPU or query the registers 735 * related to it 736 * 737 * subDeviceInstance 738 * This parameter specifies the subdevice instance within the 739 * NV04_DISPLAY_COMMON parent device to which the operation should be 740 * directed. This parameter must specify a value between zero and the 741 * total number of subdevices within the parent device. This parameter 742 * should be set to zero for default behavior. 743 * headIndex 744 * index of the head 745 * cmd 746 * specifying if setup or querying is done 747 * bEnable 748 * enable or disable CRC on the GPU 749 * gpuCrc0 750 * 0-indexed CRC register of the GPU 751 * gpuCrc1 752 * 1-indexed CRC register of the GPU 753 * gpuCrc0 754 * 2-indexed CRC register of the GPU 755 * Possible status values returned are: 756 * NVOS_STATUS_SUCCESS 757 * NVOS_STATUS_ERROR_NOT_SUPPORTED 758 */ 759 760 761 #define NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL (0x731157U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID" */ 762 763 #define NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID (0x57U) 764 765 typedef struct NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS { 766 NvU32 subDeviceInstance; 767 NvU32 headIndex; 768 NvU32 cmd; 769 NvBool bEnable; 770 NvU16 gpuCrc0; 771 NvU16 gpuCrc1; 772 NvU16 gpuCrc2; 773 } NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS; 774 775 #define NV0073_CTRL_DP_CRC_CONTROL_CMD 0:0 776 #define NV0073_CTRL_DP_CRC_CONTROL_CMD_SETUP (0x00000000U) 777 #define NV0073_CTRL_DP_CRC_CONTROL_CMD_QUERY (0x00000001U) 778 779 /* 780 * NV0073_CTRL_CMD_DFP_INIT_MUX_DATA 781 * 782 * This control call is used to configure the display MUX related data 783 * for the given display device. Clients to RM are expected to call this 784 * control call to initialize the data related to MUX before any MUX related 785 * operations such mux switch or PSR entry/ exit are performed. 786 * 787 * subDeviceInstance (in) 788 * This parameter specifies the subdevice instance within the 789 * NV04_DISPLAY_COMMON parent device to which the operation should be 790 * directed. 791 * displayId (in) 792 * ID of the display device for which the mux state has to be initialized 793 * manfId (in) 794 * Specifies the manufacturer ID of panel obtained from the EDID. This 795 * parameter is expected to be non-zero only in case of internal panel. 796 * productId (in) 797 * Specifies the product ID of panel obtained from the EDID. This 798 * parameter is expected to be non-zero only in case of internal panel. 799 * 800 * Possible status values returned are: 801 * NV_OK 802 * NV_ERR_INVALID_PARAM_STRUCT 803 * NV_ERR_INVALID_ARGUMENT 804 * NV_ERR_NOT_SUPPORTED 805 */ 806 807 #define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA (0x731158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID" */ 808 809 #define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID (0x58U) 810 811 typedef struct NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS { 812 NvU32 subDeviceInstance; 813 NvU32 displayId; 814 NvU16 manfId; 815 NvU16 productId; 816 } NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS; 817 818 819 820 /* 821 * NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX 822 * 823 * This command is used to switch the dynamic display mux between 824 * integrated GPU and discrete GPU. 825 * 826 * subDeviceInstance (in) 827 * This parameter specifies the subdevice instance within the 828 * NV04_DISPLAY_COMMON parent device to which the operation should be 829 * directed. 830 * displayId (in) 831 * ID of the display device for which the display MUX has to be switched 832 * flags (in) 833 * Flags indicating the action to be performed. Here are the possible 834 * valid values- 835 * NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU 836 * When set mux is switched from integrated to discrete GPU. 837 * NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU 838 * When set mux is switched from discrete to integrated GPU. 839 * NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS 840 * Set to true for PSR panels as we skip sideband access. 841 * auxSettleDelay (in) 842 * Time, in milliseconds, necessary for AUX channel to settle and become 843 * accessible after a mux switch. Set to zero to use the default delay. 844 * muxSwitchLatencyMs (out) 845 * mux switch latency stats in milli-seconds 846 * 847 * Possible status values returned are: 848 * NV_OK 849 * NV_ERR_INVALID_PARAM_STRUCT 850 * NV_ERR_INVALID_ARGUMENT 851 * NV_ERR_NOT_SUPPORTED 852 */ 853 854 #define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX (0x731160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */ 855 856 #define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x60U) 857 858 typedef struct NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS { 859 NvU32 subDeviceInstance; 860 NvU32 displayId; 861 NvU32 flags; 862 NvU32 auxSettleDelay; 863 NvU32 muxSwitchLatencyMs; 864 } NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS; 865 866 /* valid flags*/ 867 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH 0:0 868 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU 0x00000000 869 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU 0x00000001 870 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS 1:1 871 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_YES 0x00000001 872 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_NO 0x00000000 873 874 /* 875 * NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS 876 * 877 * This command is used to perform all the operations that need to be 878 * performed before a mux switch is started. 879 * 880 * subDeviceInstance (in) 881 * This parameter specifies the subdevice instance within the 882 * NV04_DISPLAY_COMMON parent device to which the operation should be 883 * directed. 884 * displayId (in) 885 * ID of the display device for which the pre mux switch operations have 886 * to be performed. 887 * flags (in) 888 * Flags indicating the action to be performed. Here are the possible 889 * valid values - 890 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 891 * Indicates a switch from i to d is initiated 892 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 893 * Indicates a switch from d to i is initiated 894 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO 895 * When set RM will execute the PSR enter sequence. By default RM will 896 * not skip SR enter sequence 897 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES 898 * When set RM will skip the PSR enter sequence 899 * iGpuBrightness (in) 900 * iGPU brightness value (scale 0~100) before switching mux from I2D. 901 * This is used to match brightness after switching mux to dGPU 902 * preOpsLatencyMs (out) 903 * premux switch operations latency stats in milli-seconds. This includes - 904 * - disabling SOR sequencer and enable BL GPIO control 905 * - toggling LCD VDD, BL EN and PWM MUX GPIOs 906 * - PSR entry, if not skipped 907 * psrEntryLatencyMs (out) 908 * psr entry latency stats in milli-seconds 909 * 910 * Possible status values returned are: 911 * NV_OK 912 * NV_ERR_INVALID_PARAM_STRUCT 913 * NV_ERR_INVALID_ARGUMENT 914 * NV_ERR_NOT_SUPPORTED 915 */ 916 917 #define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS (0x731161U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ 918 919 #define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x61U) 920 921 typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS { 922 NvU32 subDeviceInstance; 923 NvU32 displayId; 924 NvU32 flags; 925 NvU32 iGpuBrightness; 926 NvU32 preOpsLatencyMs; 927 NvU32 psrEntryLatencyMs; 928 } NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS; 929 930 /* valid flags*/ 931 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 932 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 0x00000000U 933 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 0x00000001U 934 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP 1:1 935 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO 0x00000000U 936 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES 0x00000001U 937 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING 2:2 938 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 0x00000000 939 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 0x00000001 940 941 #define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U 942 #define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U 943 944 /* 945 * NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS 946 * 947 * This command is used to perform all the operations that need to be 948 * performed after a successful mux switch is completed. 949 * 950 * subDeviceInstance (in) 951 * This parameter specifies the subdevice instance within the 952 * NV04_DISPLAY_COMMON parent device to which the operation should be 953 * directed. 954 * displayId (in) 955 * ID of the display device for which the post mux switch operations have 956 * to be performed. 957 * flags (in) 958 * Flags indicating the action to be performed. Here are the possible 959 * valid values - 960 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 961 * Indicates a switch from i to d is initiated 962 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 963 * Indicates a switch from d to i is initiated 964 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO 965 * When set RM will execute the PSR exit sequence. By default RM will 966 * not skip SR exit sequence 967 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES 968 * When set RM will skip the PSR exit sequence 969 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 970 * Indicates mux switches where we know when igpu powers up 971 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 972 * Indicates mux switches where we don't know when igpu powers up 973 * postOpsLatencyMs (out) 974 * postmux switch operations latency stats in milli-seconds. This includes - 975 * - restoring SOR sequencer and BL GPIO control 976 * - toggling LCD VDD, BL EN and PWM MUX GPIOs 977 * - PSR exit, if not skipped 978 * psrExitLatencyMs (out) 979 * psr exit latency stats in milli-seconds 980 * psrExitTransitionToInactiveLatencyMs (out) 981 * psr exit latency stats in milli-seconds, from state 2 (SR active) to state 4 (transition to inactive) 982 * 983 * Possible status values returned are: 984 * NV_OK 985 * NV_ERR_INVALID_PARAM_STRUCT 986 * NV_ERR_INVALID_ARGUMENT 987 * NV_ERR_NOT_SUPPORTED 988 * NV_ERR_TIMEOUT in case of SR exit failure 989 */ 990 991 #define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS (0x731162U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ 992 993 #define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x62U) 994 995 typedef struct NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS { 996 NvU32 subDeviceInstance; 997 NvU32 displayId; 998 NvU32 flags; 999 NvU32 postOpsLatencyMs; 1000 NvU32 psrExitLatencyMs; 1001 NvU32 psrExitTransitionToInactiveLatencyMs; 1002 } NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS; 1003 1004 /* valid flags*/ 1005 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 1006 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP 1:1 1007 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO 0x00000000U 1008 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES 0x00000001U 1009 1010 /* 1011 * NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS 1012 * 1013 * This command is used to query the display mux status for the given 1014 * display device 1015 * 1016 * subDeviceInstance (in) 1017 * This parameter specifies the subdevice instance within the 1018 * NV04_DISPLAY_COMMON parent device to which the operation should be 1019 * directed. 1020 * displayId (in) 1021 * ID of the display device for which the post mux switch operations have 1022 * to be performed. 1023 * muxStatus (out) 1024 * status indicating the current state of the mux. 1025 * valid values - 1026 * NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU 1027 * Indicates that the MUX is currently switched to integrated GPU. 1028 * NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU 1029 * Indicates that the MUX is currently switched to discrete GPU. 1030 * NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY 1031 * Indicates that the MUX mode is set to discrete mode, where all displays 1032 * are driven by discrete GPU. 1033 * NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY 1034 * Indicates that the MUX mode is set to integrated mode, where all 1035 * displays are driven by Integrated GPU. 1036 * NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID 1037 * Indicates that the MUX mode is set to hybrid, where internal panel is 1038 * driven by integrated GPU, while external displays might be driven by 1039 * discrete GPU. 1040 * NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC 1041 * Indicates that the MUX mode is dynamic. It is only in this mode, the 1042 * display MUX can be toggled between discrete and hybrid dynamically. 1043 * 1044 * Possible status values returned are: 1045 * NV_OK 1046 * NV_ERR_INVALID_PARAM_STRUCT 1047 * NV_ERR_INVALID_ARGUMENT 1048 * NV_ERR_NOT_SUPPORTED 1049 */ 1050 1051 #define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS (0x731163U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */ 1052 1053 #define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x63U) 1054 1055 typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { 1056 NvU32 subDeviceInstance; 1057 NvU32 displayId; 1058 NvU32 muxStatus; 1059 } NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS; 1060 1061 /* valid flags */ 1062 #define NV0073_CTRL_DFP_DISP_MUX_STATE 1:0 1063 #define NV0073_CTRL_DFP_DISP_MUX_STATE_INVALID 0x00000000U 1064 #define NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU 0x00000001U 1065 #define NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU 0x00000002U 1066 #define NV0073_CTRL_DFP_DISP_MUX_MODE 4:2 1067 #define NV0073_CTRL_DFP_DISP_MUX_MODE_INVALID 0x00000000U 1068 #define NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY 0x00000001U 1069 #define NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY 0x00000002U 1070 #define NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID 0x00000003U 1071 #define NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC 0x00000004U 1072 1073 1074 1075 /* 1076 * NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING 1077 * 1078 * This command can be used to get DSI mode timing parameters. 1079 * 1080 * subDeviceInstance 1081 * This parameter specifies the subdevice instance within the 1082 * NV04_DISPLAY_COMMON parent device to which the operation should be 1083 * directed. This parameter must specify a value between zero and the 1084 * total number of subdevices within the parent device. This parameter 1085 * should be set to zero for default behavior. 1086 * displayId 1087 * This parameter specifies the ID of the display on which the DSI 1088 * info will be set. The display ID must be a DSI-capable display. 1089 * hActive 1090 * This parameter specifies the horizontal length of the active pixel 1091 * data in the raster. 1092 * vActive 1093 * This parameter specifies the vertical lines of the active pixel 1094 * data in the raster. 1095 * hFrontPorch 1096 * This parameter specifies the number of horizontal front porch 1097 * blanking pixels in the raster. 1098 * vFrontPorch 1099 * This parameter specifies the numer of lines of the vertical front 1100 * porch in the raster. 1101 * hBackPorch 1102 * This parameter specifies the number of horizontal back porch 1103 * blanking pixels in the raster. 1104 * vBackPorch 1105 * This parameter specifies the numer of lines of the vertical back 1106 * porch in the raster. 1107 * hSyncWidth 1108 * This parameter specifies the number of horizontal sync pixels in 1109 * the raster. 1110 * vSyncWidth 1111 * This parameter specifies the numer of lines of the vertical sync 1112 * in the raster. 1113 * bpp 1114 * This parameter specifies the depth (Bits per Pixel) of the output 1115 * display stream. 1116 * refresh 1117 * This parameter specifies the refresh rate of the panel (in Hz). 1118 * pclkHz 1119 * This parameter specifies the pixel clock rate in Hz. 1120 * numLanes 1121 * Number of DSI data lanes. 1122 * dscEnable 1123 * Flag to indicate if DSC an be enabled, which in turn indicates if 1124 * panel supports DSC. 1125 * dscBpp 1126 * DSC Bits per pixel 1127 * dscNumSlices 1128 * Number of slices for DSC. 1129 * dscDuaDsc 1130 * Flag to indicate if panel supports DSC streams from two DSI 1131 * controllers. 1132 * dscSliceHeight 1133 * Height of DSC slices. 1134 * dscBlockPrediction 1135 * Flag to indicate if DSC Block Prediction needs to be enabled. 1136 * dscDecoderVersionMajor 1137 * Major version number of DSC decoder on Panel. 1138 * dscDecoderVersionMinor 1139 * Minor version number of DSC decoder on Panel. 1140 * dscUseCustomPPS 1141 * Flag to indicate if Panel uses custom PPS values which deviate from standard values. 1142 * dscCustomPPSData 1143 * 32 bytes of custom PPS data required by Panel. 1144 * dscEncoderCaps 1145 * Capabilities of DSC encoder in SoC. 1146 * 1147 * Possible status values returned are: 1148 * NV_OK 1149 * NV_ERR_INVALID_ARGUMENT 1150 * NV_ERR_NOT_SUPPORTED 1151 */ 1152 1153 #define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING (0x731166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID" */ 1154 1155 #define NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT 32U 1156 1157 #define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U) 1158 1159 typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { 1160 NvU32 subDeviceInstance; 1161 NvU32 displayId; 1162 NvU32 hActive; 1163 NvU32 vActive; 1164 NvU32 hFrontPorch; 1165 NvU32 vFrontPorch; 1166 NvU32 hBackPorch; 1167 NvU32 vBackPorch; 1168 NvU32 hSyncWidth; 1169 NvU32 vSyncWidth; 1170 NvU32 bpp; 1171 NvU32 refresh; 1172 NvU32 pclkHz; 1173 NvU32 numLanes; 1174 NvU32 dscEnable; 1175 NvU32 dscBpp; 1176 NvU32 dscNumSlices; 1177 NvU32 dscDualDsc; 1178 NvU32 dscSliceHeight; 1179 NvU32 dscBlockPrediction; 1180 NvU32 dscDecoderVersionMajor; 1181 NvU32 dscDecoderVersionMinor; 1182 NvBool dscUseCustomPPS; 1183 NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; 1184 1185 struct { 1186 NvBool bDscSupported; 1187 NvU32 encoderColorFormatMask; 1188 NvU32 lineBufferSizeKB; 1189 NvU32 rateBufferSizeKB; 1190 NvU32 bitsPerPixelPrecision; 1191 NvU32 maxNumHztSlices; 1192 NvU32 lineBufferBitDepth; 1193 } dscEncoderCaps; 1194 } NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS; 1195 1196 1197 1198 /* 1199 * NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING 1200 * 1201 * This control call is used to retrieve the display mode timing info that's 1202 * specified for a given DFP from an offline configuration blob (e.g., Device Tree). 1203 * This display timing info is intended to replace the timings exposed in a 1204 * sink's EDID. 1205 * 1206 * subDeviceInstance (in) 1207 * This parameter specifies the subdevice instance within the 1208 * NV04_DISPLAY_COMMON parent device to which the operation should be 1209 * directed. 1210 * displayId (in) 1211 * ID of the display device for which the timings should be retrieved. 1212 * stream (in) 1213 * For MST connectors with static topologies (e.g., DP serializers), 1214 * this parameter further identifies the video stream for which the 1215 * timings should be retrieved. 1216 * valid (out) 1217 * Indicates whether a valid display timing was found for this DFP. 1218 * hActive (out) 1219 * Horizontal active width in pixels 1220 * hFrontPorch (out) 1221 * Horizontal front porch 1222 * hSyncWidth (out) 1223 * Horizontal sync width 1224 * hBackPorch (out) 1225 * Horizontal back porch 1226 * vActive (out) 1227 * Vertical active height in lines 1228 * vFrontPorch (out) 1229 * Vertical front porch 1230 * vSyncWidth (out) 1231 * Vertical sync width 1232 * vBackPorch (out) 1233 * Vertical back porch 1234 * pclkKHz (out) 1235 * Pixel clock frequency in KHz 1236 * rrx1k (out) 1237 * Refresh rate in units of 0.001Hz 1238 * 1239 * Possible status values returned are: 1240 * NV_OK 1241 * NV_ERR_INVALID_ARGUMENT 1242 * NV_ERR_NOT_SUPPORTED 1243 */ 1244 #define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */ 1245 1246 #define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U) 1247 1248 typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS { 1249 NvU32 subDeviceInstance; 1250 NvU32 displayId; 1251 NvU8 stream; 1252 1253 NvBool valid; 1254 1255 NvU16 hActive; 1256 NvU16 hFrontPorch; 1257 NvU16 hSyncWidth; 1258 NvU16 hBackPorch; 1259 1260 NvU16 vActive; 1261 NvU16 vFrontPorch; 1262 NvU16 vSyncWidth; 1263 NvU16 vBackPorch; 1264 1265 NvU32 pclkKHz; 1266 NvU32 rrx1k; 1267 } NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS; 1268 1269 /* _ctrl0073dfp_h_ */ 1270