1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl0080/ctrl0080gr.finn 31 // 32 33 #include "ctrl/ctrl0080/ctrl0080base.h" 34 #include "nvcfg_sdk.h" 35 36 typedef struct NV0080_CTRL_GR_ROUTE_INFO { 37 NvU32 flags; 38 NV_DECLARE_ALIGNED(NvU64 route, 8); 39 } NV0080_CTRL_GR_ROUTE_INFO; 40 41 /* NV01_DEVICE_XX/NV03_DEVICE gr engine control commands and parameters */ 42 43 /** 44 * NV0080_CTRL_CMD_GR_GET_CAPS 45 * 46 * This command returns the set of graphics capabilities for the device 47 * in the form of an array of unsigned bytes. Graphics capabilities 48 * include supported features and required workarounds for the graphics 49 * engine(s) within the device, each represented by a byte offset into the 50 * table and a bit position within that byte. 51 * 52 * capsTblSize 53 * This parameter specifies the size in bytes of the caps table. 54 * This value should be set to NV0080_CTRL_GR_CAPS_TBL_SIZE. 55 * capsTbl 56 * This parameter specifies a pointer to the client's caps table buffer 57 * into which the graphics caps bits will be transferred by the RM. 58 * The caps table is an array of unsigned bytes. 59 */ 60 #define NV0080_CTRL_CMD_GR_GET_CAPS (0x801102) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID" */ 61 62 #define NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x2U) 63 64 typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS { 65 NvU32 capsTblSize; 66 NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); 67 } NV0080_CTRL_GR_GET_CAPS_PARAMS; 68 69 /* extract cap bit setting from tbl */ 70 #define NV0080_CTRL_GR_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) 71 72 73 74 /* 75 * Size in bytes of gr caps table. This value should be one greater 76 * than the largest byte_index value above. 77 */ 78 #define NV0080_CTRL_GR_CAPS_TBL_SIZE 23 79 80 81 82 /* 83 * NV0080_CTRL_CMD_GR_INFO 84 * 85 * This structure represents a single 32bit graphics engine value. Clients 86 * request a particular graphics engine value by specifying a unique bus 87 * information index. 88 * 89 * Legal graphics information index values are: 90 * NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS 91 * This index is used to request the number of clip IDs supported by 92 * the device. 93 * NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 94 * This index is used to request the minimum number of attributes that 95 * need to be enabled to avoid bug 261894. A return value of 0 96 * indicates that there is no minimum and the bug is not present on this 97 * system. 98 */ 99 typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO; 100 101 /* valid graphics info index values */ 102 #define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000) 103 #define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001) 104 #define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002) 105 #define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003) 106 #define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004) 107 #define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005) 108 #define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006) 109 #define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007) 110 #define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008) 111 #define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009) 112 #define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A) 113 #define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B) 114 #define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C) 115 #define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D) 116 #define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E) 117 #define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F) 118 #define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010) 119 #define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011) 120 #define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012) 121 #define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013) 122 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014) 123 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015) 124 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016) 125 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017) 126 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018) 127 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019) 128 #define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A) 129 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B) 130 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C) 131 #define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D) 132 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E) 133 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F) 134 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020) 135 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021) 136 #define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022) 137 #define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023) 138 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024) 139 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025) 140 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026) 141 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027) 142 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028) 143 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029) 144 #define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A) 145 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B) 146 #define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C) 147 #define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D) 148 #define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E) 149 150 151 #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032) 152 153 154 #define NV0080_CTRL_GR_INFO_INDEX_DUMMY (0x00000033) 155 #define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034) 156 157 /* When adding a new INDEX, please update MAX_SIZE accordingly 158 * NOTE: 0080 functionality is merged with 2080 functionality, so this max size 159 * reflects that. 160 */ 161 #define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000034) 162 #define NV0080_CTRL_GR_INFO_MAX_SIZE (0x35) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ 163 164 /* 165 * NV0080_CTRL_CMD_GR_GET_INFO 166 * 167 * This command returns graphics engine information for the associate GPU. 168 * Request to retrieve graphics information use a list of one or more 169 * NV0080_CTRL_GR_INFO structures. 170 * 171 * grInfoListSize 172 * This field specifies the number of entries on the caller's 173 * grInfoList. 174 * grInfoList 175 * This field specifies a pointer in the caller's address space 176 * to the buffer into which the bus information is to be returned. 177 * This buffer must be at least as big as grInfoListSize multiplied 178 * by the size of the NV0080_CTRL_GR_INFO structure. 179 */ 180 #define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */ 181 182 #define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U) 183 184 typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS { 185 NvU32 grInfoListSize; 186 NV_DECLARE_ALIGNED(NvP64 grInfoList, 8); 187 } NV0080_CTRL_GR_GET_INFO_PARAMS; 188 189 /* 190 * NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE 191 * This command gets the current partition mode of a TSG context. 192 * 193 * NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE 194 * This command sets the partition mode of a TSG context. 195 * 196 * NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS 197 * This structure defines the parameters used for TPC partitioning mode SET/GET commands 198 * 199 * hChannelGroup [IN] 200 * RM Handle to the TSG 201 * 202 * mode [IN/OUT] 203 * Partitioning mode enum value 204 * For the SET cmd, this is an input parameter 205 * For the GET cmd, this is an output parameter 206 * 207 * bEnableAllTpcs [IN] 208 * Flag to enable all TPCs by default 209 * 210 * grRouteInfo[IN] 211 * This parameter specifies the routing information used to 212 * disambiguate the target GR engine. 213 * 214 */ 215 #define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ 216 217 #define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ 218 219 /* Enum for listing TPC partitioning modes */ 220 typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE { 221 NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0, 222 NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1, 223 NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2, 224 } NV0080_CTRL_GR_TPC_PARTITION_MODE; 225 226 typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS { 227 NvHandle hChannelGroup; // [in] 228 NV0080_CTRL_GR_TPC_PARTITION_MODE mode; // [in/out] 229 NvBool bEnableAllTpcs; // [in/out] 230 NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in] 231 } NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS; 232 233 #define NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x7U) 234 235 typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS; 236 237 #define NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x8U) 238 239 typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; 240 241 /** 242 * NV0080_CTRL_CMD_GR_GET_CAPS_V2 243 * 244 * This command returns the same set of graphics capabilities for the device 245 * as @ref NV0080_CTRL_CMD_GR_GET_CAPS. The difference is in the structure 246 * NV0080_CTRL_GR_GET_INFO_V2_PARAMS, which contains a statically sized array, 247 * rather than a caps table pointer and a caps table size in 248 * NV0080_CTRL_GR_GET_INFO_PARAMS. Additionally, 249 * NV0080_CTRL_GR_GET_INFO_V2_PARAMS contains a parameter for specifying routing 250 * information, used for MIG. 251 * 252 * capsTbl 253 * This parameter specifies a pointer to the client's caps table buffer 254 * into which the graphics caps bits will be written by the RM. 255 * The caps table is an array of unsigned bytes. 256 * 257 * grRouteInfo 258 * This parameter specifies the routing information used to 259 * disambiguate the target GR engine. 260 * 261 * bCapsPopulated 262 * This parameter indicates that the capsTbl has been partially populated by 263 * previous calls to NV0080_CTRL_CMD_GR_GET_CAPS_V2 on other subdevices. 264 */ 265 #define NV0080_CTRL_CMD_GR_GET_CAPS_V2 (0x801109) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ 266 267 #define NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x9U) 268 269 typedef struct NV0080_CTRL_GR_GET_CAPS_V2_PARAMS { 270 NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 271 NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 272 NvBool bCapsPopulated; 273 } NV0080_CTRL_GR_GET_CAPS_V2_PARAMS; 274 275 #define NV0080_CTRL_CMD_GR_GET_INFO_V2 (0x801110) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID" */ 276 277 #define NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID (0x10U) 278 279 typedef struct NV0080_CTRL_GR_GET_INFO_V2_PARAMS { 280 NvU32 grInfoListSize; 281 NV0080_CTRL_GR_INFO grInfoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; 282 NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 283 } NV0080_CTRL_GR_GET_INFO_V2_PARAMS; 284 285 /* _ctrl0080gr_h_ */ 286