1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl2080/ctrl2080fifo.finn 31 // 32 33 #include "nvcfg_sdk.h" 34 #include "ctrl/ctrl2080/ctrl2080base.h" 35 36 /* 37 * NV2080_CTRL_CMD_SET_GPFIFO 38 * 39 * This command set the GPFIFO offset and number of entries for a channel 40 * after it has been allocated. The channel must be idle and not pending, 41 * otherwise ERROR_IN_USE will be returned. 42 * 43 * hChannel 44 * The handle to the channel. 45 * base 46 * The base of the GPFIFO in the channel ctxdma. 47 * numEntries 48 * The number of entries in the GPFIFO. 49 * 50 * Possible status values returned are: 51 * NV_OK 52 * NV_ERR_INVALID_DEVICE 53 * NV_ERR_INVALID_CHANNEL 54 * NV_ERR_STATE_IN_USE 55 * NV_ERR_INVALID_ARGUMENT 56 * 57 */ 58 #define NV2080_CTRL_CMD_SET_GPFIFO (0x20801102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID" */ 59 60 #define NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID (0x2U) 61 62 typedef struct NV2080_CTRL_CMD_SET_GPFIFO_PARAMS { 63 NvHandle hChannel; 64 NV_DECLARE_ALIGNED(NvU64 base, 8); 65 NvU32 numEntries; 66 } NV2080_CTRL_CMD_SET_GPFIFO_PARAMS; 67 68 /* 69 * NV2080_CTRL_FIFO_BIND_CHANNEL 70 * 71 * This structure is used to describe a channel that is to have 72 * it's bindable engines bound to those of other channels. 73 * 74 * hClient 75 * This structure member contains the handle of the client object 76 * that owns the channel object specified by hChannel. 77 * 78 * hChannel 79 * This structure member contains the channel handle of the channel 80 * object. 81 */ 82 83 typedef struct NV2080_CTRL_FIFO_BIND_CHANNEL { 84 NvHandle hClient; 85 NvHandle hChannel; 86 } NV2080_CTRL_FIFO_BIND_CHANNEL; 87 88 /* 89 * NV2080_CTRL_CMD_FIFO_BIND_ENGINES 90 * 91 * This control call is now deprecated. 92 * This command can be used to bind different video engines on G8X from separate 93 * channels together for operations such as idling. The set of bindable engines 94 * includes the NV2080_ENGINE_TYPE_BSP, NV2080_ENGINE_TYPE_VP and 95 * NV2080_ENGINE_TYPE_PPP engines. 96 * 97 * bindChannelCount 98 * This parameter specifies the number of channels to bind together. This 99 * parameter cannot exceed NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS. 100 * 101 * bindChannels 102 * The parameter specifies the array of channels to bind together. The first 103 * bindChannelCount entries are used in the bind channel operation. 104 * 105 * Possible status values returned are: 106 * NV_OK 107 * NV_ERR_INVALID_DEVICE 108 * NV_ERR_INVALID_CHANNEL 109 * NV_ERR_INVALID_ARGUMENT 110 * NV_ERR_NOT_SUPPORTED 111 */ 112 #define NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS (16) 113 114 #define NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID (0x3U) 115 116 typedef struct NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS { 117 NvU32 bindChannelCount; 118 NV2080_CTRL_FIFO_BIND_CHANNEL bindChannels[NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS]; 119 } NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS; 120 121 #define NV2080_CTRL_CMD_FIFO_BIND_ENGINES (0x20801103) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID" */ 122 123 /* 124 * NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES 125 * 126 * This command is used for a client to setup specialized custom operational 127 * properties that may be specific to an environment, or properties that 128 * should be set generally but are not for reasons of backward compatibility 129 * with previous chip generations 130 * 131 * flags 132 * This field specifies the operational properties to be applied 133 * 134 * Possible return status values returned are 135 * NV_OK 136 * NV_ERR_INVALID_CHANNEL 137 * NV_ERR_INVALID_ARGUMENT 138 * 139 */ 140 #define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES (0x20801104) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID" */ 141 142 #define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID (0x4U) 143 144 typedef struct NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS { 145 NvU32 flags; 146 } NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS; 147 148 #define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE 0:0 149 #define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE (0x00000000) 150 #define NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE (0x00000001) 151 152 /* 153 * NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT 154 * 155 * This command returns the maximum number of physical channels available for 156 * allocation on the current GPU. This may be less than or equal to the total 157 * number of channels supported by the current hardware. 158 * 159 * physChannelCount 160 * This output parameter contains the maximum physical channel count. 161 * 162 * physChannelCountInUse 163 * This output parameter contains the number of physical channels in use 164 * 165 * Possible return status values returned are 166 * NV_OK 167 * 168 */ 169 #define NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT (0x20801108) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID" */ 170 171 #define NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID (0x8U) 172 173 typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS { 174 NvU32 physChannelCount; 175 NvU32 physChannelCountInUse; 176 } NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS; 177 178 /* 179 * NV2080_CTRL_FIFO_INFO 180 * 181 * This structure represents a single 32bit fifo engine value. Clients 182 * request a particular FIFO engine value by specifying a unique fifo 183 * information index. 184 * 185 * Legal fifo information index values are: 186 * NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL 187 * This index can be used to request the amount of instance space 188 * in kilobytes reserved by the fifo engine. 189 * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS 190 * This index can be used to query the maximum number of channel groups 191 * that can be allocated on the GPU. 192 * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP 193 * This index can be used to query the maximum number of channels that can 194 * be allocated in a single channel group. 195 * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP 196 * This index can be used to query the maximum number of subcontext that can 197 * be allocated in a single channel group. 198 * NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET 199 * This index can be used to query the starting offset of the RM 200 * pre-allocated USERD range in BAR1. This index query is honored only 201 * on Legacy-vGPU host RM. 202 * NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE 203 * This index can be used to query the default timeslice value 204 * (microseconds) used for a channel or channel group. 205 * NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE 206 * This index can be used to query the number of channel groups that are 207 * already allocated on the GPU. 208 * NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED 209 * This index can be used to check if per runlist channel ram is supported, and 210 * to query the supported number of channels per runlist. 211 * NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE 212 * This index can be used to get max channel groups supported per engine/runlist. 213 * NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE 214 * This index can be used too get channel groups currently in use per engine/runlist. 215 * 216 */ 217 typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO; 218 219 /* valid fifo info index values */ 220 #define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000) 221 #define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS (0x000000001) 222 #define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP (0x000000002) 223 #define NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP (0x000000003) 224 #define NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET (0x000000004) 225 #define NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE (0x000000005) 226 #define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE (0x000000006) 227 #define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007) 228 #define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE (0x000000008) 229 #define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE (0x000000009) 230 231 232 /* set INDEX_MAX to greatest possible index value */ 233 #define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE 234 235 #define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT (12) 236 237 /* 238 * NV2080_CTRL_CMD_FIFO_GET_INFO 239 * 240 * This command returns fifo engine information for the associated GPU. 241 * Requests to retrieve fifo information use an array of one or more 242 * NV2080_CTRL_FIFO_INFO structures. 243 * 244 * fifoInfoTblSize 245 * This field specifies the number of valid entries in the fifoInfoList 246 * array. This value cannot exceed NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES. 247 * fifoInfoTbl 248 * This parameter contains the client's fifo info table into 249 * which the fifo info values will be transferred by the RM. 250 * The fifo info table is an array of NV2080_CTRL_FIFO_INFO structures. 251 * 252 * Possible status values returned are: 253 * NV_OK 254 * NV_ERR_INVALID_PARAM_STRUCT 255 * NV_ERR_INVALID_ARGUMENT 256 */ 257 #define NV2080_CTRL_CMD_FIFO_GET_INFO (0x20801109) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID" */ 258 259 /* maximum number of NV2080_CTRL_FIFO_INFO entries per request */ 260 #define NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES (256) 261 262 #define NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID (0x9U) 263 264 typedef struct NV2080_CTRL_FIFO_GET_INFO_PARAMS { 265 NvU32 fifoInfoTblSize; 266 /* 267 * C form: 268 * NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES]; 269 */ 270 NV2080_CTRL_FIFO_INFO fifoInfoTbl[NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES]; 271 NvU32 engineType; 272 } NV2080_CTRL_FIFO_GET_INFO_PARAMS; 273 274 275 276 /* 277 * NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL 278 * 279 * This command removes the specified channel from the associated GPU's runlist 280 * and then initiates RC recovery. If the channel is active it will first be preempted. 281 * hChannel 282 * The handle to the channel to be preempted. 283 * 284 * Possible status values returned are: 285 * NV_OK 286 * NV_ERR_INVALID_CHANNEL 287 */ 288 #define NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL (0x2080110a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID" */ 289 290 #define NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID (0xAU) 291 292 typedef struct NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS { 293 NvHandle hChannel; 294 } NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS; 295 296 /* 297 * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS 298 * 299 * This command will disable or enable scheduling of channels described in the 300 * list provided. Whether or not the channels are also preempted off the GPU 301 * can be controlled by bOnlyDisableScheduling. By default channels are preempted 302 * off the GPU. 303 * 304 * bDisable 305 * This value determines whether to disable or 306 * enable the set of channels. 307 * numChannels 308 * The number of channels to be stopped. 309 * bOnlyDisableScheduling 310 * When false and bDisable=NV_TRUE,the call will ensure none of the listed 311 * channels are running in hardware and will not run until a call with 312 * bDisable=NV_FALSE is made. When true and bDisable=NV_TRUE, the control 313 * call will ensure that none of the listed channels can be scheduled on the 314 * GPU until a call with bDisable=NV_FALSE is made, but will not remove any 315 * of the listed channels from hardware if they are currently running. When 316 * bDisable=NV_FALSE this field is ignored. 317 * bRewindGpPut 318 * If a channel is being disabled and bRewindGpPut=NV_TRUE, the channel's RAMFC 319 * will be updated so that GP_PUT is reset to the value of GP_GET. 320 * hClientList 321 * An array of NvU32 listing the client handles 322 * hChannelList 323 * An array of NvU32 listing the channel handles 324 * to be stopped. 325 * pRunlistPreemptEvent 326 * KEVENT handle for Async HW runlist preemption (unused on preMaxwell) 327 * When NULL, will revert to synchronous preemption with spinloop 328 * 329 * Possible status values returned are: 330 * NV_OK 331 * NVOS_INVALID_STATE 332 */ 333 334 #define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS (0x2080110b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */ 335 336 #define NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES (64) 337 338 #define NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0xBU) 339 340 typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS { 341 NvBool bDisable; 342 NvU32 numChannels; 343 NvBool bOnlyDisableScheduling; 344 NvBool bRewindGpPut; 345 NV_DECLARE_ALIGNED(NvP64 pRunlistPreemptEvent, 8); 346 // C form: NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES] 347 NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; 348 // C form: NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES] 349 NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; 350 } NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS; 351 352 #define NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE (0x00000000) 353 #define NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE (0x00000001) 354 #define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE (0x00000000) 355 #define NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE (0x00000001) 356 357 /* 358 * NV2080_CTRL_FIFO_MEM_INFO 359 * 360 * This structure describes the details of a block of memory. It consists 361 * of the following fields 362 * 363 * aperture 364 * One of the NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_* values 365 * base 366 * Physical base address of the memory 367 * size 368 * Size in bytes of the memory 369 */ 370 typedef struct NV2080_CTRL_FIFO_MEM_INFO { 371 NvU32 aperture; 372 NV_DECLARE_ALIGNED(NvU64 base, 8); 373 NV_DECLARE_ALIGNED(NvU64 size, 8); 374 } NV2080_CTRL_FIFO_MEM_INFO; 375 376 /* 377 * NV2080_CTRL_FIFO_CHANNEL_MEM_INFO 378 * 379 * This structure describes the details of the instance memory, ramfc 380 * and method buffers a channel. It consists of the following fields 381 * 382 * inst 383 * Structure describing the details of instance memory 384 * ramfc 385 * Structure describing the details of ramfc 386 * methodBuf 387 * Array of structures describing the details of method buffers 388 * methodBufCount 389 * Number of method buffers(one per runqueue) 390 */ 391 392 // max runqueues 393 #define NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT 0x2 394 395 typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO { 396 NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO inst, 8); 397 NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO ramfc, 8); 398 NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_MEM_INFO methodBuf[NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT], 8); 399 NvU32 methodBufCount; 400 } NV2080_CTRL_FIFO_CHANNEL_MEM_INFO; 401 402 /* 403 * NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM 404 * 405 * This command returns the memory aperture, physical base address and the 406 * size of each of the instance memory, cache1 and ramfc of a channel. 407 * 408 * hChannel 409 * The handle to the channel for which the memory information is desired. 410 * chMemInfo 411 * A NV2080_CTRL_FIFO_CHANNEL_MEM_INFO structure 412 * 413 * Possible status values returned are: 414 * NV_OK 415 * NV_ERR_INVALID_CHANNEL 416 */ 417 418 #define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO (0x2080110c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID" */ 419 420 #define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID (0xCU) 421 422 typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS { 423 NvHandle hChannel; 424 NV_DECLARE_ALIGNED(NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo, 8); 425 } NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS; 426 427 #define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID 0x00000000 428 #define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM 0x00000001 429 #define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH 0x00000002 430 #define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH 0x00000003 431 432 /* 433 * NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION 434 * 435 * This command determines the location (vidmem/sysmem) 436 * and attribute (cached/uncached/write combined) of memory where USERD is located. 437 * 438 * aperture 439 * One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_* values. 440 * 441 * attribute 442 * One of the NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_* values. 443 * 444 * Possible status values returned are: 445 * NV_OK 446 * NV_ERR_INVALID_DEVICE 447 * NV_ERR_INVALID_STATE 448 * NV_ERR_INVALID_POINTER 449 */ 450 451 #define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION (0x2080110d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID" */ 452 453 #define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID (0xDU) 454 455 typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS { 456 NvU32 aperture; 457 NvU32 attribute; 458 } NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS; 459 460 // support for CPU coherent vidmem (VIDMEM_NVILINK_COH) is not yet available in RM 461 462 #define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM 0x00000000 463 #define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM 0x00000001 464 465 #define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED 0x00000000 466 #define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED 0X00000001 467 #define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002 468 469 470 #define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN 0 471 #define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER 1 472 #define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT 2 473 #define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE 3 474 #define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE 4 475 476 // Count of the supported vGPU scheduler policies 477 #define NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT 3 478 479 #define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT 0 480 #define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE 1 481 #define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE 2 482 483 /* 484 * NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG 485 * 486 * This command returns the OBJSCHED_SW log enties. 487 * 488 * engineId 489 * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log 490 * entries are to be fetched. 491 * 492 * count 493 * This field returns the count of log entries fetched. 494 * 495 * entry 496 * The array of SW runlist log entries. 497 * 498 * timestampNs 499 * Timestamp in ns when this SW runlist was preeempted. 500 * 501 * timeRunTotalNs 502 * Total time in ns this SW runlist has run as compared to others. 503 * 504 * timeRunNs 505 * Time in ns this SW runlist ran before preemption. 506 * 507 * swrlId 508 * SW runlist Id. 509 * 510 * schedPolicy 511 * This field returns the runlist scheduling policy. It specifies the 512 * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. 513 * 514 * arrEnabled 515 * This field returns if Adaptive round robin scheduler 516 * is enabled/disabled. 517 * 518 * arrAvgFactor 519 * This field returns the average factor to be used in compensating the timeslice 520 * for Adaptive scheduler mode. 521 * 522 * targetTimesliceNs 523 * This field returns the target timeslice duration in ns for each SW runlist 524 * as configured by the user or the default value otherwise. 525 * 526 * Possible status values returned are: 527 * NV_OK 528 * NV_ERR_INVALID_ARGUMENT 529 */ 530 531 #define NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG (0x2080110e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID" */ 532 533 #define NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT 32 534 #define NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS 8 535 #define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES 200 536 537 #define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID (0xEU) 538 539 typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS { 540 NvU32 engineId; 541 NvU32 count; 542 struct { 543 NV_DECLARE_ALIGNED(NvU64 timestampNs, 8); 544 NV_DECLARE_ALIGNED(NvS64 timeRunTotalNs, 8); 545 NvU32 timeRunNs; 546 NvU32 swrlId; 547 NvU32 targetTimeSlice; 548 NV_DECLARE_ALIGNED(NvU64 cumulativePreemptionTime, 8); 549 NV_DECLARE_ALIGNED(NvU64 counters[NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS], 8); 550 } entry[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES]; 551 NvU32 schedPolicy; 552 NvU32 arrEnabled; 553 NvU32 arrAvgFactor; 554 NvU32 targetTimesliceNs; 555 } NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS; 556 557 558 559 /* 560 * NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE 561 * 562 * This command retrieves entries from the SW encoded GPU device info table 563 * from Host RM. 564 * 565 * Parameters: 566 * 567 * baseIndex [in] 568 * The starting index to read from the devinfo table. Must be a multiple of 569 * MAX_ENTRIES. 570 * 571 * entries [out] 572 * A buffer to store up to MAX_ENTRIES entries of the devinfo table. 573 * 574 * numEntries [out] 575 * Number of populated entries in the provided buffer. 576 * 577 * bMore [out] 578 * A boolean flag indicating whether more valid entries are available to be 579 * read. A value of NV_TRUE indicates that a further call to this control 580 * with baseIndex incremented by MAX_ENTRIES will yield further valid data. 581 * 582 * Possible status values returned are: 583 * NV_OK 584 */ 585 #define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ 586 587 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES 256 588 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES 32 589 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES 16 590 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA 2 591 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16 592 593 /* 594 * NV2080_CTRL_FIFO_DEVICE_ENTRY 595 * 596 * This structure contains the engine, engine name and 597 * push buffers information of FIFO device entry. It consists of the following fields 598 * 599 * engineData 600 * Type of the engine 601 * pbdmaIds 602 * List of pbdma ids associated with engine 603 * pbdmaFaultIds 604 * List of pbdma fault ids associated with engine 605 * numPbdmas 606 * Number of pbdmas 607 * engineName 608 * Name of the engine 609 */ 610 typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY { 611 NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES]; 612 NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; 613 NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; 614 NvU32 numPbdmas; 615 char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN]; 616 } NV2080_CTRL_FIFO_DEVICE_ENTRY; 617 618 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x12U) 619 620 typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS { 621 NvU32 baseIndex; 622 NvU32 numEntries; 623 NvBool bMore; 624 // C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; 625 NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; 626 } NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS; 627 628 /* 629 * NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT 630 * 631 * This command clears the ENGINE or PBDMA FAULTED bit and reschedules the faulted channel 632 * by ringing channel's doorbell 633 * 634 * Parameters: 635 * 636 * engineType [in] 637 * The NV2080_ENGINE_TYPE of the engine to which the faulted 638 * channel is bound. This may be a logical id for guest RM in 639 * case of SMC. 640 * 641 * vChid [in] 642 * Virtual channel ID on which the fault occurred 643 * 644 * faultType [in] 645 * Whether fault was triggered by engine (_ENGINE_FAULTED) or PBDMA (_PBDMA_FAULTED) 646 * The value specified must be one of the NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_* values 647 * 648 * Possible status values returned are: 649 * NV_OK 650 * NV_ERR_INVALID_STATE 651 * NV_ERR_INVALID_ARGUMENT 652 */ 653 #define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT (0x20801113) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID" */ 654 655 #define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE 0x00000001 656 #define NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA 0x00000002 657 658 #define NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID (0x13U) 659 660 typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS { 661 NvU32 engineType; 662 NvU32 vChid; 663 NvU32 faultType; 664 } NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS; 665 666 667 668 /* 669 * NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY 670 * 671 * Allows clients to set the global scheduling policy for all runlists 672 * associated to the given subdevice. 673 * 674 * Currently, this is only supported for HW runlists. 675 * 676 * Since this is a global setting, only privileged clients will be allowed to 677 * set it. Regular clients will get NV_ERR_INSUFFICIENT_PERMISSIONS error. 678 * 679 * Once a certain scheduling policy is set, that policy cannot be changed to a 680 * different one unless all clients which set it have either restored the policy 681 * (using the corresponding restore flag) or died. Clients trying to set a 682 * policy while a different one is locked by another client will get a 683 * NV_ERR_INVALID_STATE error. 684 * 685 * The same client can set a scheduling policy and later change to another one 686 * only when no other clients have set the same policy. Such sequence will be 687 * equivalent to restoring the policy in between. 688 * 689 * For instance, the following sequence: 690 * 691 * 1. Set policy A 692 * 2. Set policy B 693 * 694 * is equivalent to: 695 * 696 * 1. Set policy A 697 * 2. Restore policy 698 * 3. Set policy B 699 * 700 * Parameters: 701 * 702 * flags 703 * This field specifies the operational properties to be applied: 704 * 705 * - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE 706 * Try to set the provided 'schedPolicy' scheduling policy. If the 707 * operation succeeds, other clients will be prevented from setting a 708 * different scheduling policy until all clients using it have either 709 * restored it or died. 710 * 711 * - NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE 712 * Let the scheduler know the client no longer requires the current 713 * scheduling policy. This may or may not actually change the 714 * scheduling policy, depending on how many other clients are also 715 * using the current policy. 716 * 717 * The 'schedPolicy' parameter is ignored when this flag is set. 718 * 719 * schedPolicy 720 * One of: 721 * 722 * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT 723 * Set the default scheduling policy and prevent other clients from 724 * changing it. 725 * 726 * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED 727 * This scheduling policy will make channels to be scheduled according 728 * to their interleave level. See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL 729 * description for more details. 730 * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM 731 * This scheduling policy will make channels to be scheduled according 732 * to their interleave level per WDDM policy. 733 * See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details. 734 * 735 * Possible status values returned are: 736 * NV_OK 737 * NV_ERR_INVALID_DEVICE 738 * NV_ERR_INVALID_PARAM_STRUCT 739 * NV_ERR_INSUFFICIENT_PERMISSIONS 740 * NV_ERR_INVALID_STATE 741 * NV_ERR_NOT_SUPPORTED 742 */ 743 #define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY (0x20801115) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID" */ 744 745 /* schedPolicy values */ 746 #define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT 0x0 747 #define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED 0x1 748 #define NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM 0x2 749 750 /* SET_SCHED_POLICY flags */ 751 #define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE 0:0 752 #define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE (0x00000000) 753 #define NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE (0x00000001) 754 755 #define NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID (0x15U) 756 757 typedef struct NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS { 758 NvU32 flags; 759 NvU32 schedPolicy; 760 } NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS; 761 762 /* 763 * NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO 764 * 765 * This command updates the channel info params for an existing channel 766 * 767 * Can be a deferred Api. The control call can be used for migrating a 768 * 769 * channel to a new userd and gpfifo 770 * 771 * Parameters: 772 * [in] hClient - Client handle 773 * [in] hChannel - Channel handle 774 * [in] hUserdMemory - UserD handle 775 * [in] gpFifoEntries - Number of Gpfifo Entries 776 * [in] gpFifoOffset - Gpfifo Virtual Offset 777 * [in] userdOffset - UserD offset 778 * 779 * 780 * Possible status values returned are: 781 * NV_OK 782 * NV_ERR_INVALID_STATE 783 * NV_ERR_INVALID_ARGUMENT 784 */ 785 #define NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO (0x20801116) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID" */ 786 787 #define NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID (0x16U) 788 789 typedef struct NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS { 790 NvHandle hClient; 791 NvHandle hChannel; 792 NvHandle hUserdMemory; 793 NvU32 gpFifoEntries; 794 NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); 795 NV_DECLARE_ALIGNED(NvU64 userdOffset, 8); 796 } NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS; 797 798 /* 799 * NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS 800 * 801 * This command will disable or enable scheduling of all usermode channels. 802 * 803 * bDisable 804 * This value determines whether to disable or enable the usermode channels. 805 * 806 * Possible status values returned are: 807 * NV_OK 808 * NV_ERR_INVALID_ARGUMENT 809 */ 810 #define NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS (0x20801117) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID" */ 811 812 #define NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID (0x17U) 813 814 typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS { 815 NvBool bDisable; 816 } NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS; 817 818 /* 819 * NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB 820 * 821 * When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy 822 * page allocated by guest RM in GPA space. This command provides the parameters 823 * of the guest RMs memory descriptor to be able to create a corresponding 824 * memory descriptor on the host RM. Host RM uses this to program the PDB of a 825 * zombie subcontext. 826 * 827 * Parameters: 828 * Input parameters to describe the memory descriptor 829 * [in] base 830 * [in] size 831 * [in] addressSpace 832 * [in] cacheAttrib 833 */ 834 #define NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB (0x20801118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID" */ 835 836 #define NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID (0x18U) 837 838 typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS { 839 NV_DECLARE_ALIGNED(NvU64 base, 8); 840 NV_DECLARE_ALIGNED(NvU64 size, 8); 841 NvU32 addressSpace; 842 NvU32 cacheAttrib; 843 } NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS; 844 845 /* 846 * NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS 847 * 848 * Get's a bitmask of allocated channels. No guarantees are made about 849 * synchronization. A channel returned as allocated by this ctrl cmd might have 850 * already been destructed. 851 * 852 * Parameters: 853 * [in] runlistId 854 * [in,out] bitMask A 1 bit indicates that a channel with this index/id is 855 * allocated. This field is a multiple of 32 bits and each 32 856 * bit group must be accessed as a platform 32 bit int to 857 * correctly map channel IDs. 858 * 859 */ 860 #define NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS (0x20801119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID" */ 861 862 /* 863 * The maximum number than can be returned by 864 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS 865 */ 866 #define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS 4096 867 868 #define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID (0x19U) 869 870 typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS { 871 NvU32 runlistId; 872 NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32]; 873 } NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS; 874 875 /* 876 * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION 877 * 878 * This command will disable and preempt channels described in the 879 * list provided and mark them ready for key rotation. 880 * hClient <-> hChannel pairs should use the same index in the arrays. 881 * 882 * numChannels 883 * The number of valid entries in hChannelList array. 884 * hClientList 885 * An array of NvHandle listing the client handles 886 * hChannelList 887 * An array of NvHandle listing the channel handles 888 * to be stopped. 889 * bEnableAfterKeyRotation 890 * This determines if channel is enabled by RM after it completes key rotation. 891 * Possible status values returned are: 892 * NV_OK 893 * NVOS_INVALID_STATE 894 */ 895 #define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION (0x2080111a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */ 896 897 #define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES (64) 898 899 #define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0x1AU) 900 901 typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS { 902 NvU32 numChannels; 903 NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; 904 NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; 905 NvBool bEnableAfterKeyRotation; 906 } NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS; 907 908 909 910 /* 911 * NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE 912 * 913 * This command returns the vGPU schedular state. 914 * 915 * engineId 916 * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log 917 * entries are to be fetched. 918 * 919 * schedPolicy 920 * This field returns the runlist scheduling policy. It specifies the 921 * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. 922 * 923 * arrEnabled 924 * This field returns if Adaptive round robin scheduler 925 * is enabled/disabled. 926 * 927 * targetTimesliceNs 928 * This field returns the target timeslice duration in ns for each SW runlist 929 * as configured by the user or the default value otherwise. 930 * 931 * arrAvgFactor 932 * This field returns the average factor to be used in compensating the timeslice 933 * for Adaptive scheduler mode. 934 * 935 * Possible status values returned are: 936 * NV_OK 937 * NV_ERR_INVALID_ARGUMENT 938 */ 939 940 #define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE (0x20801120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID" */ 941 942 #define NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID (0x20U) 943 944 typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS { 945 NvU32 engineId; 946 NvU32 schedPolicy; 947 NvU32 arrEnabled; 948 NvU32 targetTimesliceNs; 949 NvU32 arrAvgFactor; 950 } NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS; 951 952 /* 953 * NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE 954 * 955 * This command set the vGPU schedular state. 956 * 957 * engineId 958 * This field specifies the NV2080_ENGINE_TYPE_* engine. 959 * 960 * schedPolicy 961 * This field sets the runlist scheduling policy. It specifies the 962 * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. 963 * 964 * enableArr 965 * This field sets the Adaptive round robin scheduler 966 * is enabled/disabled. 967 * 968 * timesliceTargetNs 969 * This field sets the time slice target time in ns. 970 * 971 * frequencyForARR 972 * This field sets the scheduling frequency for Adaptive round robin scheduler mode. 973 * 974 * avgFactorForARR 975 * This field sets the average factor to be used in compensating the timeslice 976 * for Adaptive scheduler mode. 977 * 978 * Possible status values returned are: 979 * NV_OK 980 * NV_ERR_INVALID_DEVICE 981 * NV_ERR_INVALID_STATE 982 * NV_ERR_NOT_SUPPORTED 983 * NV_ERR_INSUFFICIENT_PERMISSIONS 984 * NV_ERR_INVALID_ARGUMENT 985 * NV_ERR_INVALID_PARAM_STRUCT 986 */ 987 988 #define NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE (0x20801121) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID" */ 989 990 #define NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID (0x21U) 991 992 typedef struct NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS { 993 NvU32 engineId; 994 NvU32 schedPolicy; 995 NvU32 enableArr; 996 NvU32 timesliceTargetNs; 997 NvU32 frequencyForARR; 998 NvU32 avgFactorForARR; 999 } NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS; 1000 1001 /* 1002 * NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS 1003 * 1004 * This command returns the vGPU schedular capabilities. 1005 * 1006 * engineId [in] 1007 * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log 1008 * entries are to be fetched. 1009 * 1010 * supportedSchedulers [out] 1011 * This field returns the supported runlist scheduling policies on the device. 1012 * It specifies the NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. 1013 * 1014 * bIsArrModeSupported [out] 1015 * This field returns if Adaptive scheduler mode is enabled/disabled. 1016 * 1017 * maxTimesliceNs [out] 1018 * This field returns the maximum time slice value in ns. 1019 * 1020 * minTimesliceNs [out] 1021 * This field returns the minimum time slice value in ns. 1022 * 1023 * maxFrequencyForARR [out] 1024 * This field returns the maximum scheduling frequency for 1025 * Adaptive round robin scheduler mode. 1026 * 1027 * minFrequencyForARR [out] 1028 * This field returns the minimum scheduling frequency for 1029 * Adaptive round robin scheduler mode. 1030 * 1031 * maxAvgFactorForARR [out] 1032 * This field returns the maximum average factor in compensating 1033 * the timeslice for Adaptive scheduler mode. 1034 * 1035 * minAvgFactorForARR [out] 1036 * This field returns the minimum average factor in compensating 1037 * the timeslice for Adaptive scheduler mode. 1038 * 1039 * Possible status values returned are: 1040 * NV_OK 1041 * NV_ERR_INVALID_ARGUMENT 1042 */ 1043 1044 #define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS (0x20801122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID" */ 1045 1046 #define NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID (0x22U) 1047 1048 typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS { 1049 NvU32 engineId; 1050 NvU32 supportedSchedulers[NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT]; 1051 NvBool bIsArrModeSupported; 1052 NvU32 maxTimesliceNs; 1053 NvU32 minTimesliceNs; 1054 NvU32 maxFrequencyForARR; 1055 NvU32 minFrequencyForARR; 1056 NvU32 maxAvgFactorForARR; 1057 NvU32 minAvgFactorForARR; 1058 } NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS; 1059 1060 /* _ctrl2080fifo_h_ */ 1061