1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl2080/ctrl2080internal.finn 31 // 32 33 #include "nvimpshared.h" 34 #include "ctrl/ctrl2080/ctrl2080base.h" 35 36 #include "ctrl/ctrl2080/ctrl2080gpu.h" 37 #include "ctrl/ctrl2080/ctrl2080gr.h" /* Some controls derivative of 2080gr */ 38 #include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */ 39 #include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ 40 #include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ 41 #include "ctrl/ctrl0000/ctrl0000system.h" 42 #include "ctrl/ctrl90f1.h" 43 #include "ctrl/ctrl30f1.h" 44 #include "nvcfg_sdk.h" 45 46 /*! 47 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO 48 * 49 * This command obtains information from physical RM for use by CPU-RM. 50 * 51 * feHwSysCap 52 * Display IP v03_00 and later. 53 * Contents of capability register. 54 * 55 * windowPresentMask 56 * Display IP v03_00 and later. 57 * Mask for the present WINDOWs actually on the current chip. 58 * bFbRemapperEnabled 59 * Display IP v02_01 and later. 60 * Indicates that the display remapper HW exists and is enabled. 61 * numHeads 62 * Display IP v02_01 and later. 63 * Provides the number of heads HW support. 64 */ 65 66 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 67 68 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U) 69 70 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { 71 NvU32 feHwSysCap; 72 NvU32 windowPresentMask; 73 NvBool bFbRemapperEnabled; 74 NvU32 numHeads; 75 NvBool bPrimaryVga; 76 NvU32 i2cPort; 77 NvU32 internalDispActiveMask; 78 } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; 79 80 81 82 // 83 // MemorySystem settings that are static after GPU state init/load is finished. 84 // 85 // Fields are shared between the VGPU guest/GSP Client as well as the VGPU 86 // host/GSP-RM. 87 // 88 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU) 89 90 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { 91 /*! Determines if RM should use 1 to 1 Comptagline allocation policy */ 92 NvBool bOneToOneComptagLineAllocation; 93 94 /*! Determines if RM should use 1 to 4 Comptagline allocation policy */ 95 NvBool bUseOneToFourComptagLineAllocation; 96 97 /*! Determines if RM should use raw Comptagline allocation policy */ 98 NvBool bUseRawModeComptaglineAllocation; 99 100 /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */ 101 NvBool bDisableCompbitBacking; 102 103 /*! Determine if we need to disable post L2 compression */ 104 NvBool bDisablePostL2Compression; 105 106 /*! Is ECC DRAM feature supported? */ 107 NvBool bEnabledEccFBPA; 108 109 NvBool bL2PreFill; 110 111 /*! L2 cache size */ 112 NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8); 113 114 NvBool bReservedMemAtBottom; 115 116 /*! Indicate whether fpba is present or not */ 117 NvBool bFbpaPresent; 118 119 /*! Size covered by one comptag */ 120 NvU32 comprPageSize; 121 122 /*! log32(comprPageSize) */ 123 NvU32 comprPageShift; 124 125 /*! Maximum number of pages that can be dynamaically blacklisted */ 126 NvU16 maximumBlacklistPages; 127 128 /*! RAM type */ 129 NvU32 ramType; 130 131 /*! LTC count */ 132 NvU32 ltcCount; 133 134 /*! LTS per LTC count */ 135 NvU32 ltsPerLtcCount; 136 137 /*! Ampere PLC bug */ 138 NvBool bDisablePlcForCertainOffsetsBug3046774; 139 140 /*! FB override Start KB */ 141 NV_DECLARE_ALIGNED(NvU64 fbOverrideStartKb, 8); 142 } NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; 143 144 /*! 145 * Retrieve Memory System Static data. 146 */ 147 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */ 148 149 /* 150 * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER 151 * 152 * This command sends access counter buffer pages allocated by CPU-RM 153 * to be setup and enabled in physical RM. 154 * 155 * bufferSize 156 * Size of the access counter buffer to register. 157 * 158 * bufferPteArray 159 * Pages of access counter buffer. 160 * 161 * Possible status values returned are: 162 * NV_OK 163 */ 164 #define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ 165 166 #define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES 64 167 #define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) 168 169 typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { 170 NvU32 bufferSize; 171 NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); 172 } NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; 173 174 /* 175 * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER 176 * 177 * This command requests physical RM to disable the access counter buffer. 178 * 179 * Possible status values returned are: 180 * NV_OK 181 */ 182 #define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1E" */ 183 184 /* 185 * NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER 186 * 187 * This command requests physical RM to service the access counter buffer. 188 * 189 * Possible status values returned are: 190 * NV_OK 191 */ 192 #define NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x21" */ 193 194 /* 195 * NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE 196 * 197 * This command retrieves the access counter buffer size from physical RM. 198 * 199 * bufferSize[OUT] 200 * Size of the access counter buffer. 201 * 202 * Possible status values returned are: 203 * NV_OK 204 */ 205 #define NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ 206 207 #define NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x29U) 208 209 typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS { 210 NvU32 bufferSize; 211 } NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS; 212 213 #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 214 215 /*! 216 * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 217 */ 218 219 220 221 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { 222 NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 223 } NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; 224 225 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U) 226 227 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { 228 NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 229 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; 230 231 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */ 232 233 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU) 234 235 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS; 236 237 /*! 238 * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER 239 * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS 240 */ 241 242 243 244 #define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 245 246 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { 247 struct { 248 NvU16 gpcId; 249 NvU16 localTpcId; 250 NvU16 localSmId; 251 NvU16 globalTpcId; 252 NvU16 virtualGpcId; 253 NvU16 migratableTpcId; 254 } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM]; 255 256 NvU16 numSm; 257 NvU16 numTpc; 258 } NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; 259 260 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U) 261 262 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { 263 NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 264 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; 265 266 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ 267 268 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U) 269 270 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS; 271 272 /*! 273 * Retrieve BSP Static data. 274 */ 275 #define NV2080_CTRL_CMD_INTERNAL_BSP_GET_CAPS (0x20800a24) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */ 276 277 #define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS 8 278 279 typedef struct NV2080_CTRL_INTERNAL_BSP_CAPS { 280 NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; 281 } NV2080_CTRL_INTERNAL_BSP_CAPS; 282 283 #define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x24U) 284 285 typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS { 286 NV2080_CTRL_INTERNAL_BSP_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 287 NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 288 } NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS; 289 290 /*! 291 * Retrieve MSENC Static data. 292 */ 293 #define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */ 294 295 #define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 3 296 297 typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS { 298 NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE]; 299 } NV2080_CTRL_INTERNAL_MSENC_CAPS; 300 301 #define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x25U) 302 303 typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS { 304 NV2080_CTRL_INTERNAL_MSENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; 305 NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; 306 } NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS; 307 308 309 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 310 #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 311 312 /*! 313 * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK 314 * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK 315 * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK 316 */ 317 318 319 320 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { 321 NvU32 gpcMask; 322 323 /*! 324 * tpcMask is indexed by logical GPC ID for MIG case 325 * and indexed by physical GPC ID for non-MIG case 326 */ 327 NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 328 329 /*! 330 * tpcCount is always indexed by logical GPC ID 331 */ 332 NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 333 NvU32 physGpcMask; 334 NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 335 336 NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT]; 337 NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 338 339 /*! 340 * zcullMask is always indexed by physical GPC ID 341 */ 342 NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 343 344 NvU32 physGfxGpcMask; 345 NvU32 numGfxTpc; 346 } NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; 347 348 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U) 349 350 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { 351 /*! 352 * floorsweeping masks which are indexed via local GR index 353 */ 354 NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 355 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; 356 357 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */ 358 359 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U) 360 361 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS; 362 363 /* 364 * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES 365 * 366 * This command returns physical addresses of specified context buffer. 367 * To obtain addresses of whole buffer firstPage has to be advanced on 368 * subsequent invocations of the control until whole buffer is probed. 369 * If the buffer is contiguous, only single address will be returned by 370 * this control. 371 * 372 * bufferType[IN] 373 * Buffer type as returned by GET_CTX_BUFFER_INFO. 374 * 375 * firstPage[IN] 376 * Index of the first page to return in 'physAddrs' array. 377 * 378 * numPages[OUT] 379 * Number of entries filled in 'physAddrs' array. This will be 0 380 * if firstPage is greater or equal to number of pages managed by 'hBuffer'. 381 * 382 * physAddrs[OUT] 383 * Physical addresses of pages comprising specified buffer. 384 * 385 * bNoMorePages[OUT] 386 * End of buffer reached. Either 'physAddrs' contains last page of the 387 * buffer or 'firstPage' specifies index past the buffer. 388 */ 389 #define NV2080_CTRL_KGR_MAX_BUFFER_PTES 128 390 #define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */ 391 392 #define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U) 393 394 typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS { 395 NvHandle hUserClient; 396 NvHandle hChannel; 397 NvU32 bufferType; 398 NvU32 firstPage; 399 NvU32 numPages; 400 NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8); 401 NvBool bNoMorePages; 402 } NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS; 403 404 /*! 405 * @ref NV0080_CTRL_CMD_GR_GET_INFO 406 * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2 407 * @ref NV2080_CTRL_CMD_GR_GET_INFO 408 * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 409 */ 410 411 412 413 /*! 414 * @ref NV2080_CTRL_GR_INFO 415 */ 416 typedef struct NV2080_CTRL_INTERNAL_GR_INFO { 417 NvU32 index; 418 NvU32 data; 419 } NV2080_CTRL_INTERNAL_GR_INFO; 420 421 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { 422 NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; 423 } NV2080_CTRL_INTERNAL_STATIC_GR_INFO; 424 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU) 425 426 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { 427 NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 428 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; 429 430 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */ 431 432 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU) 433 434 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS; 435 436 /*! 437 * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO 438 */ 439 440 441 442 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO { 443 NvU32 widthAlignPixels; 444 NvU32 heightAlignPixels; 445 NvU32 pixelSquaresByAliquots; 446 NvU32 aliquotTotal; 447 NvU32 zcullRegionByteMultiplier; 448 NvU32 zcullRegionHeaderSize; 449 NvU32 zcullSubregionHeaderSize; 450 NvU32 subregionCount; 451 NvU32 subregionWidthAlignPixels; 452 NvU32 subregionHeightAlignPixels; 453 } NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; 454 455 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU) 456 457 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { 458 NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 459 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; 460 461 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ 462 463 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU) 464 465 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS; 466 467 /*! 468 * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO 469 */ 470 471 472 473 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO { 474 NvU32 ropUnitCount; 475 NvU32 ropOperationsFactor; 476 NvU32 ropOperationsCount; 477 } NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; 478 479 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU) 480 481 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { 482 NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 483 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; 484 485 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ 486 487 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU) 488 489 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS; 490 491 /*! 492 * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK 493 */ 494 495 496 497 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS { 498 NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 499 } NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; 500 501 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U) 502 503 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { 504 NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 505 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; 506 507 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */ 508 509 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U) 510 511 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS; 512 513 /*! 514 * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES 515 * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE 516 */ 517 518 519 520 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19 521 522 typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO { 523 NvU32 size; 524 NvU32 alignment; 525 } NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO; 526 527 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO { 528 NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; 529 } NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; 530 531 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U) 532 533 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { 534 NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 535 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; 536 537 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */ 538 539 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U) 540 541 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS; 542 543 /*! 544 * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER 545 */ 546 547 548 549 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER { 550 NvU8 imla0; 551 NvU8 fmla16; 552 NvU8 dp; 553 NvU8 fmla32; 554 NvU8 ffma; 555 NvU8 imla1; 556 NvU8 imla2; 557 NvU8 imla3; 558 NvU8 imla4; 559 } NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; 560 561 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U) 562 563 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { 564 NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 565 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; 566 567 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ 568 569 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U) 570 571 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; 572 573 /* 574 * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS 575 * 576 * This command obtains information from physical RM for use by CPU-RM. 577 */ 578 579 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */ 580 581 /* 582 * Maximum number of register bases to return. 583 * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs 584 * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h 585 */ 586 #define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16 587 #define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U) 588 589 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS { 590 NvU8 chipSubRev; 591 NvU32 emulationRev1; 592 NvBool isCmpSku; 593 NvU32 bar1Size; 594 NvU32 pciDeviceId; 595 NvU32 pciSubDeviceId; 596 NvU32 pciRevisionId; 597 NvU32 regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX]; 598 } NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS; 599 600 /** 601 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE 602 * 603 * Set whether or not context switch logging is enabled 604 * 605 * bEnable 606 * Enable/Disable status for context switch logging 607 */ 608 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ 609 610 /** 611 * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE 612 * 613 * Retrieve whether or not context switch logging is enabled 614 * 615 * bEnable 616 * Enable/Disable status for context switch logging 617 */ 618 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ 619 620 typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS { 621 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 622 NvBool bEnable; 623 } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; 624 625 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) 626 627 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; 628 629 #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) 630 631 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; 632 633 /** 634 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET 635 * 636 * Set read offset into FECS context switch trace record 637 * 638 * offset 639 * Value indicating number of records by which to offset 640 */ 641 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ 642 643 /** 644 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET 645 * 646 * Set write offset into FECS context switch trace record 647 * 648 * offset 649 * Value indicating number of records by which to offset 650 */ 651 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */ 652 653 /** 654 * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET 655 * 656 * Get read offset into FECS context switch trace record 657 * 658 * offset 659 * Value indicating number of records by which to offset 660 */ 661 662 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ 663 664 typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS { 665 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 666 NvU32 offset; 667 } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS; 668 669 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) 670 671 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; 672 673 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) 674 675 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; 676 677 #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) 678 679 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; 680 681 /** 682 * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE 683 * 684 * Get size of FECS record 685 * 686 * fecsRecordSize 687 * Size of FECS record 688 */ 689 690 691 692 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */ 693 694 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE { 695 NvU32 fecsRecordSize; 696 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE; 697 698 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU) 699 700 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { 701 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 702 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; 703 704 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) 705 706 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; 707 708 /** 709 * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES 710 * 711 * Get HW defines used to extract information from FECS records 712 * 713 * fecsRecordSize 714 * Size of FECS record 715 * 716 * timestampHiTagMask 717 * Mask for high bits of raw timestamp to extract tag 718 * 719 * timestampHiTagShift 720 * Shift for high bits of raw timestamp to extract tag 721 * 722 * timestampVMask 723 * Mask to extract timestamp from raw timestamp 724 * 725 * numLowerBitsZeroShift 726 * Number of bits timestamp is shifted by 727 */ 728 729 730 731 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { 732 NvU32 fecsRecordSize; 733 NvU32 timestampHiTagMask; 734 NvU8 timestampHiTagShift; 735 NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8); 736 NvU8 numLowerBitsZeroShift; 737 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; 738 739 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU) 740 741 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { 742 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); 743 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; 744 745 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */ 746 747 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU) 748 749 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS; 750 751 /** 752 * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE 753 * 754 * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel. 755 */ 756 typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { 757 NvU32 faultId; 758 NvU32 instanceId; 759 NvU32 typeEnum; 760 NvU32 resetId; 761 NvU32 devicePriBase; 762 NvU32 isEngine; 763 NvU32 rlEngId; 764 NvU32 runlistPriBase; 765 NvU32 groupId; 766 } NV2080_CTRL_INTERNAL_DEVICE_INFO; 767 #define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 88 768 769 #define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ 770 771 #define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U) 772 773 typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS { 774 NvU32 numEntries; 775 NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES]; 776 } NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS; 777 778 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */ 779 780 #define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE 4096 781 #define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096 782 783 #define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U) 784 785 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS { 786 NvU32 userRegisterAccessMapSize; 787 NvU32 compressedSize; 788 NvU8 compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE]; 789 NvU32 profilingRangesSize; 790 NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES]; 791 } NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS; 792 793 typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO { 794 NvU32 engDesc; 795 NvU32 ctxAttr; 796 NvU32 ctxBufferSize; 797 NvU32 addrSpaceList; 798 NvU32 registerBase; 799 } NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO; 800 #define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40 801 802 #define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ 803 804 #define NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0x42U) 805 806 typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS { 807 NvU32 numConstructedFalcons; 808 NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS]; 809 } NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS; 810 811 /** 812 * Get GR PDB properties synchronized between Kernel and Physical 813 * 814 * bPerSubCtxheaderSupported 815 * @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER 816 */ 817 818 819 820 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { 821 NvBool bPerSubCtxheaderSupported; 822 } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; 823 824 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U) 825 826 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { 827 NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 828 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; 829 830 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */ 831 832 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U) 833 834 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS; 835 836 /*! 837 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM 838 * 839 * This command writes instance memory information in the display hardware registers. 840 * 841 * instMemPhysAddr 842 * GPU physical address or IOVA address of the display instance memory. 843 * 844 * instMemSize 845 * Size of the display instance memory. 846 * 847 * instMemAddrSpace 848 * Address space of the display instance memory. 849 * 850 * instMemCpuCacheAttr 851 * Cache attribute of the display instance memory. 852 */ 853 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ 854 855 #define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U) 856 857 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { 858 NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); 859 NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); 860 NvU32 instMemAddrSpace; 861 NvU32 instMemCpuCacheAttr; 862 } NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; 863 864 /* 865 * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS 866 * 867 * This command issues RC recovery for all compute contexts running on the given GPU. 868 */ 869 #define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */ 870 871 /*! 872 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION 873 * 874 * This command obtains IP version of display engine for use by Kernel RM. 875 * 876 * ipVersion 877 * IP Version of display engine. 878 * 879 * Possible status values returned are: 880 * NV_OK 881 * NV_ERR_NOT_SUPPORTED - DISP has been disabled 882 */ 883 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ 884 885 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU) 886 887 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS { 888 NvU32 ipVersion; 889 } NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS; 890 891 /*! 892 * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE 893 * 894 * This command determines the current status of MIG MODE from Physical RM. 895 * 896 * smcMode [OUT] 897 * Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE* 898 */ 899 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */ 900 901 #define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU) 902 903 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS { 904 NvU32 smcMode; 905 } NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS; 906 907 /*! 908 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR 909 * 910 * head 911 * This parameter specifies the head for which the callback is to be registered/unregistered. This value must be 912 * less than the maximum number of heads supported by the GPU subdevice. 913 * 914 * rgLineNum 915 * This indicates the RG scanout line number on which the callback will be executed. 916 * 917 * intrLine 918 * Enable: [out] Which interrupt line was allocated for this head. 919 * Disable: [in] Which interrupt line to deallocate. 920 * 921 * bEnable 922 * Should we allocate or deallocate an interrupt line? 923 * 924 * Possible status values returned are: 925 * NV_OK 926 * NV_ERR_GENERIC - There was no available interrupt to allocate. 927 * NV_ERR_INVALID_ARGUMENT 928 */ 929 930 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */ 931 932 #define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU) 933 934 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { 935 NvU32 head; 936 NvU32 rgLineNum; 937 NvU32 intrLine; 938 NvBool bEnable; 939 } NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS; 940 941 /*! 942 * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO 943 * 944 * Description of a supported GPU instance. 945 * 946 * partitionFlag [OUT] 947 * Allocation flag to be used to allocate a partition with this profile. 948 * 949 * grCount [OUT] 950 * # GR engines, including the GFX capable ones. 951 * 952 * gfxGrCount [OUT] 953 * # GR engines capable of Gfx, which is a subset of the GR engines included in grCount 954 * 955 * gpcCount [OUT] 956 * # total gpcs, including the GFX capable ones. 957 * 958 * virtualGpcCount [OUT] 959 * # virtualized gpcs, including the GFX capable ones. 960 * 961 * gfxGpcCount [OUT] 962 * # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount. 963 * 964 * veidCount [OUT] 965 * # total veids 966 * 967 * smCount [OUT] 968 * # total SMs 969 * 970 * ceCount [OUT] 971 * # CE engines 972 * 973 * nvEncCount [OUT] 974 * # NVENC engines 975 * 976 * nvDecCount [OUT] 977 * # NVDEC engines 978 * 979 * nvJpgCount [OUT] 980 * # NVJPG engines 981 * 982 * nvOfaCount [OUT] 983 * # NVOFA engines 984 * 985 * validCTSIdMask [OUT] 986 * # mask of CTS IDs which can be assigned under this profile 987 */ 988 #define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20 989 990 991 992 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { 993 NvU32 partitionFlag; 994 NvU32 grCount; 995 NvU32 gfxGrCount; 996 NvU32 gpcCount; 997 NvU32 virtualGpcCount; 998 NvU32 gfxGpcCount; 999 NvU32 veidCount; 1000 NvU32 smCount; 1001 NvU32 ceCount; 1002 NvU32 nvEncCount; 1003 NvU32 nvDecCount; 1004 NvU32 nvJpgCount; 1005 NvU32 nvOfaCount; 1006 NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); 1007 } NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; 1008 1009 /*! 1010 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS 1011 * 1012 * Returns the list of supported GPU instance profiles. 1013 * 1014 * count [OUT] 1015 * Number of supported profiles. 1016 * 1017 * table [OUT] 1018 * Supported profiles. 1019 */ 1020 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU) 1021 1022 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { 1023 NvU32 count; 1024 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); 1025 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS; 1026 1027 /*! 1028 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM 1029 * 1030 * This command instructs the physical MemorySystem to set up memory partitioning 1031 * exterior boundaries in hardware. 1032 * 1033 * partitionableMemSize [input] 1034 * Size of the partitionable memory in bytes 1035 * 1036 * bottomRsvdSize [input] 1037 * Size of the reserved region below partitionable memory in bytes 1038 * 1039 * topRsvdSize [input] 1040 * Size of the reserved region above partitionable memory in bytes 1041 * 1042 * partitionableStartAddr [output] 1043 * Start address of the partitionable memory, aligned to HW constraints 1044 * 1045 * partitionableEndAddr [output] 1046 * End address of the partitionable memory, aligned to HW constraints 1047 */ 1048 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */ 1049 1050 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U) 1051 1052 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { 1053 NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8); 1054 NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8); 1055 NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8); 1056 NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8); 1057 NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8); 1058 } NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS; 1059 1060 1061 1062 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U) 1063 1064 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { 1065 NV_DECLARE_ALIGNED(NvU64 engineMask, 8); 1066 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; 1067 1068 1069 /*! 1070 * NV2080_CTRL_INTERNAL_MEMDESC_INFO 1071 * 1072 * A generic container structure representing a memory region to be used as a 1073 * component of other control call parameters. 1074 * 1075 */ 1076 typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO { 1077 NV_DECLARE_ALIGNED(NvU64 base, 8); 1078 NV_DECLARE_ALIGNED(NvU64 size, 8); 1079 NV_DECLARE_ALIGNED(NvU64 alignment, 8); 1080 NvU32 addressSpace; 1081 NvU32 cpuCacheAttrib; 1082 } NV2080_CTRL_INTERNAL_MEMDESC_INFO; 1083 1084 #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2 1085 #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID 64 1086 /*! 1087 * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS 1088 * 1089 * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM 1090 * 1091 * rlBuffers [IN] 1092 * 2D array of runlist buffers for a single partition 1093 * 1094 * runlistIdMask [IN] 1095 * Mask of runlists belonging to partition 1096 * 1097 */ 1098 #define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */ 1099 1100 #define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U) 1101 1102 typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS { 1103 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8); 1104 NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8); 1105 NvU32 swizzId; 1106 } NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS; 1107 1108 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */ 1109 1110 #define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U) 1111 1112 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { 1113 TEGRA_IMP_IMPORT_DATA tegraImpImportData; 1114 } NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; 1115 1116 /*! 1117 * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR 1118 * 1119 * This command triggers a sysmembar to flush VIDMEM writes. 1120 * This command accepts no parameters. 1121 * 1122 */ 1123 #define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */ 1124 1125 /* 1126 * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL 1127 * 1128 * Setup local PCIE P2P Mailbox 1129 * 1130 * local2Remote[IN] 1131 * Local peer ID of remote gpu on local gpu 1132 * 1133 * remote2Local[IN] 1134 * Remote peer ID of local gpu on remote gpu 1135 * 1136 * localP2PDomainRemoteAddr[IN] 1137 * P2P domain remote address on local gpu 1138 * 1139 * remoteP2PDomainLocalAddr[IN] 1140 * P2P domain local address on remote gpu 1141 * 1142 * remoteWMBoxLocalAddr[IN] 1143 * Local mailbox address on remote gpu 1144 * 1145 * p2pWmbTag[OUT] 1146 * Tag for mailbox to transport from local to remote GPU 1147 * 1148 * bNeedWarBug999673[IN] 1149 * Set to true if WAR for bug 999673 is required 1150 * 1151 * Possible status values returned are: 1152 * NV_OK 1153 * NV_ERR_NOT_SUPPORTED 1154 */ 1155 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */ 1156 1157 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U) 1158 1159 typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS { 1160 NvU32 local2Remote; 1161 NvU32 remote2Local; 1162 NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); 1163 NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); 1164 NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8); 1165 NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); 1166 NvBool bNeedWarBug999673; 1167 } NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS; 1168 1169 /* 1170 * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE 1171 * 1172 * Setup remote PCIE P2P Mailbox 1173 * 1174 * local2Remote[IN] 1175 * Local peer ID of remote gpu on local gpu 1176 * 1177 * remote2Local[IN] 1178 * Remote peer ID of local gpu on remote gpu 1179 * 1180 * localP2PDomainRemoteAddr[IN] 1181 * P2P domain remote address on local gpu 1182 * 1183 * remoteP2PDomainLocalAddr[IN] 1184 * P2P domain local address on remote gpu 1185 * 1186 * remoteWMBoxAddrU64[IN] 1187 * Mailbox address on remote gpu 1188 * 1189 * p2pWmbTag[IN] 1190 * Tag for mailbox to transport from local to remote GPU 1191 * 1192 * Possible status values returned are: 1193 * NV_OK 1194 * NV_ERR_NOT_SUPPORTED 1195 */ 1196 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */ 1197 1198 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U) 1199 1200 typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS { 1201 NvU32 local2Remote; 1202 NvU32 remote2Local; 1203 NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); 1204 NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); 1205 NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8); 1206 NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); 1207 } NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS; 1208 1209 /* 1210 * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX 1211 * 1212 * Destroy PCIE P2P Mailbox 1213 * 1214 * peerIdx[IN] 1215 * Peer ID of the P2P destination GPU 1216 * 1217 * bNeedWarBug999673[IN] 1218 * Set to true if WAR for bug 999673 is required 1219 * 1220 * Possible status values returned are: 1221 * NV_OK 1222 * NV_ERR_NOT_SUPPORTED 1223 */ 1224 #define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */ 1225 1226 #define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U) 1227 1228 typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS { 1229 NvU32 peerIdx; 1230 NvBool bNeedWarBug999673; 1231 } NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS; 1232 1233 /* 1234 * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING 1235 * 1236 * Create C2C mapping to a given peer GPU 1237 * 1238 * peerId[IN] 1239 * Peer ID for local to remote GPU 1240 * 1241 * Possible status values returned are: 1242 * NV_OK 1243 * NV_ERR_NOT_SUPPORTED 1244 */ 1245 #define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ 1246 1247 #define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U) 1248 1249 typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS { 1250 NvU32 peerId; 1251 } NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS; 1252 1253 /* 1254 * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING 1255 * 1256 * Remove C2C mapping to a given peer GPU 1257 * 1258 * peerId[IN] 1259 * Peer ID for local to remote GPU 1260 * 1261 * Possible status values returned are: 1262 * NV_OK 1263 * NV_ERR_NOT_SUPPORTED 1264 */ 1265 #define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ 1266 1267 #define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U) 1268 1269 typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS { 1270 NvU32 peerId; 1271 } NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS; 1272 1273 /*! 1274 * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES 1275 * 1276 * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings) 1277 * for the given array of GPAs. 1278 * 1279 * gfid [IN] 1280 * GFID to translate GPAs for 1281 * 1282 * numEntries [IN] 1283 * Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES) 1284 * to translate (i.e. number of elements in gpaEntries) 1285 * 1286 * gpaEntries [IN] 1287 * Array of GPAs to translate 1288 * 1289 * spaEntries [OUT] 1290 * Resulting array of SPAs 1291 */ 1292 #define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */ 1293 1294 #define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES 128 1295 1296 #define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U) 1297 1298 typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS { 1299 NvU32 gfid; 1300 NvU32 numEntries; 1301 NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); 1302 NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); 1303 } NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS; 1304 1305 /*! 1306 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER 1307 * 1308 * Pass required pushbuffer parameters from kernel RM to Physical RM 1309 * 1310 * addressSpace [IN] 1311 * Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM 1312 * 1313 * physicalAddr [IN] 1314 * Physical address of pushbuffer 1315 * 1316 * addressSpace [IN] 1317 * Limit of the pushbuffer address, it should be less than 4K 1318 * 1319 * cacheSnoop [IN] 1320 * Cachesnoop supported or not 1321 * 1322 * channelInstance [IN] 1323 * Channel instance pass by the client to get corresponding dispchannel 1324 * 1325 * hclass [IN] 1326 * External class ID pass by the client to get the channel class 1327 * 1328 * valid [IN] 1329 * This bit indicates whether pushbuffer parameters are valid or not 1330 * 1331 */ 1332 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ 1333 1334 #define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U) 1335 1336 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { 1337 NvU32 addressSpace; 1338 NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); 1339 NV_DECLARE_ALIGNED(NvU64 limit, 8); 1340 NvU32 cacheSnoop; 1341 NvU32 hclass; 1342 NvU32 channelInstance; 1343 NvBool valid; 1344 } NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; 1345 1346 /*! 1347 * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO 1348 * 1349 * This command obtains information from physical RM for use by CPU-RM. 1350 * 1351 * replayableFaultBufferSize 1352 * Default size of replayable fault buffer 1353 * 1354 * nonReplayableFaultBufferSize 1355 * Default size of non-replayable fault buffer 1356 * 1357 */ 1358 1359 #define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 1360 1361 #define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U) 1362 1363 typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { 1364 NvU32 replayableFaultBufferSize; 1365 NvU32 nonReplayableFaultBufferSize; 1366 } NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; 1367 1368 /*! 1369 * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES 1370 */ 1371 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ 1372 1373 #define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU) 1374 1375 typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS; 1376 1377 /*! 1378 * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE 1379 * 1380 * Get heap reservation size needed by different module 1381 */ 1382 #define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */ 1383 1384 #define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU) 1385 1386 typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS { 1387 NvU32 moduleIndex; 1388 NvU32 size; 1389 } NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS; 1390 1391 /*! 1392 * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE 1393 * 1394 * tableLen [OUT] 1395 * Number of valid records in table field. 1396 * 1397 * table [OUT] 1398 * Interrupt table for Kernel RM. 1399 * 1400 * subtreeMap [OUT] 1401 * Subtree range for each NV2080_INTR_CATEGORY. 1402 */ 1403 #define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ 1404 1405 #define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 1406 1407 /*! 1408 * Categories of interrupts. 1409 * 1410 * Each of these categories get a separate range of interrupt subtrees (top 1411 * level bits). 1412 */ 1413 typedef enum NV2080_INTR_CATEGORY { 1414 NV2080_INTR_CATEGORY_DEFAULT = 0, 1415 NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1, 1416 NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2, 1417 NV2080_INTR_CATEGORY_RUNLIST = 3, 1418 NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4, 1419 NV2080_INTR_CATEGORY_UVM_OWNED = 5, 1420 NV2080_INTR_CATEGORY_UVM_SHARED = 6, 1421 NV2080_INTR_CATEGORY_ENUM_COUNT = 7, 1422 } NV2080_INTR_CATEGORY; 1423 1424 #define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX 1425 1426 typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP { 1427 NvU8 subtreeStart; 1428 NvU8 subtreeEnd; 1429 } NV2080_INTR_CATEGORY_SUBTREE_MAP; 1430 1431 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { 1432 NvU16 engineIdx; 1433 NvU32 pmcIntrMask; 1434 NvU32 vectorStall; 1435 NvU32 vectorNonStall; 1436 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY; 1437 1438 #define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU) 1439 1440 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { 1441 NvU32 tableLen; 1442 NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; 1443 NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT]; 1444 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; 1445 1446 /* Index to retrieve the needed heap space for specific module */ 1447 #define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR (0x00000000) 1448 1449 /* 1450 * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK 1451 * 1452 * Checking if the reservation / release of the PERFMON HW is possible 1453 * 1454 * bReservation [IN] 1455 * NV_TRUE -> request for reservation, NV_FALSE -> request for release 1456 * 1457 */ 1458 #define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */ 1459 1460 1461 #define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U) 1462 1463 typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS { 1464 NvBool bReservation; 1465 } NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS; 1466 1467 /*! 1468 * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET 1469 * 1470 * Reserving / Releasing PERFMON HW 1471 * 1472 * bReservation [IN] 1473 * NV_TRUE -> request for reservation, NV_FALSE -> request for release 1474 * 1475 * bClientHandlesGrGating [IN] 1476 * DM-TODO: Add comment for this 1477 * 1478 * bRmHandlesIdleSlow [IN] 1479 * If the IDLE slowdown is required 1480 * 1481 */ 1482 #define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */ 1483 1484 #define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U) 1485 1486 typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS { 1487 NvBool bReservation; 1488 NvBool bClientHandlesGrGating; 1489 NvBool bRmHandlesIdleSlow; 1490 } NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS; 1491 1492 /*! 1493 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES 1494 * 1495 * Get active display devices 1496 * 1497 * displayMask [OUT] 1498 * Get the mask of the active display devices in VBIOS 1499 * 1500 * numHeads [OUT] 1501 * Number of heads display supported. 1502 * 1503 */ 1504 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */ 1505 1506 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU) 1507 1508 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { 1509 1510 NvU32 displayMask; 1511 NvU32 numHeads; 1512 } NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS; 1513 1514 1515 1516 /* 1517 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1518 * 1519 * Get FB Mem page ranges for all possible swizzIds 1520 * 1521 * fbMemPageRanges [OUT] 1522 * Mem page ranges for each swizzId in the form of {lo, hi} 1523 */ 1524 #define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ 1525 1526 #define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 1527 1528 typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { 1529 NV_DECLARE_ALIGNED(NvU64 lo, 8); 1530 NV_DECLARE_ALIGNED(NvU64 hi, 8); 1531 } NV2080_CTRL_INTERNAL_NV_RANGE; 1532 1533 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) 1534 1535 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { 1536 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8); 1537 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; 1538 1539 /*! 1540 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS 1541 * 1542 * This command is an internal command sent from Kernel RM to Physical RM 1543 * to get number of channels for a given runlist ID 1544 * 1545 * runlistId [IN] 1546 * numChannels [OUT] 1547 */ 1548 #define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */ 1549 1550 #define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U) 1551 1552 typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { 1553 NvU32 runlistId; 1554 NvU32 numChannels; 1555 } NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS; 1556 1557 /*! 1558 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES 1559 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES 1560 */ 1561 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */ 1562 1563 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U) 1564 1565 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS; 1566 1567 /*! 1568 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK 1569 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK 1570 */ 1571 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */ 1572 1573 /*! 1574 * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES 1575 * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES 1576 */ 1577 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */ 1578 1579 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U) 1580 1581 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; 1582 1583 /*! 1584 * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1585 * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1586 */ 1587 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ 1588 1589 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U) 1590 1591 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; 1592 1593 /*! 1594 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG 1595 * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG 1596 * 1597 * This command retrieves memory config from HW 1598 * 1599 * memBoundaryCfgA [OUT] 1600 * Memory boundary config A (4KB aligned) 1601 * 1602 * memBoundaryCfgB [OUT] 1603 * Memory boundary config B (4KB aligned) 1604 * 1605 * memBoundaryCfgC [OUT] 1606 * Memory boundary config C (64KB aligned) 1607 * 1608 * memBoundaryCfg [OUT] 1609 * Memory boundary config (64KB aligned) 1610 * 1611 * memBoundaryCfgValInit [OUT] 1612 * Memory boundary config initial value (64KB aligned) 1613 */ 1614 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ 1615 1616 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U) 1617 1618 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { 1619 NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); 1620 NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8); 1621 NvU32 memBoundaryCfgC; 1622 NvU32 memBoundaryCfg; 1623 NvU32 memBoundaryCfgValInit; 1624 } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; 1625 1626 #define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ 1627 1628 #define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U) 1629 1630 typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; 1631 1632 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ 1633 1634 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 1635 1636 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU) 1637 1638 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS { 1639 NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE]; 1640 } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS; 1641 1642 /*! 1643 * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT 1644 * 1645 * Invoke RC recovery after watchdog timeout is hit. 1646 */ 1647 #define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ 1648 1649 /* ! 1650 * This command disables cuda limit activation at teardown of the client. 1651 */ 1652 #define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */ 1653 1654 /* 1655 * This command is cleaning up OPTP when a client is found to have 1656 * been terminated unexpectedly. 1657 */ 1658 #define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */ 1659 1660 /* ! 1661 * This command is used to get the current AUX power state of the sub-device. 1662 */ 1663 #define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ 1664 1665 #define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U) 1666 1667 typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS { 1668 NvU32 powerState; 1669 } NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS; 1670 1671 /*! 1672 * This command can be used to boost P-State up one level or to the highest for a limited 1673 * duration for the associated subdevice. Boosts from different clients are being tracked 1674 * independently. Note that there are other factors that can limit P-States so the resulting 1675 * P-State may differ from expectation. 1676 * 1677 * flags 1678 * This parameter specifies the actual command. _CLEAR is to clear existing boost. 1679 * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost 1680 * to the highest P-State. 1681 * duration 1682 * This parameter specifies the duration of the boost in seconds. This has to be less 1683 * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. 1684 * 1685 * Possible status values returned are: 1686 * NV_OK 1687 * NV_ERR_INVALID_PARAM_STRUCT 1688 * NV_ERR_INVALID_ARGUMENT 1689 */ 1690 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ 1691 1692 #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU) 1693 1694 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X { 1695 1696 NvBool flags; 1697 NvU32 duration; 1698 } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X; 1699 1700 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE 0U 1701 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1U 1702 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1703 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */ 1704 1705 /*! 1706 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL 1707 * 1708 * Activate/Deactivate GPU Boost Sync algorithm 1709 * 1710 * bActivate [IN] 1711 * GPU Boost Sync algorithm: 1712 * NV_TRUE -> activate 1713 * NV_FALSE -> deactivate 1714 * 1715 */ 1716 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ 1717 1718 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU) 1719 1720 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS { 1721 NvBool bActivate; 1722 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS; 1723 1724 /*! 1725 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS 1726 * 1727 * Apply given limits to a specific subdevice 1728 * 1729 * flags [IN] 1730 * DM-TODO: write description here 1731 * 1732 * bBridgeless [IN] 1733 * Bridgeless information, for now supporting only MIO bridges 1734 * 1735 * currLimits 1736 * Array of limits that will be applied 1737 * 1738 */ 1739 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */ 1740 1741 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU) 1742 1743 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS { 1744 NvU32 flags; 1745 NvBool bBridgeless; 1746 NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM]; 1747 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS; 1748 1749 /*! 1750 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO 1751 * 1752 * Data for GPU Boost Sync structure initialization 1753 * 1754 * hysteresisus [OUT] 1755 * Hysteresis value for GPU Boost synchronization hysteresis algorithm. 1756 * 1757 * bHystersisEnable [OUT] 1758 * hysteresis algorithm for SLI GPU Boost synchronization: 1759 * NV_TRUE -> enabled, 1760 * NV_FALSE -> disabled 1761 * 1762 * bSliGpuBoostSyncEnable [OUT] 1763 * SLI GPU Boost feature is: 1764 * NV_TRUE -> enabled, 1765 * NV_FALSE -> disabled 1766 * 1767 */ 1768 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */ 1769 1770 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U) 1771 1772 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS { 1773 NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8); 1774 NvBool bHystersisEnable; 1775 NvBool bSliGpuBoostSyncEnable; 1776 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS; 1777 1778 /* 1779 * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER 1780 * 1781 * This command sends replayable fault buffer pages allocated by CPU-RM 1782 * to be setup and enabled in physical RM. 1783 * 1784 * hClient 1785 * Client handle. 1786 * 1787 * hObject 1788 * Object handle. 1789 * 1790 * faultBufferSize 1791 * Size of the replayable fault buffer to register. 1792 * 1793 * faultBufferPteArray 1794 * Pages of replayable fault buffer. 1795 * 1796 * Possible status values returned are: 1797 * NV_OK 1798 */ 1799 #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1800 1801 #define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES 256 1802 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU) 1803 1804 typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { 1805 NvHandle hClient; 1806 NvHandle hObject; 1807 NvU32 faultBufferSize; 1808 NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8); 1809 } NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS; 1810 1811 /* 1812 * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER 1813 * 1814 * This command requests physical RM to disable the replayable fault buffer. 1815 * 1816 * Possible status values returned are: 1817 * NV_OK 1818 */ 1819 #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ 1820 1821 // Valid fault buffer types 1822 #define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) 1823 #define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) 1824 1825 /* 1826 * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER 1827 * 1828 * This command sends client shadow fault buffer pages allocated by CPU-RM 1829 * to be setup and enabled in physical RM. 1830 * 1831 * shadowFaultBufferQueuePhysAddr 1832 * Physical address of shadow fault buffer queue. 1833 * 1834 * faultBufferSize 1835 * Size of the client shadow fault buffer to register. 1836 * 1837 * shadowFaultBufferPteArray 1838 * Pages of client shadow fault buffer. 1839 * 1840 * shadowFaultBufferType 1841 * Replayable or non-replayable fault buffer 1842 * 1843 * faultBufferSharedMemoryPhysAddr 1844 * Fault buffer shared memory address. Used only by the Replayable fault buffer. 1845 * 1846 * Possible status values returned are: 1847 * NV_OK 1848 */ 1849 #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1850 1851 #define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 1500 1852 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) 1853 1854 typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { 1855 NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); 1856 NvU32 shadowFaultBufferSize; 1857 NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); 1858 NvU32 shadowFaultBufferType; 1859 NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8); 1860 } NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; 1861 1862 /* 1863 * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER 1864 * 1865 * This command requests physical RM to disable the client shadow fault buffer. 1866 * 1867 * shadowFaultBufferType 1868 * Replayable or non-replayable fault buffer 1869 * 1870 * Possible status values returned are: 1871 * NV_OK 1872 */ 1873 #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1874 1875 #define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU) 1876 1877 typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { 1878 NvU32 shadowFaultBufferType; 1879 } NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; 1880 1881 /* 1882 * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER 1883 * 1884 * Pin PDEs for Global VA range on the server RM and then mirror the client's page 1885 * directory/tables in the server. 1886 * 1887 * Possible status values returned are: 1888 * NV_OK 1889 */ 1890 #define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */ 1891 1892 #define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU) 1893 1894 typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS { 1895 NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); 1896 } NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; 1897 1898 /*! 1899 * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X 1900 * 1901 * This command can be used to boost P-State the highest for a limited 1902 * duration for the associated subdevice. Boosts from different clients are being tracked 1903 * independently. Note that there are other factors that can limit P-States so the resulting 1904 * P-State may differ from expectation. 1905 * 1906 * flags [IN] 1907 * This parameter specifies the actual command. _CLEAR is to clear existing boost. 1908 * and _BOOST_TO_MAX is to boost to the highest P-State. 1909 * 1910 * boostDuration [IN] 1911 * This parameter specifies the duration of the boost in seconds. This has to be less 1912 * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. 1913 * 1914 * gfId [IN] 1915 * This specifies Id of the Kernel RM that is requesting the Boost 1916 * 1917 * bOverrideInfinite[IN] 1918 * This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM. 1919 * This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM 1920 * and setting the boost duration to a next maximum duration registered for the Kernel RM in question. 1921 * 1922 * Possible status values returned are: 1923 * NV_OK 1924 * NV_ERR_INVALID_PARAM_STRUCT 1925 * NV_ERR_INVALID_ARGUMENT 1926 */ 1927 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ 1928 1929 #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) 1930 1931 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X { 1932 NvU32 flags; 1933 NvU32 boostDuration; 1934 NvU32 gfId; 1935 NvBool bOverrideInfinite; 1936 } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X; 1937 1938 /*! 1939 * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X 1940 * 1941 * Clear the boost for specific Kernel RM 1942 * 1943 * bIsCudaClient [IN] 1944 * Specifies if the request is for clearing the CUDA boost or regular boost 1945 * NV_TRUE -> CUDA boost, NV_FALSE otherwise 1946 * 1947 * gfId [IN] 1948 * Specifies Id of the Kernel RM that is requesting Boost clear 1949 * 1950 */ 1951 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */ 1952 1953 #define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U) 1954 1955 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { 1956 1957 NvBool bIsCudaClient; 1958 NvU32 gfId; 1959 } NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X; 1960 1961 /* 1962 * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO 1963 * 1964 * Retrieves skyline information about the GPU. Params are sized to currently known max 1965 * values, but will need to be modified in the future should that change. 1966 */ 1967 #define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ 1968 1969 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8 1970 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8 1971 /*! 1972 * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO 1973 * skylineVgpcSize[OUT] 1974 * - TPC count of non-singleton VGPCs 1975 * singletonVgpcMask[OUT] 1976 * - Mask of active Singletons 1977 * maxInstances[OUT] 1978 * - Max allowed instances of this skyline concurrently on a GPU 1979 * computeSizeFlag 1980 * - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline 1981 * numNonSingletonVgpcs 1982 * - Number of VGPCs with non-zero TPC counts which are not singletons 1983 */ 1984 typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO { 1985 NvU8 skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS]; 1986 NvU32 singletonVgpcMask; 1987 NvU32 maxInstances; 1988 NvU32 computeSizeFlag; 1989 NvU32 numNonSingletonVgpcs; 1990 } NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO; 1991 1992 /*! 1993 * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS 1994 * skylineTable[OUT] 1995 * - TPC count of non-singleton VGPCs 1996 * - Mask of singleton vGPC IDs active 1997 * - Max Instances of this skyline possible concurrently 1998 * - Associated compute size with the indexed skyline 1999 * - Number of VGPCs with non-zero TPC counts which are not singletons 2000 * validEntries[OUT] 2001 * - Number of entries which contain valid info in skylineInfo 2002 */ 2003 #define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U) 2004 2005 typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { 2006 NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES]; 2007 NvU32 validEntries; 2008 } NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS; 2009 2010 /*! 2011 * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE 2012 */ 2013 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ 2014 2015 #define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U) 2016 2017 typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS; 2018 2019 /*! 2020 * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION 2021 */ 2022 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2023 2024 #define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U) 2025 2026 typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS; 2027 2028 /*! 2029 * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS 2030 */ 2031 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ 2032 2033 #define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U) 2034 2035 typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS; 2036 2037 /*! 2038 * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS 2039 */ 2040 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ 2041 2042 #define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U) 2043 2044 typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS; 2045 2046 /*! 2047 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED 2048 * 2049 * Tell Physical RM whether any ZBC-kind surfaces are allocated. 2050 * If PF and all VFs report false, ZBC table can be flushed by Physical RM. 2051 * 2052 * bZbcReferenced [IN] 2053 * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM 2054 * 2055 */ 2056 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ 2057 2058 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) 2059 2060 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { 2061 NvBool bZbcSurfacesExist; 2062 } NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS; 2063 2064 /*! 2065 * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE 2066 * 2067 * Export the resource and placement information about a gpu instance such that a 2068 * similar gpu instance can be recreated from scratch in the same position on the 2069 * same or similar GPU. Note that different GPUs may have different physical 2070 * resources due to floorsweeping, and an imported gpu instance is not guaranteed 2071 * to get the exact same resources as the exported gpu instance, but the imported 2072 * gpu instance should behave identically with respect to fragmentation and 2073 * placement / span positioning. 2074 */ 2075 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2076 2077 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2078 2079 /*! 2080 * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE 2081 * 2082 * Create a gpu instance resembling the exported instance info. Note that 2083 * different GPUs may have different physical resources due to floorsweeping, 2084 * and an imported gpu instance is not guaranteed to get the exact same resources 2085 * as the exported gpu instance, but the imported gpu instance should behave 2086 * identically with respect to fragmentation and placement / span positioning. 2087 */ 2088 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2089 2090 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2091 2092 #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 2093 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { 2094 NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8); 2095 NvU32 partitionFlags; 2096 NvU32 gpcMask; 2097 NvU32 virtualGpcCount; 2098 NvU32 veidOffset; 2099 NvU32 veidCount; 2100 } NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO; 2101 2102 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { 2103 NvU32 swizzId; 2104 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); 2105 } NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; 2106 2107 #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U) 2108 2109 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS; 2110 2111 #define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U) 2112 2113 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS; 2114 2115 #define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U) 2116 2117 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS; 2118 2119 #define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU) 2120 2121 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS; 2122 2123 /*! 2124 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT 2125 * 2126 * Invalidate and/or evict the L2 cache 2127 * 2128 * flags [IN] 2129 * flags that specify required actions 2130 * 2131 */ 2132 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */ 2133 2134 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU) 2135 2136 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { 2137 NvU32 flags; 2138 } NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS; 2139 2140 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL (0x00000001) 2141 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST (0x00000002) 2142 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST (0x00000004) 2143 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL (0x00000008) 2144 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN (0x00000010) 2145 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020) 2146 2147 /*! 2148 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES 2149 * 2150 * Flush all L2 Rams and Caches using the ELPG flush 2151 * 2152 */ 2153 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */ 2154 2155 /*! 2156 * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO 2157 * 2158 * This command obtains information from physical RM for use by CPU-RM 2159 * 2160 * Data fields -> 2161 * bPcieGen4Capable - tells whether PCIe is Gen4 capable 2162 */ 2163 #define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 2164 2165 #define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU) 2166 2167 typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS { 2168 NvBool bPcieGen4Capable; 2169 NvBool bIsC2CLinkUp; 2170 NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8); 2171 } NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS; 2172 2173 /*! 2174 * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG 2175 * 2176 * Program HSHUB Peer Conn Config space. 2177 * 2178 * programPeerMask[IN] 2179 * If nonzero, the peer mask for programming peers based on hshub connectivity. 2180 * 2181 * invalidatePeerMask[IN] 2182 * If nonzero, the peer mask for invalidating peers. 2183 * 2184 * programPciePeerMask[IN] 2185 * If nonzero, the peer mask for programming peers in pcie case. 2186 * 2187 * Possible status values returned are: 2188 * NV_OK 2189 * NV_WARN_NOTHING_TO_DO 2190 * If all peer masks are zero. 2191 */ 2192 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */ 2193 2194 #define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U) 2195 2196 typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS { 2197 NvU32 programPeerMask; 2198 NvU32 invalidatePeerMask; 2199 NvU32 programPciePeerMask; 2200 } NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS; 2201 2202 /*! 2203 * NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID 2204 * 2205 * Given a mask of link ids, find the first with a valid peerId. 2206 * 2207 * linkMask[IN] 2208 * Mask of linkIds to check. 2209 * 2210 * peerId[OUT] 2211 * The peerId for the lowest-index link with a valid peerId, if any. 2212 * If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK). 2213 * 2214 * Possible status values returned are: 2215 * NV_OK 2216 * 2217 */ 2218 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */ 2219 2220 #define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff 2221 2222 #define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U) 2223 2224 typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS { 2225 NvU32 linkMask; 2226 NvU32 peerId; 2227 } NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS; 2228 2229 /*! 2230 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS 2231 * 2232 * Get the Hshub Ids connected to the other end of links. 2233 * 2234 * linkMask[IN] 2235 * A mask of link ids to query. 2236 * 2237 * hshubIds[OUT] 2238 * For each set bit in the link mask, the peer Hshub Id. 2239 * 2240 * Possible status values returned are: 2241 * NV_OK 2242 * NV_WARN_NOTHING_TO_DO 2243 * If the mask is zero. 2244 */ 2245 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */ 2246 #define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32 2247 2248 #define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU) 2249 2250 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS { 2251 NvU32 linkMask; 2252 NvU8 hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE]; 2253 } NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS; 2254 2255 /*! 2256 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS 2257 * 2258 * Return the number of HSHUB units. 2259 * 2260 * numHshubs[OUT] 2261 * 2262 * Possible status values returned are: 2263 * NV_OK 2264 */ 2265 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */ 2266 2267 #define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU) 2268 2269 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS { 2270 NvU32 numHshubs; 2271 } NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS; 2272 2273 /*! 2274 * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID 2275 * 2276 * Return the next hshubId after the given hshubId. 2277 * 2278 * hshubId[IN/OUT] 2279 * 2280 * Possible status values returned are: 2281 * NV_OK 2282 */ 2283 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */ 2284 2285 #define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU) 2286 2287 typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { 2288 NvU8 hshubId; 2289 } NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; 2290 2291 2292 2293 /* 2294 * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR 2295 * 2296 * Enable compute peer addressing mode 2297 * This command accepts no parameters. 2298 */ 2299 2300 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */ 2301 2302 /* 2303 * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR 2304 * 2305 * Get/Set NVSwitch fabric address for FLA 2306 * 2307 * [In] bGet 2308 * Whether to get or set the NVSwitch fabric address 2309 * [In/Out] addr 2310 * Address that is to be set or retrieved. 2311 */ 2312 #define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU) 2313 2314 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS { 2315 NvBool bGet; 2316 NV_DECLARE_ALIGNED(NvU64 addr, 8); 2317 } NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS; 2318 2319 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */ 2320 2321 /*! 2322 * NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS 2323 * 2324 * This command obtains information from physical RM for use by CPU-RM 2325 * 2326 * Data fields -> 2327 * bCyaMaskL1 2328 * bEnableAspmDtL1 2329 */ 2330 #define NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID" */ 2331 2332 #define NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID (0xb0U) 2333 2334 typedef struct NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS { 2335 NvBool bCyaMaskL1; 2336 NvBool bEnableAspmDtL1; 2337 } NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS; 2338 2339 /*! 2340 * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT 2341 * 2342 * Sets number of VM slots that are active in VGPU's scheduler 2343 * 2344 * maxActiveVGpuVMCount [IN] 2345 * Number of VM slots that are active in vGPU's scheduler. 2346 * 2347 * Possible status values returned are: 2348 * NV_OK 2349 * NV_ERR_OUT_OF_RANGE - Passed value is out of range 2350 * NV_ERR_NO_MEMORY - Out of memory 2351 */ 2352 #define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */ 2353 2354 /*! 2355 * Maximum value of VM slots that are active in vGPU's scheduler. 2356 */ 2357 #define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32 2358 2359 #define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U) 2360 2361 typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS { 2362 NvU8 maxActiveVGpuVMCount; 2363 } NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS; 2364 2365 /*! 2366 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS 2367 * 2368 * Disable all NVLINK FB peers 2369 * 2370 */ 2371 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */ 2372 2373 /*! 2374 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE 2375 * 2376 * Program GPU in raw / legacy compression mode 2377 * 2378 */ 2379 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */ 2380 2381 #define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU) 2382 2383 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { 2384 NvBool bRawMode; 2385 } NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; 2386 2387 /* 2388 * NV2080_CTRL_CMD_INTERNAL_CCU_MAP 2389 * 2390 * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it 2391 * in physical-RM. 2392 * 2393 * Possible status values returned are: 2394 * NV_OK 2395 * NV_ERR_INVALID_ARGUMENT 2396 * NV_ERR_INVALID_ADDRESS 2397 */ 2398 #define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */ 2399 2400 #define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1 2401 #define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U) 2402 2403 typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { 2404 NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8); 2405 } NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS; 2406 /* 2407 * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP 2408 * 2409 * This command unmaps the shared buffer memory mapping in physical-RM 2410 * 2411 * Possible status values returned are: 2412 * NV_OK 2413 */ 2414 #define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */ 2415 2416 #define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U) 2417 2418 typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS { 2419 NvBool bDevShrBuf; 2420 NvBool bMigShrBuf; 2421 } NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS; 2422 2423 /*! 2424 * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO 2425 * 2426 * [in] gpuId 2427 * GPU ID. 2428 * [in] gpuInstance 2429 * GPU instance. 2430 * [in] p2pCaps 2431 * Peer to peer capabilities discovered between the GPUs. 2432 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 2433 * [in] p2pOptimalReadCEs 2434 * Mask of CEs to use for p2p reads over Nvlink. 2435 * [in] p2pOptimalWriteCEs 2436 * Mask of CEs to use for p2p writes over Nvlink. 2437 * [in] p2pCapsStatus 2438 * Status of all supported p2p capabilities. 2439 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 2440 * [in] busPeerId 2441 * Bus peer ID. For an invalid or a non-existent peer this field 2442 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 2443 */ 2444 typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO { 2445 NvU32 gpuId; 2446 NvU32 gpuInstance; 2447 NvU32 p2pCaps; 2448 NvU32 p2pOptimalReadCEs; 2449 NvU32 p2pOptimalWriteCEs; 2450 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 2451 NvU32 busPeerId; 2452 } NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO; 2453 2454 /*! 2455 * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS 2456 * 2457 * An internal call to propagate the peer to peer capabilities of peer GPUs 2458 * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin. 2459 * This control is used to both add and and update the peer to peer capabilities. 2460 * The existing GPU entries will be updated and those which don't exist will be added. 2461 * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries. 2462 * 2463 * [in] peerGpuCount 2464 * The number of the peerGpuInfos entries. 2465 * [in] peerGpuInfos 2466 * The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing 2467 * the peer to peer capabilities of the specified GPUs. 2468 * 2469 * Possible status values returned are: 2470 * NV_OK 2471 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount 2472 * NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value 2473 */ 2474 #define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2475 2476 #define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U) 2477 2478 typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS { 2479 NvU32 peerGpuCount; 2480 NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 2481 } NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS; 2482 2483 /*! 2484 * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS 2485 * 2486 * An internal call to remove the cached peer to peer capabilities of peer GPUs 2487 * from the Physical RM. 2488 * 2489 * [in] peerGpuIdCount 2490 * The number of the peerGpuIds entries. 2491 * [in] peerGpuIds 2492 * The array of GPU IDs, specifying the GPU for which the entries need to be removed. 2493 * 2494 * Possible status values returned are: 2495 * NV_OK 2496 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount 2497 * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry 2498 */ 2499 #define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2500 2501 #define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U) 2502 2503 typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { 2504 NvU32 peerGpuIdCount; 2505 NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 2506 } NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS; 2507 2508 2509 2510 /*! 2511 * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS 2512 * 2513 * This command returns the GPU's PCIE P2P caps 2514 * 2515 * [in] bCommonPciSwitchFound 2516 * All GPUs are under the same PCI switch 2517 * [out] p2pReadCapsStatus 2518 * [out] p2pWriteCapsStatus 2519 * These members returns status of all supported p2p capabilities. Valid 2520 * status values include: 2521 * NV0000_P2P_CAPS_STATUS_OK 2522 * P2P capability is supported. 2523 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 2524 * Chipset doesn't support p2p capability. 2525 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 2526 * GPU doesn't support p2p capability. 2527 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 2528 * IOH topology isn't supported. For e.g. root ports are on different 2529 * IOH. 2530 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 2531 * P2P Capability is disabled by a regkey. 2532 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 2533 * P2P Capability is not supported. 2534 * 2535 * Possible status values returned are: 2536 * NV_OK 2537 * NV_ERR_INVALID_ARGUMENT 2538 * NV_ERR_INVALID_PARAM_STRUCT 2539 */ 2540 #define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2541 2542 #define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U) 2543 2544 typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { 2545 NvBool bCommonPciSwitchFound; 2546 NvU8 p2pReadCapsStatus; 2547 NvU8 p2pWriteCapsStatus; 2548 } NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS; 2549 2550 /*! 2551 * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO 2552 * 2553 * Enable/disable PCIe Relaxed Ordering. 2554 * 2555 */ 2556 #define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ 2557 2558 #define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U) 2559 2560 typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { 2561 // Enable/disable PCIe relaxed ordering 2562 NvBool enableRo; 2563 } NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; 2564 2565 /* 2566 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE 2567 * 2568 * An internal call to invoke the sequence VGA register reads & writes to 2569 * perform save and restore of VGA 2570 * 2571 * [in] saveOrRestore 2572 * To indicate whether save or restore needs to be performed. 2573 * [in] useVbios 2574 * Primary VGA indication from OS. 2575 * 2576 * Possible status values returned are: 2577 * NV_OK 2578 * NV_ERR_GENERIC 2579 * NV_ERR_NOT_SUPPORTED 2580 */ 2581 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ 2582 2583 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) 2584 2585 typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS { 2586 2587 NvBool bSaveOrRestore; 2588 NvBool bUseVbios; 2589 } NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS; 2590 2591 /*! 2592 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE 2593 * 2594 * To perform restore operation from saved fonts. 2595 * 2596 * [in] saveOrRestore 2597 * To indicate whether save or restore needs to be performed. 2598 * [in] useVbios 2599 * Primary VGA indication from OS. 2600 * 2601 * Possible status values returned are: 2602 * NV_OK 2603 * NV_ERR_GENERIC 2604 * NV_ERR_NOT_SUPPORTED 2605 */ 2606 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID" */ 2607 2608 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID (0x77U) 2609 2610 typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS { 2611 2612 NvBool bWriteCr; 2613 } NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS; 2614 2615 /*! 2616 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES 2617 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES 2618 */ 2619 2620 /*! 2621 * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE 2622 * 2623 * This structure specifies resources in an execution partition 2624 * 2625 * computeSize[OUT] 2626 * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile 2627 * 2628 * gfxGpcCount[OUT] 2629 * - Total Number of GFX Supporting GPCs in this partition 2630 * 2631 * gpcCount[OUT] 2632 * - Total Number of GPCs in this partition (including GFX Supported GPCs) 2633 * 2634 * veidCount[OUT] 2635 * - Number of VEIDs allocated to this profile 2636 * 2637 * smCount[OUT] 2638 * - Number of SMs usable in this profile 2639 */ 2640 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { 2641 NvU8 computeSize; 2642 NvU32 gfxGpcCount; 2643 NvU32 gpcCount; 2644 NvU32 veidCount; 2645 NvU32 smCount; 2646 NvU32 physicalSlots; 2647 } NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; 2648 2649 /*! 2650 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS 2651 * 2652 * This structure specifies resources in an execution partition 2653 * 2654 * profileCount[OUT] 2655 * - Total Number of profiles filled 2656 * 2657 * profiles[OUT] 2658 * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles 2659 */ 2660 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) 2661 2662 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { 2663 NvU32 profileCount; 2664 NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; 2665 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; 2666 2667 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ 2668 2669 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU) 2670 2671 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS; 2672 2673 2674 2675 /* 2676 * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE 2677 * 2678 * This command sets the ccu stream to enable/disable state. 2679 * 2680 * Possible status values returned are: 2681 * NV_OK 2682 * NV_ERR_INVALID_ARGUMENT 2683 * NV_ERR_NOT_SUPPORTED 2684 */ 2685 2686 #define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */ 2687 2688 #define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU) 2689 2690 typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS { 2691 NvBool bStreamState; 2692 } NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS; 2693 2694 /*! 2695 * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT 2696 * 2697 * Attach GPU to the external device. 2698 * 2699 * [in] bExtDevFound 2700 * To enable GPIO interrupts. 2701 * 2702 * Possible status values returned are: 2703 * NV_OK 2704 * NV_ERR_GENERIC 2705 * NV_ERR_NOT_SUPPORTED 2706 */ 2707 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */ 2708 2709 #define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU) 2710 2711 typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS { 2712 NvBool bExtDevFound; 2713 } NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS; 2714 2715 /*! 2716 * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS 2717 * 2718 * Optimize the Gsync timing parameters 2719 * 2720 * [in] timingParameters 2721 * Timing parameters passed by client. 2722 * 2723 * Possible status values returned are: 2724 * NV_OK 2725 * NV_ERR_GENERIC 2726 * NV_ERR_NOT_SUPPORTED 2727 */ 2728 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */ 2729 2730 #define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU) 2731 2732 typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS { 2733 NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters; 2734 } NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS; 2735 2736 /*! 2737 * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS 2738 * 2739 * Get displayIDs supported by the display. 2740 * 2741 * [out] displayIds 2742 * Associated display ID with head. 2743 * 2744 * Possible status values returned are: 2745 * NV_OK 2746 * NV_ERR_GENERIC 2747 * NV_ERR_NOT_SUPPORTED 2748 */ 2749 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */ 2750 2751 #define NV2080_MAX_NUM_HEADS 4 2752 2753 #define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U) 2754 2755 typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS { 2756 NvU32 displayIds[NV2080_MAX_NUM_HEADS]; 2757 } NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS; 2758 2759 /*! 2760 * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC 2761 * 2762 * Set the Stereo sync for Gsync 2763 * 2764 * [in] slave 2765 * Slave GPU head status. 2766 * [in] localSlave 2767 * Slave GPU head status but are not coupled. 2768 * [in] master 2769 * Master GPU head status. 2770 * [in] regstatus 2771 * Register status of status1 register. 2772 * 2773 * Possible status values returned are: 2774 * NV_OK 2775 * NV_ERR_GENERIC 2776 * NV_ERR_NOT_SUPPORTED 2777 */ 2778 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */ 2779 2780 #define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U) 2781 2782 typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS { 2783 NvU32 slave[NV2080_MAX_NUM_HEADS]; 2784 NvU32 localSlave[NV2080_MAX_NUM_HEADS]; 2785 NvU32 master[NV2080_MAX_NUM_HEADS]; 2786 NvU32 regStatus; 2787 } NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS; 2788 2789 /*! 2790 * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES 2791 * 2792 * Get vertical active lines for given head. 2793 * 2794 * [in] head 2795 * For the headIdx which we need active. 2796 * [out] vActiveLines 2797 * Vertical active lines. 2798 * 2799 * Possible status values returned are: 2800 * NV_OK 2801 * NV_ERR_GENERIC 2802 * NV_ERR_NOT_SUPPORTED 2803 */ 2804 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */ 2805 2806 #define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U) 2807 2808 typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS { 2809 NvU32 headIdx; 2810 NvU32 vActiveLines; 2811 } NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS; 2812 2813 /*! 2814 * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID 2815 * 2816 * Verifies if this displayId is valid. 2817 * 2818 * [in] displays 2819 * Displays given by the client 2820 * 2821 * [out] displayId 2822 * DisplayId for the given display 2823 * 2824 * Possible status values returned are: 2825 * NV_OK 2826 * NV_ERR_GENERIC 2827 * NV_ERR_NOT_SUPPORTED 2828 */ 2829 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */ 2830 2831 #define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U) 2832 2833 typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { 2834 NvU32 displays; 2835 NvU32 displayId; 2836 } NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS; 2837 2838 /*! 2839 * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC 2840 * 2841 * Disable the raster sync gpio on the other P2060 GPU 2842 * that's connected to master over Video bridge. 2843 * 2844 * [in] bEnableMaster 2845 * If it is master gpu. 2846 * 2847 * [out] bRasterSyncGpioSaved 2848 * If raster sync GPIO direction is saved or not. 2849 * 2850 * [in/out] bRasterSyncGpioDirection 2851 * During save it gets the direction. 2852 * In restores it sets the direction. 2853 * 2854 * Possible status values returned are: 2855 * NV_OK 2856 * NV_ERR_NOT_SUPPORTED 2857 */ 2858 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */ 2859 2860 #define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU) 2861 2862 typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { 2863 NvBool bEnableMaster; 2864 NvBool bRasterSyncGpioSaved; 2865 NvU32 bRasterSyncGpioDirection; 2866 } NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS; 2867 2868 /*! 2869 * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT 2870 * 2871 * Initialize FBSR on GSP to prepare for suspend-resume 2872 * 2873 * [in] fbsrType 2874 * Fbsr object type 2875 * [in] numRegions 2876 * Number of regions that GSP should allocate records for 2877 * [in] hClient 2878 * Handle to client of SYSMEM memlist object 2879 * [in] hSysMem 2880 * Handle to SYSMEM memlist object 2881 * [in] gspFbAllocsSysOffset 2882 * Offset in SYSMEM for GSP's FB Allocations 2883 * 2884 * Possible status values returned are: 2885 * NV_OK 2886 * NV_ERR_GENERIC 2887 * NV_ERR_NOT_SUPPORTED 2888 */ 2889 2890 #define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ 2891 2892 #define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U) 2893 2894 typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { 2895 NvU32 fbsrType; 2896 NvU32 numRegions; 2897 NvHandle hClient; 2898 NvHandle hSysMem; 2899 NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8); 2900 } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; 2901 2902 /*! 2903 * NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO 2904 * 2905 * Send info of FB region that will be saved/restored by GSP on suspend-resume 2906 * 2907 * [in] fbsrType 2908 * Fbsr object type 2909 * [in] hClient 2910 * Handle to client of FBMEM memlist object 2911 * [in] hVidMem 2912 * Handle to FBMEM memlist object 2913 * [in] vidOffset 2914 * Offset in FBMEM region to save/restore 2915 * [in] sysOffset 2916 * Offset in SYSMEM region to save to/restore from 2917 * [in] size 2918 * Size of region being saved/restored 2919 */ 2920 #define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */ 2921 2922 #define NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID (0xC3U) 2923 2924 typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS { 2925 NvU32 fbsrType; 2926 NvHandle hClient; 2927 NvHandle hVidMem; 2928 NV_DECLARE_ALIGNED(NvU64 vidOffset, 8); 2929 NV_DECLARE_ALIGNED(NvU64 sysOffset, 8); 2930 NV_DECLARE_ALIGNED(NvU64 size, 8); 2931 } NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS; 2932 2933 /* 2934 * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB 2935 * 2936 * This command is used to get the amount of host reserved FB 2937 * 2938 * hostReservedFb [OUT] 2939 * Amount of FB reserved for the host 2940 * vgpuTypeId [IN] 2941 * The Type ID for VGPU profile 2942 * 2943 * Possible status values returned are: 2944 * NV_OK 2945 * NV_ERR_INVALID_ARGUMENT 2946 */ 2947 #define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */ 2948 2949 #define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U) 2950 2951 typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS { 2952 NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); 2953 NvU32 vgpuTypeId; 2954 } NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS; 2955 2956 /*! 2957 * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD 2958 * 2959 * This command initiates brightc module state load. 2960 * 2961 * Possible status values returned are: 2962 * NV_OK 2963 * NV_ERR_INVALID_ARGUMENT 2964 * NV_ERR_NOT_SUPPORTED 2965 */ 2966 2967 #define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ 2968 2969 #define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ 2970 2971 #define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U) 2972 2973 typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { 2974 NvU32 status; 2975 NvU16 backLightDataSize; 2976 NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; 2977 } NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; 2978 2979 /* 2980 * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL 2981 * 2982 * Returns number of active links allowed per IOCTRL 2983 * 2984 * [Out] numActiveLinksPerIoctrl 2985 */ 2986 #define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U) 2987 2988 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { 2989 NvU32 numActiveLinksPerIoctrl; 2990 } NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; 2991 #define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ 2992 /* 2993 * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL 2994 * 2995 * Returns number of links per IOCTRL 2996 * 2997 * [Out] numLinksPerIoctrl 2998 */ 2999 #define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U) 3000 3001 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { 3002 NvU32 numLinksPerIoctrl; 3003 } NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; 3004 #define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ 3005 3006 /*! 3007 * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE 3008 * 3009 * Update the system control capability 3010 * 3011 * bIsSysCtrlSupported [IN] 3012 If the system control is supported 3013 * bIsPlatformLegacy [OUT] 3014 If the platform is legacy 3015 * 3016 * Possible status values returned are: 3017 * NV_OK 3018 * NV_ERR_NOT_SUPPORTED 3019 */ 3020 3021 #define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */ 3022 3023 #define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU) 3024 3025 typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS { 3026 NvBool bIsSysCtrlSupported; 3027 NvBool bIsPlatformLegacy; 3028 } NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS; 3029 3030 /*! 3031 * Macros for PFM_REQ_HNDLR_STATE_SYNC data types. 3032 */ 3033 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR 0x00U 3034 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM 0x01U 3035 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U 3036 3037 /*! 3038 * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI. 3039 */ 3040 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { 3041 /*! 3042 * PFM sensor ID 3043 */ 3044 NvU32 sensorId; 3045 3046 /*! 3047 * PFM sensor limit value if required 3048 */ 3049 NvU32 limit; 3050 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; 3051 3052 /*! 3053 * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types. 3054 */ 3055 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA { 3056 /*! 3057 * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_<xyz> 3058 */ 3059 NvU8 type; 3060 3061 /*! 3062 * Type-specific information. 3063 */ 3064 union { 3065 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi; 3066 } data; 3067 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA; 3068 3069 /*! 3070 * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation. 3071 */ 3072 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD 0x00U 3073 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT 0x01U 3074 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U 3075 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET 0x03U 3076 3077 /*! 3078 * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params. 3079 */ 3080 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { 3081 /*! 3082 * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_<xyz> 3083 */ 3084 NvU8 flags; 3085 3086 /*! 3087 * Type-specific information. 3088 */ 3089 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData; 3090 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS; 3091 3092 /*! 3093 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC 3094 * 3095 * State sync with platform req handler and SMBPBI 3096 * 3097 * flags [IN] 3098 * Flags that needs sync operation between physical and kernel 3099 * 3100 * syncData [IN] 3101 * Sync payload data 3102 * 3103 */ 3104 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */ 3105 3106 #define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU) 3107 3108 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS; 3109 3110 /*! 3111 * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC 3112 * 3113 * State sync with platform req handler and SMBPBI 3114 * 3115 * flags [IN] 3116 * Flags that needs sync operation between physical and kernel 3117 * 3118 * syncData [IN] 3119 * Sync payload data 3120 * 3121 */ 3122 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */ 3123 3124 #define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU) 3125 3126 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS; 3127 3128 /*! 3129 * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE 3130 * 3131 * Query Coherent FB Aperture Size. 3132 * 3133 */ 3134 #define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ 3135 3136 #define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) 3137 3138 typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS { 3139 // Get Coherent Fb Aperture Size 3140 NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8); 3141 } NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS; 3142 3143 3144 /*! 3145 * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag 3146 */ 3147 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U 3148 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS 0x01U 3149 3150 /*! 3151 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE 3152 * 3153 * Queries PM1 Forced off / PM1 Available status 3154 * 3155 * flag [IN] 3156 * Fetch PM1 Forced off / PM1 Available status based on value. 3157 * bStatus [OUT] 3158 * PM1 Forced off / PM1 Available is true or false. 3159 * 3160 * Possible status values returned are: 3161 * NV_OK 3162 * NV_ERR_NOT_SUPPORTED 3163 * NV_ERR_INVALID_ARGUMETS 3164 */ 3165 3166 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */ 3167 3168 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU) 3169 3170 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS { 3171 /*! 3172 * Fetch PM1 Forced off / PM1 Available status based on value. 3173 */ 3174 NvU8 flag; 3175 3176 /*! 3177 * PM1 Forced off / PM1 Available status 3178 */ 3179 NvBool bStatus; 3180 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS; 3181 3182 /*! 3183 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE 3184 * 3185 * Set PM1 state to enabled / disabled (boost clocks). 3186 * 3187 * bEnable [IN] 3188 * NV_TRUE means enable PM1, NV_FALSE means disable. 3189 * 3190 * Possible status values returned are: 3191 * NV_OK 3192 * NV_ERR_NOT_SUPPORTED 3193 */ 3194 3195 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */ 3196 3197 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU) 3198 3199 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS { 3200 3201 /*! 3202 * NV_TRUE means enable PM1, NV_FALSE means disable. 3203 */ 3204 NvBool bEnable; 3205 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS; 3206 3207 /*! 3208 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT 3209 * 3210 * Updates EDPpeak Limit of GPU 3211 * 3212 * bEnable [IN] 3213 * Enable or Reset the settings 3214 * 3215 * Possible status values returned are: 3216 * NV_OK 3217 * NV_ERR_GENERIC 3218 * NV_ERR_NOT_SUPPORTED 3219 * NV_ERR_NOT_READY 3220 */ 3221 3222 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */ 3223 3224 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U) 3225 3226 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { 3227 NvBool bEnable; 3228 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; 3229 3230 /*! 3231 * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT 3232 * 3233 * Updates Target Temperature of GPU 3234 * 3235 * targetTemp [IN] 3236 * Target Temperature Set from SBIOS 3237 * 3238 * Possible status values returned are: 3239 * NV_OK 3240 * NV_ERR_NOT_SUPPORTED 3241 */ 3242 3243 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */ 3244 3245 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U) 3246 3247 typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS { 3248 NvS32 targetTemp; 3249 } NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS; 3250 3251 /*! 3252 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE 3253 * 3254 * Enable / disable CTGP MODE 3255 * 3256 * bEnable [IN] 3257 * Enable or Reset the settings 3258 * 3259 * Possible status values returned are: 3260 * NV_OK 3261 * NV_ERR_NOT_SUPPORTED 3262 */ 3263 3264 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */ 3265 3266 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U) 3267 3268 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS { 3269 NvBool bEnable; 3270 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS; 3271 3272 /*! 3273 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 3274 * 3275 * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control 3276 * 3277 * ctgpOffsetmW [IN] 3278 * TGP MODE Offset in mW 3279 * 3280 * Possible status values returned are: 3281 * NV_OK 3282 * NV_ERR_NOT_SUPPORTED 3283 */ 3284 3285 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */ 3286 3287 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U) 3288 3289 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS { 3290 NvU32 ctgpOffsetmW; 3291 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS; 3292 3293 /*! 3294 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO 3295 * 3296 * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx 3297 * 3298 * bVpsPs20Supported [OUT] 3299 * Reflects Vpstates PS20 support 3300 * vPstateIdxHighest [OUT} 3301 * Reflects Highest VPstate Idx 3302 * 3303 * Possible status values returned are: 3304 * NV_OK 3305 * NV_ERR_NOT_SUPPORTED 3306 */ 3307 3308 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */ 3309 3310 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U) 3311 3312 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS { 3313 /*! 3314 * Reflects Vpstates PS20 support 3315 */ 3316 NvBool bVpsPs20Supported; 3317 3318 /*! 3319 * Get highest VPState Idx from VBIOS 3320 */ 3321 NvU32 vPstateIdxHighest; 3322 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS; 3323 3324 /*! 3325 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING 3326 * 3327 * Get vPstate mapping for requested pStateIdx 3328 * 3329 * pStateIdx [IN] 3330 * Requested PState Idx 3331 * vPstateIdx [OUT} 3332 * Mapped VPstate Idx 3333 * 3334 * Possible status values returned are: 3335 * NV_OK 3336 * NV_ERR_NOT_SUPPORTED 3337 */ 3338 3339 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */ 3340 3341 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U) 3342 3343 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS { 3344 /*! 3345 * Requested PState Idx 3346 */ 3347 NvU32 pStateIdx; 3348 3349 /*! 3350 * Mapped VPstate Idx 3351 */ 3352 NvU32 vPstateIdxMapping; 3353 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS; 3354 3355 /*! 3356 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE 3357 * 3358 * Set requested VPstate 3359 * 3360 * vPstateIdx [IN] 3361 * VPstate Idx to be set 3362 * 3363 * Possible status values returned are: 3364 * NV_OK 3365 * NV_ERR_NOT_SUPPORTED 3366 */ 3367 3368 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */ 3369 3370 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U) 3371 3372 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { 3373 3374 /*! 3375 * NV_TRUE means enable PM1, NV_FALSE means disable. 3376 */ 3377 NvU32 vPstateIdx; 3378 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; 3379 3380 /* 3381 * NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE 3382 * 3383 * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3 3384 * 3385 * Possible status return values are: 3386 * NV_OK Success 3387 */ 3388 #define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ 3389 3390 #define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) 3391 3392 typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS { 3393 NvBool bIsSatisfied; 3394 } NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS; 3395 3396 /* 3397 * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. 3398 */ 3399 #define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ 3400 3401 /*! 3402 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS 3403 * 3404 * This command is an internal command sent from Kernel RM to Physical RM 3405 * to get number of secure channels supported on SEC2 and CE 3406 * 3407 * maxSec2SecureChannels [OUT] 3408 * maxCeSecureChannels [OUT] 3409 */ 3410 #define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */ 3411 3412 #define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U) 3413 3414 typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS { 3415 NvU32 maxSec2SecureChannels; 3416 NvU32 maxCeSecureChannels; 3417 } NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS; 3418 3419 /* 3420 * NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS 3421 * 3422 * This command is an internal command sent from Kernel RM to Physical RM 3423 * to disable the GPU system memory access after quiescing the GPU or 3424 * re-enable sysmem access. 3425 * 3426 * bDisable [IN] 3427 * If NV_TRUE the GPU is quiesced and system memory access is disabled . 3428 * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. 3429 * 3430 * Possible status values returned are: 3431 * NV_OK 3432 * NV_ERR_INVALID_PARAM_STRUCT 3433 * NV_ERR_INVALID_ARGUMENT 3434 * NV_ERR_NOT_SUPPORTED 3435 */ 3436 #define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */ 3437 3438 #define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU) 3439 3440 typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS { 3441 NvBool bDisable; 3442 } NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS; 3443 3444 #define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */ 3445 3446 #define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU) 3447 3448 typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS { 3449 NvU32 pinSetIn; // in 3450 NvU32 pinSetOut; // in 3451 NvBool bMasterScanLock; // out 3452 NvU32 masterScanLockPin; // out 3453 NvBool bSlaveScanLock; // out 3454 NvU32 slaveScanLockPin; // out 3455 } NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS; 3456 3457 #define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */ 3458 3459 #define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */ 3460 3461 #define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU) 3462 3463 typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS { 3464 NvU32 pinSet; // in 3465 NvU32 gpioFunction; // out 3466 NvU32 gpioPin; // out 3467 NvBool gpioDirection; // out 3468 } NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS; 3469 3470 /* ctrl2080internal_h */ 3471