1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl2080/ctrl2080internal.finn 31 // 32 33 #include "nvimpshared.h" 34 #include "ctrl/ctrl2080/ctrl2080base.h" 35 36 #include "ctrl/ctrl2080/ctrl2080gpu.h" 37 #include "ctrl/ctrl2080/ctrl2080gr.h" /* Some controls derivative of 2080gr */ 38 #include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */ 39 #include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ 40 #include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ 41 #include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */ 42 #include "ctrl/ctrl0000/ctrl0000system.h" 43 #include "ctrl/ctrl90f1.h" 44 #include "ctrl/ctrl30f1.h" 45 #include "nvcfg_sdk.h" 46 47 /*! 48 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO 49 * 50 * This command obtains information from physical RM for use by CPU-RM. 51 * 52 * feHwSysCap 53 * Display IP v03_00 and later. 54 * Contents of capability register. 55 * 56 * windowPresentMask 57 * Display IP v03_00 and later. 58 * Mask for the present WINDOWs actually on the current chip. 59 * bFbRemapperEnabled 60 * Display IP v02_01 and later. 61 * Indicates that the display remapper HW exists and is enabled. 62 * numHeads 63 * Display IP v02_01 and later. 64 * Provides the number of heads HW support. 65 */ 66 67 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 68 69 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U) 70 71 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { 72 NvU32 feHwSysCap; 73 NvU32 windowPresentMask; 74 NvBool bFbRemapperEnabled; 75 NvU32 numHeads; 76 NvBool bPrimaryVga; 77 NvU32 i2cPort; 78 NvU32 internalDispActiveMask; 79 NvU32 embeddedDisplayPortMask; 80 NvBool bExternalMuxSupported; 81 NvBool bInternalMuxSupported; 82 } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; 83 84 85 86 // 87 // MemorySystem settings that are static after GPU state init/load is finished. 88 // 89 // Fields are shared between the VGPU guest/GSP Client as well as the VGPU 90 // host/GSP-RM. 91 // 92 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU) 93 94 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { 95 /*! Determines if RM should use 1 to 1 Comptagline allocation policy */ 96 NvBool bOneToOneComptagLineAllocation; 97 98 /*! Determines if RM should use 1 to 4 Comptagline allocation policy */ 99 NvBool bUseOneToFourComptagLineAllocation; 100 101 /*! Determines if RM should use raw Comptagline allocation policy */ 102 NvBool bUseRawModeComptaglineAllocation; 103 104 /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */ 105 NvBool bDisableCompbitBacking; 106 107 /*! Determine if we need to disable post L2 compression */ 108 NvBool bDisablePostL2Compression; 109 110 /*! Is ECC DRAM feature supported? */ 111 NvBool bEnabledEccFBPA; 112 113 NvBool bL2PreFill; 114 115 /*! L2 cache size */ 116 NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8); 117 118 /*! Indicate whether fpba is present or not */ 119 NvBool bFbpaPresent; 120 121 /*! Size covered by one comptag */ 122 NvU32 comprPageSize; 123 124 /*! log32(comprPageSize) */ 125 NvU32 comprPageShift; 126 127 /*! RAM type */ 128 NvU32 ramType; 129 130 /*! LTC count */ 131 NvU32 ltcCount; 132 133 /*! LTS per LTC count */ 134 NvU32 ltsPerLtcCount; 135 } NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; 136 137 /*! 138 * Retrieve Memory System Static data. 139 */ 140 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */ 141 142 /* 143 * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER 144 * 145 * This command sends access counter buffer pages allocated by CPU-RM 146 * to be setup and enabled in physical RM. 147 * 148 * accessCounterIndex 149 * Index of access counter buffer to register. 150 * 151 * bufferSize 152 * Size of the access counter buffer to register. 153 * 154 * bufferPteArray 155 * Pages of access counter buffer. 156 * 157 * Possible status values returned are: 158 * NV_OK 159 */ 160 #define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ 161 162 #define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES 64 163 #define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) 164 165 typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { 166 NvU32 accessCounterIndex; 167 NvU32 bufferSize; 168 NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); 169 } NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; 170 171 /* 172 * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER 173 * 174 * This command requests physical RM to disable the access counter buffer. 175 * 176 * accessCounterIndex 177 * Index of access counter buffer to unregister. 178 * 179 * Possible status values returned are: 180 * NV_OK 181 */ 182 #define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ 183 184 #define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU) 185 186 typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS { 187 NvU32 accessCounterIndex; 188 } NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS; 189 190 #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 191 192 /*! 193 * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 194 */ 195 196 197 198 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { 199 NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 200 } NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; 201 202 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U) 203 204 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { 205 NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 206 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; 207 208 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */ 209 210 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU) 211 212 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS; 213 214 /* 215 * NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS 216 * 217 * Set flags for use by the video event buffer 218 * 219 * flags 220 * VIDEO_TRACE_FLAG__* 221 * 222 */ 223 #define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID" */ 224 225 #define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID (0x21U) 226 227 typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS { 228 NvU32 flags; 229 } NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS; 230 231 /*! 232 * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER 233 * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS 234 */ 235 236 237 238 #define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 239 240 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { 241 struct { 242 NvU16 gpcId; 243 NvU16 localTpcId; 244 NvU16 localSmId; 245 NvU16 globalTpcId; 246 NvU16 virtualGpcId; 247 NvU16 migratableTpcId; 248 } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM]; 249 250 NvU16 numSm; 251 NvU16 numTpc; 252 } NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; 253 254 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U) 255 256 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { 257 NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 258 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; 259 260 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ 261 262 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U) 263 264 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS; 265 266 /*! 267 * Retrieve BSP Static data. 268 */ 269 #define NV2080_CTRL_CMD_INTERNAL_BSP_GET_CAPS (0x20800a24) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */ 270 271 #define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS 8 272 273 typedef struct NV2080_CTRL_INTERNAL_BSP_CAPS { 274 NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; 275 } NV2080_CTRL_INTERNAL_BSP_CAPS; 276 277 #define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x24U) 278 279 typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS { 280 NV2080_CTRL_INTERNAL_BSP_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 281 NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 282 } NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS; 283 284 /*! 285 * Retrieve MSENC Static data. 286 */ 287 #define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */ 288 289 #define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 8 290 291 typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS { 292 NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE]; 293 } NV2080_CTRL_INTERNAL_MSENC_CAPS; 294 295 #define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x25U) 296 297 typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS { 298 NV2080_CTRL_INTERNAL_MSENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; 299 NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; 300 } NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS; 301 302 303 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 304 #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 305 306 /*! 307 * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK 308 * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK 309 * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK 310 */ 311 312 313 314 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { 315 NvU32 gpcMask; 316 317 /*! 318 * tpcMask is indexed by logical GPC ID for MIG case 319 * and indexed by physical GPC ID for non-MIG case 320 */ 321 NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 322 323 /*! 324 * tpcCount is always indexed by logical GPC ID 325 */ 326 NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 327 NvU32 physGpcMask; 328 NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 329 330 NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT]; 331 NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 332 333 /*! 334 * zcullMask is always indexed by physical GPC ID 335 */ 336 NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 337 338 NvU32 physGfxGpcMask; 339 NvU32 numGfxTpc; 340 } NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; 341 342 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U) 343 344 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { 345 /*! 346 * floorsweeping masks which are indexed via local GR index 347 */ 348 NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 349 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; 350 351 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */ 352 353 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U) 354 355 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS; 356 357 /* 358 * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES 359 * 360 * This command returns physical addresses of specified context buffer. 361 * To obtain addresses of whole buffer firstPage has to be advanced on 362 * subsequent invocations of the control until whole buffer is probed. 363 * If the buffer is contiguous, only single address will be returned by 364 * this control. 365 * 366 * bufferType[IN] 367 * Buffer type as returned by GET_CTX_BUFFER_INFO. 368 * 369 * firstPage[IN] 370 * Index of the first page to return in 'physAddrs' array. 371 * 372 * numPages[OUT] 373 * Number of entries filled in 'physAddrs' array. This will be 0 374 * if firstPage is greater or equal to number of pages managed by 'hBuffer'. 375 * 376 * physAddrs[OUT] 377 * Physical addresses of pages comprising specified buffer. 378 * 379 * bNoMorePages[OUT] 380 * End of buffer reached. Either 'physAddrs' contains last page of the 381 * buffer or 'firstPage' specifies index past the buffer. 382 */ 383 #define NV2080_CTRL_KGR_MAX_BUFFER_PTES 128 384 #define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */ 385 386 #define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U) 387 388 typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS { 389 NvHandle hUserClient; 390 NvHandle hChannel; 391 NvU32 bufferType; 392 NvU32 firstPage; 393 NvU32 numPages; 394 NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8); 395 NvBool bNoMorePages; 396 } NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS; 397 398 /*! 399 * NV2080_CTRL_INTERNAL_MEMDESC_INFO 400 * 401 * A generic container structure representing a memory region to be used as a 402 * component of other control call parameters. 403 * 404 */ 405 typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO { 406 NV_DECLARE_ALIGNED(NvU64 base, 8); 407 NV_DECLARE_ALIGNED(NvU64 size, 8); 408 NV_DECLARE_ALIGNED(NvU64 alignment, 8); 409 NvU32 addressSpace; 410 NvU32 cpuCacheAttrib; 411 } NV2080_CTRL_INTERNAL_MEMDESC_INFO; 412 413 /* 414 * NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY 415 * 416 * Set memory for use by the video event buffer 417 * 418 * memDescInfo 419 * Information to set up memory descriptor on GSP 420 * 421 * engDesc 422 * Video engdesc to find correct engine 423 * 424 * bEngineFound 425 * Bool for whether or not the engine is actually assigned to a video object 426 */ 427 #define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID" */ 428 429 #define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID (0x29U) 430 431 typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS { 432 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO memDescInfo, 8); 433 NvU32 engDesc; 434 NvBool bEngineFound; 435 } NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS; 436 437 /*! 438 * @ref NV0080_CTRL_CMD_GR_GET_INFO 439 * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2 440 * @ref NV2080_CTRL_CMD_GR_GET_INFO 441 * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 442 */ 443 444 445 446 /*! 447 * @ref NV2080_CTRL_GR_INFO 448 */ 449 typedef struct NV2080_CTRL_INTERNAL_GR_INFO { 450 NvU32 index; 451 NvU32 data; 452 } NV2080_CTRL_INTERNAL_GR_INFO; 453 454 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { 455 NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; 456 } NV2080_CTRL_INTERNAL_STATIC_GR_INFO; 457 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU) 458 459 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { 460 NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 461 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; 462 463 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */ 464 465 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU) 466 467 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS; 468 469 /*! 470 * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO 471 */ 472 473 474 475 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO { 476 NvU32 widthAlignPixels; 477 NvU32 heightAlignPixels; 478 NvU32 pixelSquaresByAliquots; 479 NvU32 aliquotTotal; 480 NvU32 zcullRegionByteMultiplier; 481 NvU32 zcullRegionHeaderSize; 482 NvU32 zcullSubregionHeaderSize; 483 NvU32 subregionCount; 484 NvU32 subregionWidthAlignPixels; 485 NvU32 subregionHeightAlignPixels; 486 } NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; 487 488 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU) 489 490 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { 491 NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 492 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; 493 494 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ 495 496 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU) 497 498 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS; 499 500 /*! 501 * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO 502 */ 503 504 505 506 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO { 507 NvU32 ropUnitCount; 508 NvU32 ropOperationsFactor; 509 NvU32 ropOperationsCount; 510 } NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; 511 512 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU) 513 514 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { 515 NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 516 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; 517 518 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ 519 520 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU) 521 522 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS; 523 524 /*! 525 * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK 526 */ 527 528 529 530 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS { 531 NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 532 } NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; 533 534 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U) 535 536 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { 537 NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 538 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; 539 540 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */ 541 542 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U) 543 544 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS; 545 546 /*! 547 * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES 548 * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE 549 */ 550 551 552 553 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x1a 554 555 typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO { 556 NvU32 size; 557 NvU32 alignment; 558 } NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO; 559 560 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO { 561 NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; 562 } NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; 563 564 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U) 565 566 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { 567 NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 568 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; 569 570 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */ 571 572 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U) 573 574 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS; 575 576 /*! 577 * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER 578 */ 579 580 581 582 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER { 583 NvU8 imla0; 584 NvU8 fmla16; 585 NvU8 dp; 586 NvU8 fmla32; 587 NvU8 ffma; 588 NvU8 imla1; 589 NvU8 imla2; 590 NvU8 imla3; 591 NvU8 imla4; 592 } NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; 593 594 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U) 595 596 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { 597 NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 598 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; 599 600 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ 601 602 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U) 603 604 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; 605 606 /* 607 * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS 608 * 609 * This command obtains information from physical RM for use by CPU-RM. 610 */ 611 612 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */ 613 614 /* 615 * Maximum number of register bases to return. 616 * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs 617 * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h 618 */ 619 #define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16 620 #define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U) 621 622 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS { 623 NvU8 chipSubRev; 624 NvU32 emulationRev1; 625 NvBool isCmpSku; 626 NvU32 pciDeviceId; 627 NvU32 pciSubDeviceId; 628 NvU32 pciRevisionId; 629 NvU32 regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX]; 630 } NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS; 631 632 /** 633 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE 634 * 635 * Set whether or not context switch logging is enabled 636 * 637 * bEnable 638 * Enable/Disable status for context switch logging 639 */ 640 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ 641 642 /** 643 * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE 644 * 645 * Retrieve whether or not context switch logging is enabled 646 * 647 * bEnable 648 * Enable/Disable status for context switch logging 649 */ 650 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ 651 652 typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS { 653 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 654 NvBool bEnable; 655 } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; 656 657 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) 658 659 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; 660 661 #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) 662 663 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; 664 665 /** 666 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET 667 * 668 * Set read offset into FECS context switch trace record 669 * 670 * offset 671 * Value indicating number of records by which to offset 672 */ 673 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ 674 675 /** 676 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET 677 * 678 * Set write offset into FECS context switch trace record 679 * 680 * offset 681 * Value indicating number of records by which to offset 682 */ 683 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */ 684 685 /** 686 * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET 687 * 688 * Get read offset into FECS context switch trace record 689 * 690 * offset 691 * Value indicating number of records by which to offset 692 */ 693 694 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ 695 696 typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS { 697 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 698 NvU32 offset; 699 } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS; 700 701 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) 702 703 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; 704 705 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) 706 707 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; 708 709 #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) 710 711 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; 712 713 /** 714 * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE 715 * 716 * Get size of FECS record 717 * 718 * fecsRecordSize 719 * Size of FECS record 720 */ 721 722 723 724 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */ 725 726 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE { 727 NvU32 fecsRecordSize; 728 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE; 729 730 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU) 731 732 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { 733 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 734 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; 735 736 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) 737 738 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; 739 740 /** 741 * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES 742 * 743 * Get HW defines used to extract information from FECS records 744 * 745 * fecsRecordSize 746 * Size of FECS record 747 * 748 * timestampHiTagMask 749 * Mask for high bits of raw timestamp to extract tag 750 * 751 * timestampHiTagShift 752 * Shift for high bits of raw timestamp to extract tag 753 * 754 * timestampVMask 755 * Mask to extract timestamp from raw timestamp 756 * 757 * numLowerBitsZeroShift 758 * Number of bits timestamp is shifted by 759 */ 760 761 762 763 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { 764 NvU32 fecsRecordSize; 765 NvU32 timestampHiTagMask; 766 NvU8 timestampHiTagShift; 767 NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8); 768 NvU8 numLowerBitsZeroShift; 769 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; 770 771 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU) 772 773 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { 774 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); 775 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; 776 777 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */ 778 779 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU) 780 781 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS; 782 783 /** 784 * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE 785 * 786 * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel. 787 */ 788 typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { 789 NvU32 faultId; 790 NvU32 instanceId; 791 NvU32 typeEnum; 792 NvU32 resetId; 793 NvU32 devicePriBase; 794 NvU32 isEngine; 795 NvU32 rlEngId; 796 NvU32 runlistPriBase; 797 NvU32 groupId; 798 } NV2080_CTRL_INTERNAL_DEVICE_INFO; 799 #define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256 800 801 #define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ 802 803 #define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U) 804 805 typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS { 806 NvU32 numEntries; 807 NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES]; 808 } NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS; 809 810 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */ 811 812 #define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE 4096 813 #define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096 814 815 #define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U) 816 817 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS { 818 NvU32 userRegisterAccessMapSize; 819 NvU32 compressedSize; 820 NvU8 compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE]; 821 NvU32 profilingRangesSize; 822 NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES]; 823 } NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS; 824 825 /** 826 * Get GR PDB properties synchronized between Kernel and Physical 827 * 828 * bPerSubCtxheaderSupported 829 * @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER 830 */ 831 832 833 834 typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { 835 NV_DECLARE_ALIGNED(NvU64 lo, 8); 836 NV_DECLARE_ALIGNED(NvU64 hi, 8); 837 } NV2080_CTRL_INTERNAL_NV_RANGE; 838 839 /*! 840 * NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS 841 * 842 * This structure specifies a target swizz-id and mem_range to update 843 * 844 * swizzId[IN] 845 * - Targeted swizz-id for which the memRange is being set 846 * 847 * memAddrRange[IN] 848 * - Memory Range for given GPU instance 849 */ 850 #define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U) 851 852 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS { 853 NvU32 swizzId; 854 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8); 855 } NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; 856 857 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ 858 859 #define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U) 860 861 typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; 862 863 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ 864 865 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { 866 NvBool bPerSubCtxheaderSupported; 867 } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; 868 869 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U) 870 871 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { 872 NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 873 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; 874 875 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */ 876 877 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U) 878 879 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS; 880 881 /*! 882 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM 883 * 884 * This command writes instance memory information in the display hardware registers. 885 * 886 * instMemPhysAddr 887 * GPU physical address or IOVA address of the display instance memory. 888 * 889 * instMemSize 890 * Size of the display instance memory. 891 * 892 * instMemAddrSpace 893 * Address space of the display instance memory. 894 * 895 * instMemCpuCacheAttr 896 * Cache attribute of the display instance memory. 897 */ 898 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ 899 900 #define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U) 901 902 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { 903 NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); 904 NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); 905 NvU32 instMemAddrSpace; 906 NvU32 instMemCpuCacheAttr; 907 } NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; 908 909 /* 910 * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS 911 * 912 * This command issues RC recovery for all compute contexts running on the given GPU. 913 */ 914 #define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */ 915 916 /*! 917 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION 918 * 919 * This command obtains IP version of display engine for use by Kernel RM. 920 * 921 * ipVersion 922 * IP Version of display engine. 923 * 924 * Possible status values returned are: 925 * NV_OK 926 * NV_ERR_NOT_SUPPORTED - DISP has been disabled 927 */ 928 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ 929 930 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU) 931 932 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS { 933 NvU32 ipVersion; 934 } NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS; 935 936 /*! 937 * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE 938 * 939 * This command determines the current status of MIG MODE from Physical RM. 940 * 941 * smcMode [OUT] 942 * Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE* 943 */ 944 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */ 945 946 #define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU) 947 948 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS { 949 NvU32 smcMode; 950 } NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS; 951 952 /*! 953 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR 954 * 955 * head 956 * This parameter specifies the head for which the callback is to be registered/unregistered. This value must be 957 * less than the maximum number of heads supported by the GPU subdevice. 958 * 959 * rgLineNum 960 * This indicates the RG scanout line number on which the callback will be executed. 961 * 962 * intrLine 963 * Enable: [out] Which interrupt line was allocated for this head. 964 * Disable: [in] Which interrupt line to deallocate. 965 * 966 * bEnable 967 * Should we allocate or deallocate an interrupt line? 968 * 969 * Possible status values returned are: 970 * NV_OK 971 * NV_ERR_GENERIC - There was no available interrupt to allocate. 972 * NV_ERR_INVALID_ARGUMENT 973 */ 974 975 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */ 976 977 #define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU) 978 979 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { 980 NvU32 head; 981 NvU32 rgLineNum; 982 NvU32 intrLine; 983 NvBool bEnable; 984 } NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS; 985 986 /*! 987 * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO 988 * 989 * Description of a supported GPU instance. 990 * 991 * partitionFlag [OUT] 992 * Allocation flag to be used to allocate a partition with this profile. 993 * 994 * grCount [OUT] 995 * # GR engines, including the GFX capable ones. 996 * 997 * gfxGrCount [OUT] 998 * # GR engines capable of Gfx, which is a subset of the GR engines included in grCount 999 * 1000 * gpcCount [OUT] 1001 * # total gpcs, including the GFX capable ones. 1002 * 1003 * virtualGpcCount [OUT] 1004 * # virtualized gpcs, including the GFX capable ones. 1005 * 1006 * gfxGpcCount [OUT] 1007 * # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount. 1008 * 1009 * veidCount [OUT] 1010 * # total veids 1011 * 1012 * smCount [OUT] 1013 * # total SMs 1014 * 1015 * ceCount [OUT] 1016 * # CE engines 1017 * 1018 * nvEncCount [OUT] 1019 * # NVENC engines 1020 * 1021 * nvDecCount [OUT] 1022 * # NVDEC engines 1023 * 1024 * nvJpgCount [OUT] 1025 * # NVJPG engines 1026 * 1027 * nvOfaCount [OUT] 1028 * # NVOFA engines 1029 * 1030 * validCTSIdMask [OUT] 1031 * # mask of CTS IDs which can be assigned under this profile 1032 * 1033 * validGfxCTSIdMask [OUT] 1034 * # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile 1035 */ 1036 #define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60 1037 1038 1039 1040 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { 1041 NvU32 partitionFlag; 1042 NvU32 grCount; 1043 NvU32 gfxGrCount; 1044 NvU32 gpcCount; 1045 NvU32 virtualGpcCount; 1046 NvU32 gfxGpcCount; 1047 NvU32 veidCount; 1048 NvU32 smCount; 1049 NvU32 ceCount; 1050 NvU32 nvEncCount; 1051 NvU32 nvDecCount; 1052 NvU32 nvJpgCount; 1053 NvU32 nvOfaCount; 1054 NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); 1055 NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); 1056 } NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; 1057 1058 /*! 1059 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS 1060 * 1061 * Returns the list of supported GPU instance profiles. 1062 * 1063 * count [OUT] 1064 * Number of supported profiles. 1065 * 1066 * table [OUT] 1067 * Supported profiles. 1068 */ 1069 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU) 1070 1071 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { 1072 NvU32 count; 1073 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); 1074 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS; 1075 1076 /*! 1077 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM 1078 * 1079 * This command instructs the physical MemorySystem to set up memory partitioning 1080 * exterior boundaries in hardware. 1081 * 1082 * partitionableMemSize [input] 1083 * Size of the partitionable memory in bytes 1084 * 1085 * bottomRsvdSize [input] 1086 * Size of the reserved region below partitionable memory in bytes 1087 * 1088 * topRsvdSize [input] 1089 * Size of the reserved region above partitionable memory in bytes 1090 * 1091 * partitionableStartAddr [output] 1092 * Start address of the partitionable memory, aligned to HW constraints 1093 * 1094 * partitionableEndAddr [output] 1095 * End address of the partitionable memory, aligned to HW constraints 1096 */ 1097 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */ 1098 1099 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U) 1100 1101 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { 1102 NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8); 1103 NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8); 1104 NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8); 1105 NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8); 1106 NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8); 1107 } NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS; 1108 1109 1110 1111 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE 4 1112 1113 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U) 1114 1115 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { 1116 NV_DECLARE_ALIGNED(NvU64 engineMask[NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE], 8); 1117 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; 1118 1119 #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2 1120 #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID 64 1121 /*! 1122 * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS 1123 * 1124 * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM 1125 * 1126 * rlBuffers [IN] 1127 * 2D array of runlist buffers for a single partition 1128 * 1129 * runlistIdMask [IN] 1130 * Mask of runlists belonging to partition 1131 * 1132 */ 1133 #define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */ 1134 1135 #define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U) 1136 1137 typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS { 1138 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8); 1139 NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8); 1140 NvU32 swizzId; 1141 } NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS; 1142 1143 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */ 1144 1145 #define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U) 1146 1147 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { 1148 TEGRA_IMP_IMPORT_DATA tegraImpImportData; 1149 } NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; 1150 1151 #define NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID" */ 1152 1153 #define NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID (0x55U) 1154 1155 typedef struct NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS { 1156 NvU16 pciDeviceId; 1157 NvU16 pciSubDeviceId; 1158 NvBool iseGPUBridge; 1159 NvU8 approvedBusType; 1160 } NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS; 1161 1162 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE (0x00000000) 1163 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM (0x00000001) 1164 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 (0x00000002) 1165 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 (0x00000003) 1166 1167 1168 /*! 1169 * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR 1170 * 1171 * This command triggers a sysmembar to flush VIDMEM writes. 1172 * This command accepts no parameters. 1173 * 1174 */ 1175 #define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */ 1176 1177 /* 1178 * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL 1179 * 1180 * Setup local PCIE P2P Mailbox 1181 * 1182 * local2Remote[IN] 1183 * Local peer ID of remote gpu on local gpu 1184 * 1185 * remote2Local[IN] 1186 * Remote peer ID of local gpu on remote gpu 1187 * 1188 * localP2PDomainRemoteAddr[IN] 1189 * P2P domain remote address on local gpu 1190 * 1191 * remoteP2PDomainLocalAddr[IN] 1192 * P2P domain local address on remote gpu 1193 * 1194 * remoteWMBoxLocalAddr[IN] 1195 * Local mailbox address on remote gpu 1196 * 1197 * p2pWmbTag[OUT] 1198 * Tag for mailbox to transport from local to remote GPU 1199 * 1200 * bNeedWarBug999673[IN] 1201 * Set to true if WAR for bug 999673 is required 1202 * 1203 * Possible status values returned are: 1204 * NV_OK 1205 * NV_ERR_NOT_SUPPORTED 1206 */ 1207 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */ 1208 1209 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U) 1210 1211 typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS { 1212 NvU32 local2Remote; 1213 NvU32 remote2Local; 1214 NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); 1215 NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); 1216 NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8); 1217 NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); 1218 NvBool bNeedWarBug999673; 1219 } NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS; 1220 1221 /* 1222 * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE 1223 * 1224 * Setup remote PCIE P2P Mailbox 1225 * 1226 * local2Remote[IN] 1227 * Local peer ID of remote gpu on local gpu 1228 * 1229 * remote2Local[IN] 1230 * Remote peer ID of local gpu on remote gpu 1231 * 1232 * localP2PDomainRemoteAddr[IN] 1233 * P2P domain remote address on local gpu 1234 * 1235 * remoteP2PDomainLocalAddr[IN] 1236 * P2P domain local address on remote gpu 1237 * 1238 * remoteWMBoxAddrU64[IN] 1239 * Mailbox address on remote gpu 1240 * 1241 * p2pWmbTag[IN] 1242 * Tag for mailbox to transport from local to remote GPU 1243 * 1244 * Possible status values returned are: 1245 * NV_OK 1246 * NV_ERR_NOT_SUPPORTED 1247 */ 1248 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */ 1249 1250 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U) 1251 1252 typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS { 1253 NvU32 local2Remote; 1254 NvU32 remote2Local; 1255 NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); 1256 NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); 1257 NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8); 1258 NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); 1259 } NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS; 1260 1261 /* 1262 * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX 1263 * 1264 * Destroy PCIE P2P Mailbox 1265 * 1266 * peerIdx[IN] 1267 * Peer ID of the P2P destination GPU 1268 * 1269 * bNeedWarBug999673[IN] 1270 * Set to true if WAR for bug 999673 is required 1271 * 1272 * Possible status values returned are: 1273 * NV_OK 1274 * NV_ERR_NOT_SUPPORTED 1275 */ 1276 #define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */ 1277 1278 #define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U) 1279 1280 typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS { 1281 NvU32 peerIdx; 1282 NvBool bNeedWarBug999673; 1283 } NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS; 1284 1285 /* 1286 * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING 1287 * 1288 * Create C2C mapping to a given peer GPU 1289 * 1290 * peerId[IN] 1291 * Peer ID for local to remote GPU 1292 * 1293 * Possible status values returned are: 1294 * NV_OK 1295 * NV_ERR_NOT_SUPPORTED 1296 */ 1297 #define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ 1298 1299 #define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U) 1300 1301 typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS { 1302 NvU32 peerId; 1303 } NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS; 1304 1305 /* 1306 * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING 1307 * 1308 * Remove C2C mapping to a given peer GPU 1309 * 1310 * peerId[IN] 1311 * Peer ID for local to remote GPU 1312 * 1313 * Possible status values returned are: 1314 * NV_OK 1315 * NV_ERR_NOT_SUPPORTED 1316 */ 1317 #define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ 1318 1319 #define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U) 1320 1321 typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS { 1322 NvU32 peerId; 1323 } NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS; 1324 1325 /*! 1326 * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES 1327 * 1328 * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings) 1329 * for the given array of GPAs. 1330 * 1331 * gfid [IN] 1332 * GFID to translate GPAs for 1333 * 1334 * numEntries [IN] 1335 * Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES) 1336 * to translate (i.e. number of elements in gpaEntries) 1337 * 1338 * gpaEntries [IN] 1339 * Array of GPAs to translate 1340 * 1341 * spaEntries [OUT] 1342 * Resulting array of SPAs 1343 */ 1344 #define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */ 1345 1346 #define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES 128 1347 1348 #define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U) 1349 1350 typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS { 1351 NvU32 gfid; 1352 NvU32 numEntries; 1353 NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); 1354 NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); 1355 } NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS; 1356 1357 /*! 1358 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER 1359 * 1360 * Pass required pushbuffer parameters from kernel RM to Physical RM 1361 * 1362 * addressSpace [IN] 1363 * Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM 1364 * 1365 * physicalAddr [IN] 1366 * Physical address of pushbuffer 1367 * 1368 * addressSpace [IN] 1369 * Limit of the pushbuffer address, it should be less than 4K 1370 * 1371 * cacheSnoop [IN] 1372 * Cachesnoop supported or not 1373 * 1374 * channelInstance [IN] 1375 * Channel instance pass by the client to get corresponding dispchannel 1376 * 1377 * hclass [IN] 1378 * External class ID pass by the client to get the channel class 1379 * 1380 * valid [IN] 1381 * This bit indicates whether pushbuffer parameters are valid or not 1382 * 1383 * pbTargetAperture [IN] 1384 * Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM) 1385 * 1386 */ 1387 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ 1388 1389 #define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U) 1390 1391 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { 1392 NvU32 addressSpace; 1393 NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); 1394 NV_DECLARE_ALIGNED(NvU64 limit, 8); 1395 NvU32 cacheSnoop; 1396 NvU32 hclass; 1397 NvU32 channelInstance; 1398 NvBool valid; 1399 NvU32 pbTargetAperture; 1400 } NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; 1401 1402 /*! 1403 * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO 1404 * 1405 * This command obtains information from physical RM for use by CPU-RM. 1406 * 1407 * replayableFaultBufferSize 1408 * Default size of replayable fault buffer 1409 * 1410 * nonReplayableFaultBufferSize 1411 * Default size of non-replayable fault buffer 1412 * 1413 */ 1414 1415 #define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 1416 1417 #define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U) 1418 1419 typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { 1420 NvU32 replayableFaultBufferSize; 1421 NvU32 replayableShadowFaultBufferMetadataSize; 1422 NvU32 nonReplayableFaultBufferSize; 1423 NvU32 nonReplayableShadowFaultBufferMetadataSize; 1424 } NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; 1425 1426 /*! 1427 * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES 1428 */ 1429 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ 1430 1431 #define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU) 1432 1433 typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS; 1434 1435 /*! 1436 * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE 1437 * 1438 * Get heap reservation size needed by different module 1439 */ 1440 #define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */ 1441 1442 #define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU) 1443 1444 typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS { 1445 NvU32 moduleIndex; 1446 NvU32 size; 1447 } NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS; 1448 1449 /*! 1450 * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE 1451 * 1452 * tableLen [OUT] 1453 * Number of valid records in table field. 1454 * 1455 * table [OUT] 1456 * Interrupt table for Kernel RM. 1457 * 1458 * subtreeMap [OUT] 1459 * Subtree range for each NV2080_INTR_CATEGORY. 1460 */ 1461 #define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ 1462 1463 #define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 1464 1465 /*! 1466 * Categories of interrupts. 1467 * 1468 * Each of these categories get a separate range of interrupt subtrees (top 1469 * level bits). 1470 */ 1471 typedef enum NV2080_INTR_CATEGORY { 1472 NV2080_INTR_CATEGORY_DEFAULT = 0, 1473 NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1, 1474 NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2, 1475 NV2080_INTR_CATEGORY_RUNLIST = 3, 1476 NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4, 1477 NV2080_INTR_CATEGORY_UVM_OWNED = 5, 1478 NV2080_INTR_CATEGORY_UVM_SHARED = 6, 1479 NV2080_INTR_CATEGORY_ENUM_COUNT = 7, 1480 } NV2080_INTR_CATEGORY; 1481 1482 #define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX 1483 1484 typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP { 1485 NvU8 subtreeStart; 1486 NvU8 subtreeEnd; 1487 } NV2080_INTR_CATEGORY_SUBTREE_MAP; 1488 1489 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { 1490 NvU16 engineIdx; 1491 NvU32 pmcIntrMask; 1492 NvU32 vectorStall; 1493 NvU32 vectorNonStall; 1494 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY; 1495 1496 #define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU) 1497 1498 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { 1499 NvU32 tableLen; 1500 NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; 1501 NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT]; 1502 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; 1503 1504 /* Index to retrieve the needed heap space for specific module */ 1505 #define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR (0x00000000) 1506 1507 /* 1508 * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK 1509 * 1510 * Checking if the reservation / release of the PERFMON HW is possible 1511 * 1512 * bReservation [IN] 1513 * NV_TRUE -> request for reservation, NV_FALSE -> request for release 1514 * 1515 */ 1516 #define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */ 1517 1518 1519 #define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U) 1520 1521 typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS { 1522 NvBool bReservation; 1523 } NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS; 1524 1525 /*! 1526 * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET 1527 * 1528 * Reserving / Releasing PERFMON HW 1529 * 1530 * bReservation [IN] 1531 * NV_TRUE -> request for reservation, NV_FALSE -> request for release 1532 * 1533 * bClientHandlesGrGating [IN] 1534 * DM-TODO: Add comment for this 1535 * 1536 * bRmHandlesIdleSlow [IN] 1537 * If the IDLE slowdown is required 1538 * 1539 */ 1540 #define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */ 1541 1542 #define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U) 1543 1544 typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS { 1545 NvBool bReservation; 1546 NvBool bClientHandlesGrGating; 1547 NvBool bRmHandlesIdleSlow; 1548 } NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS; 1549 1550 /*! 1551 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES 1552 * 1553 * Get active display devices 1554 * 1555 * displayMask [OUT] 1556 * Get the mask of the active display devices in VBIOS 1557 * 1558 * numHeads [OUT] 1559 * Number of heads display supported. 1560 * 1561 */ 1562 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */ 1563 1564 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU) 1565 1566 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { 1567 1568 NvU32 displayMask; 1569 NvU32 numHeads; 1570 } NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS; 1571 1572 1573 1574 /* 1575 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1576 * 1577 * Get FB Mem page ranges for all possible swizzIds 1578 * 1579 * fbMemPageRanges [OUT] 1580 * Mem page ranges for each swizzId in the form of {lo, hi} 1581 */ 1582 #define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ 1583 1584 #define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 1585 1586 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) 1587 1588 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { 1589 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8); 1590 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; 1591 1592 /*! 1593 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS 1594 * 1595 * This command is an internal command sent from Kernel RM to Physical RM 1596 * to get number of channels for a given runlist ID 1597 * 1598 * runlistId [IN] 1599 * numChannels [OUT] 1600 */ 1601 #define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */ 1602 1603 #define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U) 1604 1605 typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { 1606 NvU32 runlistId; 1607 NvU32 numChannels; 1608 } NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS; 1609 1610 /*! 1611 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES 1612 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES 1613 */ 1614 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */ 1615 1616 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U) 1617 1618 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS; 1619 1620 /*! 1621 * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES 1622 * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES 1623 */ 1624 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */ 1625 1626 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U) 1627 1628 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; 1629 1630 /*! 1631 * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1632 * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1633 */ 1634 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ 1635 1636 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U) 1637 1638 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; 1639 1640 /*! 1641 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG 1642 * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG 1643 * 1644 * This command retrieves memory config from HW 1645 * 1646 * memBoundaryCfgA [OUT] 1647 * Memory boundary config A (4KB aligned) 1648 * 1649 * memBoundaryCfgB [OUT] 1650 * Memory boundary config B (4KB aligned) 1651 * 1652 * memBoundaryCfgC [OUT] 1653 * Memory boundary config C (64KB aligned) 1654 * 1655 * memBoundaryCfg [OUT] 1656 * Memory boundary config (64KB aligned) 1657 * 1658 * memBoundaryCfgValInit [OUT] 1659 * Memory boundary config initial value (64KB aligned) 1660 */ 1661 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ 1662 1663 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U) 1664 1665 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { 1666 NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); 1667 NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8); 1668 NvU32 memBoundaryCfgC; 1669 NvU32 memBoundaryCfg; 1670 NvU32 memBoundaryCfgValInit; 1671 } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; 1672 1673 #define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ 1674 1675 #define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U) 1676 1677 typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; 1678 1679 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ 1680 1681 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 1682 1683 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU) 1684 1685 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS { 1686 NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE]; 1687 } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS; 1688 1689 /*! 1690 * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT 1691 * 1692 * Invoke RC recovery after watchdog timeout is hit. 1693 */ 1694 #define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ 1695 1696 /* ! 1697 * This command disables cuda limit activation at teardown of the client. 1698 */ 1699 #define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */ 1700 1701 /* 1702 * This command is cleaning up OPTP when a client is found to have 1703 * been terminated unexpectedly. 1704 */ 1705 #define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */ 1706 1707 /* ! 1708 * This command is used to get the current AUX power state of the sub-device. 1709 */ 1710 #define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ 1711 1712 #define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U) 1713 1714 typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS { 1715 NvU32 powerState; 1716 } NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS; 1717 1718 /*! 1719 * This command can be used to boost P-State up one level or to the highest for a limited 1720 * duration for the associated subdevice. Boosts from different clients are being tracked 1721 * independently. Note that there are other factors that can limit P-States so the resulting 1722 * P-State may differ from expectation. 1723 * 1724 * flags 1725 * This parameter specifies the actual command. _CLEAR is to clear existing boost. 1726 * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost 1727 * to the highest P-State. 1728 * duration 1729 * This parameter specifies the duration of the boost in seconds. This has to be less 1730 * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. 1731 * 1732 * Possible status values returned are: 1733 * NV_OK 1734 * NV_ERR_INVALID_PARAM_STRUCT 1735 * NV_ERR_INVALID_ARGUMENT 1736 */ 1737 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ 1738 1739 #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU) 1740 1741 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X { 1742 1743 NvBool flags; 1744 NvU32 duration; 1745 } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X; 1746 1747 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE 0U 1748 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1U 1749 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1750 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */ 1751 1752 /*! 1753 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL 1754 * 1755 * Activate/Deactivate GPU Boost Sync algorithm 1756 * 1757 * bActivate [IN] 1758 * GPU Boost Sync algorithm: 1759 * NV_TRUE -> activate 1760 * NV_FALSE -> deactivate 1761 * 1762 */ 1763 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ 1764 1765 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU) 1766 1767 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS { 1768 NvBool bActivate; 1769 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS; 1770 1771 /*! 1772 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS 1773 * 1774 * Apply given limits to a specific subdevice 1775 * 1776 * flags [IN] 1777 * DM-TODO: write description here 1778 * 1779 * bBridgeless [IN] 1780 * Bridgeless information, for now supporting only MIO bridges 1781 * 1782 * currLimits 1783 * Array of limits that will be applied 1784 * 1785 */ 1786 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */ 1787 1788 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU) 1789 1790 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS { 1791 NvU32 flags; 1792 NvBool bBridgeless; 1793 NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM]; 1794 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS; 1795 1796 /*! 1797 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO 1798 * 1799 * Data for GPU Boost Sync structure initialization 1800 * 1801 * hysteresisus [OUT] 1802 * Hysteresis value for GPU Boost synchronization hysteresis algorithm. 1803 * 1804 * bHystersisEnable [OUT] 1805 * hysteresis algorithm for SLI GPU Boost synchronization: 1806 * NV_TRUE -> enabled, 1807 * NV_FALSE -> disabled 1808 * 1809 * bSliGpuBoostSyncEnable [OUT] 1810 * SLI GPU Boost feature is: 1811 * NV_TRUE -> enabled, 1812 * NV_FALSE -> disabled 1813 * 1814 */ 1815 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */ 1816 1817 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U) 1818 1819 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS { 1820 NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8); 1821 NvBool bHystersisEnable; 1822 NvBool bSliGpuBoostSyncEnable; 1823 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS; 1824 1825 /* 1826 * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER 1827 * 1828 * This command sends replayable fault buffer pages allocated by CPU-RM 1829 * to be setup and enabled in physical RM. 1830 * 1831 * hClient 1832 * Client handle. 1833 * 1834 * hObject 1835 * Object handle. 1836 * 1837 * faultBufferSize 1838 * Size of the replayable fault buffer to register. 1839 * 1840 * faultBufferPteArray 1841 * Pages of replayable fault buffer. 1842 * 1843 * Possible status values returned are: 1844 * NV_OK 1845 */ 1846 #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1847 1848 #define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES 256 1849 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU) 1850 1851 typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { 1852 NvHandle hClient; 1853 NvHandle hObject; 1854 NvU32 faultBufferSize; 1855 NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8); 1856 } NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS; 1857 1858 /* 1859 * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER 1860 * 1861 * This command requests physical RM to disable the replayable fault buffer. 1862 * 1863 * Possible status values returned are: 1864 * NV_OK 1865 */ 1866 #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ 1867 1868 // Valid fault buffer types 1869 #define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) 1870 #define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) 1871 1872 /* 1873 * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER 1874 * 1875 * This command sends client shadow fault buffer pages allocated by CPU-RM 1876 * to be setup and enabled in physical RM. 1877 * 1878 * shadowFaultBufferQueuePhysAddr 1879 * Physical address of shadow fault buffer queue. 1880 * 1881 * faultBufferSize 1882 * Size of the client shadow fault buffer to register. 1883 * 1884 * shadowFaultBufferPteArray 1885 * Pages of client shadow fault buffer. 1886 * 1887 * shadowFaultBufferType 1888 * Replayable or non-replayable fault buffer 1889 * 1890 * faultBufferSharedMemoryPhysAddr 1891 * Fault buffer shared memory address. Used only by the Replayable fault buffer. 1892 * 1893 * Possible status values returned are: 1894 * NV_OK 1895 */ 1896 #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1897 1898 #define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 3000 1899 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) 1900 1901 typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { 1902 NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); 1903 NvU32 shadowFaultBufferSize; 1904 NvU32 shadowFaultBufferMetadataSize; 1905 NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); 1906 NvU32 shadowFaultBufferType; 1907 NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8); 1908 } NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; 1909 1910 /* 1911 * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER 1912 * 1913 * This command requests physical RM to disable the client shadow fault buffer. 1914 * 1915 * shadowFaultBufferType 1916 * Replayable or non-replayable fault buffer 1917 * 1918 * Possible status values returned are: 1919 * NV_OK 1920 */ 1921 #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1922 1923 #define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU) 1924 1925 typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { 1926 NvU32 shadowFaultBufferType; 1927 } NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; 1928 1929 /* 1930 * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER 1931 * 1932 * Pin PDEs for Global VA range on the server RM and then mirror the client's page 1933 * directory/tables in the server. 1934 * 1935 * Possible status values returned are: 1936 * NV_OK 1937 */ 1938 #define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */ 1939 1940 #define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU) 1941 1942 typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS { 1943 NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); 1944 } NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; 1945 1946 /*! 1947 * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X 1948 * 1949 * This command can be used to boost P-State the highest for a limited 1950 * duration for the associated subdevice. Boosts from different clients are being tracked 1951 * independently. Note that there are other factors that can limit P-States so the resulting 1952 * P-State may differ from expectation. 1953 * 1954 * flags [IN] 1955 * This parameter specifies the actual command. _CLEAR is to clear existing boost. 1956 * and _BOOST_TO_MAX is to boost to the highest P-State. 1957 * 1958 * boostDuration [IN] 1959 * This parameter specifies the duration of the boost in seconds. This has to be less 1960 * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. 1961 * 1962 * gfId [IN] 1963 * This specifies Id of the Kernel RM that is requesting the Boost 1964 * 1965 * bOverrideInfinite[IN] 1966 * This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM. 1967 * This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM 1968 * and setting the boost duration to a next maximum duration registered for the Kernel RM in question. 1969 * 1970 * Possible status values returned are: 1971 * NV_OK 1972 * NV_ERR_INVALID_PARAM_STRUCT 1973 * NV_ERR_INVALID_ARGUMENT 1974 */ 1975 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ 1976 1977 #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) 1978 1979 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X { 1980 NvU32 flags; 1981 NvU32 boostDuration; 1982 NvU32 gfId; 1983 NvBool bOverrideInfinite; 1984 } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X; 1985 1986 /*! 1987 * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X 1988 * 1989 * Clear the boost for specific Kernel RM 1990 * 1991 * bIsCudaClient [IN] 1992 * Specifies if the request is for clearing the CUDA boost or regular boost 1993 * NV_TRUE -> CUDA boost, NV_FALSE otherwise 1994 * 1995 * gfId [IN] 1996 * Specifies Id of the Kernel RM that is requesting Boost clear 1997 * 1998 */ 1999 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */ 2000 2001 #define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U) 2002 2003 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { 2004 2005 NvBool bIsCudaClient; 2006 NvU32 gfId; 2007 } NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X; 2008 2009 /* 2010 * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO 2011 * 2012 * Retrieves skyline information about the GPU. Params are sized to currently known max 2013 * values, but will need to be modified in the future should that change. 2014 */ 2015 #define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ 2016 2017 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8 2018 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 12 2019 /*! 2020 * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO 2021 * skylineVgpcSize[OUT] 2022 * - TPC count of non-singleton VGPCs 2023 * singletonVgpcMask[OUT] 2024 * - Mask of active Singletons 2025 * maxInstances[OUT] 2026 * - Max allowed instances of this skyline concurrently on a GPU 2027 * computeSizeFlag 2028 * - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline 2029 * numNonSingletonVgpcs 2030 * - Number of VGPCs with non-zero TPC counts which are not singletons 2031 */ 2032 typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO { 2033 NvU8 skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS]; 2034 NvU32 singletonVgpcMask; 2035 NvU32 maxInstances; 2036 NvU32 computeSizeFlag; 2037 NvU32 numNonSingletonVgpcs; 2038 } NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO; 2039 2040 /*! 2041 * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS 2042 * skylineTable[OUT] 2043 * - TPC count of non-singleton VGPCs 2044 * - Mask of singleton vGPC IDs active 2045 * - Max Instances of this skyline possible concurrently 2046 * - Associated compute size with the indexed skyline 2047 * - Number of VGPCs with non-zero TPC counts which are not singletons 2048 * validEntries[OUT] 2049 * - Number of entries which contain valid info in skylineInfo 2050 */ 2051 #define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U) 2052 2053 typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { 2054 NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES]; 2055 NvU32 validEntries; 2056 } NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS; 2057 2058 /*! 2059 * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE 2060 */ 2061 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ 2062 2063 #define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U) 2064 2065 typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS; 2066 2067 /*! 2068 * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION 2069 */ 2070 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2071 2072 #define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U) 2073 2074 typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS; 2075 2076 /*! 2077 * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS 2078 */ 2079 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ 2080 2081 #define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U) 2082 2083 typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS; 2084 2085 /*! 2086 * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS 2087 */ 2088 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ 2089 2090 #define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U) 2091 2092 typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS; 2093 2094 /*! 2095 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED 2096 * 2097 * Tell Physical RM whether any ZBC-kind surfaces are allocated. 2098 * If PF and all VFs report false, ZBC table can be flushed by Physical RM. 2099 * 2100 * bZbcReferenced [IN] 2101 * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM 2102 * 2103 */ 2104 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ 2105 2106 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) 2107 2108 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { 2109 NvBool bZbcSurfacesExist; 2110 } NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS; 2111 2112 /*! 2113 * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE 2114 * 2115 * Export the resource and placement information about a gpu instance such that a 2116 * similar gpu instance can be recreated from scratch in the same position on the 2117 * same or similar GPU. Note that different GPUs may have different physical 2118 * resources due to floorsweeping, and an imported gpu instance is not guaranteed 2119 * to get the exact same resources as the exported gpu instance, but the imported 2120 * gpu instance should behave identically with respect to fragmentation and 2121 * placement / span positioning. 2122 */ 2123 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2124 2125 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2126 2127 /*! 2128 * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE 2129 * 2130 * Create a gpu instance resembling the exported instance info. Note that 2131 * different GPUs may have different physical resources due to floorsweeping, 2132 * and an imported gpu instance is not guaranteed to get the exact same resources 2133 * as the exported gpu instance, but the imported gpu instance should behave 2134 * identically with respect to fragmentation and placement / span positioning. 2135 */ 2136 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2137 2138 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2139 2140 #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 2141 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { 2142 NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8); 2143 NvU32 partitionFlags; 2144 NvU32 gpcMask; 2145 NvU32 virtualGpcCount; 2146 NvU32 veidOffset; 2147 NvU32 veidCount; 2148 } NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO; 2149 2150 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { 2151 NvU32 swizzId; 2152 NvU8 uuid[NV_GI_UUID_LEN]; 2153 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); 2154 } NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; 2155 2156 #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U) 2157 2158 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS; 2159 2160 #define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U) 2161 2162 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS; 2163 2164 #define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U) 2165 2166 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS; 2167 2168 #define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU) 2169 2170 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS; 2171 2172 /*! 2173 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT 2174 * 2175 * Invalidate and/or evict the L2 cache 2176 * 2177 * flags [IN] 2178 * flags that specify required actions 2179 * 2180 */ 2181 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */ 2182 2183 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU) 2184 2185 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { 2186 NvU32 flags; 2187 } NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS; 2188 2189 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL (0x00000001) 2190 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST (0x00000002) 2191 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST (0x00000004) 2192 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL (0x00000008) 2193 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN (0x00000010) 2194 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020) 2195 2196 /*! 2197 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES 2198 * 2199 * Flush all L2 Rams and Caches using the ELPG flush 2200 * 2201 */ 2202 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */ 2203 2204 /*! 2205 * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO 2206 * 2207 * This command obtains information from physical RM for use by CPU-RM 2208 * 2209 * Data fields -> 2210 * bPcieGen4Capable - tells whether PCIe is Gen4 capable 2211 */ 2212 #define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 2213 2214 #define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU) 2215 2216 typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS { 2217 NvBool bPcieGen4Capable; 2218 NvBool bIsC2CLinkUp; 2219 NvBool bIsDeviceMultiFunction; 2220 NvBool bGcxPmuCfgSpaceRestore; 2221 NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8); 2222 } NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS; 2223 2224 /*! 2225 * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG 2226 * 2227 * Program HSHUB Peer Conn Config space. 2228 * 2229 * programPeerMask[IN] 2230 * If nonzero, the peer mask for programming peers based on hshub connectivity. 2231 * 2232 * invalidatePeerMask[IN] 2233 * If nonzero, the peer mask for invalidating peers. 2234 * 2235 * programPciePeerMask[IN] 2236 * If nonzero, the peer mask for programming peers in pcie case. 2237 * 2238 * Possible status values returned are: 2239 * NV_OK 2240 * NV_WARN_NOTHING_TO_DO 2241 * If all peer masks are zero. 2242 */ 2243 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */ 2244 2245 #define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U) 2246 2247 typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS { 2248 NvU32 programPeerMask; 2249 NvU32 invalidatePeerMask; 2250 NvU32 programPciePeerMask; 2251 } NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS; 2252 2253 /*! 2254 * NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID 2255 * 2256 * Given a mask of link ids, find the first with a valid peerId. 2257 * 2258 * linkMask[IN] 2259 * Mask of linkIds to check. 2260 * 2261 * peerId[OUT] 2262 * The peerId for the lowest-index link with a valid peerId, if any. 2263 * If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK). 2264 * 2265 * Possible status values returned are: 2266 * NV_OK 2267 * 2268 */ 2269 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */ 2270 2271 #define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff 2272 2273 #define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U) 2274 2275 typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS { 2276 NvU32 linkMask; 2277 NvU32 peerId; 2278 } NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS; 2279 2280 /*! 2281 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS 2282 * 2283 * Get the Hshub Ids connected to the other end of links. 2284 * 2285 * linkMask[IN] 2286 * A mask of link ids to query. 2287 * 2288 * hshubIds[OUT] 2289 * For each set bit in the link mask, the peer Hshub Id. 2290 * 2291 * Possible status values returned are: 2292 * NV_OK 2293 * NV_WARN_NOTHING_TO_DO 2294 * If the mask is zero. 2295 */ 2296 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */ 2297 #define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32 2298 2299 #define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU) 2300 2301 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS { 2302 NvU32 linkMask; 2303 NvU8 hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE]; 2304 } NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS; 2305 2306 /*! 2307 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS 2308 * 2309 * Return the number of HSHUB units. 2310 * 2311 * numHshubs[OUT] 2312 * 2313 * Possible status values returned are: 2314 * NV_OK 2315 */ 2316 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */ 2317 2318 #define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU) 2319 2320 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS { 2321 NvU32 numHshubs; 2322 } NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS; 2323 2324 /*! 2325 * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID 2326 * 2327 * Return the next hshubId after the given hshubId. 2328 * 2329 * hshubId[IN/OUT] 2330 * 2331 * Possible status values returned are: 2332 * NV_OK 2333 */ 2334 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */ 2335 2336 #define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU) 2337 2338 typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { 2339 NvU8 hshubId; 2340 } NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; 2341 2342 /*! 2343 * NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG 2344 * 2345 * Program HSHUB for EGM peer id. 2346 * 2347 * egmPeerId[IN] 2348 * EGM peer id to program in the HSHUB registers. 2349 * 2350 * Possible status values returned are: 2351 * NV_OK 2352 */ 2353 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */ 2354 2355 #define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU) 2356 2357 typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS { 2358 NvU32 egmPeerId; 2359 } NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS; 2360 2361 2362 2363 /* 2364 * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR 2365 * 2366 * Enable compute peer addressing mode 2367 * This command accepts no parameters. 2368 */ 2369 2370 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */ 2371 2372 /* 2373 * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR 2374 * 2375 * Get/Set NVSwitch fabric address for FLA 2376 * 2377 * [In] bGet 2378 * Whether to get or set the NVSwitch fabric address 2379 * [In/Out] addr 2380 * Address that is to be set or retrieved. 2381 */ 2382 #define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU) 2383 2384 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS { 2385 NvBool bGet; 2386 NV_DECLARE_ALIGNED(NvU64 addr, 8); 2387 } NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS; 2388 2389 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */ 2390 2391 /*! 2392 * NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS 2393 * 2394 * This command obtains information from physical RM for use by CPU-RM 2395 * 2396 * Data fields -> 2397 * bCyaMaskL1 2398 * bEnableAspmDtL1 2399 */ 2400 #define NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID" */ 2401 2402 #define NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID (0xb0U) 2403 2404 typedef struct NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS { 2405 NvBool bCyaMaskL1; 2406 NvBool bEnableAspmDtL1; 2407 } NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS; 2408 2409 /*! 2410 * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT 2411 * 2412 * Sets number of VM slots that are active in VGPU's scheduler 2413 * 2414 * maxActiveVGpuVMCount [IN] 2415 * Number of VM slots that are active in vGPU's scheduler. 2416 * 2417 * Possible status values returned are: 2418 * NV_OK 2419 * NV_ERR_OUT_OF_RANGE - Passed value is out of range 2420 * NV_ERR_NO_MEMORY - Out of memory 2421 */ 2422 #define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */ 2423 2424 /*! 2425 * Maximum value of VM slots that are active in vGPU's scheduler. 2426 */ 2427 #define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32 2428 2429 #define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U) 2430 2431 typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS { 2432 NvU8 maxActiveVGpuVMCount; 2433 } NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS; 2434 2435 /*! 2436 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS 2437 * 2438 * Disable all NVLINK FB peers 2439 * 2440 */ 2441 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */ 2442 2443 /*! 2444 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE 2445 * 2446 * Program GPU in raw / legacy compression mode 2447 * 2448 */ 2449 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */ 2450 2451 #define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU) 2452 2453 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { 2454 NvBool bRawMode; 2455 } NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; 2456 2457 /* 2458 * NV2080_CTRL_CMD_INTERNAL_CCU_MAP 2459 * 2460 * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it 2461 * in physical-RM. 2462 * 2463 * Possible status values returned are: 2464 * NV_OK 2465 * NV_ERR_INVALID_ARGUMENT 2466 * NV_ERR_INVALID_ADDRESS 2467 */ 2468 #define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */ 2469 2470 #define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1 2471 #define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U) 2472 2473 typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { 2474 NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8); 2475 } NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS; 2476 /* 2477 * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP 2478 * 2479 * This command unmaps the shared buffer memory mapping in physical-RM 2480 * 2481 * Possible status values returned are: 2482 * NV_OK 2483 */ 2484 #define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */ 2485 2486 #define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U) 2487 2488 typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS { 2489 NvBool bDevShrBuf; 2490 NvBool bMigShrBuf; 2491 } NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS; 2492 2493 /*! 2494 * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO 2495 * 2496 * [in] gpuId 2497 * GPU ID. 2498 * [in] gpuInstance 2499 * GPU instance. 2500 * [in] p2pCaps 2501 * Peer to peer capabilities discovered between the GPUs. 2502 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 2503 * [in] p2pOptimalReadCEs 2504 * Mask of CEs to use for p2p reads over Nvlink. 2505 * [in] p2pOptimalWriteCEs 2506 * Mask of CEs to use for p2p writes over Nvlink. 2507 * [in] p2pCapsStatus 2508 * Status of all supported p2p capabilities. 2509 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 2510 * [in] busPeerId 2511 * Bus peer ID. For an invalid or a non-existent peer this field 2512 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 2513 */ 2514 typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO { 2515 NvU32 gpuId; 2516 NvU32 gpuInstance; 2517 NvU32 p2pCaps; 2518 NvU32 p2pOptimalReadCEs; 2519 NvU32 p2pOptimalWriteCEs; 2520 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 2521 NvU32 busPeerId; 2522 } NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO; 2523 2524 /*! 2525 * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS 2526 * 2527 * An internal call to propagate the peer to peer capabilities of peer GPUs 2528 * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin. 2529 * This control is used to both add and and update the peer to peer capabilities. 2530 * The existing GPU entries will be updated and those which don't exist will be added. 2531 * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries. 2532 * 2533 * [in] peerGpuCount 2534 * The number of the peerGpuInfos entries. 2535 * [in] peerGpuInfos 2536 * The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing 2537 * the peer to peer capabilities of the specified GPUs. 2538 * 2539 * Possible status values returned are: 2540 * NV_OK 2541 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount 2542 * NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value 2543 */ 2544 #define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2545 2546 #define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U) 2547 2548 typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS { 2549 NvU32 peerGpuCount; 2550 NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 2551 } NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS; 2552 2553 /*! 2554 * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS 2555 * 2556 * An internal call to remove the cached peer to peer capabilities of peer GPUs 2557 * from the Physical RM. 2558 * 2559 * [in] peerGpuIdCount 2560 * The number of the peerGpuIds entries. 2561 * [in] peerGpuIds 2562 * The array of GPU IDs, specifying the GPU for which the entries need to be removed. 2563 * 2564 * Possible status values returned are: 2565 * NV_OK 2566 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount 2567 * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry 2568 */ 2569 #define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2570 2571 #define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U) 2572 2573 typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { 2574 NvU32 peerGpuIdCount; 2575 NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 2576 } NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS; 2577 2578 2579 2580 /*! 2581 * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS 2582 * 2583 * This command returns the GPU's PCIE P2P caps 2584 * 2585 * [in] bCommonPciSwitchFound 2586 * All GPUs are under the same PCI switch 2587 * [out] p2pReadCapsStatus 2588 * [out] p2pWriteCapsStatus 2589 * These members returns status of all supported p2p capabilities. Valid 2590 * status values include: 2591 * NV0000_P2P_CAPS_STATUS_OK 2592 * P2P capability is supported. 2593 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 2594 * Chipset doesn't support p2p capability. 2595 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 2596 * GPU doesn't support p2p capability. 2597 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 2598 * IOH topology isn't supported. For e.g. root ports are on different 2599 * IOH. 2600 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 2601 * P2P Capability is disabled by a regkey. 2602 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 2603 * P2P Capability is not supported. 2604 * 2605 * Possible status values returned are: 2606 * NV_OK 2607 * NV_ERR_INVALID_ARGUMENT 2608 * NV_ERR_INVALID_PARAM_STRUCT 2609 */ 2610 #define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2611 2612 #define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U) 2613 2614 typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { 2615 NvBool bCommonPciSwitchFound; 2616 NvU8 p2pReadCapsStatus; 2617 NvU8 p2pWriteCapsStatus; 2618 } NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS; 2619 2620 /*! 2621 * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO 2622 * 2623 * Enable/disable PCIe Relaxed Ordering. 2624 * 2625 */ 2626 #define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ 2627 2628 #define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U) 2629 2630 typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { 2631 // Enable/disable PCIe relaxed ordering 2632 NvBool enableRo; 2633 } NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; 2634 2635 /* 2636 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE 2637 * 2638 * An internal call to invoke the sequence VGA register reads & writes to 2639 * perform save and restore of VGA 2640 * 2641 * [in] bSave 2642 * To indicate whether save or restore needs to be performed. 2643 * [in] bUseVbios 2644 * Primary VGA indication from OS. 2645 * 2646 * Possible status values returned are: 2647 * NV_OK 2648 * NV_ERR_INVALID_OPERATION 2649 * NV_ERR_NOT_SUPPORTED 2650 */ 2651 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ 2652 2653 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) 2654 2655 typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS { 2656 NvBool bSave; 2657 NvBool bUseVbios; 2658 } NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS; 2659 2660 /*! 2661 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE 2662 * 2663 * To perform save or restore operation from/to saved fonts. 2664 * 2665 * [in] bSave 2666 * To indicate whether save or restore needs to be performed. 2667 * [in] bUseVbios 2668 * Primary VGA indication from OS. 2669 * [in] bVbiosCallSuccessful 2670 * Indicates if vbios invocation was successful or not. 2671 * 2672 * Possible status values returned are: 2673 * NV_OK 2674 * NV_ERR_NOT_SUPPORTED 2675 */ 2676 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ 2677 2678 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x77U) 2679 2680 typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS { 2681 NvBool bSave; 2682 NvBool bUseVbios; 2683 NvBool bVbiosCallSuccessful; 2684 } NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS; 2685 2686 /*! 2687 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES 2688 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES 2689 */ 2690 2691 /*! 2692 * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE 2693 * 2694 * This structure specifies resources in an execution partition 2695 * 2696 * computeSize[OUT] 2697 * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile 2698 * 2699 * gfxGpcCount[OUT] 2700 * - Total Number of GFX Supporting GPCs in this partition 2701 * 2702 * gpcCount[OUT] 2703 * - Total Number of GPCs in this partition (including GFX Supported GPCs) 2704 * 2705 * veidCount[OUT] 2706 * - Number of VEIDs allocated to this profile 2707 * 2708 * smCount[OUT] 2709 * - Number of SMs usable in this profile 2710 */ 2711 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { 2712 NvU8 computeSize; 2713 NvU32 gfxGpcCount; 2714 NvU32 gpcCount; 2715 NvU32 veidCount; 2716 NvU32 smCount; 2717 NvU32 physicalSlots; 2718 } NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; 2719 2720 /*! 2721 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS 2722 * 2723 * This structure specifies resources in an execution partition 2724 * 2725 * profileCount[OUT] 2726 * - Total Number of profiles filled 2727 * 2728 * profiles[OUT] 2729 * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles 2730 */ 2731 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) 2732 2733 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { 2734 NvU32 profileCount; 2735 NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; 2736 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; 2737 2738 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ 2739 2740 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU) 2741 2742 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS; 2743 2744 2745 2746 /* 2747 * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE 2748 * 2749 * This command sets the ccu stream to enable/disable state. 2750 * 2751 * Possible status values returned are: 2752 * NV_OK 2753 * NV_ERR_INVALID_ARGUMENT 2754 * NV_ERR_NOT_SUPPORTED 2755 */ 2756 2757 #define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */ 2758 2759 #define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU) 2760 2761 typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS { 2762 NvBool bStreamState; 2763 } NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS; 2764 2765 /*! 2766 * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT 2767 * 2768 * Attach GPU to the external device. 2769 * 2770 * [in] bExtDevFound 2771 * To enable GPIO interrupts. 2772 * 2773 * Possible status values returned are: 2774 * NV_OK 2775 * NV_ERR_GENERIC 2776 * NV_ERR_NOT_SUPPORTED 2777 */ 2778 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */ 2779 2780 #define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU) 2781 2782 typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS { 2783 NvBool bExtDevFound; 2784 } NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS; 2785 2786 /*! 2787 * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS 2788 * 2789 * Optimize the Gsync timing parameters 2790 * 2791 * [in] timingParameters 2792 * Timing parameters passed by client. 2793 * 2794 * Possible status values returned are: 2795 * NV_OK 2796 * NV_ERR_GENERIC 2797 * NV_ERR_NOT_SUPPORTED 2798 */ 2799 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */ 2800 2801 #define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU) 2802 2803 typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS { 2804 NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters; 2805 } NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS; 2806 2807 /*! 2808 * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS 2809 * 2810 * Get displayIDs supported by the display. 2811 * 2812 * [out] displayIds 2813 * Associated display ID with head. 2814 * 2815 * Possible status values returned are: 2816 * NV_OK 2817 * NV_ERR_GENERIC 2818 * NV_ERR_NOT_SUPPORTED 2819 */ 2820 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */ 2821 2822 #define NV2080_MAX_NUM_HEADS 4 2823 2824 #define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U) 2825 2826 typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS { 2827 NvU32 displayIds[NV2080_MAX_NUM_HEADS]; 2828 } NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS; 2829 2830 /*! 2831 * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC 2832 * 2833 * Set the Stereo sync for Gsync 2834 * 2835 * [in] slave 2836 * Slave GPU head status. 2837 * [in] localSlave 2838 * Slave GPU head status but are not coupled. 2839 * [in] master 2840 * Master GPU head status. 2841 * [in] regstatus 2842 * Register status of status1 register. 2843 * 2844 * Possible status values returned are: 2845 * NV_OK 2846 * NV_ERR_GENERIC 2847 * NV_ERR_NOT_SUPPORTED 2848 */ 2849 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */ 2850 2851 #define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U) 2852 2853 typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS { 2854 NvU32 slave[NV2080_MAX_NUM_HEADS]; 2855 NvU32 localSlave[NV2080_MAX_NUM_HEADS]; 2856 NvU32 master[NV2080_MAX_NUM_HEADS]; 2857 NvU32 regStatus; 2858 } NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS; 2859 2860 /*! 2861 * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES 2862 * 2863 * Get vertical active lines for given head. 2864 * 2865 * [in] head 2866 * For the headIdx which we need active. 2867 * [out] vActiveLines 2868 * Vertical active lines. 2869 * 2870 * Possible status values returned are: 2871 * NV_OK 2872 * NV_ERR_GENERIC 2873 * NV_ERR_NOT_SUPPORTED 2874 */ 2875 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */ 2876 2877 #define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U) 2878 2879 typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS { 2880 NvU32 headIdx; 2881 NvU32 vActiveLines; 2882 } NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS; 2883 2884 /*! 2885 * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID 2886 * 2887 * Verifies if this displayId is valid. 2888 * 2889 * [in] displays 2890 * Displays given by the client 2891 * 2892 * [out] displayId 2893 * DisplayId for the given display 2894 * 2895 * Possible status values returned are: 2896 * NV_OK 2897 * NV_ERR_GENERIC 2898 * NV_ERR_NOT_SUPPORTED 2899 */ 2900 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */ 2901 2902 #define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U) 2903 2904 typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { 2905 NvU32 displays; 2906 NvU32 displayId; 2907 } NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS; 2908 2909 /*! 2910 * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC 2911 * 2912 * Disable the raster sync gpio on the other P2060 GPU 2913 * that's connected to master over Video bridge. 2914 * 2915 * [in] bEnableMaster 2916 * If it is master gpu. 2917 * 2918 * [out] bRasterSyncGpioSaved 2919 * If raster sync GPIO direction is saved or not. 2920 * 2921 * [in/out] bRasterSyncGpioDirection 2922 * During save it gets the direction. 2923 * In restores it sets the direction. 2924 * 2925 * Possible status values returned are: 2926 * NV_OK 2927 * NV_ERR_NOT_SUPPORTED 2928 */ 2929 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */ 2930 2931 #define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU) 2932 2933 typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { 2934 NvBool bEnableMaster; 2935 NvBool bRasterSyncGpioSaved; 2936 NvU32 bRasterSyncGpioDirection; 2937 } NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS; 2938 2939 /*! 2940 * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT 2941 * 2942 * Initialize FBSR on GSP to prepare for suspend-resume 2943 * 2944 * [in] fbsrType 2945 * Fbsr object type 2946 * [in] numRegions 2947 * Number of regions that GSP should allocate records for 2948 * [in] hClient 2949 * Handle to client of SYSMEM memlist object 2950 * [in] hSysMem 2951 * Handle to SYSMEM memlist object 2952 * [in] gspFbAllocsSysOffset 2953 * Offset in SYSMEM for GSP's FB Allocations 2954 * [in] bEnteringGcoffState 2955 * Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING 2956 * 2957 * Possible status values returned are: 2958 * NV_OK 2959 * NV_ERR_GENERIC 2960 * NV_ERR_NOT_SUPPORTED 2961 */ 2962 2963 #define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ 2964 2965 #define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U) 2966 2967 typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { 2968 NvU32 fbsrType; 2969 NvU32 numRegions; 2970 NvHandle hClient; 2971 NvHandle hSysMem; 2972 NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8); 2973 NvBool bEnteringGcoffState; 2974 } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; 2975 2976 /*! 2977 * NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO 2978 * 2979 * Send info of FB region that will be saved/restored by GSP on suspend-resume 2980 * 2981 * [in] fbsrType 2982 * Fbsr object type 2983 * [in] hClient 2984 * Handle to client of FBMEM memlist object 2985 * [in] hVidMem 2986 * Handle to FBMEM memlist object 2987 * [in] vidOffset 2988 * Offset in FBMEM region to save/restore 2989 * [in] sysOffset 2990 * Offset in SYSMEM region to save to/restore from 2991 * [in] size 2992 * Size of region being saved/restored 2993 */ 2994 #define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */ 2995 2996 #define NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID (0xC3U) 2997 2998 typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS { 2999 NvU32 fbsrType; 3000 NvHandle hClient; 3001 NvHandle hVidMem; 3002 NV_DECLARE_ALIGNED(NvU64 vidOffset, 8); 3003 NV_DECLARE_ALIGNED(NvU64 sysOffset, 8); 3004 NV_DECLARE_ALIGNED(NvU64 size, 8); 3005 } NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS; 3006 3007 /* 3008 * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB 3009 * 3010 * This command is used to get the amount of host reserved FB 3011 * 3012 * hostReservedFb [OUT] 3013 * Amount of FB reserved for the host 3014 * vgpuTypeId [IN] 3015 * The Type ID for VGPU profile 3016 * 3017 * Possible status values returned are: 3018 * NV_OK 3019 * NV_ERR_INVALID_ARGUMENT 3020 */ 3021 #define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */ 3022 3023 #define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U) 3024 3025 typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS { 3026 NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); 3027 NvU32 vgpuTypeId; 3028 } NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS; 3029 3030 /*! 3031 * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD 3032 * 3033 * This command initiates brightc module state load. 3034 * 3035 * Possible status values returned are: 3036 * NV_OK 3037 * NV_ERR_INVALID_ARGUMENT 3038 * NV_ERR_NOT_SUPPORTED 3039 */ 3040 3041 #define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ 3042 3043 #define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ 3044 3045 #define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U) 3046 3047 typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { 3048 NvU32 status; 3049 NvU16 backLightDataSize; 3050 NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; 3051 } NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; 3052 3053 /* 3054 * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL 3055 * 3056 * Returns number of active links allowed per IOCTRL 3057 * 3058 * [Out] numActiveLinksPerIoctrl 3059 */ 3060 #define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U) 3061 3062 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { 3063 NvU32 numActiveLinksPerIoctrl; 3064 } NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; 3065 #define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ 3066 /* 3067 * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL 3068 * 3069 * Returns number of links per IOCTRL 3070 * 3071 * [Out] numLinksPerIoctrl 3072 */ 3073 #define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U) 3074 3075 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { 3076 NvU32 numLinksPerIoctrl; 3077 } NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; 3078 #define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ 3079 3080 /*! 3081 * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE 3082 * 3083 * Update the system control capability 3084 * 3085 * bIsSysCtrlSupported [IN] 3086 If the system control is supported 3087 * bIsPlatformLegacy [OUT] 3088 If the platform is legacy 3089 * 3090 * Possible status values returned are: 3091 * NV_OK 3092 * NV_ERR_NOT_SUPPORTED 3093 */ 3094 3095 #define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */ 3096 3097 #define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU) 3098 3099 typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS { 3100 NvBool bIsSysCtrlSupported; 3101 NvBool bIsPlatformLegacy; 3102 } NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS; 3103 3104 /*! 3105 * Macros for PFM_REQ_HNDLR_STATE_SYNC data types. 3106 */ 3107 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR 0x00U 3108 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM 0x01U 3109 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U 3110 3111 /*! 3112 * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI. 3113 */ 3114 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { 3115 /*! 3116 * PFM sensor ID 3117 */ 3118 NvU32 sensorId; 3119 3120 /*! 3121 * PFM sensor limit value if required 3122 */ 3123 NvU32 limit; 3124 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; 3125 3126 /*! 3127 * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types. 3128 */ 3129 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA { 3130 /*! 3131 * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_<xyz> 3132 */ 3133 NvU8 type; 3134 3135 /*! 3136 * Type-specific information. 3137 */ 3138 union { 3139 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi; 3140 } data; 3141 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA; 3142 3143 /*! 3144 * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation. 3145 */ 3146 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD 0x00U 3147 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT 0x01U 3148 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U 3149 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET 0x03U 3150 3151 /*! 3152 * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params. 3153 */ 3154 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { 3155 /*! 3156 * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_<xyz> 3157 */ 3158 NvU8 flags; 3159 3160 /*! 3161 * Type-specific information. 3162 */ 3163 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData; 3164 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS; 3165 3166 /*! 3167 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC 3168 * 3169 * State sync with platform req handler and SMBPBI 3170 * 3171 * flags [IN] 3172 * Flags that needs sync operation between physical and kernel 3173 * 3174 * syncData [IN] 3175 * Sync payload data 3176 * 3177 */ 3178 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */ 3179 3180 #define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU) 3181 3182 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS; 3183 3184 /*! 3185 * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC 3186 * 3187 * State sync with platform req handler and SMBPBI 3188 * 3189 * flags [IN] 3190 * Flags that needs sync operation between physical and kernel 3191 * 3192 * syncData [IN] 3193 * Sync payload data 3194 * 3195 */ 3196 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */ 3197 3198 #define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU) 3199 3200 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS; 3201 3202 /*! 3203 * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE 3204 * 3205 * Query Coherent FB Aperture Size. 3206 * 3207 */ 3208 #define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ 3209 3210 #define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) 3211 3212 typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS { 3213 // Get Coherent Fb Aperture Size 3214 NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8); 3215 } NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS; 3216 3217 3218 /*! 3219 * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag 3220 */ 3221 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U 3222 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS 0x01U 3223 3224 /*! 3225 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE 3226 * 3227 * Queries PM1 Forced off / PM1 Available status 3228 * 3229 * flag [IN] 3230 * Fetch PM1 Forced off / PM1 Available status based on value. 3231 * bStatus [OUT] 3232 * PM1 Forced off / PM1 Available is true or false. 3233 * 3234 * Possible status values returned are: 3235 * NV_OK 3236 * NV_ERR_NOT_SUPPORTED 3237 * NV_ERR_INVALID_ARGUMETS 3238 */ 3239 3240 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */ 3241 3242 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU) 3243 3244 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS { 3245 /*! 3246 * Fetch PM1 Forced off / PM1 Available status based on value. 3247 */ 3248 NvU8 flag; 3249 3250 /*! 3251 * PM1 Forced off / PM1 Available status 3252 */ 3253 NvBool bStatus; 3254 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS; 3255 3256 /*! 3257 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE 3258 * 3259 * Set PM1 state to enabled / disabled (boost clocks). 3260 * 3261 * bEnable [IN] 3262 * NV_TRUE means enable PM1, NV_FALSE means disable. 3263 * 3264 * Possible status values returned are: 3265 * NV_OK 3266 * NV_ERR_NOT_SUPPORTED 3267 */ 3268 3269 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */ 3270 3271 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU) 3272 3273 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS { 3274 3275 /*! 3276 * NV_TRUE means enable PM1, NV_FALSE means disable. 3277 */ 3278 NvBool bEnable; 3279 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS; 3280 3281 /*! 3282 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT 3283 * 3284 * Updates EDPpeak Limit of GPU 3285 * 3286 * bEnable [IN] 3287 * Enable or Reset the settings 3288 * clientLimit [IN] 3289 * Client requested limit 3290 * 3291 * Possible status values returned are: 3292 * NV_OK 3293 * NV_ERR_GENERIC 3294 * NV_ERR_NOT_SUPPORTED 3295 * NV_ERR_NOT_READY 3296 */ 3297 3298 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */ 3299 3300 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U) 3301 3302 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { 3303 NvBool bEnable; 3304 NvU32 clientLimit; 3305 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; 3306 3307 /*! 3308 * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT 3309 * 3310 * Updates Target Temperature of GPU 3311 * 3312 * targetTemp [IN] 3313 * Target Temperature Set from SBIOS 3314 * 3315 * Possible status values returned are: 3316 * NV_OK 3317 * NV_ERR_NOT_SUPPORTED 3318 */ 3319 3320 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */ 3321 3322 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U) 3323 3324 typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS { 3325 NvS32 targetTemp; 3326 } NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS; 3327 3328 /*! 3329 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE 3330 * 3331 * Enable / disable CTGP MODE 3332 * 3333 * bEnable [IN] 3334 * Enable or Reset the settings 3335 * 3336 * Possible status values returned are: 3337 * NV_OK 3338 * NV_ERR_NOT_SUPPORTED 3339 */ 3340 3341 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */ 3342 3343 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U) 3344 3345 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS { 3346 NvBool bEnable; 3347 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS; 3348 3349 /*! 3350 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 3351 * 3352 * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control 3353 * 3354 * ctgpOffsetmW [IN] 3355 * TGP MODE Offset in mW 3356 * 3357 * Possible status values returned are: 3358 * NV_OK 3359 * NV_ERR_NOT_SUPPORTED 3360 */ 3361 3362 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */ 3363 3364 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U) 3365 3366 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS { 3367 NvU32 ctgpOffsetmW; 3368 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS; 3369 3370 /*! 3371 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO 3372 * 3373 * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx 3374 * 3375 * bVpsPs20Supported [OUT] 3376 * Reflects Vpstates PS20 support 3377 * vPstateIdxHighest [OUT} 3378 * Reflects Highest VPstate Idx 3379 * 3380 * Possible status values returned are: 3381 * NV_OK 3382 * NV_ERR_NOT_SUPPORTED 3383 */ 3384 3385 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */ 3386 3387 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U) 3388 3389 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS { 3390 /*! 3391 * Reflects Vpstates PS20 support 3392 */ 3393 NvBool bVpsPs20Supported; 3394 3395 /*! 3396 * Get highest VPState Idx from VBIOS 3397 */ 3398 NvU32 vPstateIdxHighest; 3399 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS; 3400 3401 /*! 3402 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING 3403 * 3404 * Get vPstate mapping for requested pStateIdx 3405 * 3406 * pStateIdx [IN] 3407 * Requested PState Idx 3408 * vPstateIdx [OUT} 3409 * Mapped VPstate Idx 3410 * 3411 * Possible status values returned are: 3412 * NV_OK 3413 * NV_ERR_NOT_SUPPORTED 3414 */ 3415 3416 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */ 3417 3418 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U) 3419 3420 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS { 3421 /*! 3422 * Requested PState Idx 3423 */ 3424 NvU32 pStateIdx; 3425 3426 /*! 3427 * Mapped VPstate Idx 3428 */ 3429 NvU32 vPstateIdxMapping; 3430 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS; 3431 3432 /*! 3433 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE 3434 * 3435 * Set requested VPstate 3436 * 3437 * vPstateIdx [IN] 3438 * VPstate Idx to be set 3439 * 3440 * Possible status values returned are: 3441 * NV_OK 3442 * NV_ERR_NOT_SUPPORTED 3443 */ 3444 3445 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */ 3446 3447 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U) 3448 3449 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { 3450 3451 /*! 3452 * NV_TRUE means enable PM1, NV_FALSE means disable. 3453 */ 3454 NvU32 vPstateIdx; 3455 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; 3456 3457 /* 3458 * NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE 3459 * 3460 * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3 3461 * 3462 * Possible status return values are: 3463 * NV_OK Success 3464 */ 3465 #define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ 3466 3467 #define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) 3468 3469 typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS { 3470 NvBool bIsGC6Satisfied; 3471 NvBool bIsGCOFFSatisfied; 3472 } NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS; 3473 3474 /* 3475 * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. 3476 */ 3477 #define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ 3478 3479 /*! 3480 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS 3481 * 3482 * This command is an internal command sent from Kernel RM to Physical RM 3483 * to get number of secure channels supported on SEC2 and CE 3484 * 3485 * maxSec2SecureChannels [OUT] 3486 * maxCeSecureChannels [OUT] 3487 */ 3488 #define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */ 3489 3490 #define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U) 3491 3492 typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS { 3493 NvU32 maxSec2SecureChannels; 3494 NvU32 maxCeSecureChannels; 3495 } NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS; 3496 3497 /* 3498 * NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS 3499 * 3500 * This command is an internal command sent from Kernel RM to Physical RM 3501 * to disable the GPU system memory access after quiescing the GPU or 3502 * re-enable sysmem access. 3503 * 3504 * bDisable [IN] 3505 * If NV_TRUE the GPU is quiesced and system memory access is disabled . 3506 * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. 3507 * 3508 * Possible status values returned are: 3509 * NV_OK 3510 * NV_ERR_INVALID_PARAM_STRUCT 3511 * NV_ERR_INVALID_ARGUMENT 3512 * NV_ERR_NOT_SUPPORTED 3513 */ 3514 #define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */ 3515 3516 #define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU) 3517 3518 typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS { 3519 NvBool bDisable; 3520 } NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS; 3521 3522 #define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */ 3523 3524 #define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU) 3525 3526 typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS { 3527 NvU32 pinSetIn; // in 3528 NvU32 pinSetOut; // in 3529 NvBool bMasterScanLock; // out 3530 NvU32 masterScanLockPin; // out 3531 NvBool bSlaveScanLock; // out 3532 NvU32 slaveScanLockPin; // out 3533 } NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS; 3534 3535 #define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */ 3536 3537 #define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */ 3538 3539 #define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU) 3540 3541 typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS { 3542 NvU32 pinSet; // in 3543 NvU32 gpioFunction; // out 3544 NvU32 gpioPin; // out 3545 NvBool gpioDirection; // out 3546 } NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS; 3547 3548 /* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA 3549 * 3550 * This command sets up ACPI DDC Edid data. 3551 * 3552 * Possible status values returned are: 3553 * NV_OK 3554 * NV_ERR_INVALID_ARGUMENT 3555 * NV_ERR_NOT_SUPPORTED 3556 */ 3557 #define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */ 3558 3559 /* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */ 3560 #define MAX_EDID_SIZE_FROM_SBIOS 512U 3561 3562 typedef struct NV2080_CTRL_INTERNAL_EDID_DATA { 3563 NvU32 status; 3564 NvU32 acpiId; 3565 NvU32 bufferSize; 3566 NvU8 edidBuffer[MAX_EDID_SIZE_FROM_SBIOS]; 3567 } NV2080_CTRL_INTERNAL_EDID_DATA; 3568 3569 #define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU) 3570 3571 typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS { 3572 NvU32 tableLen; 3573 NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; 3574 } NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS; 3575 3576 /*! 3577 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED 3578 * 3579 * This command intializes display ACPI child devices. 3580 * This command accepts no parameters. 3581 * 3582 */ 3583 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */ 3584 3585 /* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */ 3586 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */ 3587 3588 /* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */ 3589 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */ 3590 3591 /*! 3592 * NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS 3593 * 3594 * This structure provides the params for getting GPU Fabric Probe Internal 3595 * Info from GSP to CPU RM 3596 * 3597 * numProbes[OUT] 3598 * - Number of probe requests sent 3599 */ 3600 #define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U) 3601 3602 typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS { 3603 NV_DECLARE_ALIGNED(NvU64 numProbes, 8); 3604 } NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS; 3605 3606 /*! 3607 * NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO 3608 * 3609 * This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS 3610 * from GSP to CPU RM. 3611 * This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS 3612 * 3613 */ 3614 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3615 3616 /*! 3617 * NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS 3618 * 3619 * This structure provides the params for starting GPU Fabric Probe 3620 * 3621 * bwMode[IN] 3622 * - Nvlink Bandwidth mode 3623 */ 3624 #define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U) 3625 3626 typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS { 3627 NvU8 bwMode; 3628 } NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS; 3629 3630 /*! 3631 * NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE 3632 * 3633 * This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP. 3634 * This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS 3635 * 3636 */ 3637 #define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3638 3639 /*! 3640 * NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE 3641 * 3642 * This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP. 3643 * This command accepts no parameters 3644 * 3645 */ 3646 #define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */ 3647 3648 /*! 3649 * NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE 3650 * 3651 * This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP. 3652 * This command accepts no parameters 3653 * 3654 */ 3655 #define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */ 3656 3657 3658 /*! 3659 * NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS 3660 * 3661 * This structure provides the params for resuming GPU Fabric Probe 3662 * 3663 * bwMode[IN] 3664 * - Nvlink Bandwidth mode 3665 */ 3666 #define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U) 3667 3668 typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS { 3669 NvU8 bwMode; 3670 } NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS; 3671 3672 /*! 3673 * NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE 3674 * 3675 * This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP. 3676 * This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS 3677 * 3678 */ 3679 #define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3680 3681 /*! 3682 * NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE 3683 * 3684 * This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP. 3685 * This command accepts no parameters 3686 * 3687 */ 3688 #define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */ 3689 3690 /*! 3691 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO 3692 * 3693 * This command is an internal command sent from Kernel RM to Physical RM 3694 * to get static conf compute info 3695 * 3696 * bIsBar1Trusted: [OUT] 3697 * Is BAR1 trusted to access CPR 3698 * bIsPcieTrusted: [OUT] 3699 * Is PCIE trusted to access CPR 3700 */ 3701 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 3702 3703 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U) 3704 3705 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS { 3706 NvBool bIsBar1Trusted; 3707 NvBool bIsPcieTrusted; 3708 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS; 3709 3710 /*! 3711 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS 3712 * 3713 * This command is an internal command sent from Kernel RM to Physical RM 3714 * to derive SWL keys and IV masks for a given engine 3715 * 3716 * engineId: [IN] 3717 * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived 3718 * ivMaskSet: [OUT] 3719 * Set of IV masks for given engine 3720 */ 3721 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS (0x20800ae1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID" */ 3722 3723 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U 3724 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U 3725 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U 3726 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U 3727 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U 3728 3729 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK { 3730 NvU32 ivMask[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE]; 3731 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK; 3732 3733 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID (0xE1U) 3734 3735 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS { 3736 NvU32 engineId; 3737 NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT]; 3738 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS; 3739 3740 /*! 3741 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS 3742 * 3743 * This command is an internal command sent from Kernel RM to Physical RM 3744 * to derive LCE keys and IV masks for a given engine 3745 * 3746 * engineId: [IN] 3747 * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived 3748 * ivMaskSet: [OUT] 3749 * Set of IV masks for given engine 3750 */ 3751 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS (0x20800ae2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID" */ 3752 3753 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID (0xE2U) 3754 3755 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS { 3756 NvU32 engineId; 3757 NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT]; 3758 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS; 3759 3760 /*! 3761 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE 3762 * 3763 * This control call can be used to set gpu state on GSP to accept client requests 3764 * or to block client requests. 3765 * This is a internal command sent from Kernel RM to Physical RM. 3766 * 3767 * bAcceptClientRequest:[IN] 3768 * NV_TRUE : set gpu state to accept client work requests 3769 * NV_FALSE: set gpu state to block client work requests 3770 * 3771 */ 3772 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE (0x20800ae7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID" */ 3773 3774 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID (0xE7U) 3775 3776 typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS { 3777 NvBool bAcceptClientRequest; 3778 } NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS; 3779 3780 3781 /* 3782 * NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP 3783 * 3784 * This command is used by CPU-RM to perform memory operations using GSP 3785 * 3786 * 3787 * Possible status values returned are: 3788 * NV_OK 3789 * NVOS_STATUS_TIMEOUT_RETRY 3790 * NV_ERR_NOT_SUPPORTED 3791 */ 3792 3793 #define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */ 3794 3795 typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP { 3796 NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0, 3797 NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1, 3798 } NV2080_CTRL_MEMMGR_MEMORY_OP; 3799 3800 typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO { 3801 /*! 3802 * Base physical address of the surface 3803 */ 3804 NV_DECLARE_ALIGNED(NvU64 baseAddr, 8); 3805 3806 /*! 3807 * Size of the surface in bytes 3808 */ 3809 NV_DECLARE_ALIGNED(NvU64 size, 8); 3810 3811 /*! 3812 * Offset in bytes into the surface where read/write must happen 3813 */ 3814 NV_DECLARE_ALIGNED(NvU64 offset, 8); 3815 3816 /*! 3817 * Aperture where the surface is allocated 3818 */ 3819 NvU32 aperture; 3820 3821 /*! 3822 * CPU caching attribute of the surface 3823 */ 3824 NvU32 cpuCacheAttrib; 3825 } NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO; 3826 3827 #define CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */ 3828 3829 #define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU) 3830 3831 typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS { 3832 3833 /*! 3834 * Source surface info 3835 */ 3836 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8); 3837 3838 /*! 3839 * Authentication tag if data is encrypted 3840 */ 3841 NvU8 authTag[CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES]; 3842 3843 /*! 3844 * Destination surface info 3845 */ 3846 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8); 3847 3848 /*! 3849 * Size of the data to be transferred 3850 */ 3851 NV_DECLARE_ALIGNED(NvU64 transferSize, 8); 3852 3853 /*! 3854 * To be set in case of memset 3855 */ 3856 NvU32 value; 3857 3858 /*! 3859 * Memory op to be performed 3860 */ 3861 NV2080_CTRL_MEMMGR_MEMORY_OP memop; 3862 } NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS; 3863 3864 /*! 3865 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG 3866 * 3867 * This command is an internal command sent from Kernel RM to Physical RM 3868 * to get local GPU's ATS config 3869 * 3870 * addrSysPhys : [OUT] 3871 * System Physical Address 3872 * addrWidth : [OUT] 3873 * Address width value 3874 * mask : [OUT] 3875 * Mask value 3876 * maskWidth : [OUT] 3877 * Mask width value 3878 */ 3879 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */ 3880 3881 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU) 3882 3883 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS { 3884 NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); 3885 NvU32 addrWidth; 3886 NvU32 mask; 3887 NvU32 maskWidth; 3888 } NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS; 3889 3890 /*! 3891 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG 3892 * 3893 * This command is an internal command sent from Kernel RM to Physical RM 3894 * to set peer ATS config using the parameters passed in. 3895 * 3896 * peerId : [IN] 3897 * Peer Id of the peer for which ATS config is to be programmed 3898 * addrSysPhys : [IN] 3899 * System Physical Address 3900 * addrWidth : [IN] 3901 * Address width value 3902 * mask : [IN] 3903 * Mask value 3904 * maskWidth : [IN] 3905 * Mask width value 3906 */ 3907 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */ 3908 3909 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU) 3910 3911 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS { 3912 NvU32 peerId; 3913 NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); 3914 NvU32 addrWidth; 3915 NvU32 mask; 3916 NvU32 maskWidth; 3917 } NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS; 3918 3919 /*! 3920 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO 3921 * 3922 * Get GPU EDPpeak Limit information 3923 * 3924 * limitMin [OUT] 3925 * Minimum allowed limit value on EDPp policy on both AC and DC 3926 * limitRated [OUT] 3927 * Rated/default allowed limit value on EDPp policy on AC 3928 * limitMax [OUT] 3929 * Maximum allowed limit value on EDPp policy on AC 3930 * limitCurr [OUT] 3931 * Current resultant limit effective on EDPp policy on AC and DC 3932 * limitBattRated [OUT] 3933 * Default/rated allowed limit on EDPp policy on DC 3934 * limitBattMax [OUT] 3935 * Maximum allowed limit on EDPp policy on DC 3936 * 3937 * Possible status values returned are: 3938 * NV_OK 3939 * NV_ERR_GENERIC 3940 */ 3941 3942 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */ 3943 3944 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU) 3945 3946 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS { 3947 NvU32 limitMin; 3948 NvU32 limitRated; 3949 NvU32 limitMax; 3950 NvU32 limitCurr; 3951 NvU32 limitBattRated; 3952 NvU32 limitBattMax; 3953 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS; 3954 3955 /* 3956 * NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA 3957 * 3958 * @brief Initialize RM User Shared Data memory mapping on physical RM 3959 * 3960 * @param[in] physAddr Physical address of memdesc to link physical to kernel 3961 * 0 to de-initialize 3962 * 3963 * @return NV_OK on success 3964 * @return NV_ERR_ otherwise 3965 */ 3966 #define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU) 3967 3968 typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS { 3969 NV_DECLARE_ALIGNED(NvU64 physAddr, 8); 3970 } NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS; 3971 #define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */ 3972 3973 /* 3974 * NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL 3975 * 3976 * @brief Set mask of data to be polled on physical for RUSD 3977 * 3978 * @param[in] polledDataMask Bitmask of data requested, defined in cl00de 3979 * 3980 * @return NV_OK on success 3981 * @return NV_ERR_ otherwise 3982 */ 3983 #define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU) 3984 3985 typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS { 3986 NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8); 3987 } NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS; 3988 #define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */ 3989 3990 /*! 3991 * NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS 3992 * 3993 * This structure provides the params for starting GPU Fabric Probe 3994 * 3995 * tracepointMask[IN] 3996 * - tracepoint selection filter 3997 * bufferSize[IN] 3998 * - size of gsp side logging buffer 3999 * bufferWatermark[IN] 4000 * - entry threshold for GSP to issue RPC of logged entries to kernel RM 4001 * bStart[IN] 4002 * - if true, start tracing. if false, stop tracing. 4003 */ 4004 #define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID (0xE3U) 4005 4006 typedef struct NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS { 4007 NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8); 4008 NvU32 bufferSize; 4009 NvU32 bufferWatermark; 4010 NvBool bStart; 4011 } NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS; 4012 4013 /* 4014 * NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE 4015 * 4016 * This command is used to start GSP-RM trace tool. 4017 * This command accepts NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS 4018 * 4019 */ 4020 #define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID" */ 4021 4022 /* 4023 * NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES 4024 * 4025 * @brief get state (enabled/disabled) of SEC2 classes 4026 * 4027 * 4028 * @return NV_OK on success 4029 * @return NV_ERR_ otherwise 4030 */ 4031 #define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID (0xAFU) 4032 4033 typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS { 4034 NvBool bMaxwellSec2Enabled; 4035 NvBool bNv95A1TsecEnabled; 4036 NvBool bHopperSec2WorkLaunchAEnabled; 4037 } NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS; 4038 #define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES (0x20800aaf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID" */ 4039 4040 4041 /*! 4042 * @ref NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND 4043 */ 4044 #define NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND (0x20800ae4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */ 4045 4046 #define NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0xE4U) 4047 4048 typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS; 4049 4050 /* ctrl2080internal_h */ 4051