1 /*
2  * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3  * SPDX-License-Identifier: MIT
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #pragma once
25 
26 #include <nvtypes.h>
27 
28 //
29 // This file was generated with FINN, an NVIDIA coding tool.
30 // Source file:      ctrl/ctrl90e6.finn
31 //
32 
33 #include "ctrl/ctrlxxxx.h"
34 #define NV90E6_CTRL_CMD(cat,idx)  \
35     NVXXXX_CTRL_CMD(0x90E6, NV90E6_CTRL_##cat, idx)
36 
37 
38 /* NV90E6 command categories (6bits) */
39 #define NV90E6_CTRL_RESERVED (0x00)
40 #define NV90E6_CTRL_MASTER   (0x01)
41 
42 
43 /*
44  * NV90E6_CTRL_CMD_NULL
45  *
46  * This command does nothing.
47  * This command does not take any parameters.
48  *
49  * Possible status values returned are:
50  *   NV_OK
51  */
52 
53 #define NV90E6_CTRL_CMD_NULL (0x90e60000) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_RESERVED_INTERFACE_ID << 8) | 0x0" */
54 
55 
56 
57 
58 
59 /*
60  * NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK
61  *
62  * This command is used to query the offset and mask within the object mapping
63  * that can be used to query for ECC and NVLINK interrupts.
64  *
65  * If a read of the given offset+mask is non-zero then it is possible an ECC or
66  * an NVLINK error has been reported and not yet handled. If this is true then
67  * the caller must either wait until the read returns zero or call into the
68  * corresponding count reporting APIs to get updated counts.
69  *
70  * offset
71  *   The offset into a GF100_SUBDEVICE_MASTSER's mapping where the top level
72  *   interrupt register can be found.
73  * mask
74  *   Compatibility field that contains the same bits as eccMask. This field is
75  *   deprecated and will be removed.
76  * eccMask
77  *   The mask to AND with the value found at offset to determine if any ECC
78  *   interrupts are pending.
79  * nvlinkMask
80  *   The mask to AND with the value found at offset to determine if any NVLINK
81  *   interrupts are pending.
82  *
83  *   Possible return status values are
84  *     NV_OK
85  *     NV_ERR_INVALID_ARGUMENT
86  *     NV_ERR_NOT_SUPPORTED
87  */
88 #define NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK (0x90e60101) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID" */
89 
90 #define NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS_MESSAGE_ID (0x1U)
91 
92 typedef struct NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS {
93     NvU32 offset;
94     NvU32 mask;     // TODO: remove after all users have switched to use eccMask
95     NvU32 eccMask;
96     NvU32 nvlinkMask;
97 } NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS;
98 
99 // TODO: remove once users of this interface have switched to the new name.
100 #define NV90E6_CTRL_CMD_MASTER_GET_ECC_INTR_OFFSET_MASK NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK
101 
102 typedef NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS NV90E6_CTRL_MASTER_GET_ECC_INTR_OFFSET_MASK_PARAMS;
103 
104 /*
105  * NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK
106  *
107  * This command is used to query the mask within the fastpath register
108  * (VIRTUAL_FUNCTION_ERR_CONT) that can be used to query for ECC and NVLINK interrupts.
109  *
110  * If a read of the given mask is non-zero then it is possible an ECC or
111  * an NVLINK error has been reported and not yet handled. If this is true then
112  * the caller must either wait until the read returns zero or call into the
113  * corresponding count reporting APIs to get updated counts.
114  *
115  * [out] eccMask
116  *   The mask to AND with the value found at offset to determine if any ECC
117  *   interrupts are possibly pending.
118  * [out] nvlinkMask
119  *   The mask to AND with the value found at offset to determine if any NVLINK
120  *   interrupts are possibly pending.
121  *
122  *   Possible return status values are
123  *     NV_OK
124  *     NV_ERR_INVALID_ARGUMENT
125  *     NV_ERR_NOT_SUPPORTED
126  */
127 #define NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK (0x90e60102) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_MASTER_MASTER_INTERFACE_ID << 8) | NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID" */
128 
129 #define NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_MESSAGE_ID (0x2U)
130 
131 typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS {
132     NvU32 eccMask;
133     NvU32 nvlinkMask;
134 } NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS;
135 
136 /* _ctrl90e6_h_ */
137 
138