1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl90f1.finn 31 // 32 33 #include "ctrl/ctrlxxxx.h" 34 #include "mmu_fmt_types.h" 35 #include "nvcfg_sdk.h" 36 37 #define GMMU_FMT_MAX_LEVELS 6U 38 39 /* Fermi+ GPU VASpace control commands and parameters */ 40 #define NV90F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90F1, NV90F1_CTRL_##cat, idx) 41 42 /* Command categories (6bits) */ 43 #define NV90F1_CTRL_RESERVED (0x00U) 44 #define NV90F1_CTRL_VASPACE (0x01U) 45 46 /*! 47 * Does nothing. 48 */ 49 #define NV90F1_CTRL_CMD_NULL (0x90f10000U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ 50 51 52 53 54 55 /*! 56 * Get VAS GPU MMU format. 57 */ 58 #define NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT (0x90f10101U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID" */ 59 60 #define NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID (0x1U) 61 62 typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS { 63 /*! 64 * [in] GPU sub-device handle - this API only supports unicast. 65 * Pass 0 to use subDeviceId instead. 66 */ 67 NvHandle hSubDevice; 68 69 /*! 70 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. 71 */ 72 NvU32 subDeviceId; 73 74 /*! 75 * [out] GMMU format struct. This is of RM-internal type "struct GMMU_FMT*" 76 * which can only be accessed by kernel builds since this is a kernel 77 * only API. 78 */ 79 NV_DECLARE_ALIGNED(NvP64 pFmt, 8); 80 } NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS; 81 82 /*! 83 * Get VAS page level information. 84 */ 85 #define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */ 86 87 typedef struct NV_CTRL_VASPACE_PAGE_LEVEL { 88 /*! 89 * Format of this level. 90 */ 91 NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); 92 93 /*! 94 * Level/Sublevel Formats flattened 95 */ 96 NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); 97 NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); 98 99 /*! 100 * Physical address of this page level instance. 101 */ 102 NV_DECLARE_ALIGNED(NvU64 physAddress, 8); 103 104 /*! 105 * Aperture in which this page level instance resides. 106 */ 107 NvU32 aperture; 108 109 /*! 110 * Size in bytes allocated for this level instance. 111 */ 112 NV_DECLARE_ALIGNED(NvU64 size, 8); 113 114 /*! 115 * Entry Index for this offset. 116 */ 117 NvU32 entryIndex; 118 } NV_CTRL_VASPACE_PAGE_LEVEL; 119 120 #define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U) 121 122 typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { 123 /*! 124 * [in] GPU sub-device handle - this API only supports unicast. 125 * Pass 0 to use subDeviceId instead. 126 */ 127 NvHandle hSubDevice; 128 129 /*! 130 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. 131 */ 132 NvU32 subDeviceId; 133 134 /*! 135 * [in] GPU virtual address to query. 136 */ 137 NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); 138 139 /*! 140 * [in] Page size to query. 141 */ 142 NV_DECLARE_ALIGNED(NvU64 pageSize, 8); 143 144 /*! 145 * [in] Flags 146 * Contains flags to control various aspects of page level info. 147 */ 148 NV_DECLARE_ALIGNED(NvU64 flags, 8); 149 150 /*! 151 * [out] Number of levels populated. 152 */ 153 NvU32 numLevels; 154 155 /*! 156 * [out] Per-level information. 157 */ 158 NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8); 159 } NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS; 160 161 /* valid flags parameter values */ 162 #define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE 0x0ULL 163 #define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1 NVBIT64(0) 164 165 166 /*! 167 * Reserve (allocate and bind) page directory/table entries up to 168 * a given level of the MMU format. Also referred to as "lock-down". 169 * 170 * Each range that has been reserved must be released 171 * eventually with @ref NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES. 172 * A particular VA range and level (page size) combination may only be 173 * locked down once at a given time, but each level is independent. 174 */ 175 #define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */ 176 177 #define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U) 178 179 typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS { 180 /*! 181 * [in] GPU sub-device handle - this API only supports unicast. 182 * Pass 0 to use subDeviceId instead. 183 */ 184 NvHandle hSubDevice; 185 186 /*! 187 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. 188 */ 189 NvU32 subDeviceId; 190 191 /*! 192 * [in] Page size (VA coverage) of the level to reserve. 193 * This need not be a leaf (page table) page size - it can be 194 * the coverage of an arbitrary level (including root page directory). 195 */ 196 NV_DECLARE_ALIGNED(NvU64 pageSize, 8); 197 198 /*! 199 * [in] First GPU virtual address of the range to reserve. 200 * This must be aligned to pageSize. 201 */ 202 NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); 203 204 /*! 205 * [in] Last GPU virtual address of the range to reserve. 206 * This (+1) must be aligned to pageSize. 207 */ 208 NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); 209 } NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS; 210 211 /*! 212 * Release (unbind and free) page directory/table entries up to 213 * a given level of the MMU format that has been reserved through a call to 214 * @ref NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES. Also referred to as "unlock". 215 */ 216 #define NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES (0x90f10104U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID" */ 217 218 #define NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID (0x4U) 219 220 typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS { 221 /*! 222 * [in] GPU sub-device handle - this API only supports unicast. 223 * Pass 0 to use subDeviceId instead. 224 */ 225 NvHandle hSubDevice; 226 227 /*! 228 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. 229 */ 230 NvU32 subDeviceId; 231 232 /*! 233 * [in] Page size (VA coverage) of the level to release. 234 * This need not be a leaf (page table) page size - it can be 235 * the coverage of an arbitrary level (including root page directory). 236 */ 237 NV_DECLARE_ALIGNED(NvU64 pageSize, 8); 238 239 /*! 240 * [in] First GPU virtual address of the range to release. 241 * This must be aligned to pageSize. 242 */ 243 NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); 244 245 /*! 246 * [in] Last GPU virtual address of the range to release. 247 * This (+1) must be aligned to pageSize. 248 */ 249 NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); 250 } NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS; 251 252 /*! 253 * Get VAS page level information without kernel priviledge. This will internally call 254 * NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO. 255 */ 256 #define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID" */ 257 258 #define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID (0x5U) 259 260 typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS; 261 262 /*! 263 * Pin PDEs for a given VA range on the server RM and then mirror the client's page 264 * directory/tables in the server. 265 * 266 * @ref 267 */ 268 #define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */ 269 270 #define NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID (0x6U) 271 272 typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS { 273 /*! 274 * [in] GPU sub-device handle - this API only supports unicast. 275 * Pass 0 to use subDeviceId instead. 276 */ 277 NvHandle hSubDevice; 278 279 /*! 280 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. 281 */ 282 NvU32 subDeviceId; 283 284 /*! 285 * [in] Page size (VA coverage) of the level to reserve. 286 * This need not be a leaf (page table) page size - it can be 287 * the coverage of an arbitrary level (including root page directory). 288 */ 289 NV_DECLARE_ALIGNED(NvU64 pageSize, 8); 290 291 /*! 292 * [in] First GPU virtual address of the range to reserve. 293 * This must be aligned to pageSize. 294 */ 295 NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); 296 297 /*! 298 * [in] Last GPU virtual address of the range to reserve. 299 * This (+1) must be aligned to pageSize. 300 */ 301 NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); 302 303 /*! 304 * [in] Number of PDE levels to copy. 305 */ 306 NvU32 numLevelsToCopy; 307 308 /*! 309 * [in] Per-level information. 310 */ 311 struct { 312 /*! 313 * Physical address of this page level instance. 314 */ 315 NV_DECLARE_ALIGNED(NvU64 physAddress, 8); 316 317 /*! 318 * Size in bytes allocated for this level instance. 319 */ 320 NV_DECLARE_ALIGNED(NvU64 size, 8); 321 322 /*! 323 * Aperture in which this page level instance resides. 324 */ 325 NvU32 aperture; 326 327 /*! 328 * Page shift corresponding to the level 329 */ 330 NvU8 pageShift; 331 } levels[GMMU_FMT_MAX_LEVELS]; 332 } NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS; 333 334 /*! 335 * Retrieve extra VA range that RM needs to reserve from the OS 336 */ 337 #define NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE (0x90f10107U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID" */ 338 #define NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID (0x7U) 339 340 typedef struct NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS { 341 /*! 342 * [in] GPU sub-device handle - this API only supports unicast. 343 * Pass 0 to use subDeviceId instead. 344 */ 345 NvHandle hSubDevice; 346 347 /*! 348 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. 349 */ 350 NvU32 subDeviceId; 351 352 /*! 353 * [out] The required VA range, in Megabytes 354 */ 355 NV_DECLARE_ALIGNED(NvU64 requiredVaRange, 8); 356 } NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS; 357 358 /*! 359 * Retrieve info on a VAS heap - used only for the MODS test RandomVATest 360 */ 361 #define NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO (0x90f10108U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID" */ 362 #define NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID (0x8U) 363 364 typedef struct NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS { 365 /*! 366 * [in] GPU sub-device handle - this API only supports unicast. 367 * Pass 0 to use subDeviceId instead. 368 */ 369 NvHandle hSubDevice; 370 371 /*! 372 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. 373 */ 374 NvU32 subDeviceId; 375 376 /*! 377 * [out] Number of free bytes in the heap 378 */ 379 NV_DECLARE_ALIGNED(NvU64 bytesFree, 8); 380 381 /*! 382 * [out] Number of bytes in the heap 383 */ 384 NV_DECLARE_ALIGNED(NvU64 bytesTotal, 8); 385 386 /*! 387 * [out] Offset of largest free block 388 */ 389 NV_DECLARE_ALIGNED(NvU64 largestFreeOffset, 8); 390 391 /*! 392 * [out] Size of the largest free block 393 */ 394 NV_DECLARE_ALIGNED(NvU64 largestFreeSize, 8); 395 396 /*! 397 * [out] Number of usable free bytes 398 */ 399 NV_DECLARE_ALIGNED(NvU64 usableBytesFree, 8); 400 401 /*! 402 * [out] Number of free blocks 403 */ 404 NvU32 numFreeBlocks; 405 } NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS; 406 407 /* _ctrl90f1_h_ */ 408