1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2012-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 25 #pragma once 26 27 #include <nvtypes.h> 28 29 // 30 // This file was generated with FINN, an NVIDIA coding tool. 31 // Source file: ctrl/ctrla080.finn 32 // 33 34 35 36 37 38 /* 39 * NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES 40 * 41 * This command sets primary surface properties on a virtual GPU in displayless mode 42 * 43 * Parameters: 44 * headIndex 45 * This parameter specifies the head for which surface properties are 46 * 47 * isPrimary 48 * This parameter indicates whether surface information is for primary surface. set to 1 if its a primary surface. 49 * 50 * hMemory 51 * Memory handle containing the surface (only for RM-managed heaps) 52 * 53 * offset 54 * Offset from base of allocation (hMemory for RM-managed heaps; physical 55 * memory otherwise) 56 * 57 * surfaceType 58 * This parameter indicates whether surface type is block linear or pitch 59 * 60 * surfaceBlockHeight 61 * This parameter indicates block height for the surface 62 * 63 * surfacePitch 64 * This parameter indicates pitch value for the surface 65 * 66 * surfaceFormat 67 * This parameter indicates surface format (A8R8G8B8/A1R5G5B5) 68 * 69 * surfaceWidth 70 * This parameter indicates width value for the surface 71 * 72 * surfaceHeight 73 * This parameter indicates height value for the surface 74 * 75 * surfaceSize 76 * This parameter indicates size of the surface 77 * 78 * surfaceKind 79 * This parameter indicates surface kind (only for externally-managed 80 * heaps) 81 * 82 * rectX [unused] 83 * This parameter indicates X coordinate of the region to be displayed 84 * 85 * rectY [unused] 86 * This parameter indicates Y coordinate of the region to be displayed 87 * 88 * rectWidth 89 * This parameter indicates width of the region to be displayed 90 * 91 * rectHeight 92 * This parameter indicates height of the region to be displayed 93 * 94 * hHwResDevice 95 * This parameter indicates the device associated with surface 96 * 97 * hHwResHandle 98 * This parameter indicates the handle to hardware resources allocated to surface 99 * 100 * effectiveFbPageSize 101 * This parameter indicates the actual page size used by KMD for the surface 102 * 103 * Possible status values returned are: 104 * NV_OK 105 * NV_ERR_INVALID_ARGUMENT 106 * NVOS_STATUS_NOT_SUPPORTED 107 */ 108 109 #define NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES (0xa0800103) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID" */ 110 111 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID (0x3U) 112 113 typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES { 114 NvU32 headIndex; 115 NvU32 isPrimary; 116 NvU32 hMemory; 117 NvU32 offset; 118 NvU32 surfaceType; 119 NvU32 surfaceBlockHeight; 120 NvU32 surfacePitch; 121 NvU32 surfaceFormat; 122 NvU32 surfaceWidth; 123 NvU32 surfaceHeight; 124 NvU32 rectX; 125 NvU32 rectY; 126 NvU32 rectWidth; 127 NvU32 rectHeight; 128 NvU32 surfaceSize; 129 NvU32 surfaceKind; 130 NvU32 hHwResDevice; 131 NvU32 hHwResHandle; 132 NvU32 effectiveFbPageSize; 133 } NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES; 134 135 /* valid surfaceType values */ 136 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT 0:0 137 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 138 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_PITCH 0x00000001 139 /* valid surfaceBlockHeight values */ 140 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_ONE_GOB 0x00000000 141 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_TWO_GOBS 0x00000001 142 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 143 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 144 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 145 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 146 /* valid surfaceFormat values */ 147 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_I8 0x0000001E 148 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_RF16_GF16_BF16_AF16 0x000000CA 149 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8R8G8B8 0x000000CF 150 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A2B10G10R10 0x000000D1 151 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_X2BL10GL10RL10_XRBIAS 0x00000022 152 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8B8G8R8 0x000000D5 153 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R5G6B5 0x000000E8 154 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A1R5G5B5 0x000000E9 155 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R16_G16_B16_A16 0x000000C6 156 157 /* 158 * NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS 159 * 160 * This command clears surface information related to head. 161 * It should be called while shutting down head in displayless mode on virtual GPU 162 * 163 * Parameters: 164 * headIndex 165 * This parameter specifies the head for which cleanup is requested. 166 * 167 * blankingEnabled 168 * This parameter must be set to 1 to enable blanking. 169 * 170 * Possible status values returned are: 171 * NV_OK 172 * NV_ERR_INVALID_ARGUMENT 173 * NVOS_STATUS_NOT_SUPPORTED 174 */ 175 #define NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE (0xa0800104) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID" */ 176 177 #define NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID (0x4U) 178 179 typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS { 180 NvU32 headIndex; 181 NvU32 blankingEnabled; 182 } NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS; 183 184 /* 185 * NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS 186 * 187 * This command returns CPU virtual address of the mouse pointer mapping for VGPU. 188 * The address returned by this command is the pointer address for the head 0. 189 * VGPU_POINTER_OFFSET_HEAD(i) should be added to this address to get the address of head i. 190 * VGPU mouse pointer is a 32 bit value, X location of the mouse pointer is stored in 191 * 15:0 and Y location is stored in 31:16 bits. X location value of the mouse pointer is 192 * negative if bit 15 is set. Similarly, Y location value is negative if bit 31 is set. 193 * 194 * Parameters: 195 * pPointerAddress 196 * CPU virtual address of the mouse pointer mapping for VGPU 197 * 198 * Possible status values returned are: 199 * NV_OK 200 * NV_ERR_INVALID_ARGUMENT 201 * NVOS_STATUS_NOT_SUPPORTED 202 */ 203 204 #define NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS (0xa0800105) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID" */ 205 206 #define NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID (0x5U) 207 208 typedef struct NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS { 209 NV_DECLARE_ALIGNED(NvP64 pPointerAddress, 8); 210 } NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS; 211 212 #define VGPU_POINTER_OFFSET_HEAD0_VALUE 0x00000000 213 #define VGPU_POINTER_OFFSET_HEAD0_FLAG 0x00000004 214 #define VGPU_POINTER_OFFSET_HEAD1_VALUE 0x00000008 215 #define VGPU_POINTER_OFFSET_HEAD1_FLAG 0x0000000c 216 #define VGPU_POINTER_OFFSET_HEAD2_VALUE 0x00000010 217 #define VGPU_POINTER_OFFSET_HEAD2_FLAG 0x00000014 218 #define VGPU_POINTER_OFFSET_HEAD3_VALUE 0x00000018 219 #define VGPU_POINTER_OFFSET_HEAD3_FLAG 0x0000001c 220 #define VGPU_POINTER_OFFSET_HEAD_VALUE(i) (i * 8) 221 #define VGPU_POINTER_OFFSET_HEAD_FLAG(i) (4 + i * 8) 222 #define VGPU_POINTER_OFFSET_HEAD_SIZE 4 223 224 /* 225 * NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE 226 * 227 * This command returns mappable video size to be used by each VM. 228 * 229 * Parameters: 230 * mappableVideoSize 231 * This parameter returns mappable video size in bytes. 232 * 233 * Possible status values returned are: 234 * NV_OK 235 * NV_ERR_INVALID_ARGUMENT 236 * NVOS_STATUS_NOT_SUPPORTED 237 */ 238 239 240 #define NV_VGPU_POINTER_X_LOCATION 15:0 241 #define NV_VGPU_POINTER_Y_LOCATION 31:16 242 #define NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE (0xa0800201) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID" */ 243 244 #define NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID (0x1U) 245 246 typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS { 247 NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); 248 } NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS; 249 250 /* 251 * NVA080_CTRL_CMD_MAP_SEMA_MEM 252 * 253 * This command returns GPU VA for the channel with 'hCtxDma' handle 254 * where per VM semaphore memory is mapped which is used for tracking 255 * non-stall interrupt of each VM. 256 * 257 * Parameters: 258 * hClient [in] 259 * This parameter specifies the handle to the NV01_ROOT object of 260 * the client. This object should be the parent of the object 261 * specified by hDevice. 262 * hDevice [in] 263 * This parameter specifies the handle of the NV01_DEVICE object 264 * representing the desired GPU. 265 * hMemory [in] 266 * This parameter specifies the handle for semaphore memory 267 * hCtxDma [in] 268 * This parameter specifies the handle of the NV01_CONTEXT_DMA 269 * object through which bufferId is written in semaphore memory for 270 * non-stall interrupt tracking. 271 * semaAddress [out] 272 * This parameter returns the GPU virtual address of the semaphore 273 * memory. 274 * 275 * Possible status values returned are: 276 * NV_OK 277 * NVOS_STATUS_INVALID_DATA 278 * NV_ERR_INVALID_CLIENT 279 * NV_ERR_INVALID_OBJECT_HANDLE 280 * 281 */ 282 283 #define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x2" */ 284 285 typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS { 286 NvHandle hClient; 287 NvHandle hDevice; 288 NvHandle hMemory; 289 NvHandle hCtxDma; 290 NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); 291 } NVA080_CTRL_MAP_SEMA_MEM_PARAMS; 292 293 /* 294 * NVA080_CTRL_CMD_UNMAP_SEMA_MEM 295 * 296 * This command unmaps per VM semaphore memory from GPU VA space, mapped by 297 * NVA080_CTRL_CMD_MAP_SEMA_MEM command. 298 * 299 * Parameters: 300 * Same as NVA080_CTRL_MAP_SEMA_MEM_PARAMS, except semaAddress is input 301 * parameter here. 302 * 303 * Possible status values returned are: 304 * NV_OK 305 * NVOS_STATUS_INVALID_DATA 306 * NV_ERR_INVALID_CLIENT 307 * NV_ERR_INVALID_OBJECT_HANDLE 308 * 309 */ 310 311 #define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x3" */ 312 313 /*! 314 * NVA080_CTRL_CMD_SET_FB_USAGE 315 * 316 * This command sets the current framebuffer usage value in the plugin. 317 * 318 * Parameters: 319 * fbUsed [in] 320 * This parameter holds the current FB usage value in bytes. 321 * 322 * Possible status values returned are: 323 * NV_OK 324 */ 325 #define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ 326 327 #define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) 328 329 typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { 330 NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); 331 } NVA080_CTRL_SET_FB_USAGE_PARAMS; 332 333 /*! 334 * NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM 335 * 336 * This command allocates the per engine vGPU semaphore memory and map it to 337 * GPU/CPU VA. 338 * 339 * Calculate engine's semaphore GPU VA = 340 * semaAddress + semaStride * NV2080_ENGINE_TYPE_ of that engine 341 * 342 * Parameters: 343 * hClient [in] 344 * This parameter specifies the handle to the NV01_ROOT object of 345 * the client. This object should be the parent of the object 346 * specified by hDevice. 347 * hDevice [in] 348 * This parameter specifies the handle of the NV01_DEVICE object 349 * representing the desired GPU. 350 * hMemory [in] 351 * This parameter specifies the handle for semaphore memory 352 * hCtxDma [in] 353 * This parameter specifies the handle of the NV01_CONTEXT_DMA 354 * object through which bufferId is written in semaphore memory for 355 * non-stall interrupt tracking. 356 * semaAddress [out] 357 * This parameter returns the GPU VA of the per engine semaphore memory. 358 * semaStride [out] 359 * This parameter specifies the stride of each engine's semaphore offset within this memory. 360 * 361 * Possible status values returned are: 362 * NV_OK 363 */ 364 365 #define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ 366 367 #define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) 368 369 typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS { 370 NvU32 hClient; 371 NvU32 hDevice; 372 NvHandle hMemory; 373 NvU32 hCtxDma; 374 NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); 375 NvU32 semaStride; 376 } NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; 377 378 /*! 379 * NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM 380 * 381 * This command unmaps and frees the per engine vGPU semaphore memory. 382 * 383 * Parameters: 384 * Same as NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS, except semaAddress is input 385 * parameter here. 386 * 387 * Possible status values returned are: 388 * NV_OK 389 */ 390 391 #define NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM (0xa0800206) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ 392 393 #define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U) 394 395 typedef NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; 396 397 /* 398 * NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP 399 * 400 * This command provides the guest RM with PFN information, so that it can 401 * update the shared memory with the plugin, which keeps track of guest sysmem. 402 * 403 * Parameters: 404 * destPhysAddr 405 * Start address of the segment to be tracked 406 * 407 * pageCount 408 * Number of pages in the segment 409 * 410 * pageSize 411 * Size of pages in the segment 412 * 413 * isValid: 414 * TRUE : Set bits corresponding to PFNs in bitmap and increase segment refcount 415 * FALSE: Decrease segment refcount and then unset bits if refcount is 0 416 * 417 * pfnList 418 * List of PFNs in the segment 419 * 420 * flags 421 * FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 422 * Flag set to TRUE if pteMem is CPU VA pointing to BAR1 and 423 * dstPhysAddr contains BAR1 offset. 424 * 425 * Possible status values returned are: 426 * NVOS_STATUS_SUCCESS 427 */ 428 429 #define NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP (0xa0800207) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID" */ 430 431 #define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 0:0 432 #define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_FALSE (0x00000000) 433 #define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_TRUE (0x00000001) 434 435 #define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID (0x7U) 436 437 typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { 438 NV_DECLARE_ALIGNED(NvU64 destPhysAddr, 8); 439 NvU32 pageCount; 440 NvU32 pageSize; 441 NvBool isValid; 442 NV_DECLARE_ALIGNED(NvP64 pfnList, 8); 443 NvU32 flags; 444 } NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS; 445 446 /* 447 * Blit semaphore offset location 448 */ 449 #define VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET 0x200 450 #define VGPU_BLIT_RESTORE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET) 451 452 #define VGPU_BLIT_SEMA_MEM_OFFSET 0x400 453 #define VGPU_BLIT_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_SEMA_MEM_OFFSET) 454 455 #define VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET 0x800 456 #define VGPU_FBMEMCE_PUSH_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET) 457 458 #define VGPU_FBMEMCE_SEMA_MEM_OFFSET 0x810 459 #define VGPU_FBMEMCE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_SEMA_MEM_OFFSET) 460 461 #define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET 0x820 462 #define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET) 463 464 #define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET 0x824 465 466 /* 467 * NVA080_CTRL_CMD_VGPU_GET_CONFIG 468 * 469 * This command returns VGPU configuration information for the associated GPU. 470 * 471 * Parameters: 472 * frameRateLimiter 473 * This parameter returns value of frame rate limiter 474 * swVSyncEnabled 475 * This parameter returns value of SW VSync flag (zero for disabled, 476 * non-zero for enabled) 477 * cudaEnabled 478 * This parameter returns whether CUDA is enabled or not 479 * pluginPteBlitEnabled 480 * This parameter returns whether to use plugin pte blit path 481 * disableWddm1xPreemption 482 * This parameter returns whether to disable WDDM 1.x Preemption or not 483 * debugBuffer 484 * This parameter specifies a pointer to memory which is filled with 485 * debugging information. 486 * debugBufferSize 487 * This parameter specifies the size of the debugging buffer in bytes. 488 * guestFbOffset 489 * This parameter returns FB offset start address for VM 490 * mappableCpuHostAperture 491 * This parameter returns mappable CPU host aperture size 492 * linuxInterruptOptimization 493 * This parameter returns whether stall interrupts are enabled/disabled for 494 * Linux VM 495 * vgpuDeviceCapsBits 496 * This parameter specifies CAP bits to ON/OFF features from guest OS. 497 * CAPS_SW_VSYNC_ENABLED 498 * cap bit to indicate if SW VSync flag enabled/disabled. 499 * Please note, currently, guest doesn't honour this bit. 500 * CAPS_CUDA_ENABLED 501 * cap bit to indicate if CUDA enabled/disabled. 502 * Please note, currently, guest doesn't honour this bit. 503 * CAPS_WDDM1_PREEMPTION_DISABLED 504 * cap bit to indicate if WDDM 1.x Preemption disabled/enabled. 505 * Please note, currently, guest doesn't honour this bit. 506 * CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 507 * cap bit to indicate if stall interrupts are enabled/disabled for 508 * Linux VM. Please note, currently, guest doesn't honour this bit. 509 * CAPS_PTE_BLIT_ENABLED 510 * cap bit to indicate if PTE blit is enabled/disabled. 511 * Please note, currently, guest doesn't honour this bit. 512 * CAPS_PDE_BLIT_ENABLED 513 * cap bit to indicate if PDE blit is enabled/disabled. 514 * CAPS_GET_PDE_INFO_CTRL_DISABLED 515 * cap bit to indicate if GET_PDE_INFO RM Ctrl is disabled/enabled. 516 * CAPS_GUEST_FB_OFFSET_DISABLED 517 * cap bit to indicate if FB Offset is exposed to guest or not. 518 * If set, FB Offset is not exposed to guest. 519 * CAPS_CILP_DISABLED_ON_WDDM 520 * cap bit to indicate if CILP on WDDM disabled/enabled. 521 * CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 522 * cap bit to indicate if guest needs to use doorbell token value updated 523 * dynamically by host after migration. 524 * CAPS_SRIOV_ENABLED 525 * Cap bit to indicate if the vGPU is running in SRIOV mode or not. 526 * CAPS_GUEST_MANAGED_VA_ENABLED 527 * Cap bit to indicate if the Guest is managing the VA. 528 * CAPS_VGPU_1TO1_COMPTAG_ENABLED 529 * Cap bit to indicate if the 1to1 comptag enabled. This is always TRUE 530 * when SR-IOV is enabled. 531 * CAPS_MBP_ENABLED 532 * Cap bit to indicate if the Mid Buffer Preemption enabled. 533 * CAPS_ASYNC_MBP_ENABLED 534 * Cap bit to indicate if the asynchronus Mid buffer Preemption enabled. 535 * CAPS_TLB_INVALIDATE_ENABLED 536 * Cap bit to indicate if the vGPU supports TLB Invalidation operation or not. 537 * CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 538 * Cap bit to indicate if the vGPU supports PTE blit for page table updates using BAR1 539 * CAPS_SRIOV_HEAVY_ENABLED 540 * Cap bit to indicate if vGPU is running in SRIOV Heavy mode or not. 541 * When set true SRIOV Heavy is enabled. 542 * When set false and CAPS_SRIOV_ENABLED is set true, SRIOV Standard is enabled. 543 * CAPS_TIMESLICE_OVERRIDE_ENABLED 544 * Cap bit to indicate whether TSG timeslice override is enabled or not. 545 * When set true, TSG timeslice override is enabled. 546 * When false, TSG timeslice override is disabled. 547 * CAPS_GUEST_HIBERNATION_ENABLED 548 * Cap bit to indicate whether Guest OS Hibernation is supported or not. 549 * uvmEnabledFeatures 550 * This parameter returns mask of UVM enabled features on vGPU. It comprises of 551 * UVM managed APIs and replayable faults that are enabled or disabled based on 552 * vGPU version. 553 * enableKmdSysmemScratch 554 * This parameter is used to overwrite guest regkey PreferSystemMemoryScratch. 555 * Setting vgpu parameter "vgpu_enable_kmd_sysmem_scratch" in plugin will 556 * set this parameter. If the parameter is set, guest moves shader buffer 557 * allocation from FB to sysmem. 558 * 559 * Possible status values returned are: 560 * NV_OK 561 * NV_ERR_INVALID_PARAM_STRUCT 562 * NV_ERR_INVALID_ARGUMENT 563 */ 564 #define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET) 565 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */ 566 567 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0 568 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_FALSE (0x00000000) 569 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_TRUE (0x00000001) 570 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED 1:1 571 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_FALSE (0x00000000) 572 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_TRUE (0x00000001) 573 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED 2:2 574 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_FALSE (0x00000000) 575 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_TRUE (0x00000001) 576 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 3:3 577 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_FALSE (0x00000000) 578 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_TRUE (0x00000001) 579 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED 4:4 580 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_FALSE (0x00000000) 581 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_TRUE (0x00000001) 582 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED 5:5 583 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_FALSE (0x00000000) 584 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_TRUE (0x00000001) 585 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED 6:6 586 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_FALSE (0x00000000) 587 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_TRUE (0x00000001) 588 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED 7:7 589 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_FALSE (0x00000000) 590 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_TRUE (0x00000001) 591 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM 8:8 592 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_FALSE (0x00000000) 593 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_TRUE (0x00000001) 594 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED 9:9 595 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_FALSE (0x00000000) 596 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_TRUE (0x00000001) 597 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 10:10 598 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_FALSE (0x00000000) 599 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_TRUE (0x00000001) 600 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED 11:11 601 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_FALSE (0x00000000) 602 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_TRUE (0x00000001) 603 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED 12:12 604 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_FALSE (0x00000000) 605 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_TRUE (0x00000001) 606 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED 13:13 607 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_FALSE (0x00000000) 608 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_TRUE (0x00000001) 609 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED 14:14 610 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_FALSE (0x00000000) 611 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_TRUE (0x00000001) 612 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED 15:15 613 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_FALSE (0x00000000) 614 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_TRUE (0x00000001) 615 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED 16:16 616 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_FALSE (0x00000000) 617 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_TRUE (0x00000001) 618 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 17:17 619 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_FALSE (0x00000000) 620 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_TRUE (0x00000001) 621 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED 18:18 622 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_FALSE (0x00000000) 623 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_TRUE (0x00000001) 624 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED 19:19 625 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_FALSE (0x00000000) 626 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_TRUE (0x00000001) 627 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED 20:20 628 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE (0x00000000) 629 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE (0x00000001) 630 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS 21:21 631 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_FALSE (0x00000000) 632 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_TRUE (0x00000001) 633 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22 634 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_FALSE (0x00000000) 635 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_TRUE (0x00000001) 636 637 /* UVM supported features */ 638 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 639 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_FALSE (0x00000000) 640 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_TRUE (0x00000001) 641 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED 1:1 642 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_FALSE (0x00000000) 643 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_TRUE (0x00000001) 644 645 #define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U) 646 647 typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS { 648 NvU32 frameRateLimiter; 649 NvU32 swVSyncEnabled; 650 NvU32 cudaEnabled; 651 NvU32 pluginPteBlitEnabled; 652 NvU32 disableWddm1xPreemption; 653 NvU32 debugBufferSize; 654 NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8); 655 NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); 656 NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8); 657 NvU32 linuxInterruptOptimization; 658 NvU32 vgpuDeviceCapsBits; 659 NvU32 maxPixels; 660 NvU32 uvmEnabledFeatures; 661 NvBool enableKmdSysmemScratch; 662 } NVA080_CTRL_VGPU_GET_CONFIG_PARAMS; 663 664 665 666 /* _ctrla080_h_ */ 667