1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrla080.finn 31 // 32 33 #include "ctrl/ctrlxxxx.h" 34 /* KEPLER_DEVICE_VGPU control commands and parameters */ 35 36 #define NVA080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA080, NVA080_CTRL_##cat, idx) 37 38 /* Command categories (6bits) */ 39 #define NVA080_CTRL_RESERVED (0x00) 40 #define NVA080_CTRL_VGPU_DISPLAY (0x01) 41 #define NVA080_CTRL_VGPU_MEMORY (0x02) 42 #define NVA080_CTRL_VGPU_OTHERS (0x03) 43 44 /* 45 * NVA080_CTRL_CMD_NULL 46 * 47 * This command does nothing. 48 * This command does not take any parameters. 49 * 50 * Possible status values returned are: 51 * NV_OK 52 */ 53 54 #define NVA080_CTRL_CMD_NULL (0xa0800000) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_RESERVED_INTERFACE_ID << 8) | 0x0" */ 55 56 57 58 59 60 /* 61 * NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES 62 * 63 * This command sets primary surface properties on a virtual GPU in displayless mode 64 * 65 * Parameters: 66 * headIndex 67 * This parameter specifies the head for which surface properties are 68 * 69 * isPrimary 70 * This parameter indicates whether surface information is for primary surface. set to 1 if its a primary surface. 71 * 72 * hMemory 73 * Memory handle containing the surface (only for RM-managed heaps) 74 * 75 * offset 76 * Offset from base of allocation (hMemory for RM-managed heaps; physical 77 * memory otherwise) 78 * 79 * surfaceType 80 * This parameter indicates whether surface type is block linear or pitch 81 * 82 * surfaceBlockHeight 83 * This parameter indicates block height for the surface 84 * 85 * surfacePitch 86 * This parameter indicates pitch value for the surface 87 * 88 * surfaceFormat 89 * This parameter indicates surface format (A8R8G8B8/A1R5G5B5) 90 * 91 * surfaceWidth 92 * This parameter indicates width value for the surface 93 * 94 * surfaceHeight 95 * This parameter indicates height value for the surface 96 * 97 * surfaceSize 98 * This parameter indicates size of the surface 99 * 100 * surfaceKind 101 * This parameter indicates surface kind (only for externally-managed 102 * heaps) 103 * 104 * rectX [unused] 105 * This parameter indicates X coordinate of the region to be displayed 106 * 107 * rectY [unused] 108 * This parameter indicates Y coordinate of the region to be displayed 109 * 110 * rectWidth 111 * This parameter indicates width of the region to be displayed 112 * 113 * rectHeight 114 * This parameter indicates height of the region to be displayed 115 * 116 * hHwResDevice 117 * This parameter indicates the device associated with surface 118 * 119 * hHwResHandle 120 * This parameter indicates the handle to hardware resources allocated to surface 121 * 122 * effectiveFbPageSize 123 * This parameter indicates the actual page size used by KMD for the surface 124 * 125 * Possible status values returned are: 126 * NV_OK 127 * NV_ERR_INVALID_ARGUMENT 128 * NVOS_STATUS_NOT_SUPPORTED 129 */ 130 131 #define NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES (0xa0800103) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID" */ 132 133 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID (0x3U) 134 135 typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES { 136 NvU32 headIndex; 137 NvU32 isPrimary; 138 NvU32 hMemory; 139 NvU32 offset; 140 NvU32 surfaceType; 141 NvU32 surfaceBlockHeight; 142 NvU32 surfacePitch; 143 NvU32 surfaceFormat; 144 NvU32 surfaceWidth; 145 NvU32 surfaceHeight; 146 NvU32 rectX; 147 NvU32 rectY; 148 NvU32 rectWidth; 149 NvU32 rectHeight; 150 NvU32 surfaceSize; 151 NvU32 surfaceKind; 152 NvU32 hHwResDevice; 153 NvU32 hHwResHandle; 154 NvU32 effectiveFbPageSize; 155 } NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES; 156 157 /* valid surfaceType values */ 158 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT 0:0 159 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 160 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_PITCH 0x00000001 161 /* valid surfaceBlockHeight values */ 162 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_ONE_GOB 0x00000000 163 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_TWO_GOBS 0x00000001 164 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 165 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 166 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 167 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 168 /* valid surfaceFormat values */ 169 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_I8 0x0000001E 170 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_RF16_GF16_BF16_AF16 0x000000CA 171 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8R8G8B8 0x000000CF 172 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A2B10G10R10 0x000000D1 173 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_X2BL10GL10RL10_XRBIAS 0x00000022 174 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8B8G8R8 0x000000D5 175 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R5G6B5 0x000000E8 176 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A1R5G5B5 0x000000E9 177 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R16_G16_B16_A16 0x000000C6 178 179 /* 180 * NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS 181 * 182 * This command clears surface information related to head. 183 * It should be called while shutting down head in displayless mode on virtual GPU 184 * 185 * Parameters: 186 * headIndex 187 * This parameter specifies the head for which cleanup is requested. 188 * 189 * blankingEnabled 190 * This parameter must be set to 1 to enable blanking. 191 * 192 * Possible status values returned are: 193 * NV_OK 194 * NV_ERR_INVALID_ARGUMENT 195 * NVOS_STATUS_NOT_SUPPORTED 196 */ 197 #define NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE (0xa0800104) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID" */ 198 199 #define NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID (0x4U) 200 201 typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS { 202 NvU32 headIndex; 203 NvU32 blankingEnabled; 204 } NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS; 205 206 207 208 /*! 209 * NVA080_CTRL_CMD_SET_FB_USAGE 210 * 211 * This command sets the current framebuffer usage value in the plugin. 212 * 213 * Parameters: 214 * fbUsed [in] 215 * This parameter holds the current FB usage value in bytes. 216 * 217 * Possible status values returned are: 218 * NV_OK 219 */ 220 #define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ 221 222 #define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) 223 224 typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { 225 NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); 226 } NVA080_CTRL_SET_FB_USAGE_PARAMS; 227 228 229 /* 230 * NVA080_CTRL_CMD_VGPU_GET_CONFIG 231 * 232 * This command returns VGPU configuration information for the associated GPU. 233 * 234 * Parameters: 235 * frameRateLimiter 236 * This parameter returns value of frame rate limiter 237 * swVSyncEnabled 238 * This parameter returns value of SW VSync flag (zero for disabled, 239 * non-zero for enabled) 240 * cudaEnabled 241 * This parameter returns whether CUDA is enabled or not 242 * pluginPteBlitEnabled 243 * This parameter returns whether to use plugin pte blit path 244 * disableWddm1xPreemption 245 * This parameter returns whether to disable WDDM 1.x Preemption or not 246 * debugBuffer 247 * This parameter specifies a pointer to memory which is filled with 248 * debugging information. 249 * debugBufferSize 250 * This parameter specifies the size of the debugging buffer in bytes. 251 * guestFbOffset 252 * This parameter returns FB offset start address for VM 253 * mappableCpuHostAperture 254 * This parameter returns mappable CPU host aperture size 255 * linuxInterruptOptimization 256 * This parameter returns whether stall interrupts are enabled/disabled for 257 * Linux VM 258 * vgpuDeviceCapsBits 259 * This parameter specifies CAP bits to ON/OFF features from guest OS. 260 * CAPS_SW_VSYNC_ENABLED 261 * cap bit to indicate if SW VSync flag enabled/disabled. 262 * Please note, currently, guest doesn't honour this bit. 263 * CAPS_CUDA_ENABLED 264 * cap bit to indicate if CUDA enabled/disabled. 265 * Please note, currently, guest doesn't honour this bit. 266 * CAPS_WDDM1_PREEMPTION_DISABLED 267 * cap bit to indicate if WDDM 1.x Preemption disabled/enabled. 268 * Please note, currently, guest doesn't honour this bit. 269 * CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 270 * cap bit to indicate if stall interrupts are enabled/disabled for 271 * Linux VM. Please note, currently, guest doesn't honour this bit. 272 * CAPS_PTE_BLIT_ENABLED 273 * cap bit to indicate if PTE blit is enabled/disabled. 274 * Please note, currently, guest doesn't honour this bit. 275 * CAPS_PDE_BLIT_ENABLED 276 * cap bit to indicate if PDE blit is enabled/disabled. 277 * CAPS_GET_PDE_INFO_CTRL_DISABLED 278 * cap bit to indicate if GET_PDE_INFO RM Ctrl is disabled/enabled. 279 * CAPS_GUEST_FB_OFFSET_DISABLED 280 * cap bit to indicate if FB Offset is exposed to guest or not. 281 * If set, FB Offset is not exposed to guest. 282 * CAPS_CILP_DISABLED_ON_WDDM 283 * cap bit to indicate if CILP on WDDM disabled/enabled. 284 * CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 285 * cap bit to indicate if guest needs to use doorbell token value updated 286 * dynamically by host after migration. 287 * CAPS_SRIOV_ENABLED 288 * Cap bit to indicate if the vGPU is running in SRIOV mode or not. 289 * CAPS_GUEST_MANAGED_VA_ENABLED 290 * Cap bit to indicate if the Guest is managing the VA. 291 * CAPS_VGPU_1TO1_COMPTAG_ENABLED 292 * Cap bit to indicate if the 1to1 comptag enabled. This is always TRUE 293 * when SR-IOV is enabled. 294 * CAPS_MBP_ENABLED 295 * Cap bit to indicate if the Mid Buffer Preemption enabled. 296 * CAPS_ASYNC_MBP_ENABLED 297 * Cap bit to indicate if the asynchronus Mid buffer Preemption enabled. 298 * CAPS_TLB_INVALIDATE_ENABLED 299 * Cap bit to indicate if the vGPU supports TLB Invalidation operation or not. 300 * CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 301 * Cap bit to indicate if the vGPU supports PTE blit for page table updates using BAR1 302 * CAPS_SRIOV_HEAVY_ENABLED 303 * Cap bit to indicate if vGPU is running in SRIOV Heavy mode or not. 304 * When set true SRIOV Heavy is enabled. 305 * When set false and CAPS_SRIOV_ENABLED is set true, SRIOV Standard is enabled. 306 * CAPS_TIMESLICE_OVERRIDE_ENABLED 307 * Cap bit to indicate whether TSG timeslice override is enabled or not. 308 * When set true, TSG timeslice override is enabled. 309 * When false, TSG timeslice override is disabled. 310 * CAPS_GUEST_HIBERNATION_ENABLED 311 * Cap bit to indicate whether Guest OS Hibernation is supported or not. 312 * uvmEnabledFeatures 313 * This parameter returns mask of UVM enabled features on vGPU. It comprises of 314 * UVM managed APIs and replayable faults that are enabled or disabled based on 315 * vGPU version. 316 * enableKmdSysmemScratch 317 * This parameter is used to overwrite guest regkey PreferSystemMemoryScratch. 318 * Setting vgpu parameter "vgpu_enable_kmd_sysmem_scratch" in plugin will 319 * set this parameter. If the parameter is set, guest moves shader buffer 320 * allocation from FB to sysmem. 321 * 322 * Possible status values returned are: 323 * NV_OK 324 * NV_ERR_INVALID_PARAM_STRUCT 325 * NV_ERR_INVALID_ARGUMENT 326 */ 327 328 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */ 329 330 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0 331 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_FALSE (0x00000000) 332 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_TRUE (0x00000001) 333 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED 1:1 334 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_FALSE (0x00000000) 335 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_TRUE (0x00000001) 336 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED 2:2 337 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_FALSE (0x00000000) 338 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_TRUE (0x00000001) 339 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 3:3 340 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_FALSE (0x00000000) 341 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_TRUE (0x00000001) 342 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED 4:4 343 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_FALSE (0x00000000) 344 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_TRUE (0x00000001) 345 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED 5:5 346 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_FALSE (0x00000000) 347 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_TRUE (0x00000001) 348 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED 6:6 349 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_FALSE (0x00000000) 350 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_TRUE (0x00000001) 351 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED 7:7 352 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_FALSE (0x00000000) 353 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_TRUE (0x00000001) 354 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM 8:8 355 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_FALSE (0x00000000) 356 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_TRUE (0x00000001) 357 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED 9:9 358 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_FALSE (0x00000000) 359 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_TRUE (0x00000001) 360 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 10:10 361 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_FALSE (0x00000000) 362 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_TRUE (0x00000001) 363 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED 11:11 364 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_FALSE (0x00000000) 365 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_TRUE (0x00000001) 366 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED 12:12 367 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_FALSE (0x00000000) 368 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_TRUE (0x00000001) 369 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED 13:13 370 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_FALSE (0x00000000) 371 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_TRUE (0x00000001) 372 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED 14:14 373 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_FALSE (0x00000000) 374 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_TRUE (0x00000001) 375 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED 15:15 376 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_FALSE (0x00000000) 377 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_TRUE (0x00000001) 378 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED 16:16 379 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_FALSE (0x00000000) 380 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_TRUE (0x00000001) 381 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 17:17 382 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_FALSE (0x00000000) 383 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_TRUE (0x00000001) 384 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED 18:18 385 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_FALSE (0x00000000) 386 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_TRUE (0x00000001) 387 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED 19:19 388 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_FALSE (0x00000000) 389 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_TRUE (0x00000001) 390 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED 20:20 391 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE (0x00000000) 392 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE (0x00000001) 393 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS 21:21 394 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_FALSE (0x00000000) 395 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_TRUE (0x00000001) 396 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22 397 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_FALSE (0x00000000) 398 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_TRUE (0x00000001) 399 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23 400 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_FALSE (0x00000000) 401 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_TRUE (0x00000001) 402 403 /* UVM supported features */ 404 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 405 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_FALSE (0x00000000) 406 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_TRUE (0x00000001) 407 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED 1:1 408 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_FALSE (0x00000000) 409 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_TRUE (0x00000001) 410 411 #define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U) 412 413 typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS { 414 NvU32 frameRateLimiter; 415 NvU32 swVSyncEnabled; 416 NvU32 cudaEnabled; 417 NvU32 pluginPteBlitEnabled; 418 NvU32 disableWddm1xPreemption; 419 NvU32 debugBufferSize; 420 NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8); 421 NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); 422 NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8); 423 NvU32 linuxInterruptOptimization; 424 NvU32 vgpuDeviceCapsBits; 425 NvU32 maxPixels; 426 NvU32 uvmEnabledFeatures; 427 NvBool enableKmdSysmemScratch; 428 } NVA080_CTRL_VGPU_GET_CONFIG_PARAMS; 429 430 431 432 /* _ctrla080_h_ */ 433