1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2012-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 25 #pragma once 26 27 #include <nvtypes.h> 28 29 // 30 // This file was generated with FINN, an NVIDIA coding tool. 31 // Source file: ctrl/ctrla080.finn 32 // 33 34 35 36 37 38 /* 39 * NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES 40 * 41 * This command sets primary surface properties on a virtual GPU in displayless mode 42 * 43 * Parameters: 44 * headIndex 45 * This parameter specifies the head for which surface properties are 46 * 47 * isPrimary 48 * This parameter indicates whether surface information is for primary surface. set to 1 if its a primary surface. 49 * 50 * hMemory 51 * Memory handle containing the surface (only for RM-managed heaps) 52 * 53 * offset 54 * Offset from base of allocation (hMemory for RM-managed heaps; physical 55 * memory otherwise) 56 * 57 * surfaceType 58 * This parameter indicates whether surface type is block linear or pitch 59 * 60 * surfaceBlockHeight 61 * This parameter indicates block height for the surface 62 * 63 * surfacePitch 64 * This parameter indicates pitch value for the surface 65 * 66 * surfaceFormat 67 * This parameter indicates surface format (A8R8G8B8/A1R5G5B5) 68 * 69 * surfaceWidth 70 * This parameter indicates width value for the surface 71 * 72 * surfaceHeight 73 * This parameter indicates height value for the surface 74 * 75 * surfaceSize 76 * This parameter indicates size of the surface 77 * 78 * surfaceKind 79 * This parameter indicates surface kind (only for externally-managed 80 * heaps) 81 * 82 * rectX [unused] 83 * This parameter indicates X coordinate of the region to be displayed 84 * 85 * rectY [unused] 86 * This parameter indicates Y coordinate of the region to be displayed 87 * 88 * rectWidth 89 * This parameter indicates width of the region to be displayed 90 * 91 * rectHeight 92 * This parameter indicates height of the region to be displayed 93 * 94 * hHwResDevice 95 * This parameter indicates the device associated with surface 96 * 97 * hHwResHandle 98 * This parameter indicates the handle to hardware resources allocated to surface 99 * 100 * effectiveFbPageSize 101 * This parameter indicates the actual page size used by KMD for the surface 102 * 103 * Possible status values returned are: 104 * NV_OK 105 * NV_ERR_INVALID_ARGUMENT 106 * NVOS_STATUS_NOT_SUPPORTED 107 */ 108 109 #define NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES (0xa0800103) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID" */ 110 111 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID (0x3U) 112 113 typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES { 114 NvU32 headIndex; 115 NvU32 isPrimary; 116 NvU32 hMemory; 117 NvU32 offset; 118 NvU32 surfaceType; 119 NvU32 surfaceBlockHeight; 120 NvU32 surfacePitch; 121 NvU32 surfaceFormat; 122 NvU32 surfaceWidth; 123 NvU32 surfaceHeight; 124 NvU32 rectX; 125 NvU32 rectY; 126 NvU32 rectWidth; 127 NvU32 rectHeight; 128 NvU32 surfaceSize; 129 NvU32 surfaceKind; 130 NvU32 hHwResDevice; 131 NvU32 hHwResHandle; 132 NvU32 effectiveFbPageSize; 133 } NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES; 134 135 /* valid surfaceType values */ 136 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT 0:0 137 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 138 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_PITCH 0x00000001 139 /* valid surfaceBlockHeight values */ 140 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_ONE_GOB 0x00000000 141 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_TWO_GOBS 0x00000001 142 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 143 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 144 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 145 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 146 /* valid surfaceFormat values */ 147 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_I8 0x0000001E 148 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_RF16_GF16_BF16_AF16 0x000000CA 149 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8R8G8B8 0x000000CF 150 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A2B10G10R10 0x000000D1 151 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_X2BL10GL10RL10_XRBIAS 0x00000022 152 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8B8G8R8 0x000000D5 153 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R5G6B5 0x000000E8 154 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A1R5G5B5 0x000000E9 155 #define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R16_G16_B16_A16 0x000000C6 156 157 /* 158 * NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS 159 * 160 * This command clears surface information related to head. 161 * It should be called while shutting down head in displayless mode on virtual GPU 162 * 163 * Parameters: 164 * headIndex 165 * This parameter specifies the head for which cleanup is requested. 166 * 167 * blankingEnabled 168 * This parameter must be set to 1 to enable blanking. 169 * 170 * Possible status values returned are: 171 * NV_OK 172 * NV_ERR_INVALID_ARGUMENT 173 * NVOS_STATUS_NOT_SUPPORTED 174 */ 175 #define NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE (0xa0800104) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID" */ 176 177 #define NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID (0x4U) 178 179 typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS { 180 NvU32 headIndex; 181 NvU32 blankingEnabled; 182 } NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS; 183 184 /* 185 * NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS 186 * 187 * This command returns CPU virtual address of the mouse pointer mapping for VGPU. 188 * The address returned by this command is the pointer address for the head 0. 189 * VGPU_POINTER_OFFSET_HEAD(i) should be added to this address to get the address of head i. 190 * VGPU mouse pointer is a 32 bit value, X location of the mouse pointer is stored in 191 * 15:0 and Y location is stored in 31:16 bits. X location value of the mouse pointer is 192 * negative if bit 15 is set. Similarly, Y location value is negative if bit 31 is set. 193 * 194 * Parameters: 195 * pPointerAddress 196 * CPU virtual address of the mouse pointer mapping for VGPU 197 * 198 * Possible status values returned are: 199 * NV_OK 200 * NV_ERR_INVALID_ARGUMENT 201 * NVOS_STATUS_NOT_SUPPORTED 202 */ 203 204 #define NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS (0xa0800105) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID" */ 205 206 #define NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID (0x5U) 207 208 typedef struct NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS { 209 NV_DECLARE_ALIGNED(NvP64 pPointerAddress, 8); 210 } NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS; 211 212 #define VGPU_POINTER_OFFSET_HEAD0_VALUE 0x00000000 213 #define VGPU_POINTER_OFFSET_HEAD0_FLAG 0x00000004 214 #define VGPU_POINTER_OFFSET_HEAD1_VALUE 0x00000008 215 #define VGPU_POINTER_OFFSET_HEAD1_FLAG 0x0000000c 216 #define VGPU_POINTER_OFFSET_HEAD2_VALUE 0x00000010 217 #define VGPU_POINTER_OFFSET_HEAD2_FLAG 0x00000014 218 #define VGPU_POINTER_OFFSET_HEAD3_VALUE 0x00000018 219 #define VGPU_POINTER_OFFSET_HEAD3_FLAG 0x0000001c 220 #define VGPU_POINTER_OFFSET_HEAD_VALUE(i) (i * 8) 221 #define VGPU_POINTER_OFFSET_HEAD_FLAG(i) (4 + i * 8) 222 #define VGPU_POINTER_OFFSET_HEAD_SIZE 4 223 224 /* 225 * NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE 226 * 227 * This command returns mappable video size to be used by each VM. 228 * 229 * Parameters: 230 * mappableVideoSize 231 * This parameter returns mappable video size in bytes. 232 * 233 * Possible status values returned are: 234 * NV_OK 235 * NV_ERR_INVALID_ARGUMENT 236 * NVOS_STATUS_NOT_SUPPORTED 237 */ 238 239 240 #define NV_VGPU_POINTER_X_LOCATION 15:0 241 #define NV_VGPU_POINTER_Y_LOCATION 31:16 242 #define NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE (0xa0800201) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID" */ 243 244 #define NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID (0x1U) 245 246 typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS { 247 NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); 248 } NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS; 249 250 /* 251 * NVA080_CTRL_CMD_MAP_SEMA_MEM 252 * 253 * This command returns GPU VA for the channel with 'hCtxDma' handle 254 * where per VM semaphore memory is mapped which is used for tracking 255 * non-stall interrupt of each VM. 256 * 257 * Parameters: 258 * hClient [in] 259 * This parameter specifies the handle to the NV01_ROOT object of 260 * the client. This object should be the parent of the object 261 * specified by hDevice. 262 * hDevice [in] 263 * This parameter specifies the handle of the NV01_DEVICE object 264 * representing the desired GPU. 265 * hMemory [in] 266 * This parameter specifies the handle for semaphore memory 267 * hCtxDma [in] 268 * This parameter specifies the handle of the NV01_CONTEXT_DMA 269 * object through which bufferId is written in semaphore memory for 270 * non-stall interrupt tracking. 271 * semaAddress [out] 272 * This parameter returns the GPU virtual address of the semaphore 273 * memory. 274 * 275 * Possible status values returned are: 276 * NV_OK 277 * NVOS_STATUS_INVALID_DATA 278 * NV_ERR_INVALID_CLIENT 279 * NV_ERR_INVALID_OBJECT_HANDLE 280 * 281 */ 282 283 #define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID" */ 284 285 typedef struct NVA080_CTRL_SEMA_MEM_PARAMS { 286 NvHandle hClient; 287 NvHandle hDevice; 288 NvHandle hMemory; 289 NvHandle hCtxDma; 290 NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); 291 } NVA080_CTRL_SEMA_MEM_PARAMS; 292 293 #define NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x2U) 294 295 typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_MAP_SEMA_MEM_PARAMS; 296 297 /* 298 * NVA080_CTRL_CMD_UNMAP_SEMA_MEM 299 * 300 * This command unmaps per VM semaphore memory from GPU VA space, mapped by 301 * NVA080_CTRL_CMD_MAP_SEMA_MEM command. 302 * 303 * Parameters: 304 * Same as NVA080_CTRL_MAP_SEMA_MEM_PARAMS, except semaAddress is input 305 * parameter here. 306 * 307 * Possible status values returned are: 308 * NV_OK 309 * NVOS_STATUS_INVALID_DATA 310 * NV_ERR_INVALID_CLIENT 311 * NV_ERR_INVALID_OBJECT_HANDLE 312 * 313 */ 314 315 #define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID" */ 316 317 #define NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x3U) 318 319 typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS; 320 321 /*! 322 * NVA080_CTRL_CMD_SET_FB_USAGE 323 * 324 * This command sets the current framebuffer usage value in the plugin. 325 * 326 * Parameters: 327 * fbUsed [in] 328 * This parameter holds the current FB usage value in bytes. 329 * 330 * Possible status values returned are: 331 * NV_OK 332 */ 333 #define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ 334 335 #define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) 336 337 typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { 338 NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); 339 } NVA080_CTRL_SET_FB_USAGE_PARAMS; 340 341 /*! 342 * NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM 343 * 344 * This command allocates the per engine vGPU semaphore memory and map it to 345 * GPU/CPU VA. 346 * 347 * Calculate engine's semaphore GPU VA = 348 * semaAddress + semaStride * NV2080_ENGINE_TYPE_ of that engine 349 * 350 * Parameters: 351 * hClient [in] 352 * This parameter specifies the handle to the NV01_ROOT object of 353 * the client. This object should be the parent of the object 354 * specified by hDevice. 355 * hDevice [in] 356 * This parameter specifies the handle of the NV01_DEVICE object 357 * representing the desired GPU. 358 * hMemory [in] 359 * This parameter specifies the handle for semaphore memory 360 * hCtxDma [in] 361 * This parameter specifies the handle of the NV01_CONTEXT_DMA 362 * object through which bufferId is written in semaphore memory for 363 * non-stall interrupt tracking. 364 * semaAddress [out] 365 * This parameter returns the GPU VA of the per engine semaphore memory. 366 * semaStride [out] 367 * This parameter specifies the stride of each engine's semaphore offset within this memory. 368 * 369 * Possible status values returned are: 370 * NV_OK 371 */ 372 373 #define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ 374 375 typedef struct NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS { 376 NvU32 hClient; 377 NvU32 hDevice; 378 NvHandle hMemory; 379 NvU32 hCtxDma; 380 NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); 381 NvU32 semaStride; 382 } NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS; 383 384 #define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) 385 386 typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; 387 388 /*! 389 * NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM 390 * 391 * This command unmaps and frees the per engine vGPU semaphore memory. 392 * 393 * Parameters: 394 * Same as NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS, except semaAddress is input 395 * parameter here. 396 * 397 * Possible status values returned are: 398 * NV_OK 399 */ 400 401 #define NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM (0xa0800206) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ 402 403 #define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U) 404 405 typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; 406 407 /* 408 * NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP 409 * 410 * This command provides the guest RM with PFN information, so that it can 411 * update the shared memory with the plugin, which keeps track of guest sysmem. 412 * 413 * Parameters: 414 * destPhysAddr 415 * Start address of the segment to be tracked 416 * 417 * pageCount 418 * Number of pages in the segment 419 * 420 * pageSize 421 * Size of pages in the segment 422 * 423 * isValid: 424 * TRUE : Set bits corresponding to PFNs in bitmap and increase segment refcount 425 * FALSE: Decrease segment refcount and then unset bits if refcount is 0 426 * 427 * pfnList 428 * List of PFNs in the segment 429 * 430 * flags 431 * FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 432 * Flag set to TRUE if pteMem is CPU VA pointing to BAR1 and 433 * dstPhysAddr contains BAR1 offset. 434 * 435 * Possible status values returned are: 436 * NVOS_STATUS_SUCCESS 437 */ 438 439 #define NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP (0xa0800207) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID" */ 440 441 #define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 0:0 442 #define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_FALSE (0x00000000) 443 #define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_TRUE (0x00000001) 444 445 #define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID (0x7U) 446 447 typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { 448 NV_DECLARE_ALIGNED(NvU64 destPhysAddr, 8); 449 NvU32 pageCount; 450 NvU32 pageSize; 451 NvBool isValid; 452 NV_DECLARE_ALIGNED(NvP64 pfnList, 8); 453 NvU32 flags; 454 } NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS; 455 456 /* 457 * Blit semaphore offset location 458 */ 459 #define VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET 0x200 460 #define VGPU_BLIT_RESTORE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET) 461 462 #define VGPU_BLIT_SEMA_MEM_OFFSET 0x400 463 #define VGPU_BLIT_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_SEMA_MEM_OFFSET) 464 465 #define VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET 0x800 466 #define VGPU_FBMEMCE_PUSH_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET) 467 468 #define VGPU_FBMEMCE_SEMA_MEM_OFFSET 0x810 469 #define VGPU_FBMEMCE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_SEMA_MEM_OFFSET) 470 471 #define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET 0x820 472 #define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET) 473 474 #define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET 0x824 475 476 /* 477 * NVA080_CTRL_CMD_VGPU_GET_CONFIG 478 * 479 * This command returns VGPU configuration information for the associated GPU. 480 * 481 * Parameters: 482 * frameRateLimiter 483 * This parameter returns value of frame rate limiter 484 * swVSyncEnabled 485 * This parameter returns value of SW VSync flag (zero for disabled, 486 * non-zero for enabled) 487 * cudaEnabled 488 * This parameter returns whether CUDA is enabled or not 489 * pluginPteBlitEnabled 490 * This parameter returns whether to use plugin pte blit path 491 * disableWddm1xPreemption 492 * This parameter returns whether to disable WDDM 1.x Preemption or not 493 * debugBuffer 494 * This parameter specifies a pointer to memory which is filled with 495 * debugging information. 496 * debugBufferSize 497 * This parameter specifies the size of the debugging buffer in bytes. 498 * guestFbOffset 499 * This parameter returns FB offset start address for VM 500 * mappableCpuHostAperture 501 * This parameter returns mappable CPU host aperture size 502 * linuxInterruptOptimization 503 * This parameter returns whether stall interrupts are enabled/disabled for 504 * Linux VM 505 * vgpuDeviceCapsBits 506 * This parameter specifies CAP bits to ON/OFF features from guest OS. 507 * CAPS_SW_VSYNC_ENABLED 508 * cap bit to indicate if SW VSync flag enabled/disabled. 509 * Please note, currently, guest doesn't honour this bit. 510 * CAPS_CUDA_ENABLED 511 * cap bit to indicate if CUDA enabled/disabled. 512 * Please note, currently, guest doesn't honour this bit. 513 * CAPS_WDDM1_PREEMPTION_DISABLED 514 * cap bit to indicate if WDDM 1.x Preemption disabled/enabled. 515 * Please note, currently, guest doesn't honour this bit. 516 * CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 517 * cap bit to indicate if stall interrupts are enabled/disabled for 518 * Linux VM. Please note, currently, guest doesn't honour this bit. 519 * CAPS_PTE_BLIT_ENABLED 520 * cap bit to indicate if PTE blit is enabled/disabled. 521 * Please note, currently, guest doesn't honour this bit. 522 * CAPS_PDE_BLIT_ENABLED 523 * cap bit to indicate if PDE blit is enabled/disabled. 524 * CAPS_GET_PDE_INFO_CTRL_DISABLED 525 * cap bit to indicate if GET_PDE_INFO RM Ctrl is disabled/enabled. 526 * CAPS_GUEST_FB_OFFSET_DISABLED 527 * cap bit to indicate if FB Offset is exposed to guest or not. 528 * If set, FB Offset is not exposed to guest. 529 * CAPS_CILP_DISABLED_ON_WDDM 530 * cap bit to indicate if CILP on WDDM disabled/enabled. 531 * CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 532 * cap bit to indicate if guest needs to use doorbell token value updated 533 * dynamically by host after migration. 534 * CAPS_SRIOV_ENABLED 535 * Cap bit to indicate if the vGPU is running in SRIOV mode or not. 536 * CAPS_GUEST_MANAGED_VA_ENABLED 537 * Cap bit to indicate if the Guest is managing the VA. 538 * CAPS_VGPU_1TO1_COMPTAG_ENABLED 539 * Cap bit to indicate if the 1to1 comptag enabled. This is always TRUE 540 * when SR-IOV is enabled. 541 * CAPS_MBP_ENABLED 542 * Cap bit to indicate if the Mid Buffer Preemption enabled. 543 * CAPS_ASYNC_MBP_ENABLED 544 * Cap bit to indicate if the asynchronus Mid buffer Preemption enabled. 545 * CAPS_TLB_INVALIDATE_ENABLED 546 * Cap bit to indicate if the vGPU supports TLB Invalidation operation or not. 547 * CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 548 * Cap bit to indicate if the vGPU supports PTE blit for page table updates using BAR1 549 * CAPS_SRIOV_HEAVY_ENABLED 550 * Cap bit to indicate if vGPU is running in SRIOV Heavy mode or not. 551 * When set true SRIOV Heavy is enabled. 552 * When set false and CAPS_SRIOV_ENABLED is set true, SRIOV Standard is enabled. 553 * CAPS_TIMESLICE_OVERRIDE_ENABLED 554 * Cap bit to indicate whether TSG timeslice override is enabled or not. 555 * When set true, TSG timeslice override is enabled. 556 * When false, TSG timeslice override is disabled. 557 * CAPS_GUEST_HIBERNATION_ENABLED 558 * Cap bit to indicate whether Guest OS Hibernation is supported or not. 559 * uvmEnabledFeatures 560 * This parameter returns mask of UVM enabled features on vGPU. It comprises of 561 * UVM managed APIs and replayable faults that are enabled or disabled based on 562 * vGPU version. 563 * enableKmdSysmemScratch 564 * This parameter is used to overwrite guest regkey PreferSystemMemoryScratch. 565 * Setting vgpu parameter "vgpu_enable_kmd_sysmem_scratch" in plugin will 566 * set this parameter. If the parameter is set, guest moves shader buffer 567 * allocation from FB to sysmem. 568 * 569 * Possible status values returned are: 570 * NV_OK 571 * NV_ERR_INVALID_PARAM_STRUCT 572 * NV_ERR_INVALID_ARGUMENT 573 */ 574 #define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET) 575 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */ 576 577 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0 578 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_FALSE (0x00000000) 579 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_TRUE (0x00000001) 580 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED 1:1 581 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_FALSE (0x00000000) 582 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_TRUE (0x00000001) 583 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED 2:2 584 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_FALSE (0x00000000) 585 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_TRUE (0x00000001) 586 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 3:3 587 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_FALSE (0x00000000) 588 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_TRUE (0x00000001) 589 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED 4:4 590 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_FALSE (0x00000000) 591 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_TRUE (0x00000001) 592 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED 5:5 593 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_FALSE (0x00000000) 594 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_TRUE (0x00000001) 595 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED 6:6 596 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_FALSE (0x00000000) 597 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_TRUE (0x00000001) 598 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED 7:7 599 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_FALSE (0x00000000) 600 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_TRUE (0x00000001) 601 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM 8:8 602 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_FALSE (0x00000000) 603 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_TRUE (0x00000001) 604 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED 9:9 605 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_FALSE (0x00000000) 606 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_TRUE (0x00000001) 607 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 10:10 608 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_FALSE (0x00000000) 609 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_TRUE (0x00000001) 610 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED 11:11 611 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_FALSE (0x00000000) 612 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_TRUE (0x00000001) 613 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED 12:12 614 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_FALSE (0x00000000) 615 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_TRUE (0x00000001) 616 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED 13:13 617 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_FALSE (0x00000000) 618 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_TRUE (0x00000001) 619 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED 14:14 620 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_FALSE (0x00000000) 621 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_TRUE (0x00000001) 622 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED 15:15 623 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_FALSE (0x00000000) 624 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_TRUE (0x00000001) 625 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED 16:16 626 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_FALSE (0x00000000) 627 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_TRUE (0x00000001) 628 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 17:17 629 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_FALSE (0x00000000) 630 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_TRUE (0x00000001) 631 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED 18:18 632 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_FALSE (0x00000000) 633 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_TRUE (0x00000001) 634 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED 19:19 635 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_FALSE (0x00000000) 636 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_TRUE (0x00000001) 637 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED 20:20 638 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE (0x00000000) 639 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE (0x00000001) 640 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS 21:21 641 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_FALSE (0x00000000) 642 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_TRUE (0x00000001) 643 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22 644 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_FALSE (0x00000000) 645 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_TRUE (0x00000001) 646 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23 647 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_FALSE (0x00000000) 648 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_TRUE (0x00000001) 649 650 /* UVM supported features */ 651 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 652 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_FALSE (0x00000000) 653 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_TRUE (0x00000001) 654 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED 1:1 655 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_FALSE (0x00000000) 656 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_TRUE (0x00000001) 657 658 #define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U) 659 660 typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS { 661 NvU32 frameRateLimiter; 662 NvU32 swVSyncEnabled; 663 NvU32 cudaEnabled; 664 NvU32 pluginPteBlitEnabled; 665 NvU32 disableWddm1xPreemption; 666 NvU32 debugBufferSize; 667 NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8); 668 NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); 669 NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8); 670 NvU32 linuxInterruptOptimization; 671 NvU32 vgpuDeviceCapsBits; 672 NvU32 maxPixels; 673 NvU32 uvmEnabledFeatures; 674 NvBool enableKmdSysmemScratch; 675 } NVA080_CTRL_VGPU_GET_CONFIG_PARAMS; 676 677 678 679 /* _ctrla080_h_ */ 680