1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrlb0cc/ctrlb0ccpower.finn 31 // 32 33 #include "ctrl/ctrlb0cc/ctrlb0ccbase.h" 34 35 /* 36 * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES 37 * 38 * This command attempts to enable or disable various clock-gating features of 39 * the GPU on behalf of the profiler. If this command is unable to set the 40 * clock-gating feature state of any of the requested features, this command 41 * will fail and none of the requested features will be modified. If this 42 * command fails because one or more clock-gating feature requests were 43 * rejected, it will return NV_ERR_STATE_IN_USE in the globalStatus 44 * parameter and the fields in the statusMask parameter for the features for 45 * which the requests were rejected will have the value 46 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED. 47 * If a given feature is not supported on the GPU, the field for that clock- 48 * gating feature will have the value 49 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED in the 50 * statusMask parameter, but this condition by itself will not cause the 51 * command to fail. Even if this command fails, the field for clock-gating 52 * features which would have successfully changed will have the value 53 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_FULFILLED in the statusMask 54 * parameter. 55 * 56 * Each of the clock-gating features is reference-counted individually, so 57 * that multiple MAXWELL_PROFILER objects may request and rely on the same 58 * settings for the features simultaneously. Each clock-gating feature is 59 * locked to the requested state until the MAXWELL_PROFILER object is freed or 60 * the NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES command is called for that 61 * feature. 62 * 63 * Currently, only MAXWELL_PROFILER requests for power features using this 64 * command are reference counted. Changes to the power feature settings made 65 * either by other control commands or the RM itself may interfere with the 66 * settings requested by MAXWELL_PROFILER instances. 67 * 68 * This command will always return NV_OK when given valid 69 * parameters. If there is any other failure that prevents the clock-gating 70 * features from being set appropriately, the globalStatus parameter will 71 * indicate this and the statusMask parameter will indicate which clock-gating 72 * feature requests failed and why. 73 * 74 * controlMask 75 * This parameter indicates which clock-gating features the request should 76 * apply to. This parameter has the following fields: 77 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG 78 * The value of this field indicates whether this request should apply 79 * to engine-level clock-gating of the GR engine. Valid values for 80 * this field are: 81 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE 82 * This value indicates that the GR engine-level clock-gating 83 * should be ignored. This will not affect the reference count for 84 * this feature. 85 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE 86 * This value indicates that the GR engine-level clock-gating 87 * should be disabled. 88 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE 89 * This value indicates that the GR engine-level clock-gating 90 * should be enabled. 91 * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG 92 * The value of this field indicates whether this request should apply 93 * to block-level clock-gating. Valid values for this field are: 94 * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE 95 * This value indicates that block-level clock-gating should be 96 * ignored. This will not affect the reference count for this 97 * feature. 98 * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE 99 * This value indicates that block-level clock-gating should be 100 * disabled. 101 * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE 102 * This value indicates that block-level clock-gating should be 103 * enabled. 104 * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG 105 * The value of this field indicates whether this request should apply 106 * to second-level clock-gating. Valid values for this field are: 107 * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE 108 * This value indicates that second-level clock-gating should be 109 * ignored. This will not affect the reference count for this 110 * feature. 111 * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE 112 * This value indicates that second-level clock-gating should be 113 * disabled. 114 * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE 115 * This value indicates that second-level clock-gating should be 116 * enabled. 117 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG 118 * The value of this field indicates whether this request should apply 119 * to GR engine-level power-gating. Valid values for this field are: 120 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE 121 * This value indicates that engine-level power-gating should be 122 * ignored. This will not affect the reference count for this 123 * feature. 124 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE 125 * This value indicates that engine-level power-gating should be 126 * disabled. 127 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE 128 * This value indicates that engine-level power-gating should be 129 * enabled. 130 * Note that this field is only temporary to allow reference counting 131 * restricted to MAXWELL_PROFILER instances, until the time when the 132 * existing controls for this power feature can be updated to support 133 * reference counting across all clients and the RM. 134 * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN 135 * The value of this field indicates whether this request should apply 136 * to SM idle slowdown. Valid values for this field are: 137 * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE 138 * This value indicates that SM idle slowdown should be ignored. 139 * This will not affect the reference count for this feature. 140 * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE 141 * This value indicates that SM idle slowdown should be disabled. 142 * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE 143 * This value indicates that SM idle slowdown should be enabled. 144 * Note that this field is only temporary to allow reference counting 145 * restricted to MAXWELL_PROFILER instances, until the time when the 146 * existing controls for this power feature can be updated to support 147 * reference counting across all clients and the RM. 148 * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT 149 * The value of this field indicates whether this request should apply 150 * to VAT. Valid values for this field are: 151 * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE 152 * This value indicates that VAT should be ignored. 153 * This will not affect the reference count for this feature. 154 * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE 155 * This value indicates that VAT should be disabled. 156 * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE 157 * This value indicates that VAT should be enabled. 158 * Note that this field is only temporary to allow reference counting 159 * restricted to MAXWELL_PROFILER instances, until the time when the 160 * existing controls for this power feature can be updated to support 161 * reference counting across all clients and the RM. 162 * globalStatus 163 * This parameter returns the overall status of the requests for all 164 * clock-gating controls. If the value of this parameter is not 165 * NV_OK, none of the clock-gating controls will be set as 166 * requested. Possible values for this parameter are: 167 * NV_OK 168 * This value indicates that all of the clock-gating control requests 169 * were either fulfilled or not supported on the hardware. 170 * NV_ERR_INVALID_REQUEST 171 * This value indicates that at least one of the clock-gating control 172 * requests were invalid given the MAXWELL_PROFILER instance's 173 * outstanding requests. 174 * NV_ERR_STATE_IN_USE 175 * This value indicates that at least one of the clock-gating controls 176 * has already been locked to a conflicting state by another 177 * MAXWELL_PROFILER instance or the RM itself. 178 * statusMask 179 * This parameter returns the status of the request to set each clock- 180 * gating control specified by the controlMask parameter. The fields are 181 * identical to those of the controlMask parameter. For each field for 182 * which the corresponding field in the controlMask parameter has the 183 * value NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE, the value is 184 * undefined. For each field for which the corresponding field in the 185 * controlMask parameter has the value 186 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST, the value will be 187 * one of the following: 188 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FULFILLED 189 * This value indicates that the clock-gating feature corresponding to 190 * the field in question was enabled or disabled according to the 191 * controlMask parameter, and the reference count for the feature was 192 * incremented accordingly. 193 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_REJECTED 194 * This value indicates that the clock-gating feature corresponding to 195 * the field in question was not set to the expected state according 196 * to the controlMask parameter because another conflicting request is 197 * currently outstanding for the clock-gating feature. 198 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_FAILED 199 * This value indicates that the clock-gating feature corresponding to 200 * the field in question was not set to the expected state according 201 * to the controlMask parameter because the attempt to do so failed 202 * with an error other than a conflicting request. 203 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_REQUEST_NOT_SUPPORTED 204 * This value indicates that the clock-gating feature corresponding to 205 * the field in question is not supported on this GPU. 206 * 207 * Possible status values returned are: 208 * NV_OK 209 * NV_ERR_INVALID_ARGUMENT 210 */ 211 #define NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES (0xb0cc0301) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID" */ 212 213 #define NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID (0x1U) 214 215 typedef struct NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS { 216 NvU32 globalStatus; 217 NvU32 controlMask; 218 NvU32 statusMask; 219 } NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS; 220 221 /* valid fields for the controlMask and statusMask parameters */ 222 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG 1:0 223 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG 3:2 224 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG 5:4 225 226 /* 227 * The following are temporary fields for the controlMask and statusMask 228 * parameters. They are required to reference count their respective features 229 * until the existing RM controls can be safely updated, and the definitions 230 * for these features will be removed soon after that. 231 */ 232 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG 7:6 233 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN 9:8 234 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT 11:10 235 236 /* valid values for fields in the controlMask parameter */ 237 #define NVB0CC_CTRL_POWER_FEATURE_IGNORE (0x00000000) 238 #define NVB0CC_CTRL_POWER_FEATURE_DISABLE (0x00000001) 239 #define NVB0CC_CTRL_POWER_FEATURE_ENABLE (0x00000002) 240 241 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE 242 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE 243 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE 244 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE 245 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE 246 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE 247 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE 248 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE 249 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE 250 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE 251 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE 252 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE 253 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE 254 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE 255 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE 256 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE NVB0CC_CTRL_POWER_FEATURE_IGNORE 257 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE NVB0CC_CTRL_POWER_FEATURE_DISABLE 258 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE NVB0CC_CTRL_POWER_FEATURE_ENABLE 259 /* possible values for fields in the statusMask parameter */ 260 #define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED (0x00000000) 261 #define NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED (0x00000001) 262 #define NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED (0x00000002) 263 #define NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED (0x00000003) 264 265 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED 266 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED 267 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED 268 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED 269 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED 270 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED 271 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED 272 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED 273 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED 274 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED 275 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED 276 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED 277 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED 278 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED 279 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED 280 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED 281 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED 282 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED 283 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED 284 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED 285 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED 286 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED 287 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED 288 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED 289 290 /* utility masks for the controlMask parameter for all controls */ 291 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL \ 292 DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG) | \ 293 DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG) | \ 294 DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG) | \ 295 DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG) | \ 296 DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN) | \ 297 DRF_SHIFTMASK(NVB0CC_CTRL_POWER_FEATURE_MASK_VAT) 298 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_IGNORE \ 299 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _IGNORE) | \ 300 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _IGNORE) | \ 301 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _IGNORE) | \ 302 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _IGNORE) | \ 303 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _IGNORE) | \ 304 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _IGNORE) 305 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_DISABLE \ 306 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _DISABLE) | \ 307 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _DISABLE) | \ 308 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _DISABLE) | \ 309 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _DISABLE) | \ 310 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _DISABLE)| \ 311 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _DISABLE) 312 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_ENABLE \ 313 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _ENABLE) | \ 314 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _ENABLE) | \ 315 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _ENABLE) | \ 316 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _ENABLE) | \ 317 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _ENABLE) | \ 318 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _ENABLE) 319 320 /* 321 * NVB0CC_CTRL_CMD_POWER_RELEASE_FEATUERS 322 * 323 * This command releases the MAXWELL_PROFILER's request for the given clock- 324 * gating features that was previously created by the 325 * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES command. If the MAXWELL_PROFILER 326 * object does not have an outstanding request to one or more of the given 327 * clock-gating features, those features will be ignored while the other 328 * feature requests will be released. 329 * 330 * After calling this command, the calling client may not rely on the current 331 * value of any of the released clock-gating features to remain, even if 332 * several identical requests for the given clock-gating features were made 333 * using NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES. The RM only reference- 334 * counts the settings requested by MAXWELL_PROFILER instances - it does not 335 * reference-count multiple identical requests made using the same 336 * MAXWELL_PROFILER instance. 337 * 338 * All outstanding requests made using this MAXWELL_PROFILER object are 339 * implicitly released when the MAXWELL_PROFILER is freed. 340 * 341 * controlMask 342 * This parameter indicates which clock-gating features the RM should 343 * release the MAXWELL_PROFILER's reference to. See 344 * NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES for valid fields. Valid 345 * values for each field are: 346 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE 347 * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE 348 * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE 349 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE 350 * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE 351 * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE 352 * This value indicates that the clock-gating feature associated with 353 * the field should not be released, even if the MAXWELL_PROFILER has an 354 * outstanding request for it. This will not affect the reference 355 * count for the feature. 356 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE 357 * NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE 358 * NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE 359 * NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE 360 * NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE 361 * NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE 362 * This value indicates that the MAXWELL_PROFILER's outstanding request 363 * for the clock-gating feature associated with the field should be 364 * released. This will decrement the reference count for the feature 365 * if the MAXWELL_PROFILER has an outstanding request for it. 366 * 367 * Possible status values returned are: 368 * NV_OK 369 * NV_ERR_INVALID_ARGUMENT 370 */ 371 #define NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES (0xb0cc0302) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_POWER_INTERFACE_ID << 8) | NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID" */ 372 373 #define NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID (0x2U) 374 375 typedef struct NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS { 376 NvU32 controlMask; 377 } NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS; 378 379 /* 380 * valid values for the controlMask parameter in addition to 381 * NVB0CC_CTRL_POWER_FEATURE_MASK_*_IGNORE 382 */ 383 #define NVB0CC_CTRL_POWER_FEATURE_RELEASE (0x00000003) 384 385 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE 386 #define NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE 387 #define NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE 388 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE 389 #define NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE 390 #define NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE NVB0CC_CTRL_POWER_FEATURE_RELEASE 391 392 393 /* _ctrlb0ccpower_h_ */ 394 395 /* utility mask for the controlMask parameter for all fields */ 396 #define NVB0CC_CTRL_POWER_FEATURE_MASK_ALL_RELEASE \ 397 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELCG, _RELEASE) | \ 398 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _BLCG, _RELEASE) | \ 399 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _SLCG, _RELEASE) | \ 400 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _ELPG, _RELEASE) | \ 401 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _IDLE_SLOWDOWN, _RELEASE)| \ 402 DRF_DEF(B0CC, _CTRL_POWER_FEATURE_MASK, _VAT, _RELEASE) 403