1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __NVKMS_TYPES_H__ 25 #define __NVKMS_TYPES_H__ 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #include "nvidia-modeset-os-interface.h" 32 33 #include "nvctassert.h" 34 #include "nv_list.h" 35 36 #include <ctrl/ctrl0073/ctrl0073specific.h> /* NV0073_CTRL_SPECIFIC_OR_PROTOCOL_* */ 37 #include <ctrl/ctrl0073/ctrl0073system.h> /* NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE */ 38 #include <ctrl/ctrl0000/ctrl0000gpu.h> /* NV0000_CTRL_GPU_MAX_ATTACHED_GPUS */ 39 #include <ctrl/ctrl0080/ctrl0080unix.h> /* NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO */ 40 #include <ctrl/ctrl2080/ctrl2080gpu.h> /* NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_* */ 41 #include <ctrl/ctrl30f1.h> /* NV30F1_CTRL_MAX_GPUS_PER_GSYNC */ 42 #include <ctrl/ctrl5070/ctrl5070system.h> /* NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE */ 43 #include <ctrl/ctrl0073/ctrl0073dfp.h> 44 45 #include "nvkms-api.h" 46 #include "nvkms-prealloc-types.h" 47 48 #include "nvos.h" 49 50 #include "nv_common_utils.h" 51 #include "nv_assert.h" 52 #include "unix_rm_handle.h" 53 54 #include "nvmisc.h" 55 56 #include "nvidia-push-init.h" 57 58 #include "timing/nvtiming.h" 59 #include "timing/nvt_dsc_pps.h" 60 #include "hdmipacket/nvhdmi_frlInterface.h" // HDMI_{SRC,SINK}_CAPS 61 62 #include <stddef.h> 63 64 #if defined(DEBUG) || defined(DEVELOP) 65 #define NVKMS_PROCFS_ENABLE 1 66 #else 67 #define NVKMS_PROCFS_ENABLE 0 68 #endif 69 70 #define NV_DMA_EVO_PUSH_BUFFER_SIZE (4 * 1024) 71 #define NV_DMA_EVO_PUSH_BUFFER_PAD_SIZE (4 * 12) 72 #define NV_DMA_EVO_NOTIFIER_SIZE 4096 73 74 #define NV_NUM_EVO_LUT_ENTRIES 1025 75 /* 76 * Size of the nvdisplay 3 LUT variable segment size header, in LUT entries 77 * (which are 8 bytes each). 78 */ 79 #define NV_LUT_VSS_HEADER_SIZE 4 80 81 #define NV_EVO_SUBDEV_STACK_SIZE 10 82 83 #define NV_DP_READ_EDID_RETRIES 18 84 #define NV_DP_REREAD_EDID_DELAY_USEC 500 /* in microseconds */ 85 86 #define NV_EVO_SURFACE_ALIGNMENT 0x1000 87 88 /* 89 * Prior to nvdisplay 4.0, the final address for all scanout surfaces must be 90 * 256B-aligned. 91 * 92 * For nvdisplay 4.0, the final address for all scanout surfaces must be 93 * 512B-aligned for GPU, and 1KB-aligned for Tegra. 94 * 95 * NVKMS already uses NV_EVO_SURFACE_ALIGNMENT to force 4KB-alignment for the 96 * base address of each scanout surface. As such, we're forcing 1KB-alignment 97 * for the corresponding ctxdma offsets in order to be compatible with all 98 * display architectures. 99 */ 100 #define NV_SURFACE_OFFSET_ALIGNMENT_SHIFT 10 101 102 #define NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH 6U /* 64 bytes (2^6) */ 103 #define NVKMS_BLOCK_LINEAR_GOB_WIDTH ((NvU32)1 << NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH) 104 105 #define NVKMS_BLOCK_LINEAR_LOG_GOB_HEIGHT 3U /* 8 rows (2^3) */ 106 #define NVKMS_BLOCK_LINEAR_GOB_HEIGHT ((NvU32)1 << NVKMS_BLOCK_LINEAR_LOG_GOB_HEIGHT) 107 108 #define NV_INVALID_OR 0xFFFFFFFF 109 110 #define NVKMS_RM_HEAP_ID 0xDCBA 111 112 #define NVKMS_MAX_WINDOWS_PER_DISP 32 113 114 #define NV_SYNCPT_GLOBAL_TABLE_LENGTH 1024 115 116 #define HEAD_MASK_QUERY(_mask, _head) (!!((_mask) & (1 << (_head)))) 117 #define HEAD_MASK_SET(_mask, _head) ((_mask) | (1 << (_head))) 118 #define HEAD_MASK_UNSET(_mask, _head) ((_mask) & ~(1 << (_head))) 119 120 #define NVKMS_COMPOSITION_FOR_MATCH_BITS(__colorKeySelect, __match) \ 121 for ((__match) = (((__colorKeySelect) == \ 122 NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE) ? 1 : 0); \ 123 (__match) <= 1; (__match)++) 124 125 typedef struct _NVEvoApiHandlesRec *NVEvoApiHandlesPtr; 126 typedef struct _NVEvoSubDeviceRec *NVSubDeviceEvoPtr; 127 typedef struct _NVEvoDevRec *NVDevEvoPtr; 128 typedef struct _NVDIFRStateEvoRec *NVDIFRStateEvoPtr; 129 typedef struct _NVDmaBufferEvoRec *NVDmaBufferEvoPtr; 130 typedef struct _NVEvoChannel *NVEvoChannelPtr; 131 typedef struct _NVEvoHeadControl *NVEvoHeadControlPtr; 132 typedef struct _NVEvoCapabilities *NVEvoCapabilitiesPtr; 133 typedef struct _NVEvoSubDevHeadStateRec *NVEvoSubDevHeadStatePtr; 134 typedef struct _NVEvoSubDevRec *NVEvoSubDevPtr; 135 typedef struct _NVEvoColorRec *NVEvoColorPtr; 136 typedef struct _NVHwModeViewPortEvo *NVHwModeViewPortEvoPtr; 137 typedef struct _NVHwModeTimingsEvo *NVHwModeTimingsEvoPtr; 138 typedef struct _NVConnectorEvoRec *NVConnectorEvoPtr; 139 typedef struct _NVVblankSyncObjectRec *NVVblankSyncObjectPtr; 140 typedef struct _NVDispHeadStateEvoRec *NVDispHeadStateEvoPtr; 141 typedef struct _NVDispEvoRec *NVDispEvoPtr; 142 typedef struct _NVParsedEdidEvoRec *NVParsedEdidEvoPtr; 143 typedef struct _NVVBlankCallbackRec *NVVBlankCallbackPtr; 144 typedef struct _NVRgLine1CallbackRec *NVRgLine1CallbackPtr; 145 typedef struct _NVDpyEvoRec *NVDpyEvoPtr; 146 typedef struct _NVLutSurfaceEvo *NVLutSurfaceEvoPtr; 147 typedef struct _NVFrameLockEvo *NVFrameLockEvoPtr; 148 typedef struct _NVEvoInfoString *NVEvoInfoStringPtr; 149 typedef struct _NVSurfaceEvoRec NVSurfaceEvoRec, *NVSurfaceEvoPtr; 150 typedef struct _NVDeferredRequestFifoRec *NVDeferredRequestFifoPtr; 151 typedef struct _NVSwapGroupRec *NVSwapGroupPtr; 152 typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; 153 154 /* 155 * _NVHs*EvoRec are defined in nvkms-headsurface-priv.h; they are intentionally 156 * opaque outside of the nvkms-headsurface code. 157 */ 158 typedef struct _NVHsDeviceEvoRec *NVHsDeviceEvoPtr; 159 typedef struct _NVHsChannelEvoRec *NVHsChannelEvoPtr; 160 typedef struct _NVHsSurfaceRec *NVHsSurfacePtr; 161 162 /* _nv_dplibXXX are defined in dp/nvdp-connector-event-sink.h */ 163 typedef struct _nv_dplibconnector NVDPLibConnectorRec, *NVDPLibConnectorPtr; 164 typedef struct _nv_dplibdevice NVDPLibDeviceRec, *NVDPLibDevicePtr; 165 typedef struct __nv_dplibmodesetstate NVDPLibModesetStateRec, *NVDPLibModesetStatePtr; 166 167 /* _nv_dplibtimer is defined in nvdp-timer.hpp */ 168 typedef struct _nv_dplibtimer NVDPLibTimerRec, *NVDPLibTimerPtr; 169 170 typedef struct _NVEvoApiHandlesRec { 171 void **pointers; /* Dynamically allocated array of pointers. */ 172 NvU32 numPointers; /* Number of elements in pointers array. */ 173 NvU32 defaultSize; 174 } NVEvoApiHandlesRec; 175 176 typedef struct _NVEvoDma 177 { 178 NvU32 memoryHandle; 179 NvU32 ctxHandle; 180 181 NvU64 limit; 182 183 /* Whether this is sysmem, or vidmem accessed through a BAR1 mapping. */ 184 NvBool isBar1Mapping; 185 186 void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; 187 } NVEvoDma, *NVEvoDmaPtr; 188 189 typedef struct _NVDmaBufferEvoRec 190 { 191 NVEvoDma dma; 192 193 NvU32 channel_handle; // handles 194 NvU32 num_channels; 195 void *control[NVKMS_MAX_SUBDEVICES]; 196 NvU32 *base; // Push buffer start pointer 197 NvU32 *buffer;// Push buffer current pointer 198 NvU32 *end; // Push buffer end pointer 199 NvU32 offset_max; // Push buffer max offset (in bytes) 200 NvU32 put_offset; // Push buffer last kicked off offset 201 NvU32 fifo_free_count; // fifo free space (in words) 202 NvU32 currentSubDevMask; 203 NVDevEvoPtr pDevEvo; 204 } NVDmaBufferEvoRec; 205 206 /* EVO capabilities */ 207 typedef struct { 208 NvBool flipLock; 209 NvBool stereo; 210 NvBool scanLock; 211 } NVEvoLockPinCaps; 212 #define NV_EVO_NUM_LOCK_PIN_CAPS 16 213 214 typedef struct { 215 NvBool supportsInterlaced; 216 NvBool supportsSemiPlanar; 217 NvBool supportsPlanar; 218 NvBool supportsHVFlip; 219 NvBool supportsDSI; 220 } NVEvoMiscCaps; 221 222 static inline NvU8 NVEvoScalerTapsToNum(NVEvoScalerTaps taps) 223 { 224 NvU8 numTaps = 1; 225 226 switch (taps) { 227 case NV_EVO_SCALER_8TAPS: 228 numTaps = 8; 229 break; 230 case NV_EVO_SCALER_5TAPS: 231 numTaps = 5; 232 break; 233 case NV_EVO_SCALER_3TAPS: 234 numTaps = 3; 235 break; 236 case NV_EVO_SCALER_2TAPS: 237 numTaps = 2; 238 break; 239 case NV_EVO_SCALER_1TAP: 240 numTaps = 1; 241 break; 242 } 243 244 return numTaps; 245 } 246 247 #define NV_EVO_SCALE_FACTOR_1X (1 << 10) 248 #define NV_EVO_SCALE_FACTOR_2X (2 << 10) 249 #define NV_EVO_SCALE_FACTOR_3X (3 << 10) 250 #define NV_EVO_SCALE_FACTOR_4X (4 << 10) 251 252 typedef struct { 253 NvU32 maxPixelsVTaps; 254 NvU16 maxVDownscaleFactor; /* Scaled by 1024 */ 255 NvU16 maxHDownscaleFactor; /* Scaled by 1024 */ 256 } NVEvoScalerTapsCaps; 257 258 typedef struct { 259 NvBool present; 260 NVEvoScalerTapsCaps taps[NV_EVO_SCALER_TAPS_MAX + 1]; 261 } NVEvoScalerCaps; 262 263 typedef struct { 264 NvBool usable; 265 NvBool supportsHDMIYUV420HW; 266 NVEvoScalerCaps scalerCaps; 267 } NVEvoHeadCaps; 268 #define NV_EVO_NUM_HEAD_CAPS 8 269 270 typedef struct { 271 NvBool dualTMDS; 272 NvU32 maxTMDSClkKHz; 273 } NVEvoSorCaps; 274 #define NV_EVO_NUM_SOR_CAPS 8 275 276 typedef struct { 277 } NVEvoPiorCaps; 278 #define NV_EVO_NUM_PIOR_CAPS 4 279 280 typedef struct { 281 NvBool usable; 282 NvBool csc0MatricesPresent; 283 NvBool cscLUTsPresent; 284 NvBool csc1MatricesPresent; 285 NvBool tmoPresent; 286 NVEvoScalerCaps scalerCaps; 287 } NVEvoWindowCaps; 288 #define NV_EVO_NUM_WINDOW_CAPS 32 289 290 typedef NvU64 NVEvoChannelMask; 291 292 #define NV_EVO_CHANNEL_MASK_CORE 0:0 293 #define NV_EVO_CHANNEL_MASK_CORE_ENABLE 1 294 #define NV_EVO_CHANNEL_MASK_CORE_DISABLE 0 295 #define NV_EVO_CHANNEL_MASK_WINDOW_FIELD 32:1 296 #define NV_EVO_CHANNEL_MASK_WINDOW(_n) (1+(_n)):(1+(_n)) 297 #define NV_EVO_CHANNEL_MASK_WINDOW__SIZE 32 298 #define NV_EVO_CHANNEL_MASK_WINDOW_ENABLE 1 299 #define NV_EVO_CHANNEL_MASK_WINDOW_DISABLE 0 300 #define NV_EVO_CHANNEL_MASK_CURSOR_FIELD 40:33 301 #define NV_EVO_CHANNEL_MASK_CURSOR(_n) (33+(_n)):(33+(_n)) 302 #define NV_EVO_CHANNEL_MASK_CURSOR__SIZE 8 303 #define NV_EVO_CHANNEL_MASK_CURSOR_ENABLE 1 304 #define NV_EVO_CHANNEL_MASK_CURSOR_DISABLE 0 305 #define NV_EVO_CHANNEL_MASK_BASE_FIELD 44:41 306 #define NV_EVO_CHANNEL_MASK_BASE(_n) (41+(_n)):(41+(_n)) 307 #define NV_EVO_CHANNEL_MASK_BASE__SIZE 4 308 #define NV_EVO_CHANNEL_MASK_BASE_ENABLE 1 309 #define NV_EVO_CHANNEL_MASK_BASE_DISABLE 0 310 #define NV_EVO_CHANNEL_MASK_OVERLAY_FIELD 48:45 311 #define NV_EVO_CHANNEL_MASK_OVERLAY(_n) (45+(_n)):(45+(_n)) 312 #define NV_EVO_CHANNEL_MASK_OVERLAY__SIZE 4 313 #define NV_EVO_CHANNEL_MASK_OVERLAY_ENABLE 1 314 #define NV_EVO_CHANNEL_MASK_OVERLAY_DISABLE 0 315 /* Window Immediate channels get only one bit. */ 316 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM 49:49 317 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM_ENABLE 1 318 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM_DISABLE 0 319 320 #define NV_EVO_CHANNEL_MASK_WINDOW_ALL \ 321 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_WINDOW_FIELD) 322 #define NV_EVO_CHANNEL_MASK_CURSOR_ALL \ 323 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_CURSOR_FIELD) 324 #define NV_EVO_CHANNEL_MASK_BASE_ALL \ 325 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_BASE_FIELD) 326 #define NV_EVO_CHANNEL_MASK_OVERLAY_ALL \ 327 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_OVERLAY_FIELD) 328 329 static inline NvU32 NV_EVO_CHANNEL_MASK_POPCOUNT(NvU64 mask) 330 { 331 // It's tempting to use __builtin_popcountll here, but that depends on 332 // intrinsics not available to nvkms in the kernel. 333 return nvPopCount64(mask); 334 } 335 336 static inline NvU32 NV_EVO_CHANNEL_MASK_BASE_HEAD_NUMBER(NvU64 mask) 337 { 338 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1); 339 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _BASE_FIELD, mask)); 340 } 341 static inline NvU32 NV_EVO_CHANNEL_MASK_OVERLAY_HEAD_NUMBER(NvU64 mask) 342 { 343 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1); 344 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _OVERLAY_FIELD, mask)); 345 } 346 static inline NvU32 NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(NvU64 mask) 347 { 348 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1); 349 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _WINDOW_FIELD, mask)); 350 } 351 352 /* EVO structures */ 353 354 typedef struct { 355 struct { 356 NVEvoChannelMask channelMask; 357 NVEvoChannelMask noCoreInterlockMask; 358 /* Each channel in this mask was programmed with a "flip lock 359 * qualifying" flip. */ 360 NVEvoChannelMask flipLockQualifyingMask; 361 /* Channels set here are transitioning from NULL ctxdma to non-NULL 362 * ctxdma or vice-versa on this update. Only necessary/valid on Turing 363 * (class C5*). */ 364 NVEvoChannelMask flipTransitionWAR; 365 366 struct { 367 NvBool vrrTearing; 368 } base[NVKMS_MAX_HEADS_PER_DISP]; 369 370 /* 371 * Window immediate channels with pending methods are represented 372 * here by NV_EVO_CHANNEL_MASK_WINDOW(n) for window immediate 373 * channel n. 374 */ 375 NVEvoChannelMask winImmChannelMask; 376 377 /* 378 * Each window channel NV_EVO_CHANNEL_MASK_WINDOW(n) needs to 379 * be interlocked with its corresponding window immediate channel n. 380 */ 381 NVEvoChannelMask winImmInterlockMask; 382 383 } subdev[NVKMS_MAX_SUBDEVICES]; 384 385 } NVEvoUpdateState; 386 387 struct _NVEvoModesetUpdateState { 388 NVEvoUpdateState updateState; 389 NVDpyIdList connectorIds; 390 const NVDPLibModesetStateRec 391 *pDpLibModesetState[NVKMS_MAX_HEADS_PER_DISP]; 392 NvBool windowMappingChanged; 393 }; 394 395 typedef struct { 396 struct { 397 NVEvoChannelMask channelMask; 398 } subdev[NVKMS_MAX_SUBDEVICES]; 399 } NVEvoIdleChannelState; 400 401 typedef struct { 402 NvU8 validTimeStampBits; 403 NvBool tearingFlips :1; 404 NvBool vrrTearingFlips :1; 405 NvBool perEyeStereoFlips :1; 406 } NVEvoChannelCaps; 407 408 enum NVEvoImmChannel { 409 NV_EVO_IMM_CHANNEL_NONE, 410 NV_EVO_IMM_CHANNEL_PIO, 411 NV_EVO_IMM_CHANNEL_DMA, 412 }; 413 414 typedef struct { 415 NvU32 handle; 416 void *control[NVKMS_MAX_SUBDEVICES]; 417 } NVEvoPioChannel; 418 419 /*! basic syncpt structure used for pre and post syncpt usage */ 420 typedef struct _NVEvoSyncpt { 421 /*! syncpt id (only useful for post-syncpt) */ 422 NvU32 id; 423 /*! bitmask of channels using this syncpt */ 424 NVEvoChannelMask channelMask; 425 /*! handle of context dma allocated to this syncpt */ 426 NvU32 hCtxDma; 427 /*! handle of syncpt object */ 428 NvU32 hSyncpt; 429 /*! stores syncpt max value */ 430 NvU32 syncptMaxVal; 431 } NVEvoSyncpt; 432 433 /* Tracks internal state of a vblank sync object. */ 434 typedef struct _NVVblankSyncObjectRec { 435 /* Whether the vblank sync object is currently in use by some client. */ 436 NvBool inUse; 437 438 /* Whether the vblank sync object is enabled or disabled. */ 439 NvBool enabled; 440 441 /* 442 * The index of this Rec inside of the HeadState's vblankSyncObjects array. 443 * Also corresponds with the index of the sync object in hardware. 444 */ 445 NvU32 index; 446 447 /* 448 * This syncpoint object should be created as part of 449 * nvRmSetupEvoCoreChannel(). 450 */ 451 NVEvoSyncpt evoSyncpt; 452 } NVVblankSyncObjectRec; 453 454 /* EVO channel, encompassing multiple subdevices and a single pushbuf */ 455 typedef struct _NVEvoChannel { 456 /* Pointer to array of per subdev notifier dma structs */ 457 NVEvoDmaPtr notifiersDma; 458 459 NvU32 hwclass; 460 NvU32 instance; 461 NVEvoChannelMask channelMask; /* only one bit should be set */ 462 463 NVDmaBufferEvoRec pb; 464 465 NVOS10_EVENT_KERNEL_CALLBACK_EX completionNotifierEventCallback; 466 NvU32 completionNotifierEventHandle; 467 468 /* 469 * GV100 timestamped flips need a duplicate update which only changes 470 * TIMESTAMP_MODE and MIN_PRESENT_INTERVAL fields in SET_PRESENT_CONTROL; 471 * to allow updating these fields without changing anything else in 472 * SET_PRESENT_CONTROL, normal updates to SET_PRESENT_CONTROL are cached 473 * here. (bug 1990958) 474 */ 475 NvU32 oldPresentControl; 476 477 // On Turing, RM wants to be notified when the tearing mode changes. 478 NvBool oldTearingMode; 479 480 struct { 481 enum NVEvoImmChannel type; 482 union { 483 NVEvoPioChannel *pio; 484 struct _NVEvoChannel *dma; 485 } u; 486 } imm; 487 488 NVEvoChannelCaps caps; 489 490 NVEvoSyncpt postSyncpt; 491 492 struct { 493 NvBool enabled; 494 NvU32 srcMaxLum; 495 NvU32 targetMaxLums[NVKMS_MAX_SUBDEVICES]; 496 } tmoParams; 497 } NVEvoChannel; 498 499 typedef enum { 500 NV_EVO_NO_LOCK, 501 NV_EVO_FRAME_LOCK, 502 NV_EVO_RASTER_LOCK, 503 } NVEvoLockMode; 504 505 typedef enum { 506 NV_EVO_LOCK_PIN_ERROR = -1, 507 NV_EVO_LOCK_PIN_INTERNAL_0 = 0, 508 NV_EVO_LOCK_PIN_0 = 0x20, 509 } NVEvoLockPin; 510 511 typedef struct _NVEvoHeadControl { 512 NvBool interlaced; 513 NVEvoLockMode clientLock; 514 NVEvoLockPin clientLockPin; 515 int clientLockoutWindow; 516 NVEvoLockMode serverLock; 517 NVEvoLockPin serverLockPin; 518 NvBool flipLock; 519 NVEvoLockPin flipLockPin; 520 NVEvoLockPin stereoPin; 521 522 /* 523 * Whether or not this GPU is stereo locked. True if all heads are either 524 * frame or raster locked, and all heads are driving non-interlaced modes. 525 */ 526 NvBool stereoLocked; 527 528 /* 529 * Whether or not this head is driving a HDMI 3D frame packed mode. Used 530 * in headcontrol only on >=GV100. 531 */ 532 NvBool hdmi3D; 533 534 /* 535 * Whether or not this head is driving a mode requiring the HW YUV420 536 * packer. Used in headcontrol only on >=nvdisplay 4.0. 537 */ 538 NvBool hwYuv420; 539 540 /* This isn't actually part of HeadControl, but it's convenient */ 541 NvU32 lockChainPosition; 542 } NVEvoHeadControl; 543 544 typedef struct _NVEvoCapabilities { 545 NVEvoLockPinCaps pin[NV_EVO_NUM_LOCK_PIN_CAPS]; 546 NVEvoMiscCaps misc; 547 NVEvoHeadCaps head[NV_EVO_NUM_HEAD_CAPS]; 548 NVEvoSorCaps sor[NV_EVO_NUM_SOR_CAPS]; 549 NVEvoPiorCaps pior[NV_EVO_NUM_PIOR_CAPS]; 550 NVEvoWindowCaps window[NV_EVO_NUM_WINDOW_CAPS]; 551 } NVEvoCapabilities; 552 553 typedef struct { 554 NVSurfaceEvoPtr pSurfaceEvo; 555 enum NvKmsNIsoFormat format; 556 NvU16 offsetInWords; 557 } NVFlipNIsoSurfaceEvoHwState; 558 559 typedef struct { 560 NVFlipNIsoSurfaceEvoHwState surface; 561 NvBool awaken; 562 } NVFlipCompletionNotifierEvoHwState; 563 564 typedef struct { 565 NvBool usingSyncpt; 566 union { 567 struct { 568 NVFlipNIsoSurfaceEvoHwState acquireSurface; 569 NvU32 acquireValue; 570 NVFlipNIsoSurfaceEvoHwState releaseSurface; 571 NvU32 releaseValue; 572 } semaphores; 573 struct { 574 NvBool isPreSyncptSpecified; 575 NvU32 preSyncpt; 576 NvU32 preValue; 577 578 NvU32 postCtxDma; 579 NvU32 postValue; 580 } syncpts; 581 } u; 582 } NVFlipSyncObjectEvoHwState; 583 584 typedef struct { 585 NVLutSurfaceEvoPtr pLutSurfaceEvo; 586 } NVFlipLutHwState; 587 588 typedef struct { 589 NVSurfaceEvoPtr pSurfaceEvo; 590 NvS16 x, y; 591 592 struct NvKmsCompositionParams cursorCompParams; 593 } NVFlipCursorEvoHwState; 594 595 typedef struct { 596 NVSurfaceEvoPtr pSurfaceEvo[NVKMS_MAX_EYES]; 597 NVFlipCompletionNotifierEvoHwState completionNotifier; 598 NVFlipSyncObjectEvoHwState syncObject; 599 600 // Non-zero timeStamp value is only allowed if the channel's 601 // 'timeStampFlipBits' capability is > 0. 602 NvU64 timeStamp; 603 NvU8 minPresentInterval; 604 // True means immediate or tearing flip. False means flip-at-vblank. 605 NvBool tearing; 606 // The tearing mode passed to RM's VRR code via 607 // NV_VRR_TRAP_ARGUMENT_MAX_FPS_TEARING. 608 NvBool vrrTearing; 609 NvBool perEyeStereoFlip; 610 611 struct NvKmsSize sizeIn; 612 struct NvKmsSize sizeOut; 613 struct NvKmsSignedPoint outputPosition; 614 615 NVEvoScalerTaps hTaps; 616 NVEvoScalerTaps vTaps; 617 618 struct NvKmsCscMatrix cscMatrix; 619 620 NVFlipLutHwState inputLut; 621 622 struct NvKmsRRParams rrParams; 623 624 struct NvKmsCompositionParams composition; 625 626 NVFlipLutHwState tmoLut; 627 struct { 628 struct NvKmsHDRStaticMetadata val; 629 NvBool enabled; 630 } hdrStaticMetadata; 631 632 enum NvKmsInputColorSpace colorspace; 633 634 struct { 635 NvBool specified; 636 637 /* 638 * Maximum vertical downscale factor (scaled by 1024) 639 * 640 * For example, if the downscale factor is 1.5, then maxVDownscaleFactor 641 * would be 1.5 x 1024 = 1536. 642 */ 643 NvU16 vertical; 644 645 /* 646 * Maximum horizontal downscale factor (scaled by 1024) 647 * 648 * See the example above for vertical. 649 */ 650 NvU16 horizontal; 651 } maxDownscaleFactors; 652 } NVFlipChannelEvoHwState; 653 654 enum NvKmsDpyAttributeColorBpcValue { 655 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN = 0, 656 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10 = 10, 657 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8 = 8, 658 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6 = 6, 659 }; 660 661 typedef struct _NVColorFormatInfoRec { 662 struct { 663 enum NvKmsDpyAttributeColorBpcValue maxBpc; 664 } rgb444, yuv444, yuv422; 665 } NVColorFormatInfoRec; 666 667 typedef struct { 668 struct NvKmsPoint viewPortPointIn; 669 NVFlipCursorEvoHwState cursor; 670 NVFlipChannelEvoHwState layer[NVKMS_MAX_LAYERS_PER_HEAD]; 671 struct NvKmsUsageBounds usage; 672 NvBool disableMidFrameAndDWCFWatermark; 673 enum NvKmsOutputTf tf; 674 675 NvBool skipLayerPendingFlips[NVKMS_MAX_LAYERS_PER_HEAD]; 676 677 struct { 678 NvBool viewPortPointIn : 1; 679 NvBool cursorSurface : 1; 680 NvBool cursorPosition : 1; 681 NvBool tf : 1; 682 NvBool hdrStaticMetadata : 1; 683 684 NvBool layerPosition[NVKMS_MAX_LAYERS_PER_HEAD]; 685 NvBool layerSyncObjects[NVKMS_MAX_LAYERS_PER_HEAD]; 686 NvBool layer[NVKMS_MAX_LAYERS_PER_HEAD]; 687 } dirty; 688 } NVFlipEvoHwState; 689 690 enum NvKmsHDROutputState { 691 NVKMS_HDR_OUTPUT_STATE_SDR = 0, 692 NVKMS_HDR_OUTPUT_STATE_HDR = 1, 693 NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR = 2, 694 }; 695 696 /*! 697 * State requested through the NVKMS API. This may differ from 698 * the current hardware state (e.g., if the head has been 699 * momentarily blanked during DP link training). 700 */ 701 typedef struct _NVEvoSubDevHeadStateRec { 702 struct NvKmsPoint viewPortPointIn; 703 NVFlipCursorEvoHwState cursor; 704 NVFlipChannelEvoHwState layer[NVKMS_MAX_LAYERS_PER_HEAD]; 705 // Current usage bounds programmed into the hardware. 706 struct NvKmsUsageBounds usage; 707 // Usage bounds required after the last scheduled flip completes. 708 struct NvKmsUsageBounds targetUsage; 709 // Preallocated usage bounds that will be required for upcoming flips. 710 struct NvKmsUsageBounds preallocatedUsage; 711 712 // Current state of MidFrameAndDWCFWatermark programmed into the hardware. 713 NvBool disableMidFrameAndDWCFWatermark; 714 // 715 // State of MidFrameAndDWCFWatermark required after the last scheduled 716 // flip completes. 717 // 718 NvBool targetDisableMidFrameAndDWCFWatermark; 719 } NVEvoSubDevHeadStateRec; 720 721 #define NVKMS_HEAD_SURFACE_MAX_BUFFERS 2 722 723 /* 724 * HeadSurface state that applies to a single head, but spans across 725 * all subdevices. 726 */ 727 typedef struct { 728 /* 729 * The size of the headSurfaces for this head, across all subdevices. 730 * headSurface might only use a subset of the surfaces on one or more 731 * subdevices in SLI Mosaic. 732 */ 733 struct NvKmsSize size; 734 struct NvKmsSize stagingSize; 735 736 /* 737 * The surfaces allocated for use by headSurface on this head. 738 * Surface allocations are broadcast across subdevices, though 739 * headSurface may unicast its rendering to the headSurface 740 * surface allocations on specific subdevices. 741 */ 742 struct { 743 NVHsSurfacePtr pSurface; 744 NVHsSurfacePtr pStagingSurface; 745 } surfaces[NVKMS_MAX_EYES][NVKMS_HEAD_SURFACE_MAX_BUFFERS]; 746 747 /* 748 * The number of surfaces in the NVKMS_HEAD_SURFACE_MAX_BUFFERS dimension of 749 * the surfaces[][] array. Elements [0,surfaceCount-1] in the surfaces[][] 750 * array will be populated. 751 */ 752 NvU32 surfaceCount; 753 } NVHsStateOneHeadAllDisps; 754 755 /* Subdevice-specific, channel-independent state */ 756 typedef struct _NVEvoSubDevRec { 757 NvU32 subDeviceInstance; 758 759 NVEvoCapabilities capabilities; 760 761 NVDispEvoPtr pDispEvo; 762 763 NvU32 setSwSpareA[NVKMS_MAX_HEADS_PER_DISP]; 764 765 NVEvoSubDevHeadStateRec headState[NVKMS_MAX_HEADS_PER_DISP]; 766 NVEvoHeadControl headControl[NVKMS_MAX_HEADS_PER_DISP]; 767 NVEvoHeadControl headControlAssy[NVKMS_MAX_HEADS_PER_DISP]; 768 void *cursorPio[NVKMS_MAX_HEADS_PER_DISP]; 769 NvBool (*scanLockState)(NVDispEvoPtr pDispEvo, 770 NVEvoSubDevPtr pEvoSubDev, 771 NvU32 action, 772 /* NV_INVALID_HEAD-terminated 773 * array of head indices */ 774 const NvU32 *pHeads); 775 776 /* 777 * EVO state machine refcounter for the number of SLI or proxy framelock 778 * clients that are connected to this server. 779 */ 780 NvU32 frameLockSliProxyClients; 781 782 /* 783 * Since we add all active heads as framelock clients whenever we enable 784 * the second head as a framelock client, there's no need for EVO state 785 * transitions for heads 3 and more. Instead of those state transitions, 786 * we use the frameLockExtraClients ref counter to keep track of heads 787 * 3 and greater being added as framelock clients. 788 * 789 * XXX The state machine currently will naively framelock heads 3 and 790 * greater during this state transition, even if they're not capable 791 * of being framelocked (for example, when they have very different 792 * refresh rates). Bug 976532 793 */ 794 NvU32 frameLockExtraClients; 795 796 /* 797 * All of the following except the "armed" versions are set by the EVO 798 * state machine to the desired HW configuration given the current locking 799 * state. 800 * The "armed" versions represent the current hardware configuration, used 801 * to avoid excess hardware updates. 802 */ 803 NvU32 frameLockServerMaskArmed; 804 NvU32 frameLockServerMaskAssy; 805 NvU32 frameLockClientMaskArmed; 806 NvU32 frameLockClientMaskAssy; 807 NvU32 frameLockExtRefClkMaskArmed; 808 NvU32 frameLockExtRefClkMaskAssy; 809 NvBool frameLockHouseSync; 810 811 NvU8 flipLockPinSetForFrameLockHeadMask; 812 NvU8 flipLockEnabledForFrameLockHeadMask; 813 NvU8 flipLockPinSetForSliHeadMask; 814 NvU8 flipLockEnabledForSliHeadMask; 815 816 NvU32 flipLockProhibitedHeadMask; 817 818 NvU32 sliRasterLockServerMask; 819 NvU32 sliRasterLockClientMask; 820 821 NVEvoLockPin sliServerLockPin; 822 NVEvoLockPin sliClientLockPin; 823 NvBool forceZeroClientLockoutWindow; 824 } NVEvoSubDevRec; 825 826 typedef struct _NVEvoColorRec { 827 NvU16 red; 828 NvU16 green; 829 NvU16 blue; 830 } NVEvoColorRec; 831 832 typedef struct { 833 NvU16 Red; 834 NvU16 Green; 835 NvU16 Blue; 836 NvU16 Unused; 837 } NVEvoLutEntryRec; 838 839 typedef struct { 840 NVEvoLutEntryRec base[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES]; 841 // The output LUT requires 8-bit alignment. 842 NVEvoLutEntryRec output[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES] 843 __attribute__((aligned(0x100))); 844 } NVEvoLutDataRec; 845 846 typedef struct { 847 NvBool supportsDP13 :1; 848 NvBool supportsHDMI20 :1; 849 NvBool inputLutAppliesToBase :1; 850 NvU8 validNIsoFormatMask; 851 NvU8 genericPageKind; 852 NvU32 maxPitchValue; 853 int maxWidthInBytes; 854 int maxWidthInPixels; 855 int maxHeight; 856 NvU32 maxRasterWidth; 857 NvU32 maxRasterHeight; 858 struct NvKmsCompositionCapabilities cursorCompositionCaps; 859 NvU16 validLayerRRTransforms; 860 struct NvKmsLayerCapabilities layerCaps[NVKMS_MAX_LAYERS_PER_HEAD]; 861 NvU8 legacyNotifierFormatSizeBytes[NVKMS_MAX_LAYERS_PER_HEAD]; 862 NvU8 dpYCbCr422MaxBpc; 863 NvU8 hdmiYCbCr422MaxBpc; 864 } NVEvoCapsRec; 865 866 typedef struct { 867 NvU32 coreChannelClass; 868 size_t dmaArmedSize; 869 NvU32 dmaArmedOffset; 870 } NVEvoCoreChannelDmaRec; 871 872 873 typedef struct _NVEvoSubDeviceRec { 874 NvU32 handle; 875 NvU32 gpuId; 876 #define NV_INVALID_GPU_LOG_INDEX 0xFF 877 NvU8 gpuLogIndex; 878 char gpuString[NVKMS_GPU_STRING_SIZE]; 879 880 NvU32 numEngines; 881 NvU32 *supportedEngines; 882 883 /* Core channel memory mapping for ARM values */ 884 void *pCoreDma; 885 886 /* ISO ctxdma programmed by EVO2 hal, into the overlay channel */ 887 NvU32 overlayContextDmaIso[NVKMS_MAX_HEADS_PER_DISP]; 888 enum NvKmsSurfaceMemoryFormat overlaySurfFormat[NVKMS_MAX_HEADS_PER_DISP]; 889 890 /* Per head surface programmed into the core channel */ 891 const NVSurfaceEvoRec *pCoreChannelSurface[NVKMS_MAX_HEADS_PER_DISP]; 892 893 /* EVO2 only, TRUE if a valid base surface passed to ->Flip() */ 894 NvBool isBaseSurfSpecified[NVKMS_MAX_HEADS_PER_DISP]; 895 enum NvKmsSurfaceMemoryFormat baseSurfFormat[NVKMS_MAX_HEADS_PER_DISP]; 896 897 /* Composition parameters considered for hardware programming by EVO2 hal */ 898 struct { 899 NvBool initialized; 900 enum NvKmsCompositionColorKeySelect colorKeySelect; 901 NVColorKey colorKey; 902 } baseComp[NVKMS_MAX_HEADS_PER_DISP], overlayComp[NVKMS_MAX_HEADS_PER_DISP]; 903 904 } NVEvoSubDeviceRec; 905 906 enum NvKmsLUTState { 907 NvKmsLUTStateUninitialized = 0, 908 NvKmsLUTStateIdentity = 1, 909 NvKmsLUTStatePQ = 2, 910 }; 911 912 /* Device-specific EVO state (subdevice- and channel-independent) */ 913 typedef struct _NVEvoDevRec { 914 915 NvU8 gpuLogIndex; 916 NvU32 allocRefCnt; /* number of ALLOC_DEVICE calls */ 917 NVListRec devListEntry; 918 919 /* array of gpuIds opened with nvkms_open_gpu() */ 920 NvU32 openedGpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; 921 922 NVUnixRmHandleAllocatorRec handleAllocator; 923 NvU32 deviceId; 924 925 NvU32 deviceHandle; 926 struct NvKmsPerOpenDev *pNvKmsOpenDev; 927 928 struct { 929 NvPushDeviceRec device; 930 NvU32 handlePool[NV_PUSH_DEVICE_HANDLE_POOL_NUM]; 931 } nvPush; 932 933 /* SLI Info */ 934 struct { 935 NvBool mosaic; 936 struct { 937 NvBool present :1; 938 939 /* Current hardware state */ 940 NvBool powered :1; 941 942 /* Software state tracking needs from hardware */ 943 NvBool powerNeededForRasterLock :1; 944 } bridge; 945 } sli; 946 947 NvU32 numHeads; 948 NvU32 numWindows; /* NVDisplay only. */ 949 950 NvU32 displayHandle; 951 952 953 /*! 954 * modesetOwner points to the pOpenDev of the client that called 955 * NVKMS_IOCTL_GRAB_OWNERSHIP. 956 */ 957 const struct NvKmsPerOpenDev *modesetOwner; 958 959 /*! 960 * Indicates whether modeset ownership is changed since 961 * last modeset. 962 */ 963 NvBool modesetOwnerChanged; 964 965 /*! 966 * NVEvoDevRec::numSubDevices is the number of GPUs in the SLI 967 * device. This is the number of NVEvoSubDevPtrs in 968 * NVEvoDevRec::gpus[] and the number of NVSubDeviceEvoPtr in 969 * NVEvoDevRec::pSubDevices. 970 * 971 * The data structure organization is summarized by the following table: 972 * 973 * NVDevEvoRec::numSubDevices (# of pSubDevs) 974 * | NVDevEvoRec::nDispEvo (# of pDispEvos) 975 * | | NVDispEvoRec::numSubDevices (# of sd per disp) 976 * | | | 977 * no SLI 1 1 1 978 * SLI Mosaic N N 1 979 */ 980 NvU32 numSubDevices; 981 NVSubDeviceEvoPtr pSubDevices[NVKMS_MAX_SUBDEVICES]; 982 983 NvU32 dispClass; 984 NvU32 displayCommonHandle; 985 NvU32 rmCtrlHandle; 986 987 unsigned int nDispEvo; 988 NVDispEvoPtr pDispEvo[NVKMS_MAX_SUBDEVICES]; 989 990 NVEvoChannelPtr base[NVKMS_MAX_HEADS_PER_DISP]; 991 NVEvoChannelPtr core; 992 NVEvoChannelPtr overlay[NVKMS_MAX_HEADS_PER_DISP]; 993 NVEvoChannelPtr window[NVKMS_MAX_WINDOWS_PER_DISP]; 994 995 /* NVDisplay head<->window mapping */ 996 NvU32 headForWindow[NVKMS_MAX_WINDOWS_PER_DISP]; 997 998 struct { 999 NVEvoChannelPtr layer[NVKMS_MAX_LAYERS_PER_HEAD]; 1000 NvU32 numLayers; 1001 } head[NVKMS_MAX_HEADS_PER_DISP]; 1002 1003 /* Pointer to array of subdev structs */ 1004 NVEvoSubDevPtr gpus; 1005 1006 NvU32 subDevMaskStack[NV_EVO_SUBDEV_STACK_SIZE]; 1007 NvU32 subDevMaskStackDepth; 1008 1009 NvU32 cursorHandle[NVKMS_MAX_HEADS_PER_DISP]; 1010 1011 NVDPLibTimerPtr dpTimer; 1012 1013 NvU8 capsBits[NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE]; 1014 NvU8 commonCapsBits[NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE]; 1015 1016 NVEvoCapsRec caps; 1017 1018 NVEvoCoreChannelDmaRec coreChannelDma; 1019 NvU32 nvkmsGpuVASpace; 1020 1021 NvBool mobile : 1; 1022 NvBool usesTegraDevice : 1; 1023 1024 /* 1025 * IO coherency modes that display supports for ISO and NISO memory 1026 * allocations, respectively. 1027 */ 1028 NvKmsDispIOCoherencyModes isoIOCoherencyModes; 1029 NvKmsDispIOCoherencyModes nisoIOCoherencyModes; 1030 1031 /* 1032 * Indicates whether the init_no_update methods that were pushed by the 1033 * hardware during core channel allocation are still pending. 1034 */ 1035 NvBool coreInitMethodsPending : 1; 1036 /* 1037 * Indicates that NVKMS restored the console and freeing the core channel 1038 * should leave the display configuration alone. 1039 * 1040 * This should be set to FALSE whenever an update is sent that flips away 1041 * from the framebuffer console. 1042 * 1043 * TODO: Remove this in favor of passing a parameter explicitly to the 1044 * functions that use it. 1045 */ 1046 NvBool skipConsoleRestore : 1; 1047 /* 1048 * Indicates that hotplug events that occur while NVKMS is the modeset owner 1049 * should trigger console restore modesets. 1050 */ 1051 NvBool handleConsoleHotplugs : 1; 1052 /* 1053 * Cached from NvKmsSetModeRequest::allowHeadSurfaceInNvKms when the 1054 * modeset owner does a modeset. This is needed so that when non-modeset 1055 * owners do a partial modeset they don't override this value. 1056 */ 1057 NvBool allowHeadSurfaceInNvKms : 1; 1058 1059 NvBool gc6Allowed : 1; 1060 1061 /* 1062 * Indicates whether NVKMS is driving an SOC display device, or an external 1063 * dGPU device. 1064 */ 1065 NvBool isSOCDisplay : 1; 1066 1067 /* 1068 * Indicates whether NVKMS is supporting syncpts. 1069 */ 1070 NvBool supportsSyncpts : 1; 1071 1072 /* 1073 * Indicates whether the display device that NVKMS is driving requires all 1074 * memory allocations that display will access to come from sysmem. 1075 * 1076 * For SOC display devices, this should be set to TRUE since the only 1077 * memory aperture that they support is sysmem. 1078 */ 1079 NvBool requiresAllAllocationsInSysmem : 1; 1080 /* 1081 * Indicates whether the device that NVKMS is driving supports headSurface 1082 * composition. 1083 * 1084 * For SOC display devices (e.g., Orin), this should be set to FALSE since 1085 * there's currently zero nvgpu support, and no Tegra clients should be 1086 * using headSurface right now. 1087 */ 1088 NvBool isHeadSurfaceSupported : 1; 1089 1090 nvkms_timer_handle_t *postFlipIMPTimer; 1091 nvkms_timer_handle_t *consoleRestoreTimer; 1092 1093 nvkms_timer_handle_t *lowerDispBandwidthTimer; 1094 1095 NvU32 simulationType; 1096 1097 NvU32 numClasses; 1098 NvU32 *supportedClasses; 1099 1100 struct { 1101 /* name[0] == '\0' for unused registryKeys[] array elements. */ 1102 char name[NVKMS_MAX_DEVICE_REGISTRY_KEYNAME_LEN]; 1103 NvU32 value; 1104 } registryKeys[NVKMS_MAX_DEVICE_REGISTRY_KEYS]; 1105 1106 /* Returns true if the Quadro Sync card connected to this GPU has 1107 * a firmware version incompatible with this GPU. 1108 */ 1109 NvBool badFramelockFirmware; 1110 1111 const struct _nv_evo_hal *hal; 1112 const struct _nv_evo_cursor_hal *cursorHal; 1113 1114 /*! 1115 * ref_ptr to the structure. 1116 * 1117 * nvkms_timer_handle_t objects refer to the pDevEvo via references to this, 1118 * so that timers that fire after the pDevEvo has been freed can detect that 1119 * case and do nothing. 1120 */ 1121 struct nvkms_ref_ptr *ref_ptr; 1122 1123 struct { 1124 void *handle; 1125 } hdmiLib; 1126 1127 struct { 1128 NvU32 semaphoreHandle; 1129 void *pSemaphores; 1130 NvBool enabled; 1131 NvBool active; 1132 NvU32 flipCounter; 1133 } vrr; 1134 1135 /* 1136 * Information about the framebuffer console returned by 1137 * NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO. 1138 */ 1139 NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS vtFbInfo; 1140 1141 /* 1142 * Handle referencing the memory reserved by RM that is used by the kernel 1143 * as the framebuffer console surface. 1144 */ 1145 NvKmsSurfaceHandle fbConsoleSurfaceHandle; 1146 1147 NVHsDeviceEvoPtr pHsDevice; 1148 1149 /* The current headSurface configuration. */ 1150 NVHsStateOneHeadAllDisps apiHeadSurfaceAllDisps[NVKMS_MAX_HEADS_PER_DISP]; 1151 1152 struct NVDevPreallocRec prealloc; 1153 1154 struct { 1155 NvU32 handle; 1156 NVOS10_EVENT_KERNEL_CALLBACK_EX callback; 1157 } nonStallInterrupt; 1158 1159 /* 1160 * Track the LUT with per-head, per-pDisp scope. The LUT itself 1161 * is triple buffered. 1162 * 1163 * RM surface allocations are broadcast in SLI, so LUT is allocated with 1164 * per-device scope. However, writes into the LUT are unicast with 1165 * per-pDisp scope. 1166 * 1167 * The LUT surface in the core channel contains both the base and output 1168 * LUTs. 1169 */ 1170 struct { 1171 struct { 1172 NVLutSurfaceEvoPtr LUT[3]; 1173 struct { 1174 NvBool waitForPreviousUpdate; 1175 NvBool curBaseLutEnabled; 1176 NvBool curOutputLutEnabled; 1177 NvU8 curLUTIndex; 1178 nvkms_timer_handle_t *updateTimer; 1179 } disp[NVKMS_MAX_SUBDEVICES]; 1180 } apiHead[NVKMS_MAX_HEADS_PER_DISP]; 1181 NVLutSurfaceEvoPtr defaultLut; 1182 enum NvKmsLUTState defaultBaseLUTState[NVKMS_MAX_SUBDEVICES]; 1183 enum NvKmsLUTState defaultOutputLUTState[NVKMS_MAX_SUBDEVICES]; 1184 } lut; 1185 1186 /*! stores pre-syncpts */ 1187 NVEvoSyncpt *preSyncptTable; 1188 NvBool *pAllSyncptUsedInCurrentFlip; 1189 1190 /* DIFR prefetch event handling. */ 1191 NVOS10_EVENT_KERNEL_CALLBACK_EX difrPrefetchCallback; 1192 NvU32 difrPrefetchEventHandler; 1193 1194 /* DIFR runtime state. */ 1195 NVDIFRStateEvoPtr pDifrState; 1196 1197 NvU32 numApiHeads; 1198 1199 struct { 1200 NvU32 numLayers; 1201 } apiHead[NVKMS_MAX_HEADS_PER_DISP]; 1202 } NVDevEvoRec; 1203 1204 /* 1205 * The NVHwModeTimingsEvo structure stores all the values necessary to 1206 * perform a modeset with EVO 1207 */ 1208 1209 typedef struct _NVHwModeViewPortEvo { 1210 struct { 1211 /* 1212 * note that EVO centers ViewPortOut within the active raster, 1213 * so xAdjust,yAdjust are signed; to position ViewPortOut at 1214 * 0,0 within active raster: 1215 * 1216 * viewPortOut.xAdjust = (activeRaster.w - viewPortOut.w)/2 * -1; 1217 * viewPortOut.yAdjust = (activeRaster.h - viewPortOut.h)/2 * -1; 1218 */ 1219 NvS16 xAdjust; 1220 NvS16 yAdjust; 1221 NvU16 width; 1222 NvU16 height; 1223 } out; 1224 1225 struct { 1226 NvU16 width; 1227 NvU16 height; 1228 } in; 1229 1230 NVEvoScalerTaps hTaps; 1231 NVEvoScalerTaps vTaps; 1232 1233 // These are the window features that may be possible if the required ISO 1234 // bw is available at the time that the feature needs to be enabled. By 1235 // default possibleUsage is set considering that everything is supported 1236 // by the HW and for dGPU, IMP will scale it as needed. 1237 struct NvKmsUsageBounds possibleUsage; 1238 1239 // Guaranteed usage bounds allowed by IMP. These are never assigned to 1240 // NVDpyEvoRec::usage or the hardware directly, but rather are used to 1241 // validate usage bound change requests. 1242 struct NvKmsUsageBounds guaranteedUsage; 1243 } NVHwModeViewPortEvo; 1244 1245 static inline NvBool nvIsImageSharpeningAvailable( 1246 const NVHwModeViewPortEvo *pViewPort) 1247 { 1248 return (pViewPort->out.width != pViewPort->in.width) || 1249 (pViewPort->out.height != pViewPort->in.height); 1250 } 1251 1252 enum nvKmsPixelDepth { 1253 NVKMS_PIXEL_DEPTH_18_444, 1254 NVKMS_PIXEL_DEPTH_24_444, 1255 NVKMS_PIXEL_DEPTH_30_444, 1256 NVKMS_PIXEL_DEPTH_20_422, 1257 NVKMS_PIXEL_DEPTH_16_422, 1258 }; 1259 1260 enum nvKmsTimingsProtocol { 1261 NVKMS_PROTOCOL_DAC_RGB, 1262 1263 NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A, 1264 NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B, 1265 NVKMS_PROTOCOL_SOR_DUAL_TMDS, 1266 NVKMS_PROTOCOL_SOR_DP_A, 1267 NVKMS_PROTOCOL_SOR_DP_B, 1268 NVKMS_PROTOCOL_SOR_LVDS_CUSTOM, 1269 NVKMS_PROTOCOL_SOR_HDMI_FRL, 1270 1271 NVKMS_PROTOCOL_DSI, 1272 1273 NVKMS_PROTOCOL_PIOR_EXT_TMDS_ENC, 1274 }; 1275 1276 /* 1277 * This structure defines all of the values necessary to program mode timings 1278 * on EVO hardware. 1279 * NOTE: if you add anything to this, consider adding it to 1280 * RasterLockPossible() in nvkms-evo.c 1281 */ 1282 typedef struct _NVHwModeTimingsEvo { 1283 struct NvKmsPoint rasterSize; 1284 struct NvKmsPoint rasterSyncEnd; 1285 struct NvKmsPoint rasterBlankEnd; 1286 struct NvKmsPoint rasterBlankStart; 1287 NvU32 rasterVertBlank2Start; 1288 NvU32 rasterVertBlank2End; 1289 1290 NvU32 pixelClock; /* in kHz */ 1291 enum nvKmsTimingsProtocol protocol; 1292 /* 1293 * yuv420Mode reflects whether this mode requires YUV 4:2:0 decimation into 1294 * a half-width output through headsurface (SW YUV420) or >=nvdisplay 4.0 HW 1295 * CSC (HW YUV420). 1296 * 1297 * If a mode requires SW YUV 4:2:0 emulation, the pixelClock and width 1298 * values in NvModeTimings will still be the full width values specified by 1299 * the mode parsed from the EDID (e.g. 3840x2160@60), but the pixelClock 1300 * and width values in NVHwModeTimingsEvo will be the "real" half width 1301 * values programmed in HW and rendered to through a headSurface transform 1302 * (e.g. 1920x2160@60). If a mode requires HW YUV 4:2:0 CSC, the 1303 * pixelClock and width values in both NvModeTimings and NVHwModeTimingsEvo 1304 * will be full width, and the decimation to the half width scanout surface 1305 * is performed in HW. In both cases, only the full width values should 1306 * ever be reported to the client. 1307 */ 1308 enum NvYuv420Mode yuv420Mode; 1309 /* *SyncPol is TRUE if negative */ 1310 NvBool hSyncPol : 1; 1311 NvBool vSyncPol : 1; 1312 NvBool interlaced : 1; 1313 NvBool doubleScan : 1; 1314 /* 1315 * hdmi3D reflects whether this mode is a HDMI 3D frame packed mode. True 1316 * only if the user selected HDMI 3D stereo mode and the GPU supports it. 1317 * If true, then pixelClock is doubled. 1318 */ 1319 NvBool hdmi3D : 1; 1320 1321 struct { 1322 /* The vrr type for which this mode is adjusted. */ 1323 enum NvKmsDpyVRRType type; 1324 } vrr; 1325 1326 /* DisplayPort Display Stream Compression */ 1327 struct { 1328 NvBool enable; 1329 1330 /* 1331 * The DSC target bits per pixel (bpp) rate value multiplied by 16 that 1332 * is being used by the DSC encoder. 1333 * 1334 * It maps respectively to {pps4[1:0], pps5[7:0]}. 1335 */ 1336 NvU32 bitsPerPixelX16; 1337 1338 /* 1339 * The DSC picture parameter set (PPS), which the DSC encoder must 1340 * communicate to the decoder. 1341 */ 1342 NvU32 pps[DSC_MAX_PPS_SIZE_DWORD]; 1343 } dpDsc; 1344 1345 HDMI_FRL_CONFIG hdmiFrlConfig; 1346 1347 NVHwModeViewPortEvo viewPort; 1348 } NVHwModeTimingsEvo; 1349 1350 static inline NvU64 nvEvoFrametimeUsFromTimings(const NVHwModeTimingsEvo *pTimings) 1351 { 1352 NvU64 pixelsPerFrame = pTimings->rasterSize.x * pTimings->rasterSize.y; 1353 NvU64 pixelsPerSecond = KHzToHz(pTimings->pixelClock); 1354 NvU64 framesPerSecond = pixelsPerSecond / pixelsPerFrame; 1355 1356 return 1000000ULL / framesPerSecond; 1357 } 1358 1359 static inline NvU16 nvEvoVisibleWidth(const NVHwModeTimingsEvo *pTimings) 1360 { 1361 return pTimings->rasterBlankStart.x - pTimings->rasterBlankEnd.x; 1362 } 1363 1364 static inline NvU16 nvEvoVisibleHeight(const NVHwModeTimingsEvo *pTimings) 1365 { 1366 /* rasterVertBlank2{Start,End} should only be != 0 for interlaced modes. */ 1367 nvAssert(pTimings->interlaced || 1368 ((pTimings->rasterVertBlank2Start == 0) && 1369 (pTimings->rasterVertBlank2End == 0))); 1370 1371 return pTimings->rasterBlankStart.y - pTimings->rasterBlankEnd.y + 1372 pTimings->rasterVertBlank2Start - pTimings->rasterVertBlank2End; 1373 } 1374 1375 /* 1376 * Calculate BackendSizeHeight, based on this HD or SD quality is 1377 * defined. 1378 */ 1379 static inline NvBool nvEvoIsHDQualityVideoTimings( 1380 const NVHwModeTimingsEvo *pTimings) 1381 { 1382 NvU32 height = nvEvoVisibleHeight(pTimings); 1383 1384 // as per windows code, nvva uses < 720. 1385 if (height <= 576) { 1386 // SD quality: 240, 288, 480, 576 1387 return FALSE; 1388 } 1389 1390 // HD quality: 720, 1080 1391 return TRUE; 1392 } 1393 1394 static inline struct NvKmsRect nvEvoViewPortOutHwView( 1395 const NVHwModeTimingsEvo *pTimings) 1396 { 1397 const NVHwModeViewPortEvo *pViewPort = &pTimings->viewPort; 1398 const NvU16 hVisible = nvEvoVisibleWidth(pTimings); 1399 const NvU16 vVisible = nvEvoVisibleHeight(pTimings); 1400 struct NvKmsRect viewPortOut = { 0 }; 1401 1402 viewPortOut.width = pViewPort->out.width; 1403 viewPortOut.height = pViewPort->out.height; 1404 viewPortOut.x = pViewPort->out.xAdjust + 1405 (hVisible - pViewPort->out.width) / 2; 1406 viewPortOut.y = (pViewPort->out.yAdjust + 1407 (vVisible - pViewPort->out.height) / 2); 1408 1409 return viewPortOut; 1410 } 1411 1412 static inline struct NvKmsRect nvEvoViewPortOutClientView( 1413 const NVHwModeTimingsEvo *pTimings) 1414 { 1415 struct NvKmsRect viewPortOut = nvEvoViewPortOutHwView(pTimings); 1416 1417 if (pTimings->doubleScan) { 1418 1419 nvAssert((viewPortOut.x % 2) == 0); 1420 viewPortOut.x /= 2; 1421 1422 nvAssert((viewPortOut.height % 2) == 0); 1423 viewPortOut.height /= 2; 1424 } 1425 1426 return viewPortOut; 1427 } 1428 1429 /* 1430 * The ELD contains a subset of the digital display device's EDID 1431 * information related to audio capabilities. The GPU driver sends the 1432 * ELD to hardware and the audio driver reads it by issuing the ELD 1433 * command verb. 1434 */ 1435 1436 #define NV_MAX_AUDIO_DEVICE_ENTRIES \ 1437 (NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 + 1) 1438 1439 typedef enum { 1440 NV_ELD_PRE_MODESET = 0, 1441 NV_ELD_POST_MODESET, 1442 NV_ELD_POWER_ON_RESET, 1443 } NvEldCase; 1444 1445 /* OR indices are per OR-type. The maximum OR index for each type 1446 * on each GPU is: 1447 * 1448 * Pre-GV10X : 8 SORs, 4 PIORs and 4 Dacs; 1449 * GV10X : 8 SORs, 4 PIORs; 1450 * TU10X+ : 8 SORs; 1451 */ 1452 #define NV_EVO_MAX_ORS 8 1453 1454 /* 1455 * The scoping of heads, ORs, and dpys relative to connectors can be 1456 * complicated. Here is how objects are scoped for various configurations: 1457 * 1458 * #heads #ORs #dpys #NVConnectorEvoRecs 1459 * DP 1.1 1 1 1 1 1460 * DP-MST n 1 n 1 1461 * DP cloning: 1 1 n 1 1462 * 2-Heads-1-OR: 2 2 1 1 1463 */ 1464 typedef struct _NVConnectorEvoRec { 1465 char name[NVKMS_DPY_NAME_SIZE]; 1466 1467 NVDispEvoPtr pDispEvo; 1468 1469 NVListRec connectorListEntry; 1470 1471 NvBool detectComplete; /* For sync'ing dpy detection w/ DP lib */ 1472 NVDPLibConnectorPtr pDpLibConnector; // DP Lib 1473 NvBool dpSerializerEnabled; 1474 1475 struct { 1476 NvU8 maxLinkBW; 1477 NvU8 maxLaneCount; 1478 NvBool supportsMST; 1479 } dpSerializerCaps; 1480 1481 NVDpyId displayId; // RM Display ID 1482 NvKmsConnectorSignalFormat signalFormat; 1483 NvKmsConnectorType type; 1484 NvU32 typeIndex; 1485 NvU32 legacyType; /* NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_ */ 1486 NvU32 legacyTypeIndex; 1487 NvU32 physicalIndex; 1488 NvU32 physicalLocation; 1489 NvU32 validHeadMask; 1490 1491 /* 1492 * [2Heads1OR] XXX Implement the dynamic api-head to hardware-heads mapping 1493 * and remove NVConnectorEvoRec::validApiHeadMask and 1494 * NvKmsQueryConnectorStaticDataReply::headMask. 1495 */ 1496 NvU32 validApiHeadMask; 1497 1498 NvU32 dfpInfo; /* DFP info query through NV0073_CTRL_CMD_DFP_GET_INFO */ 1499 1500 NVDpyIdList ddcPartnerDpyIdsList; 1501 1502 struct { 1503 NvU32 type; 1504 NvU32 protocol; // NV0073_CTRL_SPECIFIC_OR_PROTOCOL_* 1505 NvU32 location; // NV0073_CTRL_SPECIFIC_OR_LOCATION_* 1506 NvU32 ditherType; 1507 NvU32 ditherAlgo; 1508 /* Hardware heads attached to assigned OR */ 1509 NvU32 ownerHeadMask[NV_EVO_MAX_ORS]; 1510 /* ORs mask assigned to this connector */ 1511 NvU32 mask; 1512 } or; 1513 1514 NvEldCase audioDevEldCase[NV_MAX_AUDIO_DEVICE_ENTRIES]; 1515 1516 NvBool isHdmiEnabled; 1517 } NVConnectorEvoRec; 1518 1519 static inline NvU32 nvConnectorGetAttachedHeadMaskEvo( 1520 const NVConnectorEvoRec *pConnectorEvo) 1521 { 1522 NvU32 headMask = 0x0; 1523 NvU32 orIndex; 1524 1525 FOR_EACH_INDEX_IN_MASK(32, orIndex, pConnectorEvo->or.mask) { 1526 headMask |= pConnectorEvo->or.ownerHeadMask[orIndex]; 1527 } FOR_EACH_INDEX_IN_MASK_END; 1528 1529 return headMask; 1530 } 1531 1532 static inline 1533 NvBool nvIsConnectorActiveEvo(const NVConnectorEvoRec *pConnectorEvo) 1534 { 1535 NvU32 orIndex; 1536 1537 FOR_EACH_INDEX_IN_MASK(32, orIndex, pConnectorEvo->or.mask) { 1538 if (pConnectorEvo->or.ownerHeadMask[orIndex] != 0x0) { 1539 return TRUE; 1540 } 1541 } FOR_EACH_INDEX_IN_MASK_END; 1542 1543 return FALSE; 1544 } 1545 1546 /* 1547 * In case of 2-Heads-1-OR: NV0073_CTRL_CMD_DFP_ASSIGN_SOR assigns 2 SORs, 1548 * lowest SOR index is for primary head. 1549 */ 1550 static inline NvU32 nvEvoConnectorGetPrimaryOr( 1551 const NVConnectorEvoRec *pConnectorEvo) 1552 { 1553 return (pConnectorEvo->or.mask == 0x0 ? 1554 NV_INVALID_OR : 1555 BIT_IDX_32(LOWESTBIT(pConnectorEvo->or.mask))); 1556 } 1557 1558 typedef struct _NVDpyAttributeCurrentDitheringConfigRec { 1559 NvBool enabled; 1560 enum NvKmsDpyAttributeCurrentDitheringDepthValue depth; 1561 enum NvKmsDpyAttributeCurrentDitheringModeValue mode; 1562 } NVDpyAttributeCurrentDitheringConfig; 1563 1564 typedef struct __NVAttributesSetEvoRec { 1565 1566 #define NV_EVO_DVC_MIN (-1024) 1567 #define NV_EVO_DVC_MAX 1023 1568 #define NV_EVO_DVC_DEFAULT 0 1569 1570 NvS32 dvc; 1571 1572 /* 1573 * For both colorSpace and colorRange, the value for 1574 * NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_{SPACE,RANGE} sent by the client is 1575 * stored in NVDpyEvoRec::requestedColor(Space, Range}. The structure stores 1576 * the actual color space and color range in use. 1577 * 1578 * nvChooseCurrentColorSpaceAndRangeEvo() chooses the actual color 1579 * space, color bpc, and color range, for a dpy. It sets colorBpc 1580 * to the max bpc supported by the given dpy. 1581 * 1582 * Since YUV444 mode only allows limited color range, changes to the 1583 * current color space may trigger changes to the current color 1584 * range (see nvChooseCurrentColorSpaceAndRangeEvo()). 1585 * 1586 * For SW YUV420 mode, these values are ignored in 1587 * HEAD_SET_PROCAMP and applied in the headSurface composite shader. 1588 */ 1589 enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; 1590 enum NvKmsDpyAttributeColorBpcValue colorBpc; 1591 enum NvKmsDpyAttributeColorRangeValue colorRange; 1592 1593 NVDpyAttributeCurrentDitheringConfig dithering; 1594 1595 #define NV_EVO_IMAGE_SHARPENING_MIN 0 1596 #define NV_EVO_IMAGE_SHARPENING_MAX 255 1597 #define NV_EVO_IMAGE_SHARPENING_DEFAULT 127 1598 1599 struct { 1600 NvBool available; 1601 NvU32 value; 1602 } imageSharpening; 1603 1604 enum NvKmsDpyAttributeDigitalSignalValue digitalSignal; 1605 } NVAttributesSetEvoRec; 1606 1607 #define NV_EVO_DEFAULT_ATTRIBUTES_SET \ 1608 (NVAttributesSetEvoRec) { \ 1609 .dvc = NV_EVO_DVC_DEFAULT, \ 1610 .colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB, \ 1611 .colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL, \ 1612 .dithering = { \ 1613 .enabled = FALSE, \ 1614 .mode = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE, \ 1615 .depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE, \ 1616 }, \ 1617 .imageSharpening = { \ 1618 .value = NV_EVO_IMAGE_SHARPENING_DEFAULT, \ 1619 }, \ 1620 } 1621 1622 1623 typedef struct _NVEldEvoRec { 1624 NvU32 size; 1625 NvU8 buffer[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; 1626 } NVEldEvoRec; 1627 1628 /* 1629 * This structure stores information about the active per-head audio state. 1630 */ 1631 typedef struct _NVDispHeadAudioStateEvoRec { 1632 NvU32 maxFreqSupported; 1633 NVEldEvoRec eld; 1634 1635 NvBool isAudioOverHdmi : 1; 1636 NvBool supported : 1; 1637 NvBool enabled : 1; 1638 } NVDispHeadAudioStateEvoRec; 1639 1640 typedef struct _NVDispHeadInfoFrameStateEvoRec { 1641 NVT_VIDEO_INFOFRAME_CTRL ctrl; 1642 NvBool hdTimings; 1643 } NVDispHeadInfoFrameStateEvoRec; 1644 1645 /* 1646 * This structure stores information about the active per-head display state. 1647 */ 1648 typedef struct _NVDispHeadStateEvoRec { 1649 1650 /*! Cached, to preserve across modesets. */ 1651 struct NvKmsModeValidationParams modeValidationParams; 1652 1653 /* 1654 * Heads on the same NVDevEvoRec with the same non-zero 1655 * NVDispHeadStateEvoRec::allowFlipLockGroup value are eligible to 1656 * be flipLocked, from an NVKMS client point of view, if the 1657 * hardware requirements for flipLock are met. 1658 */ 1659 NvU8 allowFlipLockGroup; 1660 1661 /* 1662 * For Turing and newer, enable display composition bypass mode. 1663 * 1664 * This is intended to be used by console restore to avoid bug 2168873. 1665 */ 1666 NvBool bypassComposition : 1; 1667 1668 struct { 1669 NVT_COLOR_FORMAT colorFormat; 1670 NVT_COLORIMETRY colorimetry; 1671 NVT_COLOR_RANGE colorRange; 1672 NvU32 satCos; 1673 } procAmp; 1674 1675 /* 1676 * The activeRmId is the identifier that we use to talk to RM 1677 * about the display device(s) on this head. It is zero except 1678 * when a mode is being driven by this head. For DP MST, it is the 1679 * identifier of the displayport library group to which the driven 1680 * DP device belongs. Otherwise, it is the identifier of the connector 1681 * driven by the head. 1682 */ 1683 NvU32 activeRmId; 1684 1685 NVHwModeTimingsEvo timings; 1686 NVConnectorEvoRec *pConnectorEvo; /* NULL if the head is not active */ 1687 1688 enum nvKmsPixelDepth pixelDepth; 1689 1690 NVDispHeadAudioStateEvoRec audio; 1691 1692 enum NvKmsOutputTf tf; 1693 1694 struct { 1695 enum NvKmsHDROutputState outputState; 1696 struct NvKmsHDRStaticMetadata staticMetadata; 1697 } hdr; 1698 1699 struct { 1700 NVLutSurfaceEvoPtr pCurrSurface; 1701 NvBool outputLutEnabled : 1; 1702 NvBool baseLutEnabled : 1; 1703 } lut; 1704 1705 /* 1706 * The api head can be mapped onto the N harware heads, a frame presented 1707 * by the api head gets split horizontally into N tiles, 'tilePosition' 1708 * describe the tile presented by this hardware head. 1709 */ 1710 NvU8 tilePosition; 1711 } NVDispHeadStateEvoRec; 1712 1713 typedef struct _NVDispStereoParamsEvoRec { 1714 enum NvKmsStereoMode mode; 1715 NvBool isAegis; 1716 } NVDispStereoParamsEvoRec; 1717 1718 typedef struct _NVDispFlipOccurredEventDataEvoRec { 1719 NVDispEvoPtr pDispEvo; 1720 NvU32 apiHead; 1721 NvU32 layer; 1722 } NVDispFlipOccurredEventDataEvoRec; 1723 1724 typedef struct _NVDispApiHeadStateEvoRec { 1725 /* 1726 * The mask of hardware heads mapped onto this api head, 1727 * set to zero if the api head is not active. 1728 */ 1729 NvU32 hwHeadsMask; 1730 1731 NVDpyIdList activeDpys; /* Empty if the head is not active */ 1732 NVAttributesSetEvoRec attributes; 1733 1734 enum NvKmsOutputTf tf; 1735 nvkms_timer_handle_t *hdrToSdrTransitionTimer; 1736 1737 /* 1738 * Hardware timings which are split across hardware heads. 1739 * 1740 * XXX[2Heads1OR] The api-head state does not require to track full 1741 * hardware timings. Replace 'timings' by minimal per api-head hardware 1742 * timings information used in code. 1743 */ 1744 NVHwModeTimingsEvo timings; 1745 1746 NVDispStereoParamsEvoRec stereo; 1747 1748 struct NvKmsPoint viewPortPointIn; 1749 1750 NVDispHeadInfoFrameStateEvoRec infoFrame; 1751 1752 /* 1753 * Each head can have up to NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD 1754 * programmable Core semaphores. 1755 * 1756 * The numVblankSyncObjectsCreated will ideally always be equal to 1757 * NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD, but could be lower if errors 1758 * occured during syncpt allocation in nvRMSetupEvoCoreChannel(). 1759 */ 1760 NvU8 numVblankSyncObjectsCreated; 1761 NVVblankSyncObjectRec vblankSyncObjects[NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD]; 1762 1763 struct { 1764 struct nvkms_ref_ptr *ref_ptr; 1765 NVDispFlipOccurredEventDataEvoRec data; 1766 } flipOccurredEvent[NVKMS_MAX_LAYERS_PER_HEAD]; 1767 1768 NvU32 rmVBlankCallbackHandle; 1769 NVListRec vblankCallbackList; 1770 1771 NvBool hs10bpcHint : 1; 1772 } NVDispApiHeadStateEvoRec; 1773 1774 typedef struct _NVDispEvoRec { 1775 NvU8 gpuLogIndex; 1776 NVDevEvoPtr pDevEvo; 1777 NvU32 hotplugEventHandle; 1778 NvU32 DPIRQEventHandle; 1779 NVOS10_EVENT_KERNEL_CALLBACK_EX rmHotplugCallback; 1780 NVOS10_EVENT_KERNEL_CALLBACK_EX rmDPIRQCallback; 1781 1782 NVDispHeadStateEvoRec headState[NVKMS_MAX_HEADS_PER_DISP]; 1783 NVDispApiHeadStateEvoRec apiHeadState[NVKMS_MAX_HEADS_PER_DISP]; 1784 1785 NVDpyIdList vbiosDpyConfig[NVKMS_MAX_HEADS_PER_DISP]; 1786 1787 NvU32 isoBandwidthKBPS; 1788 NvU32 dramFloorKBPS; 1789 1790 /* 1791 * The list of physical connector display IDs. This is the union 1792 * of pConnectorEvo->displayId values, which is also the union of 1793 * pDpyEvo->id values for non-MST pDpys. 1794 */ 1795 NVDpyIdList connectorIds; 1796 1797 NVListRec connectorList; 1798 1799 NvU32 displayOwner; 1800 1801 NVListRec dpyList; 1802 1803 NVDpyIdList bootDisplays; 1804 NVDpyIdList validDisplays; 1805 NVDpyIdList connectedDisplays; 1806 1807 /* 1808 * displayPortMSTIds is a superset of dynamicDpyIds because not all DP MST 1809 * dpys are dynamic dpys. For example, the DP MST dpys that are driven by 1810 * a DP serializer connector are part of a fixed topology, and are static in 1811 * nature. 1812 */ 1813 NVDpyIdList displayPortMSTIds; /* DP MST dpys */ 1814 NVDpyIdList dynamicDpyIds; 1815 1816 NVDpyIdList muxDisplays; 1817 1818 struct { 1819 nvkms_timer_handle_t *unstallTimer; 1820 } vrr; 1821 1822 NVFrameLockEvoPtr pFrameLockEvo; 1823 struct { 1824 NVDpyId server; 1825 NVDpyIdList clients; 1826 NvBool syncEnabled; /* GPU is syncing to framelock */ 1827 NvU32 connectorIndex;/* NV30F1_GSYNC_CONNECTOR_* */ 1828 NvU32 currentServerHead; /* used for disabling */ 1829 NvU32 currentClientHeadsMask; /* used for disabling */ 1830 NvBool currentHouseSync; /* if state machine thinks house sync 1831 is enabled -- used for disabling */ 1832 1833 /* Framelock event-related data */ 1834 #define NV_FRAMELOCK_SYNC_LOSS 0 1835 #define NV_FRAMELOCK_SYNC_GAIN 1 1836 #define NV_FRAMELOCK_NUM_EVENTS 2 1837 1838 struct { 1839 NvU32 handle; 1840 NVOS10_EVENT_KERNEL_CALLBACK_EX callback; 1841 } gsyncEvent[NV_FRAMELOCK_NUM_EVENTS]; 1842 1843 } framelock; 1844 1845 /* NVDevEvoRec::pHsChannel[] is indexed by the api heads */ 1846 NVHsChannelEvoPtr pHsChannel[NVKMS_MAX_HEADS_PER_DISP]; 1847 1848 /* NVDevEvoRec::pSwapGroup[] is indexed by the api heads */ 1849 NVSwapGroupPtr pSwapGroup[NVKMS_MAX_HEADS_PER_DISP]; 1850 1851 /*! 1852 * ref_ptr to the structure. 1853 * 1854 * nvkms_timer_handle_t objects refer to the pDispEvo via references to 1855 * this, so that timers that fire after the pDispEvo has been freed can 1856 * detect that case and do nothing. 1857 */ 1858 struct nvkms_ref_ptr *ref_ptr; 1859 1860 /* 1861 * Indicates that NV_KMS_DISP_ATTRIBUTE_QUERY_DP_AUX_LOG has been queried at 1862 * least once on this device. If set, nvRmDestroyDisplays() will flush any 1863 * remaining AUX log messages to the system log. 1864 */ 1865 NvBool dpAuxLoggingEnabled; 1866 1867 struct nvkms_backlight_device *backlightDevice; 1868 } NVDispEvoRec; 1869 1870 /* 1871 * XXX[2Head1OR] Remove nvHardwareHeadToApiHead(), before implementing logic to 1872 * map multiple hardware heads onto the single api head. 1873 */ 1874 static inline NvU32 nvHardwareHeadToApiHead(const NVDevEvoRec *pDevEvo, 1875 const NvU32 head) 1876 { 1877 /* 1878 * Force a non-identity mapping between hardware heads and api heads, 1879 * to identify bugs in api head handling. 1880 */ 1881 1882 if (head < pDevEvo->numHeads) { 1883 if (!nvkms_force_api_to_hw_head_identity_mappings()) { 1884 return (pDevEvo->numHeads - 1) - head; 1885 } else { 1886 return head; 1887 } 1888 } else { 1889 nvAssert(head == NV_INVALID_HEAD); 1890 return head; 1891 } 1892 } 1893 1894 static inline NvU32 GetNextHwHead(NvU32 hwHeadsMask, const NvU32 prevHwHead) 1895 { 1896 if ((hwHeadsMask == 0x0) || 1897 ((prevHwHead != NV_INVALID_HEAD) && 1898 ((hwHeadsMask &= ~((1 << (prevHwHead + 1)) -1 )) == 0x0))) { 1899 return NV_INVALID_HEAD; 1900 } 1901 return BIT_IDX_32(LOWESTBIT(hwHeadsMask)); 1902 } 1903 1904 #define FOR_EACH_EVO_HW_HEAD_IN_MASK(__hwHeadsMask, __hwHead) \ 1905 for ((__hwHead) = GetNextHwHead((__hwHeadsMask), NV_INVALID_HEAD); \ 1906 (__hwHead) != NV_INVALID_HEAD; \ 1907 (__hwHead) = GetNextHwHead((__hwHeadsMask), (__hwHead))) 1908 1909 #define FOR_EACH_EVO_HW_HEAD(__pDispEvo, __apiHead, __hwHead) \ 1910 FOR_EACH_EVO_HW_HEAD_IN_MASK((__pDispEvo)->apiHeadState[(__apiHead)].hwHeadsMask, \ 1911 (__hwHead)) 1912 1913 static inline NvU32 nvGetPrimaryHwHead(const NVDispEvoRec *pDispEvo, 1914 const NvU32 apiHead) 1915 { 1916 return (apiHead != NV_INVALID_HEAD) ? 1917 GetNextHwHead(pDispEvo->apiHeadState[apiHead].hwHeadsMask, 1918 NV_INVALID_HEAD) : NV_INVALID_HEAD; 1919 } 1920 1921 typedef enum { 1922 NV_EVO_PASSIVE_DP_DONGLE_UNUSED, 1923 NV_EVO_PASSIVE_DP_DONGLE_DP2DVI, 1924 NV_EVO_PASSIVE_DP_DONGLE_DP2HDMI_TYPE_1, 1925 NV_EVO_PASSIVE_DP_DONGLE_DP2HDMI_TYPE_2, 1926 } NVEvoPassiveDpDongleType; 1927 1928 typedef struct NVEdidRec { 1929 NvU8 *buffer; 1930 size_t length; 1931 } NVEdidRec, *NVEdidPtr; 1932 1933 typedef struct _NVParsedEdidEvoRec { 1934 NvBool valid; 1935 NVT_EDID_INFO info; 1936 NVT_EDID_RANGE_LIMIT limits; 1937 char monitorName[NVT_EDID_MONITOR_NAME_STRING_LENGTH]; 1938 char serialNumberString[NVT_EDID_LDD_PAYLOAD_SIZE+1]; 1939 } NVParsedEdidEvoRec; 1940 1941 typedef void (*NVVBlankCallbackProc)(NVDispEvoRec *pDispEvo, 1942 NVVBlankCallbackPtr pCallbackData); 1943 1944 typedef struct _NVVBlankCallbackRec { 1945 NVListRec vblankCallbackListEntry; 1946 NVVBlankCallbackProc pCallback; 1947 void *pUserData; 1948 NvU32 apiHead; 1949 } NVVBlankCallbackRec; 1950 1951 typedef void (*NVRgLine1CallbackProc)(NVDispEvoRec *pDispEvo, 1952 const NvU32 head, 1953 NVRgLine1CallbackPtr pCallbackData); 1954 1955 typedef struct _NVRgLine1CallbackRec { 1956 NVRgLine1CallbackProc pCallbackProc; 1957 void *pUserData; 1958 } NVRgLine1CallbackRec; 1959 1960 typedef struct _NVDpyAttributeRequestedDitheringConfigRec { 1961 enum NvKmsDpyAttributeRequestedDitheringValue state; 1962 enum NvKmsDpyAttributeRequestedDitheringDepthValue depth; 1963 enum NvKmsDpyAttributeRequestedDitheringModeValue mode; 1964 } NVDpyAttributeRequestedDitheringConfig; 1965 1966 typedef struct _NVDpyEvoRec { 1967 NVListRec dpyListEntry; 1968 NVDpyId id; 1969 1970 char name[NVKMS_DPY_NAME_SIZE]; 1971 1972 NvU32 apiHead; 1973 1974 struct _NVDispEvoRec *pDispEvo; 1975 NVConnectorEvoPtr pConnectorEvo; 1976 1977 NvBool hasBacklightBrightness : 1; 1978 NvBool internal : 1; 1979 NvBool allowDVISpecPClkOverride : 1; 1980 1981 /* whether the connected dpy is HDMI capable */ 1982 NvBool hdmiCapable : 1; 1983 NvBool isVrHmd : 1; 1984 1985 /* 1986 * Maximum single link and total allowed pixel clock. This is first 1987 * reported by RM through DpyProbeMaxPixelClock, and then potentially 1988 * overridden by the EVO SOR capabilities for HDMI and DVI through 1989 * UpdateMaxPixelClock. 1990 */ 1991 NvU32 maxPixelClockKHz; 1992 NvU32 maxSingleLinkPixelClockKHz; 1993 1994 NVEdidRec edid; 1995 NVParsedEdidEvoRec parsedEdid; 1996 1997 NVDpyAttributeRequestedDitheringConfig requestedDithering; 1998 1999 enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace; 2000 enum NvKmsDpyAttributeColorRangeValue requestedColorRange; 2001 2002 NVAttributesSetEvoRec currentAttributes; 2003 2004 struct { 2005 char *addressString; 2006 NVDPLibDevicePtr pDpLibDevice; // DP Lib's notion of the device. 2007 NvBool inbandStereoSignaling; 2008 2009 NvU8 laneCount; // NV0073_CTRL_DP_DATA_SET_LANE_COUNT 2010 NvU8 linkRate; // NV0073_CTRL_DP_DATA_SET_LINK_BW 2011 enum NvKmsDpyAttributeDisplayportConnectorTypeValue connectorType; 2012 NvBool sinkIsAudioCapable; 2013 2014 struct { 2015 NvBool valid; 2016 NvU8 buffer[NVKMS_GUID_SIZE]; 2017 char str[NVKMS_GUID_STRING_SIZE]; 2018 } guid; 2019 2020 /* 2021 * When the DP serializer is in MST mode, this field is used to uniquely 2022 * identify each MST DPY that's connected to the DP serializer. 2023 * 2024 * This field is only valid for DP serializer DPYs, and pDpLibDevice 2025 * must be NULL in this case. 2026 */ 2027 NvU8 serializerStreamIndex; 2028 } dp; 2029 2030 struct { 2031 HDMI_SRC_CAPS srcCaps; 2032 HDMI_SINK_CAPS sinkCaps; 2033 } hdmi; 2034 2035 struct { 2036 NvBool ycbcr422Capable; 2037 NvBool ycbcr444Capable; 2038 } colorSpaceCaps; 2039 2040 struct { 2041 NvBool supported : 1; 2042 NvBool requiresModetimingPatching : 1; 2043 NvBool isDLP : 1; 2044 NvBool isAegis : 1; 2045 NvBool requiresVbiAdjustment : 1; 2046 NvU32 subType; 2047 int indexInOverrideTimings; 2048 } stereo3DVision; 2049 2050 struct { 2051 enum NvKmsDpyVRRType type; 2052 } vrr; 2053 2054 } NVDpyEvoRec; 2055 2056 static inline NvBool nvDpyEvoIsDPMST(const NVDpyEvoRec *pDpyEvo) 2057 { 2058 return nvDpyIdIsInDpyIdList(pDpyEvo->id, 2059 pDpyEvo->pDispEvo->displayPortMSTIds); 2060 } 2061 2062 // Return a pDpy's connector's display ID 2063 static inline NvU32 nvDpyEvoGetConnectorId(const NVDpyEvoRec *pDpyEvo) 2064 { 2065 NvU32 rmDpyId = nvDpyIdToNvU32(pDpyEvo->pConnectorEvo->displayId); 2066 2067 // This function shouldn't be used for DP MST dynamic devices. 2068 nvAssert(!nvDpyEvoIsDPMST(pDpyEvo)); 2069 nvAssert(ONEBITSET(rmDpyId)); 2070 2071 return rmDpyId; 2072 } 2073 2074 static inline 2075 NvBool nvConnectorIsInternal(const NVConnectorEvoRec *pConnectorEvo) 2076 { 2077 /* For mobile GPUs check for LVDS or embedded DisplayPort signal flag. 2078 * If found, DFP is internal*/ 2079 return (pConnectorEvo->legacyType == 2080 NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP) && 2081 (((pConnectorEvo->pDispEvo->pDevEvo->mobile) && 2082 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _SIGNAL, _LVDS, 2083 pConnectorEvo->dfpInfo))) || 2084 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _SIGNAL, _DSI, 2085 pConnectorEvo->dfpInfo)) || 2086 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _EMBEDDED_DISPLAYPORT, _TRUE, 2087 pConnectorEvo->dfpInfo))); 2088 } 2089 2090 static inline NvU32 NV_EVO_LOCK_PIN(NvU32 n) 2091 { 2092 return NV_EVO_LOCK_PIN_0 + n; 2093 } 2094 2095 static inline NvU32 NV_EVO_LOCK_PIN_INTERNAL(NvU32 n) 2096 { 2097 return NV_EVO_LOCK_PIN_INTERNAL_0 + n; 2098 } 2099 2100 static inline NvBool NV_EVO_LOCK_PIN_IS_INTERNAL(NvU32 n) 2101 { 2102 ct_assert(NV_IS_UNSIGNED(n) && NV_EVO_LOCK_PIN_INTERNAL_0 == 0); 2103 return n < NV_EVO_LOCK_PIN_0; 2104 } 2105 2106 2107 /* 2108 * Utility macro for looping over all the pConnectorsEvo on a pDispEvo. 2109 */ 2110 #define FOR_ALL_EVO_CONNECTORS(_pConnectorEvo, _pDispEvo) \ 2111 nvListForEachEntry((_pConnectorEvo), \ 2112 &(_pDispEvo)->connectorList, connectorListEntry) 2113 2114 /* 2115 * Utility macro for declaring a for loop to walk over all the 2116 * pDispEvos on a particular pDevEvo. 2117 */ 2118 #define FOR_ALL_EVO_DISPLAYS(_pDispEvo, _i, _pDevEvo) \ 2119 for ((_i) = 0, \ 2120 (_pDispEvo) = (_pDevEvo)->pDispEvo[0]; \ 2121 (_pDispEvo); \ 2122 (_i)++, (_pDispEvo) = ((_i) < (_pDevEvo)->nDispEvo) ? \ 2123 (_pDevEvo)->pDispEvo[(_i)] : NULL) 2124 2125 #define FOR_ALL_EVO_DPYS(_pDpyEvo, _dpyIdList, _pDispEvo) \ 2126 nvListForEachEntry((_pDpyEvo), &(_pDispEvo)->dpyList, dpyListEntry) \ 2127 if (nvDpyIdIsInDpyIdList((_pDpyEvo)->id, (_dpyIdList))) 2128 2129 #define FOR_ALL_EVO_FRAMELOCKS(_pFrameLockEvo) \ 2130 nvListForEachEntry(_pFrameLockEvo, &nvEvoGlobal.frameLockList, \ 2131 frameLockListEntry) 2132 2133 #define FOR_ALL_EVO_DEVS(_pDevEvo) \ 2134 nvListForEachEntry(_pDevEvo, &nvEvoGlobal.devList, devListEntry) 2135 2136 #define FOR_ALL_DEFERRED_REQUEST_FIFOS_IN_SWAP_GROUP( \ 2137 _pSwapGroup, _pDeferredRequestFifo) \ 2138 nvListForEachEntry((_pDeferredRequestFifo), \ 2139 &(_pSwapGroup)->deferredRequestFifoList, \ 2140 swapGroup.deferredRequestFifoListEntry) 2141 2142 #define FOR_EACH_SUBDEV_IN_MASK(_sd, _mask) \ 2143 FOR_EACH_INDEX_IN_MASK(32, _sd, _mask) 2144 2145 #define FOR_EACH_SUBDEV_IN_MASK_END \ 2146 FOR_EACH_INDEX_IN_MASK_END 2147 2148 static inline NVDpyEvoPtr nvGetOneArbitraryDpyEvo(NVDpyIdList dpyIdList, 2149 const NVDispEvoRec *pDispEvo) 2150 { 2151 NVDpyEvoPtr pDpyEvo; 2152 2153 nvAssert(nvDpyIdListIsASubSetofDpyIdList(dpyIdList, 2154 pDispEvo->validDisplays)); 2155 2156 FOR_ALL_EVO_DPYS(pDpyEvo, dpyIdList, pDispEvo) { 2157 return pDpyEvo; 2158 } 2159 2160 return NULL; 2161 } 2162 2163 2164 /* 2165 * Return whether or not the display devices on the connector should 2166 * be handled by the DP library. 2167 */ 2168 static inline NvBool nvConnectorUsesDPLib(const NVConnectorEvoRec 2169 *pConnectorEvo) 2170 { 2171 return (pConnectorEvo->pDpLibConnector != NULL); 2172 } 2173 2174 static inline 2175 NvBool nvConnectorIsDPSerializer(const NVConnectorEvoRec *pConnectorEvo) 2176 { 2177 return (pConnectorEvo->type == NVKMS_CONNECTOR_TYPE_DP_SERIALIZER); 2178 } 2179 2180 /* 2181 * Return whether or not the display device given is handled by the DP 2182 * library. 2183 */ 2184 static inline NvBool nvDpyUsesDPLib(const NVDpyEvoRec *pDpyEvo) 2185 { 2186 return nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo); 2187 } 2188 2189 /* 2190 * Return whether this dpy is active. The dpy is active if it is 2191 * driven by a head. 2192 */ 2193 static inline NvBool nvDpyEvoIsActive(const NVDpyEvoRec *pDpyEvo) 2194 { 2195 return (pDpyEvo->apiHead != NV_INVALID_HEAD); 2196 } 2197 2198 /* 2199 * Return true if this dpy reports an EDID supporting HDMI 3D and 2200 * isn't connected via active DisplayPort. 2201 */ 2202 static inline NvBool nvDpyEvoSupportsHdmi3D(const NVDpyEvoRec *pDpyEvo) 2203 { 2204 return (pDpyEvo->parsedEdid.valid && 2205 pDpyEvo->parsedEdid.info.HDMI3DSupported && 2206 !((pDpyEvo->pConnectorEvo->or.protocol == 2207 NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A) || 2208 (pDpyEvo->pConnectorEvo->or.protocol == 2209 NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B))); 2210 2211 } 2212 2213 static inline NvBool nvHeadIsActive(const NVDispEvoRec *pDispEvo, 2214 const NvU32 head) 2215 { 2216 return (head < ARRAY_LEN(pDispEvo->headState)) && 2217 (pDispEvo->headState[head].pConnectorEvo != NULL); 2218 } 2219 2220 static inline NvBool nvApiHeadIsActive(const NVDispEvoRec *pDispEvo, 2221 const NvU32 apiHead) 2222 { 2223 return (apiHead < ARRAY_LEN(pDispEvo->apiHeadState)) && 2224 (!nvDpyIdListIsEmpty(pDispEvo->apiHeadState[apiHead].activeDpys)); 2225 } 2226 2227 /*! 2228 * Return the mask of active heads on this pDispEvo. 2229 */ 2230 static inline NvU32 nvGetActiveHeadMask(NVDispEvoPtr pDispEvo) 2231 { 2232 NvU32 head; 2233 NvU32 headMask = 0; 2234 2235 for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { 2236 if (nvHeadIsActive(pDispEvo, head)) { 2237 headMask |= 1 << head; 2238 } 2239 } 2240 2241 return headMask; 2242 } 2243 2244 static inline NvBool nvAllHeadsInactive(const NVDevEvoRec *pDevEvo) 2245 { 2246 NVDispEvoPtr pDispEvo; 2247 NvU32 dispIndex; 2248 NvU32 head; 2249 2250 FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { 2251 for (head = 0; head < pDevEvo->numHeads; head++) { 2252 if (nvHeadIsActive(pDispEvo, head)) { 2253 return FALSE; 2254 } 2255 } 2256 } 2257 2258 return TRUE; 2259 } 2260 2261 /* 2262 * Return the list of dpys that are currently active on the given disp. 2263 */ 2264 static inline NVDpyIdList nvActiveDpysOnDispEvo(const NVDispEvoRec *pDispEvo) 2265 { 2266 NVDpyIdList dpyIdList = nvEmptyDpyIdList(); 2267 NvU32 apiHead; 2268 2269 for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { 2270 const NVDispApiHeadStateEvoRec *pApiHeadState = 2271 &pDispEvo->apiHeadState[apiHead]; 2272 2273 dpyIdList = nvAddDpyIdListToDpyIdList(dpyIdList, 2274 pApiHeadState->activeDpys); 2275 } 2276 2277 return dpyIdList; 2278 } 2279 2280 static inline NvU32 nvGpuIdOfDispEvo(const NVDispEvoRec *pDispEvo) 2281 { 2282 nvAssert(pDispEvo->displayOwner < pDispEvo->pDevEvo->numSubDevices); 2283 return pDispEvo->pDevEvo->pSubDevices[pDispEvo->displayOwner]->gpuId; 2284 } 2285 2286 static inline NvBool nvIsEmulationEvo(const NVDevEvoRec *pDevEvo) 2287 { 2288 return pDevEvo->simulationType != 2289 NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE; 2290 } 2291 2292 static inline NvBool nvIs3DVisionStereoEvo(const enum NvKmsStereoMode stereo) 2293 { 2294 return (stereo == NVKMS_STEREO_NVIDIA_3D_VISION || 2295 stereo == NVKMS_STEREO_NVIDIA_3D_VISION_PRO); 2296 } 2297 2298 /* 2299 * Utility macro for iterating over all head bits set in a head bit mask 2300 */ 2301 #define FOR_ALL_HEADS(_head, _headMask) \ 2302 for((_head) = 0; \ 2303 (_headMask) >> (_head); \ 2304 (_head)++) \ 2305 if ((_headMask) & (1 << (_head))) 2306 2307 typedef struct _NVLutSurfaceEvo { 2308 NVDevEvoPtr pDevEvo; 2309 2310 NvU32 handle; 2311 NvU32 size; 2312 2313 NvU32 dispCtxDma; 2314 2315 NvU32 allocRefCnt; /* Only used for dynamically allocated LUTs */ 2316 2317 NvU64 gpuAddress; 2318 void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; 2319 2320 /* Keep track of prefetched surfaces. */ 2321 NvU32 difrLastPrefetchPass; 2322 2323 } NVLutSurfaceEvoRec; 2324 2325 typedef struct _NVFrameLockEvo { 2326 NVListRec frameLockListEntry; 2327 2328 /* array of subdev GPU IDs */ 2329 NvU32 nGpuIds; 2330 NvU32 gpuIds[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; 2331 2332 NvU32 gsyncId; 2333 NvU32 device; /* RM device handle for this object */ 2334 2335 int fpgaIdAndRevision; /* FPGA revId (including firmware version 2336 * and board ID) */ 2337 2338 int firmwareMajorVersion; /* FPGA firmware major version */ 2339 int firmwareMinorVersion; /* FPGA firmware minor version */ 2340 NvU32 boardId; /* NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_* */ 2341 NvU32 caps; /* Various capabilities flags */ 2342 2343 NvU32 maxSyncSkew; /* Max sync skew increment */ 2344 NvU32 syncSkewResolution; /* In nanoseconds */ 2345 NvU32 maxSyncInterval; /* Max sync interval */ 2346 2347 NvU32 houseSyncUseable; 2348 2349 /* House sync mode requested by user */ 2350 enum NvKmsFrameLockAttributeHouseSyncModeValue houseSyncMode; 2351 NvU32 houseSyncModeValidValues; 2352 2353 NvBool houseSyncAssy; /* Current desired state */ 2354 NvBool houseSyncArmed; /* Current hardware state */ 2355 2356 NvU8 connectedGpuMask; /* bitmask of GPUs that are connected */ 2357 NvU8 syncReadyGpuMask; /* bitmask of GPUs that are syncReady */ 2358 2359 NvBool syncReadyLast; /* Previous NV_CTRL_FRAMELOCK_SYNC_READY 2360 * value changed either from nvctrl or 2361 * the RM, used to avoid resending events 2362 * since RM doesn't trigger a SYNC_READY 2363 * event on framelock disable */ 2364 2365 NvBool videoModeReadOnly; /* If video mode is read-only */ 2366 2367 NvU32 maxMulDivValue; /* Max sync multiply/divide value */ 2368 2369 NvBool mulDivSupported; /* Whether this board supports setting a sync 2370 * multiplier/divider; maxMulDivValue is only 2371 * valid if this is true */ 2372 2373 /* Current device state */ 2374 enum NvKmsFrameLockAttributePolarityValue polarity; 2375 NvU32 syncDelay; 2376 NvU32 syncInterval; 2377 enum NvKmsFrameLockAttributeVideoModeValue videoMode; 2378 NvU8 mulDivValue; 2379 enum NvKmsFrameLockAttributeMulDivModeValue mulDivMode; 2380 NvBool testMode; 2381 2382 } NVFrameLockEvoRec; 2383 2384 /*! 2385 * The buffer that accumulates a string with information returned to 2386 * the client. 2387 */ 2388 typedef struct _NVEvoInfoString { 2389 NvU16 length; /*! strlen(s); excludes the nul terminator */ 2390 NvU16 totalLength; /*! number of bytes in the buffer pointed to by 's' */ 2391 char *s; /*! pointer to the buffer to be written to */ 2392 } NVEvoInfoStringRec; 2393 2394 enum NvHsMapPermissions { 2395 NvHsMapPermissionsNone, 2396 NvHsMapPermissionsReadOnly, 2397 NvHsMapPermissionsReadWrite, 2398 }; 2399 2400 #define NV_HS_BAD_GPU_ADDRESS ((NvU64) -1) 2401 2402 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED1BPP ( \ 2403 NVBIT64(NvKmsSurfaceMemoryFormatI8)) 2404 2405 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED2BPP ( \ 2406 NVBIT64(NvKmsSurfaceMemoryFormatA1R5G5B5) | \ 2407 NVBIT64(NvKmsSurfaceMemoryFormatX1R5G5B5) | \ 2408 NVBIT64(NvKmsSurfaceMemoryFormatR5G6B5)) 2409 2410 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED4BPP ( \ 2411 NVBIT64(NvKmsSurfaceMemoryFormatA8R8G8B8) | \ 2412 NVBIT64(NvKmsSurfaceMemoryFormatX8R8G8B8) | \ 2413 NVBIT64(NvKmsSurfaceMemoryFormatA2B10G10R10) | \ 2414 NVBIT64(NvKmsSurfaceMemoryFormatX2B10G10R10) | \ 2415 NVBIT64(NvKmsSurfaceMemoryFormatA8B8G8R8) | \ 2416 NVBIT64(NvKmsSurfaceMemoryFormatX8B8G8R8)) 2417 2418 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED8BPP ( \ 2419 NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) | \ 2420 NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) | \ 2421 NVBIT64(NvKmsSurfaceMemoryFormatR16G16B16A16)) 2422 2423 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PACKED422 ( \ 2424 NVBIT64(NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422) | \ 2425 NVBIT64(NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422)) 2426 2427 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP420 ( \ 2428 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N420) | \ 2429 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N420)) 2430 2431 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP422 ( \ 2432 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N422) | \ 2433 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N422)) 2434 2435 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP444 ( \ 2436 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N444) | \ 2437 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N444)) 2438 2439 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP420 ( \ 2440 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N420) | \ 2441 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N420) | \ 2442 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N420) | \ 2443 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N420)) 2444 2445 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP422 ( \ 2446 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N422) | \ 2447 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N422) | \ 2448 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N422) | \ 2449 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N422)) 2450 2451 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP444 ( \ 2452 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N444) | \ 2453 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N444) | \ 2454 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N444) | \ 2455 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N444)) 2456 2457 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PLANAR444 ( \ 2458 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8___V8_N444)) 2459 2460 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PLANAR420 ( \ 2461 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8___V8_N420)) 2462 2463 struct _NVSurfaceEvoRec { 2464 /* 2465 * By default, all NVSurfaceEvoRecs will have requireCtxDma == TRUE, and 2466 * have a ctxDma allocated and placed in the display engine hash table for 2467 * each plane. 2468 * 2469 * But, if the client specified the noDisplayHardwareAccess flag, 2470 * requireCtxDma will be FALSE, and ctxDma will be 0 for all planes. 2471 * 2472 * requireCtxDma is used to remember what the client requested, so that 2473 * we correctly honor noDisplayHardwareAccess across 2474 * FreeSurfaceCtxDmasForAllOpens() / 2475 * AllocSurfaceCtxDmasForAllOpens() cycles. 2476 */ 2477 NvBool requireCtxDma; 2478 2479 struct { 2480 NvU32 rmHandle; 2481 NvU32 ctxDma; 2482 NvU32 pitch; 2483 NvU64 offset; 2484 NvU64 rmObjectSizeInBytes; 2485 } planes[NVKMS_MAX_PLANES_PER_SURFACE]; 2486 2487 struct { 2488 const struct NvKmsPerOpenDev *pOpenDev; 2489 NvKmsSurfaceHandle surfaceHandle; 2490 } owner; 2491 2492 NvU32 widthInPixels; 2493 NvU32 heightInPixels; 2494 2495 NvU32 log2GobsPerBlockY; 2496 2497 /* 2498 * GPU virtual address of the surface, in NVKMS's VA space for use by 2499 * headSurface. 2500 */ 2501 NvU64 gpuAddress; 2502 2503 /* 2504 * HeadSurface needs a CPU mapping of surfaces containing semaphores. 2505 */ 2506 void *cpuAddress[NVKMS_MAX_SUBDEVICES]; 2507 2508 enum NvKmsSurfaceMemoryLayout layout; 2509 enum NvKmsSurfaceMemoryFormat format; 2510 2511 NvKmsMemoryIsoType isoType; 2512 2513 /* 2514 * A surface has two reference counts: 2515 * 2516 * - rmRefCnt indicates how many uses of the surface reference 2517 * NVSurfaceEvoRec::planes[]::rmHandle (the surface owner who registered 2518 * the surface, EVO currently displaying the surface, an open 2519 * surface grant file descriptor). 2520 * 2521 * - structRefCnt indicates how many uses of the surface reference 2522 * the NVSurfaceEvoRec. In addition to the rmRefCnt uses, this 2523 * will also count NVKMS clients who acquired the surface 2524 * through GRANT_SURFACE/ACQUIRE_SURFACE. 2525 * 2526 * When a client registers a surface, both reference counts will 2527 * be initialized to 1. The RM surface for each plane will be unduped when 2528 * rmRefCnt reaches zero. The NVSurfaceEvoRec structure will be 2529 * freed when structRefCnt reaches zero. 2530 * 2531 * In most cases, one of the following will be true: 2532 * (rmRefCnt == 0) && (structRefCnt == 0) 2533 * (rmRefCnt != 0) && (structRefCnt != 0) 2534 * The only exception is when the owner of the surface unregisters it while 2535 * other clients still have references to it; in that case, the rmRefCnt 2536 * can drop to zero while structRefCnt is still non-zero. 2537 * 2538 * If rmRefCnt reaches zero before structRefCnt, the surface is 2539 * "orphaned": it still exists in ACQUIRE_SURFACE clients' handle 2540 * namespaces and/or granted FDs, but is not usable in subsequent API 2541 * requests (e.g., to flip, specify cursor image, etc). 2542 * 2543 * Described in a table: 2544 * 2545 * ACTION rmRefCnt structRefCnt 2546 * a) NVKMS_IOCTL_REGISTER_SURFACE =1 =1 2547 * b) flip to surface +1 +1 2548 * c) NVKMS_IOCTL_GRANT_SURFACE(grantFd) n/a +1 2549 * d) NVKMS_IOCTL_ACQUIRE_SURFACE n/a +1 2550 * e) NVKMS_IOCTL_UNREGISTER_SURFACE -1 -1 2551 * f) flip away from surface -1 -1 2552 * g) close(grantFd) n/a -1 2553 * h) NVKMS_IOCTL_RELEASE_SURFACE n/a -1 2554 * i) ..._REGISTER_DEFERRED_REQUEST_FIFO +1 +1 2555 * j) ..._UNREGISTER_DEFERRED_REQUEST_FIFO -1 -1 2556 * 2557 * (e) complements (a) 2558 * (f) complements (b) 2559 * (g) complements (c) 2560 * (h) complements (d) 2561 * (j) complements (i) 2562 */ 2563 NvU64 rmRefCnt; 2564 NvU64 structRefCnt; 2565 2566 #if NVKMS_PROCFS_ENABLE 2567 NvBool procFsFlag; 2568 #endif 2569 2570 /* 2571 * Disallow DIFR if display caching is forbidden. This will be set for 2572 * CPU accessible surfaces. 2573 */ 2574 NvBool noDisplayCaching; 2575 2576 /* Keep track of prefetched surfaces. */ 2577 NvU32 difrLastPrefetchPass; 2578 }; 2579 2580 typedef struct _NVDeferredRequestFifoRec { 2581 NVSurfaceEvoPtr pSurfaceEvo; 2582 struct NvKmsDeferredRequestFifo *fifo; 2583 2584 /* A deferred request fifo may be joined to a swapGroup. */ 2585 struct { 2586 NVSwapGroupPtr pSwapGroup; 2587 NVListRec deferredRequestFifoListEntry; 2588 NvBool ready; 2589 NvBool perEyeStereo; 2590 NvBool pendingJoined; 2591 NvBool pendingReady; 2592 NvU32 semaphoreIndex; 2593 struct NvKmsPerOpen *pOpenUnicastEvent; 2594 } swapGroup; 2595 } NVDeferredRequestFifoRec; 2596 2597 typedef struct _NVSwapGroupRec { 2598 NVListRec deferredRequestFifoList; 2599 NvBool zombie; 2600 NvBool pendingFlip; 2601 NvU32 nMembers; 2602 NvU32 nMembersReady; 2603 NvU32 nMembersPendingJoined; 2604 2605 NvU16 nClips; 2606 struct NvKmsRect *pClipList; 2607 NvBool swapGroupIsFullscreen; 2608 2609 NvU64 refCnt; 2610 } NVSwapGroupRec; 2611 2612 typedef struct { 2613 NvU32 clientHandle; 2614 2615 NVListRec devList; 2616 NVListRec frameLockList; 2617 2618 #if defined(DEBUG) 2619 NVListRec debugMemoryAllocationList; 2620 #endif 2621 2622 struct NvKmsPerOpen *nvKmsPerOpen; 2623 2624 } NVEvoGlobal; 2625 2626 extern NVEvoGlobal nvEvoGlobal; 2627 2628 /* 2629 * These enums are used during IMP validation: 2630 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE means that no changes will be made to 2631 * the current display bandwidth values. 2632 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE means that NVKMS will increase the 2633 * current display bandwidth values if required by IMP. This is typically 2634 * specified pre-modeset/flip. 2635 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST means that NVKMS may potentially 2636 * decrease the current display bandwidth values to match the current display 2637 * configuration. This is typically specified post-modeset/flip. 2638 */ 2639 typedef enum { 2640 NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE = 0, 2641 NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE = 1, 2642 NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST = 2, 2643 } NVEvoReallocateBandwidthMode; 2644 2645 typedef struct { 2646 struct { 2647 /* pTimings == NULL => this head is disabled */ 2648 const NVHwModeTimingsEvo *pTimings; 2649 enum nvKmsPixelDepth pixelDepth; 2650 const struct NvKmsUsageBounds *pUsage; 2651 NvU32 displayId; 2652 NvU32 orIndex; 2653 NvU8 orType; /* NV0073_CTRL_SPECIFIC_OR_TYPE_* */ 2654 } head[NVKMS_MAX_HEADS_PER_DISP]; 2655 2656 NvBool requireBootClocks; 2657 NVEvoReallocateBandwidthMode reallocBandwidth; 2658 } NVEvoIsModePossibleDispInput; 2659 2660 typedef struct { 2661 NvBool possible; 2662 NvU32 minRequiredBandwidthKBPS; 2663 NvU32 floorBandwidthKBPS; 2664 } NVEvoIsModePossibleDispOutput; 2665 2666 /* CRC-query specific defines */ 2667 /*! 2668 * Structure that defines information about where a single variable is stored in 2669 * the CRC32NotifierEntry structure 2670 */ 2671 typedef struct _CRC32NotifierEntryRec { 2672 NvU32 field_offset; /* Var's offset from start of CRC32Notifier Struct */ 2673 NvU32 field_base_bit; /* LSB bit index for variable in entry */ 2674 NvU32 field_extent_bit; /* MSB bit index for variable in entry */ 2675 struct NvKmsDpyCRC32 *field_frame_values; /* Array to store read field values across frames */ 2676 } CRC32NotifierEntryRec; 2677 2678 /*! 2679 * Internally identifies flag read from CRC32Notifier's Status for error-checking 2680 */ 2681 enum CRC32NotifierFlagType { 2682 NVEvoCrc32NotifierFlagCount, 2683 NVEvoCrc32NotifierFlagCrcOverflow, 2684 }; 2685 2686 /*! 2687 * Structure that defines information about where a single flag is stored in 2688 * the Status of the CRC32NotifierEntry structure 2689 */ 2690 typedef struct _CRC32NotifierEntryFlags { 2691 NvU32 flag_base_bit; /* LSB bit index for flag in entry */ 2692 NvU32 flag_extent_bit; /* MSB bit index for flag in entry */ 2693 enum CRC32NotifierFlagType flag_type; /* Type of error-checking to perform on flag */ 2694 } CRC32NotifierEntryFlags; 2695 2696 /*! 2697 * Internal Crc32NotifierRead structure used to collect multiple frames of CRC 2698 * data from a QueryCRC32 call. Arrays should be allocated to match 2699 * entry_count frames. 2700 */ 2701 typedef struct _CRC32NotifierCrcOut { 2702 /*! 2703 * Array of CRCs generated from the Compositor hardware 2704 */ 2705 struct NvKmsDpyCRC32 *compositorCrc32; 2706 2707 /*! 2708 * CRCs generated from the RG hardware, if head is driving RG/SF. 2709 */ 2710 struct NvKmsDpyCRC32 *rasterGeneratorCrc32; 2711 2712 /*! 2713 * Crc values generated from the target SF/OR depending on connector's OR type 2714 */ 2715 struct NvKmsDpyCRC32 *outputCrc32; 2716 2717 } CRC32NotifierCrcOut; 2718 2719 2720 typedef const struct _nv_evo_hal { 2721 void (*SetRasterParams) (NVDevEvoPtr pDevEvo, int head, 2722 const NVHwModeTimingsEvo *pTimings, 2723 const NVEvoColorRec *pOverscanColor, 2724 NVEvoUpdateState *updateState); 2725 void (*SetProcAmp) (NVDispEvoPtr pDispEvo, const NvU32 head, 2726 NVEvoUpdateState *updateState); 2727 void (*SetHeadControl) (NVDevEvoPtr, int sd, int head, 2728 NVEvoUpdateState *updateState); 2729 void (*SetHeadRefClk) (NVDevEvoPtr, int head, NvBool external, 2730 NVEvoUpdateState *updateState); 2731 void (*HeadSetControlOR) (NVDevEvoPtr pDevEvo, 2732 const int head, 2733 const NVHwModeTimingsEvo *pTimings, 2734 const enum nvKmsPixelDepth pixelDepth, 2735 const NvBool colorSpaceOverride, 2736 NVEvoUpdateState *updateState); 2737 void (*ORSetControl) (NVDevEvoPtr pDevEvo, 2738 const NVConnectorEvoRec *pConnectorEvo, 2739 const enum nvKmsTimingsProtocol protocol, 2740 const NvU32 orIndex, 2741 const NvU32 headMask, 2742 NVEvoUpdateState *updateState); 2743 void (*HeadSetDisplayId) (NVDevEvoPtr pDevEvo, 2744 const NvU32 head, const NvU32 displayId, 2745 NVEvoUpdateState *updateState); 2746 NvBool (*SetUsageBounds) (NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, 2747 const struct NvKmsUsageBounds *pUsage, 2748 NVEvoUpdateState *updateState); 2749 void (*Update) (NVDevEvoPtr, 2750 const NVEvoUpdateState *updateState, 2751 NvBool releaseElv); 2752 void (*IsModePossible) (NVDispEvoPtr, 2753 const NVEvoIsModePossibleDispInput *, 2754 NVEvoIsModePossibleDispOutput *); 2755 void (*PrePostIMP) (NVDispEvoPtr, NvBool isPre); 2756 void (*SetNotifier) (NVDevEvoRec *pDevEvo, 2757 const NvBool notify, 2758 const NvBool awaken, 2759 const NvU32 notifier, 2760 NVEvoUpdateState *updateState); 2761 NvBool (*GetCapabilities) (NVDevEvoPtr); 2762 void (*Flip) (NVDevEvoPtr pDevEvo, 2763 NVEvoChannelPtr pChannel, 2764 const NVFlipChannelEvoHwState *pHwState, 2765 NVEvoUpdateState *updateState, 2766 NvBool bypassComposition); 2767 void (*FlipTransitionWAR) (NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, 2768 const NVEvoSubDevHeadStateRec *pSdHeadState, 2769 const NVFlipEvoHwState *pFlipState, 2770 NVEvoUpdateState *updateState); 2771 void (*FillLUTSurface) (NVEvoLutEntryRec *pLUTBuffer, 2772 const NvU16 *red, 2773 const NvU16 *green, 2774 const NvU16 *blue, 2775 int nColorMapEntries, int depth); 2776 void (*SetLUTContextDma) (const NVDispEvoRec *pDispEvo, 2777 const int head, 2778 NVLutSurfaceEvoPtr pLutSurfEvo, 2779 NvBool enableBaseLut, 2780 NvBool enableOutputLut, 2781 NVEvoUpdateState *updateState, 2782 NvBool bypassComposition); 2783 void (*SetOutputScaler) (const NVDispEvoRec *pDispEvo, const NvU32 head, 2784 const NvU32 imageSharpeningValue, 2785 NVEvoUpdateState *updateState); 2786 void (*SetViewportPointIn) (NVDevEvoPtr pDevEvo, const int head, 2787 NvU16 x, NvU16 y, 2788 NVEvoUpdateState *updateState); 2789 void (*SetViewportInOut) (NVDevEvoPtr pDevEvo, const int head, 2790 const NVHwModeViewPortEvo *pViewPortOutMin, 2791 const NVHwModeViewPortEvo *pViewPortOut, 2792 const NVHwModeViewPortEvo *pViewPortOutMax, 2793 NVEvoUpdateState *updateState); 2794 void (*SetCursorImage) (NVDevEvoPtr pDevEvo, const int head, 2795 const NVSurfaceEvoRec *, 2796 NVEvoUpdateState *updateState, 2797 const struct NvKmsCompositionParams *pCursorCompParams); 2798 NvBool (*ValidateCursorSurface)(const NVDevEvoRec *pDevEvo, 2799 const NVSurfaceEvoRec *pSurfaceEvo); 2800 NvBool (*ValidateWindowFormat)(const enum NvKmsSurfaceMemoryFormat format, 2801 const struct NvKmsRect *sourceFetchRect, 2802 NvU32 *hwFormatOut); 2803 void (*InitCompNotifier) (const NVDispEvoRec *pDispEvo, int idx); 2804 NvBool (*IsCompNotifierComplete) (NVDispEvoPtr pDispEvo, int idx); 2805 void (*WaitForCompNotifier) (const NVDispEvoRec *pDispEvo, int idx); 2806 void (*SetDither) (NVDispEvoPtr pDispEvo, const int head, 2807 const NvBool enabled, const NvU32 type, 2808 const NvU32 algo, 2809 NVEvoUpdateState *updateState); 2810 void (*SetStallLock) (NVDispEvoPtr pDispEvo, const int head, 2811 NvBool enable, NVEvoUpdateState *updateState); 2812 void (*SetDisplayRate) (NVDispEvoPtr pDispEvo, const int head, 2813 NvBool enable, 2814 NVEvoUpdateState *updateState, 2815 NvU32 timeoutMicroseconds); 2816 void (*InitChannel) (NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel); 2817 void (*InitDefaultLut) (NVDevEvoPtr pDevEvo); 2818 void (*InitWindowMapping) (const NVDispEvoRec *pDispEvo, 2819 NVEvoModesetUpdateState *pModesetUpdateState); 2820 NvBool (*IsChannelIdle) (NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd, 2821 NvBool *result); 2822 NvBool (*IsChannelMethodPending)(NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd, 2823 NvBool *result); 2824 NvBool (*ForceIdleSatelliteChannel)(NVDevEvoPtr, 2825 const NVEvoIdleChannelState *idleChannelState); 2826 NvBool (*ForceIdleSatelliteChannelIgnoreLock)(NVDevEvoPtr, 2827 const NVEvoIdleChannelState *idleChannelState); 2828 2829 void (*AccelerateChannel)(NVDevEvoPtr pDevEvo, 2830 NVEvoChannelPtr pChannel, 2831 const NvU32 sd, 2832 const NvBool trashPendingMethods, 2833 const NvBool unblockMethodsInExecutation, 2834 NvU32 *pOldAccelerators); 2835 2836 void (*ResetChannelAccelerators)(NVDevEvoPtr pDevEvo, 2837 NVEvoChannelPtr pChannel, 2838 const NvU32 sd, 2839 const NvBool trashPendingMethods, 2840 const NvBool unblockMethodsInExecutation, 2841 NvU32 oldAccelerators); 2842 2843 NvBool (*AllocRmCtrlObject) (NVDevEvoPtr); 2844 void (*FreeRmCtrlObject) (NVDevEvoPtr); 2845 void (*SetImmPointOut) (NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd, 2846 NVEvoUpdateState *updateState, 2847 NvU16 x, NvU16 y); 2848 void (*StartCRC32Capture) (NVDevEvoPtr pDevEvo, 2849 NVEvoDmaPtr pDma, 2850 NVConnectorEvoPtr pConnectorEvo, 2851 const enum nvKmsTimingsProtocol protocol, 2852 const NvU32 orIndex, 2853 NvU32 head, 2854 NvU32 sd, 2855 NVEvoUpdateState *updateState /* out */); 2856 void (*StopCRC32Capture) (NVDevEvoPtr pDevEvo, 2857 NvU32 head, 2858 NVEvoUpdateState *updateState /* out */); 2859 NvBool (*QueryCRC32) (NVDevEvoPtr pDevEvo, 2860 NVEvoDmaPtr pDma, 2861 NvU32 sd, 2862 NvU32 entry_count, 2863 CRC32NotifierCrcOut *crc32 /* out */, 2864 NvU32 *numCRC32 /* out */); 2865 void (*GetScanLine) (const NVDispEvoRec *pDispEvo, 2866 const NvU32 head, 2867 NvU16 *pScanLine, 2868 NvBool *pInBlankingPeriod); 2869 void (*ConfigureVblankSyncObject) (NVDevEvoPtr pDevEvo, 2870 NvU16 rasterLine, 2871 NvU32 head, 2872 NvU32 semaphoreIndex, 2873 NvU32 hCtxDma, 2874 NVEvoUpdateState* pUpdateState); 2875 2876 void (*SetDscParams) (const NVDispEvoRec *pDispEvo, 2877 const NvU32 head, 2878 const NVHwModeTimingsEvo *pTimings, 2879 const enum nvKmsPixelDepth pixelDepth); 2880 2881 void (*EnableMidFrameAndDWCFWatermark)(NVDevEvoPtr pDevEvo, 2882 NvU32 sd, 2883 NvU32 head, 2884 NvBool enable, 2885 NVEvoUpdateState *pUpdateState); 2886 2887 NvU32 (*GetActiveViewportOffset)(NVDispEvoRec *pDispEvo, NvU32 head); 2888 2889 void (*ClearSurfaceUsage) (NVDevEvoPtr pDevEvo, 2890 NVSurfaceEvoPtr pSurfaceEvo); 2891 2892 NvBool (*ComputeWindowScalingTaps)(const NVDevEvoRec *pDevEvo, 2893 const NVEvoChannel *pChannel, 2894 NVFlipChannelEvoHwState *pHwState); 2895 2896 const NVEvoScalerCaps* (*GetWindowScalingCaps)(const NVDevEvoRec *pDevEvo); 2897 2898 struct { 2899 NvU32 supportsNonInterlockedUsageBoundsUpdate :1; 2900 NvU32 supportsDisplayRate :1; 2901 NvU32 supportsFlipLockRGStatus :1; 2902 NvU32 needDefaultLutSurface :1; 2903 NvU32 hasUnorm16OLUT :1; 2904 NvU32 supportsDigitalVibrance :1; 2905 NvU32 supportsImageSharpening :1; 2906 NvU32 supportsHDMIVRR :1; 2907 NvU32 supportsCoreChannelSurface :1; 2908 NvU32 supportsHDMIFRL :1; 2909 NvU32 supportsSetStorageMemoryLayout :1; 2910 NvU32 supportsIndependentAcqRelSemaphore :1; 2911 NvU32 supportsCoreLut :1; 2912 NvU32 supportsSynchronizedOverlayPositionUpdate :1; 2913 NvU32 supportsVblankSyncObjects :1; 2914 NvU32 requiresScalingTapsInBothDimensions :1; 2915 2916 NvU32 supportedDitheringModes; 2917 size_t impStructSize; 2918 NVEvoScalerTaps minScalerTaps; 2919 NvU64 xEmulatedSurfaceMemoryFormats; 2920 } caps; 2921 } NVEvoHAL, *NVEvoHALPtr; 2922 2923 typedef const struct _nv_evo_cursor_hal { 2924 NvU32 klass; 2925 2926 void (*MoveCursor) (NVDevEvoPtr, NvU32 sd, NvU32 head, 2927 NvS16 x, NvS16 y); 2928 void (*ReleaseElv) (NVDevEvoPtr, NvU32 sd, NvU32 head); 2929 2930 struct { 2931 NvU16 maxSize; 2932 } caps; 2933 } NVEvoCursorHAL, *NVEvoCursorHALPtr; 2934 2935 NvU32 nvEvoGetHeadSetStoragePitchValue(const NVDevEvoRec *pDevEvo, 2936 enum NvKmsSurfaceMemoryLayout layout, 2937 NvU32 pitch); 2938 2939 NvBool nvEvoGetHeadSetControlCursorValue90(const NVDevEvoRec *pDevEvo, 2940 const NVSurfaceEvoRec *pSurfaceEvo, 2941 NvU32 *pValue); 2942 2943 static inline NvBool nvEvoScalingUsageBoundsEqual( 2944 const struct NvKmsScalingUsageBounds *a, 2945 const struct NvKmsScalingUsageBounds *b) 2946 { 2947 return (a->maxVDownscaleFactor == b->maxVDownscaleFactor) && 2948 (a->maxHDownscaleFactor == b->maxHDownscaleFactor) && 2949 (a->vTaps == b->vTaps) && 2950 (a->vUpscalingAllowed == b->vUpscalingAllowed); 2951 } 2952 2953 static inline NvBool 2954 nvEvoLayerUsageBoundsEqual(const struct NvKmsUsageBounds *a, 2955 const struct NvKmsUsageBounds *b, 2956 const NvU32 layer) 2957 { 2958 return (a->layer[layer].usable == b->layer[layer].usable) && 2959 (a->layer[layer].supportedSurfaceMemoryFormats == 2960 b->layer[layer].supportedSurfaceMemoryFormats) && 2961 nvEvoScalingUsageBoundsEqual(&a->layer[layer].scaling, 2962 &b->layer[layer].scaling); 2963 } 2964 2965 #ifdef __cplusplus 2966 }; 2967 #endif 2968 2969 #endif /* __NVKMS_TYPES_H__ */ 2970