1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __NVKMS_TYPES_H__ 25 #define __NVKMS_TYPES_H__ 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #include "nvidia-modeset-os-interface.h" 32 33 #include "nvctassert.h" 34 #include "nv_list.h" 35 36 #include <ctrl/ctrl0073/ctrl0073specific.h> /* NV0073_CTRL_SPECIFIC_OR_PROTOCOL_* */ 37 #include <ctrl/ctrl0073/ctrl0073system.h> /* NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE */ 38 #include <ctrl/ctrl0000/ctrl0000gpu.h> /* NV0000_CTRL_GPU_MAX_ATTACHED_GPUS */ 39 #include <ctrl/ctrl0080/ctrl0080unix.h> /* NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO */ 40 #include <ctrl/ctrl2080/ctrl2080gpu.h> /* NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_* */ 41 #include <ctrl/ctrl30f1.h> /* NV30F1_CTRL_MAX_GPUS_PER_GSYNC */ 42 #include <ctrl/ctrl5070/ctrl5070system.h> /* NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE */ 43 #include <ctrl/ctrl0073/ctrl0073dfp.h> 44 45 #include "nvkms-api.h" 46 #include "nvkms-prealloc-types.h" 47 48 #include "nvos.h" 49 50 #include "nv_common_utils.h" 51 #include "nv_assert.h" 52 #include "unix_rm_handle.h" 53 54 #include "nvmisc.h" 55 56 #include "nvidia-push-init.h" 57 58 #include "timing/nvtiming.h" 59 #include "timing/nvt_dsc_pps.h" 60 #include "hdmipacket/nvhdmi_frlInterface.h" // HDMI_{SRC,SINK}_CAPS 61 62 #include <stddef.h> 63 64 #if defined(DEBUG) || defined(DEVELOP) 65 #define NVKMS_PROCFS_ENABLE 1 66 #else 67 #define NVKMS_PROCFS_ENABLE 0 68 #endif 69 70 #define NV_DMA_EVO_PUSH_BUFFER_SIZE (4 * 1024) 71 #define NV_DMA_EVO_PUSH_BUFFER_PAD_SIZE (4 * 12) 72 #define NV_DMA_EVO_NOTIFIER_SIZE 4096 73 74 #define NV_NUM_EVO_LUT_ENTRIES 1025 75 /* 76 * Size of the nvdisplay 3 LUT variable segment size header, in LUT entries 77 * (which are 8 bytes each). 78 */ 79 #define NV_LUT_VSS_HEADER_SIZE 4 80 81 #define NV_EVO_SUBDEV_STACK_SIZE 10 82 83 #define NV_DP_READ_EDID_RETRIES 18 84 #define NV_DP_REREAD_EDID_DELAY_USEC 500 /* in microseconds */ 85 86 #define NV_EVO_SURFACE_ALIGNMENT 0x1000 87 88 /* 89 * Prior to nvdisplay 4.0, the final address for all scanout surfaces must be 90 * 256B-aligned. 91 * 92 * For nvdisplay 4.0, the final address for all scanout surfaces must be 93 * 512B-aligned for GPU, and 1KB-aligned for Tegra. 94 * 95 * NVKMS already uses NV_EVO_SURFACE_ALIGNMENT to force 4KB-alignment for the 96 * base address of each scanout surface. As such, we're forcing 1KB-alignment 97 * for the corresponding ctxdma offsets in order to be compatible with all 98 * display architectures. 99 */ 100 #define NV_SURFACE_OFFSET_ALIGNMENT_SHIFT 10 101 102 #define NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH 6U /* 64 bytes (2^6) */ 103 #define NVKMS_BLOCK_LINEAR_GOB_WIDTH ((NvU32)1 << NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH) 104 105 #define NVKMS_BLOCK_LINEAR_LOG_GOB_HEIGHT 3U /* 8 rows (2^3) */ 106 #define NVKMS_BLOCK_LINEAR_GOB_HEIGHT ((NvU32)1 << NVKMS_BLOCK_LINEAR_LOG_GOB_HEIGHT) 107 108 #define NV_INVALID_OR 0xFFFFFFFF 109 110 #define NVKMS_RM_HEAP_ID 0xDCBA 111 112 #define NVKMS_MAX_WINDOWS_PER_DISP 32 113 114 #define NV_SYNCPT_GLOBAL_TABLE_LENGTH 1024 115 116 #define HEAD_MASK_QUERY(_mask, _head) (!!((_mask) & (1 << (_head)))) 117 #define HEAD_MASK_SET(_mask, _head) ((_mask) | (1 << (_head))) 118 #define HEAD_MASK_UNSET(_mask, _head) ((_mask) & ~(1 << (_head))) 119 120 #define NVKMS_COMPOSITION_FOR_MATCH_BITS(__colorKeySelect, __match) \ 121 for ((__match) = (((__colorKeySelect) == \ 122 NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE) ? 1 : 0); \ 123 (__match) <= 1; (__match)++) 124 125 typedef struct _NVEvoApiHandlesRec *NVEvoApiHandlesPtr; 126 typedef struct _NVEvoSubDeviceRec *NVSubDeviceEvoPtr; 127 typedef struct _NVEvoDevRec *NVDevEvoPtr; 128 typedef struct _NVDIFRStateEvoRec *NVDIFRStateEvoPtr; 129 typedef struct _NVDmaBufferEvoRec *NVDmaBufferEvoPtr; 130 typedef struct _NVEvoChannel *NVEvoChannelPtr; 131 typedef struct _NVEvoHeadControl *NVEvoHeadControlPtr; 132 typedef struct _NVEvoCapabilities *NVEvoCapabilitiesPtr; 133 typedef struct _NVEvoSubDevHeadStateRec *NVEvoSubDevHeadStatePtr; 134 typedef struct _NVEvoSubDevRec *NVEvoSubDevPtr; 135 typedef struct _NVEvoColorRec *NVEvoColorPtr; 136 typedef struct _NVHwModeViewPortEvo *NVHwModeViewPortEvoPtr; 137 typedef struct _NVHwModeTimingsEvo *NVHwModeTimingsEvoPtr; 138 typedef struct _NVConnectorEvoRec *NVConnectorEvoPtr; 139 typedef struct _NVVblankSyncObjectRec *NVVblankSyncObjectPtr; 140 typedef struct _NVDispHeadStateEvoRec *NVDispHeadStateEvoPtr; 141 typedef struct _NVDispEvoRec *NVDispEvoPtr; 142 typedef struct _NVParsedEdidEvoRec *NVParsedEdidEvoPtr; 143 typedef struct _NVVBlankCallbackRec *NVVBlankCallbackPtr; 144 typedef struct _NVRgLine1CallbackRec *NVRgLine1CallbackPtr; 145 typedef struct _NVDpyEvoRec *NVDpyEvoPtr; 146 typedef struct _NVLutSurfaceEvo *NVLutSurfaceEvoPtr; 147 typedef struct _NVFrameLockEvo *NVFrameLockEvoPtr; 148 typedef struct _NVEvoInfoString *NVEvoInfoStringPtr; 149 typedef struct _NVSurfaceEvoRec NVSurfaceEvoRec, *NVSurfaceEvoPtr; 150 typedef struct _NVDeferredRequestFifoRec *NVDeferredRequestFifoPtr; 151 typedef struct _NVSwapGroupRec *NVSwapGroupPtr; 152 typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; 153 typedef struct _NVEvoRasterLockTopology *RasterLockTopologyPtr; 154 155 /* 156 * _NVHs*EvoRec are defined in nvkms-headsurface-priv.h; they are intentionally 157 * opaque outside of the nvkms-headsurface code. 158 */ 159 typedef struct _NVHsDeviceEvoRec *NVHsDeviceEvoPtr; 160 typedef struct _NVHsChannelEvoRec *NVHsChannelEvoPtr; 161 typedef struct _NVHsSurfaceRec *NVHsSurfacePtr; 162 163 /* _nv_dplibXXX are defined in dp/nvdp-connector-event-sink.h */ 164 typedef struct _nv_dplibconnector NVDPLibConnectorRec, *NVDPLibConnectorPtr; 165 typedef struct _nv_dplibdevice NVDPLibDeviceRec, *NVDPLibDevicePtr; 166 typedef struct __nv_dplibmodesetstate NVDPLibModesetStateRec, *NVDPLibModesetStatePtr; 167 168 /* _nv_dplibtimer is defined in nvdp-timer.hpp */ 169 typedef struct _nv_dplibtimer NVDPLibTimerRec, *NVDPLibTimerPtr; 170 171 typedef struct _NVEvoApiHandlesRec { 172 void **pointers; /* Dynamically allocated array of pointers. */ 173 NvU32 numPointers; /* Number of elements in pointers array. */ 174 NvU32 defaultSize; 175 } NVEvoApiHandlesRec; 176 177 typedef struct _NVEvoDma 178 { 179 NvU32 memoryHandle; 180 NvU32 ctxHandle; 181 182 NvU64 limit; 183 184 /* Whether this is sysmem, or vidmem accessed through a BAR1 mapping. */ 185 NvBool isBar1Mapping; 186 187 struct { 188 NvU8 vrrNotifierNextSlot; 189 } vrrNotifierHead[NV_MAX_HEADS]; 190 191 void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; 192 } NVEvoDma, *NVEvoDmaPtr; 193 194 typedef struct _NVDmaBufferEvoRec 195 { 196 NVEvoDma dma; 197 198 NvU32 channel_handle; // handles 199 NvU32 num_channels; 200 void *control[NVKMS_MAX_SUBDEVICES]; 201 NvU32 *base; // Push buffer start pointer 202 NvU32 *buffer;// Push buffer current pointer 203 NvU32 *end; // Push buffer end pointer 204 NvU32 offset_max; // Push buffer max offset (in bytes) 205 NvU32 put_offset; // Push buffer last kicked off offset 206 NvU32 fifo_free_count; // fifo free space (in words) 207 NvU32 currentSubDevMask; 208 NVDevEvoPtr pDevEvo; 209 } NVDmaBufferEvoRec; 210 211 /* EVO capabilities */ 212 typedef struct { 213 NvBool flipLock; 214 NvBool stereo; 215 NvBool scanLock; 216 } NVEvoLockPinCaps; 217 #define NV_EVO_NUM_LOCK_PIN_CAPS 16 218 219 typedef struct { 220 NvBool supportsInterlaced; 221 NvBool supportsSemiPlanar; 222 NvBool supportsPlanar; 223 NvBool supportsHVFlip; 224 NvBool supportsDSI; 225 } NVEvoMiscCaps; 226 227 static inline NvU8 NVEvoScalerTapsToNum(NVEvoScalerTaps taps) 228 { 229 NvU8 numTaps = 1; 230 231 switch (taps) { 232 case NV_EVO_SCALER_8TAPS: 233 numTaps = 8; 234 break; 235 case NV_EVO_SCALER_5TAPS: 236 numTaps = 5; 237 break; 238 case NV_EVO_SCALER_3TAPS: 239 numTaps = 3; 240 break; 241 case NV_EVO_SCALER_2TAPS: 242 numTaps = 2; 243 break; 244 case NV_EVO_SCALER_1TAP: 245 numTaps = 1; 246 break; 247 } 248 249 return numTaps; 250 } 251 252 #define NV_EVO_SCALE_FACTOR_1X (1 << 10) 253 #define NV_EVO_SCALE_FACTOR_2X (2 << 10) 254 #define NV_EVO_SCALE_FACTOR_3X (3 << 10) 255 #define NV_EVO_SCALE_FACTOR_4X (4 << 10) 256 257 typedef struct { 258 NvU32 maxPixelsVTaps; 259 NvU16 maxVDownscaleFactor; /* Scaled by 1024 */ 260 NvU16 maxHDownscaleFactor; /* Scaled by 1024 */ 261 } NVEvoScalerTapsCaps; 262 263 typedef struct { 264 NvBool present; 265 NVEvoScalerTapsCaps taps[NV_EVO_SCALER_TAPS_MAX + 1]; 266 } NVEvoScalerCaps; 267 268 typedef struct { 269 NvBool usable; 270 NvU32 maxPClkKHz; 271 NvBool supportsHDMIYUV420HW; 272 NVEvoScalerCaps scalerCaps; 273 } NVEvoHeadCaps; 274 #define NV_EVO_NUM_HEAD_CAPS 8 275 276 typedef struct { 277 NvBool dualTMDS; 278 NvU32 maxTMDSClkKHz; 279 } NVEvoSorCaps; 280 #define NV_EVO_NUM_SOR_CAPS 8 281 282 typedef struct { 283 } NVEvoPiorCaps; 284 #define NV_EVO_NUM_PIOR_CAPS 4 285 286 typedef struct { 287 NvBool usable; 288 NvBool csc0MatricesPresent; 289 NvBool cscLUTsPresent; 290 NvBool csc1MatricesPresent; 291 NvBool tmoPresent; 292 NVEvoScalerCaps scalerCaps; 293 } NVEvoWindowCaps; 294 #define NV_EVO_NUM_WINDOW_CAPS 32 295 296 typedef NvU64 NVEvoChannelMask; 297 298 #define NV_EVO_CHANNEL_MASK_CORE 0:0 299 #define NV_EVO_CHANNEL_MASK_CORE_ENABLE 1 300 #define NV_EVO_CHANNEL_MASK_CORE_DISABLE 0 301 #define NV_EVO_CHANNEL_MASK_WINDOW_FIELD 32:1 302 #define NV_EVO_CHANNEL_MASK_WINDOW(_n) (1+(_n)):(1+(_n)) 303 #define NV_EVO_CHANNEL_MASK_WINDOW__SIZE 32 304 #define NV_EVO_CHANNEL_MASK_WINDOW_ENABLE 1 305 #define NV_EVO_CHANNEL_MASK_WINDOW_DISABLE 0 306 #define NV_EVO_CHANNEL_MASK_CURSOR_FIELD 40:33 307 #define NV_EVO_CHANNEL_MASK_CURSOR(_n) (33+(_n)):(33+(_n)) 308 #define NV_EVO_CHANNEL_MASK_CURSOR__SIZE 8 309 #define NV_EVO_CHANNEL_MASK_CURSOR_ENABLE 1 310 #define NV_EVO_CHANNEL_MASK_CURSOR_DISABLE 0 311 #define NV_EVO_CHANNEL_MASK_BASE_FIELD 44:41 312 #define NV_EVO_CHANNEL_MASK_BASE(_n) (41+(_n)):(41+(_n)) 313 #define NV_EVO_CHANNEL_MASK_BASE__SIZE 4 314 #define NV_EVO_CHANNEL_MASK_BASE_ENABLE 1 315 #define NV_EVO_CHANNEL_MASK_BASE_DISABLE 0 316 #define NV_EVO_CHANNEL_MASK_OVERLAY_FIELD 48:45 317 #define NV_EVO_CHANNEL_MASK_OVERLAY(_n) (45+(_n)):(45+(_n)) 318 #define NV_EVO_CHANNEL_MASK_OVERLAY__SIZE 4 319 #define NV_EVO_CHANNEL_MASK_OVERLAY_ENABLE 1 320 #define NV_EVO_CHANNEL_MASK_OVERLAY_DISABLE 0 321 /* Window Immediate channels get only one bit. */ 322 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM 49:49 323 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM_ENABLE 1 324 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM_DISABLE 0 325 326 #define NV_EVO_CHANNEL_MASK_WINDOW_ALL \ 327 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_WINDOW_FIELD) 328 #define NV_EVO_CHANNEL_MASK_CURSOR_ALL \ 329 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_CURSOR_FIELD) 330 #define NV_EVO_CHANNEL_MASK_BASE_ALL \ 331 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_BASE_FIELD) 332 #define NV_EVO_CHANNEL_MASK_OVERLAY_ALL \ 333 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_OVERLAY_FIELD) 334 335 static inline NvU32 NV_EVO_CHANNEL_MASK_POPCOUNT(NvU64 mask) 336 { 337 // It's tempting to use __builtin_popcountll here, but that depends on 338 // intrinsics not available to nvkms in the kernel. 339 return nvPopCount64(mask); 340 } 341 342 static inline NvU32 NV_EVO_CHANNEL_MASK_BASE_HEAD_NUMBER(NvU64 mask) 343 { 344 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1); 345 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _BASE_FIELD, mask)); 346 } 347 static inline NvU32 NV_EVO_CHANNEL_MASK_OVERLAY_HEAD_NUMBER(NvU64 mask) 348 { 349 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1); 350 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _OVERLAY_FIELD, mask)); 351 } 352 static inline NvU32 NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(NvU64 mask) 353 { 354 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1); 355 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _WINDOW_FIELD, mask)); 356 } 357 358 /* EVO structures */ 359 360 typedef struct { 361 struct { 362 NVEvoChannelMask channelMask; 363 NVEvoChannelMask noCoreInterlockMask; 364 /* Each channel in this mask was programmed with a "flip lock 365 * qualifying" flip. */ 366 NVEvoChannelMask flipLockQualifyingMask; 367 /* Channels set here are transitioning from NULL ctxdma to non-NULL 368 * ctxdma or vice-versa on this update. Only necessary/valid on Turing 369 * (class C5*). */ 370 NVEvoChannelMask flipTransitionWAR; 371 372 struct { 373 NvBool vrrTearing; 374 } base[NVKMS_MAX_HEADS_PER_DISP]; 375 376 /* 377 * Window immediate channels with pending methods are represented 378 * here by NV_EVO_CHANNEL_MASK_WINDOW(n) for window immediate 379 * channel n. 380 */ 381 NVEvoChannelMask winImmChannelMask; 382 383 /* 384 * Each window channel NV_EVO_CHANNEL_MASK_WINDOW(n) needs to 385 * be interlocked with its corresponding window immediate channel n. 386 */ 387 NVEvoChannelMask winImmInterlockMask; 388 389 } subdev[NVKMS_MAX_SUBDEVICES]; 390 391 } NVEvoUpdateState; 392 393 struct _NVEvoModesetUpdateState { 394 NVEvoUpdateState updateState; 395 NVDpyIdList connectorIds; 396 const NVDPLibModesetStateRec 397 *pDpLibModesetState[NVKMS_MAX_HEADS_PER_DISP]; 398 NvBool windowMappingChanged; 399 struct { 400 struct _NVEvoModesetUpdateStateOneLayer { 401 struct nvkms_ref_ptr *ref_ptr; 402 NvBool changed; 403 } layer[NVKMS_MAX_LAYERS_PER_HEAD]; 404 } flipOccurredEvent[NVKMS_MAX_HEADS_PER_DISP]; 405 }; 406 407 typedef struct { 408 struct { 409 NVEvoChannelMask channelMask; 410 } subdev[NVKMS_MAX_SUBDEVICES]; 411 } NVEvoIdleChannelState; 412 413 typedef struct { 414 NvU8 validTimeStampBits; 415 NvBool tearingFlips :1; 416 NvBool vrrTearingFlips :1; 417 NvBool perEyeStereoFlips :1; 418 } NVEvoChannelCaps; 419 420 enum NVEvoImmChannel { 421 NV_EVO_IMM_CHANNEL_NONE, 422 NV_EVO_IMM_CHANNEL_PIO, 423 NV_EVO_IMM_CHANNEL_DMA, 424 }; 425 426 typedef struct { 427 NvU32 handle; 428 void *control[NVKMS_MAX_SUBDEVICES]; 429 } NVEvoPioChannel; 430 431 /*! basic syncpt structure used for pre and post syncpt usage */ 432 typedef struct _NVEvoSyncpt { 433 /*! syncpt id (only useful for post-syncpt) */ 434 NvU32 id; 435 /*! bitmask of channels using this syncpt */ 436 NVEvoChannelMask channelMask; 437 /*! handle of context dma allocated to this syncpt */ 438 NvU32 hCtxDma; 439 /*! handle of syncpt object */ 440 NvU32 hSyncpt; 441 /*! stores syncpt max value */ 442 NvU32 syncptMaxVal; 443 } NVEvoSyncpt; 444 445 /* Tracks internal state of a vblank sync object. */ 446 typedef struct _NVVblankSyncObjectRec { 447 /* Whether the vblank sync object is currently in use by some client. */ 448 NvBool inUse; 449 450 /* Whether the vblank sync object is enabled or disabled. */ 451 NvBool enabled; 452 453 /* 454 * The index of this Rec inside of the HeadState's vblankSyncObjects array. 455 * Also corresponds with the index of the sync object in hardware. 456 */ 457 NvU32 index; 458 459 /* 460 * This syncpoint object should be created as part of 461 * nvRmSetupEvoCoreChannel(). 462 */ 463 NVEvoSyncpt evoSyncpt; 464 } NVVblankSyncObjectRec; 465 466 /* EVO channel, encompassing multiple subdevices and a single pushbuf */ 467 typedef struct _NVEvoChannel { 468 /* Pointer to array of per subdev notifier dma structs */ 469 NVEvoDmaPtr notifiersDma; 470 471 NvU32 hwclass; 472 NvU32 instance; 473 NVEvoChannelMask channelMask; /* only one bit should be set */ 474 475 NVDmaBufferEvoRec pb; 476 477 NVOS10_EVENT_KERNEL_CALLBACK_EX completionNotifierEventCallback; 478 const struct nvkms_ref_ptr *completionNotifierEventRefPtr; 479 NvU32 completionNotifierEventHandle; 480 481 /* 482 * GV100 timestamped flips need a duplicate update which only changes 483 * TIMESTAMP_MODE and MIN_PRESENT_INTERVAL fields in SET_PRESENT_CONTROL; 484 * to allow updating these fields without changing anything else in 485 * SET_PRESENT_CONTROL, normal updates to SET_PRESENT_CONTROL are cached 486 * here. (bug 1990958) 487 */ 488 NvU32 oldPresentControl; 489 490 // On Turing, RM wants to be notified when the tearing mode changes. 491 NvBool oldTearingMode; 492 493 struct { 494 enum NVEvoImmChannel type; 495 union { 496 NVEvoPioChannel *pio; 497 struct _NVEvoChannel *dma; 498 } u; 499 } imm; 500 501 NVEvoChannelCaps caps; 502 503 NVEvoSyncpt postSyncpt; 504 505 struct { 506 NvBool enabled; 507 NvU32 srcMaxLum; 508 NvU32 targetMaxLums[NVKMS_MAX_SUBDEVICES]; 509 } tmoParams; 510 } NVEvoChannel; 511 512 typedef enum { 513 NV_EVO_NO_LOCK, 514 NV_EVO_FRAME_LOCK, 515 NV_EVO_RASTER_LOCK, 516 } NVEvoLockMode; 517 518 typedef enum { 519 NV_EVO_LOCK_PIN_ERROR = -1, 520 NV_EVO_LOCK_PIN_INTERNAL_0 = 0, 521 NV_EVO_LOCK_PIN_0 = 0x20, 522 } NVEvoLockPin; 523 524 typedef struct _NVEvoHeadControl { 525 NvBool interlaced; 526 NVEvoLockMode clientLock; 527 NVEvoLockPin clientLockPin; 528 int clientLockoutWindow; 529 NVEvoLockMode serverLock; 530 NVEvoLockPin serverLockPin; 531 NvBool flipLock; 532 NVEvoLockPin flipLockPin; 533 NVEvoLockPin stereoPin; 534 535 NvBool mergeMode; 536 NvBool setLockOffsetX; 537 538 NvU32 stallLockPin; 539 NvBool useStallLockPin; 540 NvBool crashLockUnstallMode; 541 542 /* 543 * Whether or not this GPU is stereo locked. True if all heads are either 544 * frame or raster locked, and all heads are driving non-interlaced modes. 545 */ 546 NvBool stereoLocked; 547 548 /* 549 * Whether or not this head is driving a HDMI 3D frame packed mode. Used 550 * in headcontrol only on >=GV100. 551 */ 552 NvBool hdmi3D; 553 554 /* 555 * Whether or not this head is driving a mode requiring the HW YUV420 556 * packer. Used in headcontrol only on >=nvdisplay 4.0. 557 */ 558 NvBool hwYuv420; 559 560 /* This isn't actually part of HeadControl, but it's convenient */ 561 NvU32 lockChainPosition; 562 } NVEvoHeadControl; 563 564 typedef struct _NVEvoCapabilities { 565 NVEvoLockPinCaps pin[NV_EVO_NUM_LOCK_PIN_CAPS]; 566 NVEvoMiscCaps misc; 567 NVEvoHeadCaps head[NV_EVO_NUM_HEAD_CAPS]; 568 NVEvoSorCaps sor[NV_EVO_NUM_SOR_CAPS]; 569 NVEvoPiorCaps pior[NV_EVO_NUM_PIOR_CAPS]; 570 NVEvoWindowCaps window[NV_EVO_NUM_WINDOW_CAPS]; 571 } NVEvoCapabilities; 572 573 typedef struct { 574 NVSurfaceEvoPtr pSurfaceEvo; 575 enum NvKmsNIsoFormat format; 576 NvU16 offsetInWords; 577 } NVFlipNIsoSurfaceEvoHwState; 578 579 typedef struct { 580 NVFlipNIsoSurfaceEvoHwState surface; 581 NvBool awaken; 582 } NVFlipCompletionNotifierEvoHwState; 583 584 typedef struct { 585 NvBool usingSyncpt; 586 union { 587 struct { 588 NVFlipNIsoSurfaceEvoHwState acquireSurface; 589 NvU32 acquireValue; 590 NVFlipNIsoSurfaceEvoHwState releaseSurface; 591 NvU32 releaseValue; 592 } semaphores; 593 struct { 594 NvBool isPreSyncptSpecified; 595 NvU32 preSyncpt; 596 NvU32 preValue; 597 598 NvU32 postCtxDma; 599 NvU32 postValue; 600 } syncpts; 601 } u; 602 } NVFlipSyncObjectEvoHwState; 603 604 typedef struct { 605 NVLutSurfaceEvoPtr pLutSurfaceEvo; 606 } NVFlipLutHwState; 607 608 typedef struct { 609 NVSurfaceEvoPtr pSurfaceEvo; 610 NvS16 x, y; 611 612 struct NvKmsCompositionParams cursorCompParams; 613 } NVFlipCursorEvoHwState; 614 615 typedef struct { 616 NVSurfaceEvoPtr pSurfaceEvo[NVKMS_MAX_EYES]; 617 NVFlipCompletionNotifierEvoHwState completionNotifier; 618 NVFlipSyncObjectEvoHwState syncObject; 619 620 // Non-zero timeStamp value is only allowed if the channel's 621 // 'timeStampFlipBits' capability is > 0. 622 NvU64 timeStamp; 623 NvU8 minPresentInterval; 624 // True means immediate or tearing flip. False means flip-at-vblank. 625 NvBool tearing; 626 // The tearing mode passed to RM's VRR code via 627 // NV_VRR_TRAP_ARGUMENT_MAX_FPS_TEARING. 628 NvBool vrrTearing; 629 NvBool perEyeStereoFlip; 630 631 struct NvKmsSize sizeIn; 632 struct NvKmsSize sizeOut; 633 struct NvKmsSignedPoint outputPosition; 634 635 NVEvoScalerTaps hTaps; 636 NVEvoScalerTaps vTaps; 637 638 struct NvKmsCscMatrix cscMatrix; 639 640 NVFlipLutHwState inputLut; 641 642 struct NvKmsRRParams rrParams; 643 644 struct NvKmsCompositionParams composition; 645 646 NVFlipLutHwState tmoLut; 647 struct { 648 struct NvKmsHDRStaticMetadata val; 649 NvBool enabled; 650 } hdrStaticMetadata; 651 652 enum NvKmsInputColorSpace colorspace; 653 654 struct { 655 NvBool specified; 656 657 /* 658 * Maximum vertical downscale factor (scaled by 1024) 659 * 660 * For example, if the downscale factor is 1.5, then maxVDownscaleFactor 661 * would be 1.5 x 1024 = 1536. 662 */ 663 NvU16 vertical; 664 665 /* 666 * Maximum horizontal downscale factor (scaled by 1024) 667 * 668 * See the example above for vertical. 669 */ 670 NvU16 horizontal; 671 } maxDownscaleFactors; 672 } NVFlipChannelEvoHwState; 673 674 enum NvKmsDpyAttributeColorBpcValue { 675 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN = 0, 676 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10 = 10, 677 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8 = 8, 678 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6 = 6, 679 }; 680 681 typedef struct _NVColorFormatInfoRec { 682 struct { 683 enum NvKmsDpyAttributeColorBpcValue maxBpc; 684 } rgb444, yuv444, yuv422; 685 } NVColorFormatInfoRec; 686 687 typedef struct { 688 struct NvKmsPoint viewPortPointIn; 689 NVFlipCursorEvoHwState cursor; 690 NVFlipChannelEvoHwState layer[NVKMS_MAX_LAYERS_PER_HEAD]; 691 struct NvKmsUsageBounds usage; 692 NvBool disableMidFrameAndDWCFWatermark; 693 enum NvKmsOutputTf tf; 694 695 NvBool skipLayerPendingFlips[NVKMS_MAX_LAYERS_PER_HEAD]; 696 697 struct { 698 NvBool viewPortPointIn : 1; 699 NvBool cursorSurface : 1; 700 NvBool cursorPosition : 1; 701 NvBool tf : 1; 702 NvBool hdrStaticMetadata : 1; 703 704 NvBool layerPosition[NVKMS_MAX_LAYERS_PER_HEAD]; 705 NvBool layerSyncObjects[NVKMS_MAX_LAYERS_PER_HEAD]; 706 NvBool layer[NVKMS_MAX_LAYERS_PER_HEAD]; 707 } dirty; 708 } NVFlipEvoHwState; 709 710 enum NvKmsHDROutputState { 711 NVKMS_HDR_OUTPUT_STATE_SDR = 0, 712 NVKMS_HDR_OUTPUT_STATE_HDR = 1, 713 NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR = 2, 714 }; 715 716 /*! 717 * State requested through the NVKMS API. This may differ from 718 * the current hardware state (e.g., if the head has been 719 * momentarily blanked during DP link training). 720 */ 721 typedef struct _NVEvoSubDevHeadStateRec { 722 struct NvKmsPoint viewPortPointIn; 723 NVFlipCursorEvoHwState cursor; 724 NVFlipChannelEvoHwState layer[NVKMS_MAX_LAYERS_PER_HEAD]; 725 // Current usage bounds programmed into the hardware. 726 struct NvKmsUsageBounds usage; 727 // Usage bounds required after the last scheduled flip completes. 728 struct NvKmsUsageBounds targetUsage; 729 // Preallocated usage bounds that will be required for upcoming flips. 730 struct NvKmsUsageBounds preallocatedUsage; 731 732 // Current state of MidFrameAndDWCFWatermark programmed into the hardware. 733 NvBool disableMidFrameAndDWCFWatermark; 734 // 735 // State of MidFrameAndDWCFWatermark required after the last scheduled 736 // flip completes. 737 // 738 NvBool targetDisableMidFrameAndDWCFWatermark; 739 } NVEvoSubDevHeadStateRec; 740 741 #define NVKMS_HEAD_SURFACE_MAX_BUFFERS 2 742 743 /* 744 * HeadSurface state that applies to a single head, but spans across 745 * all subdevices. 746 */ 747 typedef struct { 748 /* 749 * The size of the headSurfaces for this head, across all subdevices. 750 * headSurface might only use a subset of the surfaces on one or more 751 * subdevices in SLI Mosaic. 752 */ 753 struct NvKmsSize size; 754 struct NvKmsSize stagingSize; 755 756 /* 757 * The surfaces allocated for use by headSurface on this head. 758 * Surface allocations are broadcast across subdevices, though 759 * headSurface may unicast its rendering to the headSurface 760 * surface allocations on specific subdevices. 761 */ 762 struct { 763 NVHsSurfacePtr pSurface; 764 NVHsSurfacePtr pStagingSurface; 765 } surfaces[NVKMS_MAX_EYES][NVKMS_HEAD_SURFACE_MAX_BUFFERS]; 766 767 /* 768 * The number of surfaces in the NVKMS_HEAD_SURFACE_MAX_BUFFERS dimension of 769 * the surfaces[][] array. Elements [0,surfaceCount-1] in the surfaces[][] 770 * array will be populated. 771 */ 772 NvU32 surfaceCount; 773 } NVHsStateOneHeadAllDisps; 774 775 /* Subdevice-specific, channel-independent state */ 776 typedef struct _NVEvoSubDevRec { 777 NvU32 subDeviceInstance; 778 779 NVEvoCapabilities capabilities; 780 781 NVDispEvoPtr pDispEvo; 782 783 NvU32 setSwSpareA[NVKMS_MAX_HEADS_PER_DISP]; 784 785 NVEvoSubDevHeadStateRec headState[NVKMS_MAX_HEADS_PER_DISP]; 786 NVEvoHeadControl headControl[NVKMS_MAX_HEADS_PER_DISP]; 787 NVEvoHeadControl headControlAssy[NVKMS_MAX_HEADS_PER_DISP]; 788 void *cursorPio[NVKMS_MAX_HEADS_PER_DISP]; 789 NvBool (*scanLockState)(NVDispEvoPtr pDispEvo, 790 NVEvoSubDevPtr pEvoSubDev, 791 NvU32 action, 792 /* NV_INVALID_HEAD-terminated 793 * array of head indices */ 794 const NvU32 *pHeads); 795 796 /* 797 * EVO state machine refcounter for the number of SLI or proxy framelock 798 * clients that are connected to this server. 799 */ 800 NvU32 frameLockSliProxyClients; 801 802 /* 803 * Since we add all active heads as framelock clients whenever we enable 804 * the second head as a framelock client, there's no need for EVO state 805 * transitions for heads 3 and more. Instead of those state transitions, 806 * we use the frameLockExtraClients ref counter to keep track of heads 807 * 3 and greater being added as framelock clients. 808 * 809 * XXX The state machine currently will naively framelock heads 3 and 810 * greater during this state transition, even if they're not capable 811 * of being framelocked (for example, when they have very different 812 * refresh rates). Bug 976532 813 */ 814 NvU32 frameLockExtraClients; 815 816 /* 817 * All of the following except the "armed" versions are set by the EVO 818 * state machine to the desired HW configuration given the current locking 819 * state. 820 * The "armed" versions represent the current hardware configuration, used 821 * to avoid excess hardware updates. 822 */ 823 NvU32 frameLockServerMaskArmed; 824 NvU32 frameLockServerMaskAssy; 825 NvU32 frameLockClientMaskArmed; 826 NvU32 frameLockClientMaskAssy; 827 NvU32 frameLockExtRefClkMaskArmed; 828 NvU32 frameLockExtRefClkMaskAssy; 829 NvBool frameLockHouseSync; 830 831 NvU8 flipLockPinSetForFrameLockHeadMask; 832 NvU8 flipLockEnabledForFrameLockHeadMask; 833 NvU8 flipLockPinSetForSliHeadMask; 834 NvU8 flipLockEnabledForSliHeadMask; 835 836 NvU32 flipLockProhibitedHeadMask; 837 838 NvU32 sliRasterLockServerMask; 839 NvU32 sliRasterLockClientMask; 840 841 NVEvoLockPin sliServerLockPin; 842 NVEvoLockPin sliClientLockPin; 843 NvBool forceZeroClientLockoutWindow; 844 } NVEvoSubDevRec; 845 846 typedef struct _NVEvoColorRec { 847 NvU16 red; 848 NvU16 green; 849 NvU16 blue; 850 } NVEvoColorRec; 851 852 typedef struct { 853 NvU16 Red; 854 NvU16 Green; 855 NvU16 Blue; 856 NvU16 Unused; 857 } NVEvoLutEntryRec; 858 859 typedef struct { 860 NVEvoLutEntryRec base[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES]; 861 // The output LUT requires 8-bit alignment. 862 NVEvoLutEntryRec output[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES] 863 __attribute__((aligned(0x100))); 864 } NVEvoLutDataRec; 865 866 typedef struct { 867 NvBool supportsDP13 :1; 868 NvBool supportsHDMI20 :1; 869 NvBool inputLutAppliesToBase :1; 870 NvU8 validNIsoFormatMask; 871 NvU8 genericPageKind; 872 NvU32 maxPitchValue; 873 int maxWidthInBytes; 874 int maxWidthInPixels; 875 int maxHeight; 876 NvU32 maxRasterWidth; 877 NvU32 maxRasterHeight; 878 struct NvKmsCompositionCapabilities cursorCompositionCaps; 879 NvU16 validLayerRRTransforms; 880 struct NvKmsLayerCapabilities layerCaps[NVKMS_MAX_LAYERS_PER_HEAD]; 881 NvU8 legacyNotifierFormatSizeBytes[NVKMS_MAX_LAYERS_PER_HEAD]; 882 NvU8 dpYCbCr422MaxBpc; 883 NvU8 hdmiYCbCr422MaxBpc; 884 } NVEvoCapsRec; 885 886 typedef struct { 887 NvU32 coreChannelClass; 888 size_t dmaArmedSize; 889 NvU32 dmaArmedOffset; 890 } NVEvoCoreChannelDmaRec; 891 892 893 typedef struct _NVEvoSubDeviceRec { 894 NvU32 handle; 895 NvU32 gpuId; 896 #define NV_INVALID_GPU_LOG_INDEX 0xFF 897 NvU8 gpuLogIndex; 898 char gpuString[NVKMS_GPU_STRING_SIZE]; 899 900 NvU32 numEngines; 901 NvU32 *supportedEngines; 902 903 /* Core channel memory mapping for ARM values */ 904 void *pCoreDma; 905 906 /* ISO ctxdma programmed by EVO2 hal, into the overlay channel */ 907 NvU32 overlayContextDmaIso[NVKMS_MAX_HEADS_PER_DISP]; 908 enum NvKmsSurfaceMemoryFormat overlaySurfFormat[NVKMS_MAX_HEADS_PER_DISP]; 909 910 /* Per head surface programmed into the core channel */ 911 const NVSurfaceEvoRec *pCoreChannelSurface[NVKMS_MAX_HEADS_PER_DISP]; 912 913 /* EVO2 only, TRUE if a valid base surface passed to ->Flip() */ 914 NvBool isBaseSurfSpecified[NVKMS_MAX_HEADS_PER_DISP]; 915 enum NvKmsSurfaceMemoryFormat baseSurfFormat[NVKMS_MAX_HEADS_PER_DISP]; 916 917 /* Composition parameters considered for hardware programming by EVO2 hal */ 918 struct { 919 NvBool initialized; 920 enum NvKmsCompositionColorKeySelect colorKeySelect; 921 NVColorKey colorKey; 922 } baseComp[NVKMS_MAX_HEADS_PER_DISP], overlayComp[NVKMS_MAX_HEADS_PER_DISP]; 923 924 } NVEvoSubDeviceRec; 925 926 enum NvKmsLUTState { 927 NvKmsLUTStateUninitialized = 0, 928 NvKmsLUTStateIdentity = 1, 929 NvKmsLUTStatePQ = 2, 930 }; 931 932 /* Device-specific EVO state (subdevice- and channel-independent) */ 933 typedef struct _NVEvoDevRec { 934 935 NvU8 gpuLogIndex; 936 NvU32 allocRefCnt; /* number of ALLOC_DEVICE calls */ 937 NVListRec devListEntry; 938 939 /* array of gpuIds opened with nvkms_open_gpu() */ 940 NvU32 openedGpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; 941 942 NVUnixRmHandleAllocatorRec handleAllocator; 943 NvU32 deviceId; 944 945 NvU32 deviceHandle; 946 struct NvKmsPerOpenDev *pNvKmsOpenDev; 947 948 struct { 949 NvPushDeviceRec device; 950 NvU32 handlePool[NV_PUSH_DEVICE_HANDLE_POOL_NUM]; 951 } nvPush; 952 953 /* SLI Info */ 954 struct { 955 NvBool mosaic; 956 struct { 957 NvBool present :1; 958 959 /* Current hardware state */ 960 NvBool powered :1; 961 962 /* Software state tracking needs from hardware */ 963 NvBool powerNeededForRasterLock :1; 964 } bridge; 965 } sli; 966 967 NvU32 numHeads; 968 NvU32 numWindows; /* NVDisplay only. */ 969 970 NvU32 displayHandle; 971 972 973 /*! 974 * modesetOwner points to the pOpenDev of the client that called 975 * NVKMS_IOCTL_GRAB_OWNERSHIP. 976 */ 977 const struct NvKmsPerOpenDev *modesetOwner; 978 979 /*! 980 * Indicates whether modeset ownership is changed since 981 * last modeset. 982 */ 983 NvBool modesetOwnerChanged; 984 985 /*! 986 * NVEvoDevRec::numSubDevices is the number of GPUs in the SLI 987 * device. This is the number of NVEvoSubDevPtrs in 988 * NVEvoDevRec::gpus[] and the number of NVSubDeviceEvoPtr in 989 * NVEvoDevRec::pSubDevices. 990 * 991 * The data structure organization is summarized by the following table: 992 * 993 * NVDevEvoRec::numSubDevices (# of pSubDevs) 994 * | NVDevEvoRec::nDispEvo (# of pDispEvos) 995 * | | NVDispEvoRec::numSubDevices (# of sd per disp) 996 * | | | 997 * no SLI 1 1 1 998 * SLI Mosaic N N 1 999 */ 1000 NvU32 numSubDevices; 1001 NVSubDeviceEvoPtr pSubDevices[NVKMS_MAX_SUBDEVICES]; 1002 1003 NvU32 dispClass; 1004 NvU32 displayCommonHandle; 1005 NvU32 rmCtrlHandle; 1006 1007 unsigned int nDispEvo; 1008 NVDispEvoPtr pDispEvo[NVKMS_MAX_SUBDEVICES]; 1009 1010 NVEvoChannelPtr base[NVKMS_MAX_HEADS_PER_DISP]; 1011 NVEvoChannelPtr core; 1012 NVEvoChannelPtr overlay[NVKMS_MAX_HEADS_PER_DISP]; 1013 NVEvoChannelPtr window[NVKMS_MAX_WINDOWS_PER_DISP]; 1014 1015 /* NVDisplay head<->window mapping */ 1016 NvU32 headForWindow[NVKMS_MAX_WINDOWS_PER_DISP]; 1017 1018 struct { 1019 NVEvoChannelPtr layer[NVKMS_MAX_LAYERS_PER_HEAD]; 1020 NvU32 numLayers; 1021 } head[NVKMS_MAX_HEADS_PER_DISP]; 1022 1023 /* Pointer to array of subdev structs */ 1024 NVEvoSubDevPtr gpus; 1025 1026 NvU32 subDevMaskStack[NV_EVO_SUBDEV_STACK_SIZE]; 1027 NvU32 subDevMaskStackDepth; 1028 1029 NvU32 cursorHandle[NVKMS_MAX_HEADS_PER_DISP]; 1030 1031 NVDPLibTimerPtr dpTimer; 1032 1033 NvU8 capsBits[NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE]; 1034 NvU8 commonCapsBits[NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE]; 1035 1036 NVEvoCapsRec caps; 1037 1038 NVEvoCoreChannelDmaRec coreChannelDma; 1039 NvU32 nvkmsGpuVASpace; 1040 1041 NvBool mobile : 1; 1042 NvBool usesTegraDevice : 1; 1043 1044 /* 1045 * IO coherency modes that display supports for ISO and NISO memory 1046 * allocations, respectively. 1047 */ 1048 NvKmsDispIOCoherencyModes isoIOCoherencyModes; 1049 NvKmsDispIOCoherencyModes nisoIOCoherencyModes; 1050 1051 /* 1052 * Indicates whether the init_no_update methods that were pushed by the 1053 * hardware during core channel allocation are still pending. 1054 */ 1055 NvBool coreInitMethodsPending : 1; 1056 /* 1057 * Indicates that NVKMS restored the console and freeing the core channel 1058 * should leave the display configuration alone. 1059 * 1060 * This should be set to FALSE whenever an update is sent that flips away 1061 * from the framebuffer console. 1062 * 1063 * TODO: Remove this in favor of passing a parameter explicitly to the 1064 * functions that use it. 1065 */ 1066 NvBool skipConsoleRestore : 1; 1067 /* 1068 * Indicates that hotplug events that occur while NVKMS is the modeset owner 1069 * should trigger console restore modesets. 1070 */ 1071 NvBool handleConsoleHotplugs : 1; 1072 /* 1073 * Cached from NvKmsSetModeRequest::allowHeadSurfaceInNvKms when the 1074 * modeset owner does a modeset. This is needed so that when non-modeset 1075 * owners do a partial modeset they don't override this value. 1076 */ 1077 NvBool allowHeadSurfaceInNvKms : 1; 1078 1079 NvBool gc6Allowed : 1; 1080 1081 /* 1082 * Indicates whether NVKMS is driving an SOC display device, or an external 1083 * dGPU device. 1084 */ 1085 NvBool isSOCDisplay : 1; 1086 1087 /* 1088 * Indicates whether NVKMS is supporting syncpts. 1089 */ 1090 NvBool supportsSyncpts : 1; 1091 1092 /* 1093 * Indicates whether the display device that NVKMS is driving requires all 1094 * memory allocations that display will access to come from sysmem. 1095 * 1096 * For SOC display devices, this should be set to TRUE since the only 1097 * memory aperture that they support is sysmem. 1098 */ 1099 NvBool requiresAllAllocationsInSysmem : 1; 1100 /* 1101 * Indicates whether the device that NVKMS is driving supports headSurface 1102 * composition. 1103 * 1104 * For SOC display devices (e.g., Orin), this should be set to FALSE since 1105 * there's currently zero nvgpu support, and no Tegra clients should be 1106 * using headSurface right now. 1107 */ 1108 NvBool isHeadSurfaceSupported : 1; 1109 1110 nvkms_timer_handle_t *postFlipIMPTimer; 1111 nvkms_timer_handle_t *consoleRestoreTimer; 1112 1113 nvkms_timer_handle_t *lowerDispBandwidthTimer; 1114 1115 NvU32 simulationType; 1116 1117 NvU32 numClasses; 1118 NvU32 *supportedClasses; 1119 1120 struct { 1121 /* name[0] == '\0' for unused registryKeys[] array elements. */ 1122 char name[NVKMS_MAX_DEVICE_REGISTRY_KEYNAME_LEN]; 1123 NvU32 value; 1124 } registryKeys[NVKMS_MAX_DEVICE_REGISTRY_KEYS]; 1125 1126 /* Returns true if the Quadro Sync card connected to this GPU has 1127 * a firmware version incompatible with this GPU. 1128 */ 1129 NvBool badFramelockFirmware; 1130 1131 const struct _nv_evo_hal *hal; 1132 const struct _nv_evo_cursor_hal *cursorHal; 1133 1134 /*! 1135 * ref_ptr to the structure. 1136 * 1137 * nvkms_timer_handle_t objects refer to the pDevEvo via references to this, 1138 * so that timers that fire after the pDevEvo has been freed can detect that 1139 * case and do nothing. 1140 */ 1141 struct nvkms_ref_ptr *ref_ptr; 1142 1143 struct { 1144 void *handle; 1145 } hdmiLib; 1146 1147 struct { 1148 NvU32 semaphoreHandle; 1149 void *pSemaphores; 1150 NvBool enabled; 1151 NvBool active; 1152 NvU32 flipCounter; 1153 } vrr; 1154 1155 /* 1156 * Information about the framebuffer console returned by 1157 * NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO. 1158 */ 1159 NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS vtFbInfo; 1160 1161 /* 1162 * Handle referencing the memory reserved by RM that is used by the kernel 1163 * as the framebuffer console surface. 1164 */ 1165 NvKmsSurfaceHandle fbConsoleSurfaceHandle; 1166 1167 NVHsDeviceEvoPtr pHsDevice; 1168 1169 /* The current headSurface configuration. */ 1170 NVHsStateOneHeadAllDisps apiHeadSurfaceAllDisps[NVKMS_MAX_HEADS_PER_DISP]; 1171 1172 struct NVDevPreallocRec prealloc; 1173 1174 struct { 1175 NvU32 handle; 1176 NVOS10_EVENT_KERNEL_CALLBACK_EX callback; 1177 } nonStallInterrupt; 1178 1179 /* 1180 * Track the LUT with per-head, per-pDisp scope. The LUT itself 1181 * is triple buffered. 1182 * 1183 * RM surface allocations are broadcast in SLI, so LUT is allocated with 1184 * per-device scope. However, writes into the LUT are unicast with 1185 * per-pDisp scope. 1186 * 1187 * The LUT surface in the core channel contains both the base and output 1188 * LUTs. 1189 */ 1190 struct { 1191 struct { 1192 NVLutSurfaceEvoPtr LUT[3]; 1193 struct { 1194 NvBool waitForPreviousUpdate; 1195 NvBool curBaseLutEnabled; 1196 NvBool curOutputLutEnabled; 1197 NvU8 curLUTIndex; 1198 nvkms_timer_handle_t *updateTimer; 1199 } disp[NVKMS_MAX_SUBDEVICES]; 1200 } apiHead[NVKMS_MAX_HEADS_PER_DISP]; 1201 NVLutSurfaceEvoPtr defaultLut; 1202 enum NvKmsLUTState defaultBaseLUTState[NVKMS_MAX_SUBDEVICES]; 1203 enum NvKmsLUTState defaultOutputLUTState[NVKMS_MAX_SUBDEVICES]; 1204 } lut; 1205 1206 /*! stores pre-syncpts */ 1207 NVEvoSyncpt *preSyncptTable; 1208 NvBool *pAllSyncptUsedInCurrentFlip; 1209 1210 /* DIFR prefetch event handling. */ 1211 NVOS10_EVENT_KERNEL_CALLBACK_EX difrPrefetchCallback; 1212 NvU32 difrPrefetchEventHandler; 1213 1214 /* DIFR runtime state. */ 1215 NVDIFRStateEvoPtr pDifrState; 1216 1217 NvU32 numApiHeads; 1218 1219 struct { 1220 NvU32 numLayers; 1221 } apiHead[NVKMS_MAX_HEADS_PER_DISP]; 1222 } NVDevEvoRec; 1223 1224 static inline NvBool nvEvoIsConsoleActive(const NVDevEvoRec *pDevEvo) 1225 { 1226 /* 1227 * If (pDevEvo->modesetOwner == NULL) that means either the vbios 1228 * console or the NVKMS console might be active. 1229 */ 1230 if (pDevEvo->modesetOwner == NULL) { 1231 return TRUE; 1232 } 1233 1234 /* 1235 * If (pDevEvo->modesetOwner != NULL) but 1236 * pDevEvo->modesetOwnerChanged is TRUE, that means the modeset 1237 * ownership is grabbed by the external client but it hasn't 1238 * performed any modeset and the console is still active. 1239 */ 1240 if ((pDevEvo->modesetOwner != NULL) && pDevEvo->modesetOwnerChanged) { 1241 return TRUE; 1242 } 1243 1244 return FALSE; 1245 } 1246 1247 /* 1248 * The NVHwModeTimingsEvo structure stores all the values necessary to 1249 * perform a modeset with EVO 1250 */ 1251 1252 typedef struct _NVHwModeViewPortEvo { 1253 struct { 1254 /* 1255 * note that EVO centers ViewPortOut within the active raster, 1256 * so xAdjust,yAdjust are signed; to position ViewPortOut at 1257 * 0,0 within active raster: 1258 * 1259 * viewPortOut.xAdjust = (activeRaster.w - viewPortOut.w)/2 * -1; 1260 * viewPortOut.yAdjust = (activeRaster.h - viewPortOut.h)/2 * -1; 1261 */ 1262 NvS16 xAdjust; 1263 NvS16 yAdjust; 1264 NvU16 width; 1265 NvU16 height; 1266 } out; 1267 1268 struct { 1269 NvU16 width; 1270 NvU16 height; 1271 } in; 1272 1273 NVEvoScalerTaps hTaps; 1274 NVEvoScalerTaps vTaps; 1275 1276 // These are the window features that may be possible if the required ISO 1277 // bw is available at the time that the feature needs to be enabled. By 1278 // default possibleUsage is set considering that everything is supported 1279 // by the HW and for dGPU, IMP will scale it as needed. 1280 struct NvKmsUsageBounds possibleUsage; 1281 1282 // Guaranteed usage bounds allowed by IMP. These are never assigned to 1283 // NVDpyEvoRec::usage or the hardware directly, but rather are used to 1284 // validate usage bound change requests. 1285 struct NvKmsUsageBounds guaranteedUsage; 1286 } NVHwModeViewPortEvo; 1287 1288 static inline NvBool nvIsImageSharpeningAvailable( 1289 const NVHwModeViewPortEvo *pViewPort) 1290 { 1291 return (pViewPort->out.width != pViewPort->in.width) || 1292 (pViewPort->out.height != pViewPort->in.height); 1293 } 1294 1295 enum nvKmsPixelDepth { 1296 NVKMS_PIXEL_DEPTH_18_444, 1297 NVKMS_PIXEL_DEPTH_24_444, 1298 NVKMS_PIXEL_DEPTH_30_444, 1299 NVKMS_PIXEL_DEPTH_20_422, 1300 NVKMS_PIXEL_DEPTH_16_422, 1301 }; 1302 1303 enum nvKmsTimingsProtocol { 1304 NVKMS_PROTOCOL_DAC_RGB, 1305 1306 NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A, 1307 NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B, 1308 NVKMS_PROTOCOL_SOR_DUAL_TMDS, 1309 NVKMS_PROTOCOL_SOR_DP_A, 1310 NVKMS_PROTOCOL_SOR_DP_B, 1311 NVKMS_PROTOCOL_SOR_LVDS_CUSTOM, 1312 NVKMS_PROTOCOL_SOR_HDMI_FRL, 1313 1314 NVKMS_PROTOCOL_DSI, 1315 1316 NVKMS_PROTOCOL_PIOR_EXT_TMDS_ENC, 1317 }; 1318 1319 enum NVDscInfoEvoType { 1320 NV_DSC_INFO_EVO_TYPE_DISABLED = 0, 1321 NV_DSC_INFO_EVO_TYPE_HDMI = 1, 1322 NV_DSC_INFO_EVO_TYPE_DP = 3, 1323 }; 1324 1325 enum NVDscEvoMode { 1326 NV_DSC_EVO_MODE_SINGLE = 0, 1327 NV_DSC_EVO_MODE_DUAL = 1, 1328 }; 1329 1330 typedef struct _NVDscInfoEvoRec { 1331 union { 1332 /* DisplayPort Display Stream Compression */ 1333 struct { 1334 /* 1335 * The DSC target bits per pixel (bpp) rate value multiplied by 16 that 1336 * is being used by the DSC encoder. 1337 * 1338 * It maps respectively to {pps4[1:0], pps5[7:0]}. 1339 */ 1340 NvU32 bitsPerPixelX16; 1341 1342 /* 1343 * The DSC picture parameter set (PPS), which the DSC encoder must 1344 * communicate to the decoder. 1345 */ 1346 NvU32 pps[DSC_MAX_PPS_SIZE_DWORD]; 1347 enum NVDscEvoMode dscMode; 1348 } dp; 1349 1350 struct { 1351 NvU32 bitsPerPixelX16; 1352 NvU32 pps[HDMI_DSC_MAX_PPS_SIZE_DWORD]; 1353 NvU32 dscHActiveBytes; 1354 NvU32 dscHActiveTriBytes; 1355 NvU32 dscHBlankTriBytes; 1356 NvU32 dscTBlankToTTotalRatioX1k; 1357 NvU32 hblankMin; 1358 enum NVDscEvoMode dscMode; 1359 } hdmi; 1360 }; 1361 1362 enum NVDscInfoEvoType type; 1363 } NVDscInfoEvoRec; 1364 1365 /* 1366 * This structure defines all of the values necessary to program mode timings 1367 * on EVO hardware. 1368 * NOTE: if you add anything to this, consider adding it to 1369 * RasterLockPossible() in nvkms-evo.c 1370 */ 1371 typedef struct _NVHwModeTimingsEvo { 1372 struct NvKmsPoint rasterSize; 1373 struct NvKmsPoint rasterSyncEnd; 1374 struct NvKmsPoint rasterBlankEnd; 1375 struct NvKmsPoint rasterBlankStart; 1376 NvU32 rasterVertBlank2Start; 1377 NvU32 rasterVertBlank2End; 1378 1379 NvU32 pixelClock; /* in kHz */ 1380 enum nvKmsTimingsProtocol protocol; 1381 /* 1382 * yuv420Mode reflects whether this mode requires YUV 4:2:0 decimation into 1383 * a half-width output through headsurface (SW YUV420) or >=nvdisplay 4.0 HW 1384 * CSC (HW YUV420). 1385 * 1386 * If a mode requires SW YUV 4:2:0 emulation, the pixelClock and width 1387 * values in NvModeTimings will still be the full width values specified by 1388 * the mode parsed from the EDID (e.g. 3840x2160@60), but the pixelClock 1389 * and width values in NVHwModeTimingsEvo will be the "real" half width 1390 * values programmed in HW and rendered to through a headSurface transform 1391 * (e.g. 1920x2160@60). If a mode requires HW YUV 4:2:0 CSC, the 1392 * pixelClock and width values in both NvModeTimings and NVHwModeTimingsEvo 1393 * will be full width, and the decimation to the half width scanout surface 1394 * is performed in HW. In both cases, only the full width values should 1395 * ever be reported to the client. 1396 */ 1397 enum NvYuv420Mode yuv420Mode; 1398 /* *SyncPol is TRUE if negative */ 1399 NvBool hSyncPol : 1; 1400 NvBool vSyncPol : 1; 1401 NvBool interlaced : 1; 1402 NvBool doubleScan : 1; 1403 /* 1404 * hdmi3D reflects whether this mode is a HDMI 3D frame packed mode. True 1405 * only if the user selected HDMI 3D stereo mode and the GPU supports it. 1406 * If true, then pixelClock is doubled. 1407 */ 1408 NvBool hdmi3D : 1; 1409 1410 struct { 1411 /* The vrr type for which this mode is adjusted. */ 1412 enum NvKmsDpyVRRType type; 1413 NvU32 timeoutMicroseconds; 1414 NvBool needsSwFramePacing; 1415 } vrr; 1416 1417 NVHwModeViewPortEvo viewPort; 1418 } NVHwModeTimingsEvo; 1419 1420 static inline NvBool nvIsAdaptiveSyncDpyVrrType(enum NvKmsDpyVRRType type) 1421 { 1422 return ((type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED) || 1423 (type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED)); 1424 } 1425 1426 static inline NvU64 nvEvoFrametimeUsFromTimings(const NVHwModeTimingsEvo *pTimings) 1427 { 1428 NvU64 pixelsPerFrame = pTimings->rasterSize.x * pTimings->rasterSize.y; 1429 NvU64 pixelsPerSecond = KHzToHz(pTimings->pixelClock); 1430 NvU64 framesPerSecond = pixelsPerSecond / pixelsPerFrame; 1431 1432 return 1000000ULL / framesPerSecond; 1433 } 1434 1435 static inline NvU16 nvEvoVisibleWidth(const NVHwModeTimingsEvo *pTimings) 1436 { 1437 return pTimings->rasterBlankStart.x - pTimings->rasterBlankEnd.x; 1438 } 1439 1440 static inline NvU16 nvEvoVisibleHeight(const NVHwModeTimingsEvo *pTimings) 1441 { 1442 /* rasterVertBlank2{Start,End} should only be != 0 for interlaced modes. */ 1443 nvAssert(pTimings->interlaced || 1444 ((pTimings->rasterVertBlank2Start == 0) && 1445 (pTimings->rasterVertBlank2End == 0))); 1446 1447 return pTimings->rasterBlankStart.y - pTimings->rasterBlankEnd.y + 1448 pTimings->rasterVertBlank2Start - pTimings->rasterVertBlank2End; 1449 } 1450 1451 /* 1452 * Calculate BackendSizeHeight, based on this HD or SD quality is 1453 * defined. 1454 */ 1455 static inline NvBool nvEvoIsHDQualityVideoTimings( 1456 const NVHwModeTimingsEvo *pTimings) 1457 { 1458 NvU32 height = nvEvoVisibleHeight(pTimings); 1459 1460 // as per windows code, nvva uses < 720. 1461 if (height <= 576) { 1462 // SD quality: 240, 288, 480, 576 1463 return FALSE; 1464 } 1465 1466 // HD quality: 720, 1080 1467 return TRUE; 1468 } 1469 1470 static inline struct NvKmsRect nvEvoViewPortOutHwView( 1471 const NVHwModeTimingsEvo *pTimings) 1472 { 1473 const NVHwModeViewPortEvo *pViewPort = &pTimings->viewPort; 1474 const NvU16 hVisible = nvEvoVisibleWidth(pTimings); 1475 const NvU16 vVisible = nvEvoVisibleHeight(pTimings); 1476 struct NvKmsRect viewPortOut = { 0 }; 1477 1478 viewPortOut.width = pViewPort->out.width; 1479 viewPortOut.height = pViewPort->out.height; 1480 viewPortOut.x = pViewPort->out.xAdjust + 1481 (hVisible - pViewPort->out.width) / 2; 1482 viewPortOut.y = (pViewPort->out.yAdjust + 1483 (vVisible - pViewPort->out.height) / 2); 1484 1485 return viewPortOut; 1486 } 1487 1488 static inline struct NvKmsRect nvEvoViewPortOutClientView( 1489 const NVHwModeTimingsEvo *pTimings) 1490 { 1491 struct NvKmsRect viewPortOut = nvEvoViewPortOutHwView(pTimings); 1492 1493 if (pTimings->doubleScan) { 1494 1495 nvAssert((viewPortOut.x % 2) == 0); 1496 viewPortOut.x /= 2; 1497 1498 nvAssert((viewPortOut.height % 2) == 0); 1499 viewPortOut.height /= 2; 1500 } 1501 1502 return viewPortOut; 1503 } 1504 1505 /* 1506 * The ELD contains a subset of the digital display device's EDID 1507 * information related to audio capabilities. The GPU driver sends the 1508 * ELD to hardware and the audio driver reads it by issuing the ELD 1509 * command verb. 1510 */ 1511 1512 #define NV_MAX_AUDIO_DEVICE_ENTRIES \ 1513 (NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 + 1) 1514 1515 typedef enum { 1516 NV_ELD_PRE_MODESET = 0, 1517 NV_ELD_POST_MODESET, 1518 NV_ELD_POWER_ON_RESET, 1519 } NvEldCase; 1520 1521 /* OR indices are per OR-type. The maximum OR index for each type 1522 * on each GPU is: 1523 * 1524 * Pre-GV10X : 8 SORs, 4 PIORs and 4 Dacs; 1525 * GV10X : 8 SORs, 4 PIORs; 1526 * TU10X+ : 8 SORs; 1527 */ 1528 #define NV_EVO_MAX_ORS 8 1529 1530 /* 1531 * The scoping of heads, ORs, and dpys relative to connectors can be 1532 * complicated. Here is how objects are scoped for various configurations: 1533 * 1534 * #heads #ORs #dpys #NVConnectorEvoRecs 1535 * DP 1.1 1 1 1 1 1536 * DP-MST n 1 n 1 1537 * DP cloning: 1 1 n 1 1538 * 2-Heads-1-OR: 2 2 1 1 1539 */ 1540 typedef struct _NVConnectorEvoRec { 1541 char name[NVKMS_DPY_NAME_SIZE]; 1542 1543 NVDispEvoPtr pDispEvo; 1544 1545 NVListRec connectorListEntry; 1546 1547 NvBool detectComplete; /* For sync'ing dpy detection w/ DP lib */ 1548 NVDPLibConnectorPtr pDpLibConnector; // DP Lib 1549 NvBool dpSerializerEnabled; 1550 1551 struct { 1552 NvU8 maxLinkBW; 1553 NvU8 maxLaneCount; 1554 NvBool supportsMST; 1555 } dpSerializerCaps; 1556 1557 NVDpyId displayId; // RM Display ID 1558 NvKmsConnectorSignalFormat signalFormat; 1559 NvKmsConnectorType type; 1560 NvU32 typeIndex; 1561 NvU32 legacyType; /* NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_ */ 1562 NvU32 legacyTypeIndex; 1563 NvU32 physicalIndex; 1564 NvU32 physicalLocation; 1565 1566 NvU32 dfpInfo; /* DFP info query through NV0073_CTRL_CMD_DFP_GET_INFO */ 1567 1568 NVDpyIdList ddcPartnerDpyIdsList; 1569 1570 struct { 1571 NvU32 type; 1572 NvU32 protocol; // NV0073_CTRL_SPECIFIC_OR_PROTOCOL_* 1573 NvU32 location; // NV0073_CTRL_SPECIFIC_OR_LOCATION_* 1574 NvU32 ditherType; 1575 NvU32 ditherAlgo; 1576 /* Hardware heads attached to assigned OR */ 1577 NvU32 ownerHeadMask[NV_EVO_MAX_ORS]; 1578 /* The mask of secondary ORs assigned to this connector */ 1579 NvU32 secondaryMask; 1580 /* The primary OR assigned to this connector */ 1581 NvU32 primary; 1582 } or; 1583 1584 NvEldCase audioDevEldCase[NV_MAX_AUDIO_DEVICE_ENTRIES]; 1585 1586 NvBool isHdmiEnabled; 1587 } NVConnectorEvoRec; 1588 1589 static inline NvU32 nvConnectorGetORMaskEvo(const NVConnectorEvoRec *pConnectorEvo) 1590 { 1591 if (pConnectorEvo->or.primary != NV_INVALID_OR) { 1592 return NVBIT(pConnectorEvo->or.primary) | pConnectorEvo->or.secondaryMask; 1593 } 1594 return 0x0; 1595 } 1596 1597 static inline NvU32 nvConnectorGetAttachedHeadMaskEvo( 1598 const NVConnectorEvoRec *pConnectorEvo) 1599 { 1600 NvU32 headMask = 0x0; 1601 NvU32 orIndex; 1602 1603 FOR_EACH_INDEX_IN_MASK(32, orIndex, nvConnectorGetORMaskEvo(pConnectorEvo)) { 1604 headMask |= pConnectorEvo->or.ownerHeadMask[orIndex]; 1605 } FOR_EACH_INDEX_IN_MASK_END; 1606 1607 return headMask; 1608 } 1609 1610 static inline 1611 NvBool nvIsConnectorActiveEvo(const NVConnectorEvoRec *pConnectorEvo) 1612 { 1613 return (pConnectorEvo->or.primary != NV_INVALID_OR) && 1614 (pConnectorEvo->or.ownerHeadMask[pConnectorEvo->or.primary] != 0x0); 1615 } 1616 1617 typedef struct _NVDpyAttributeCurrentDitheringConfigRec { 1618 NvBool enabled; 1619 enum NvKmsDpyAttributeCurrentDitheringDepthValue depth; 1620 enum NvKmsDpyAttributeCurrentDitheringModeValue mode; 1621 } NVDpyAttributeCurrentDitheringConfig; 1622 1623 typedef struct __NVAttributesSetEvoRec { 1624 1625 #define NV_EVO_DVC_MIN (-1024) 1626 #define NV_EVO_DVC_MAX 1023 1627 #define NV_EVO_DVC_DEFAULT 0 1628 1629 NvS32 dvc; 1630 1631 /* 1632 * For both colorSpace and colorRange, the value for 1633 * NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_{SPACE,RANGE} sent by the client is 1634 * stored in NVDpyEvoRec::requestedColor(Space, Range}. The structure stores 1635 * the actual color space and color range in use. 1636 * 1637 * nvChooseCurrentColorSpaceAndRangeEvo() chooses the actual color 1638 * space, color bpc, and color range, for a dpy. It sets colorBpc 1639 * to the max bpc supported by the given dpy. 1640 * 1641 * Since YUV444 mode only allows limited color range, changes to the 1642 * current color space may trigger changes to the current color 1643 * range (see nvChooseCurrentColorSpaceAndRangeEvo()). 1644 * 1645 * For SW YUV420 mode, these values are ignored in 1646 * HEAD_SET_PROCAMP and applied in the headSurface composite shader. 1647 */ 1648 enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; 1649 enum NvKmsDpyAttributeColorBpcValue colorBpc; 1650 enum NvKmsDpyAttributeColorRangeValue colorRange; 1651 1652 NVDpyAttributeCurrentDitheringConfig dithering; 1653 1654 #define NV_EVO_IMAGE_SHARPENING_MIN 0 1655 #define NV_EVO_IMAGE_SHARPENING_MAX 255 1656 #define NV_EVO_IMAGE_SHARPENING_DEFAULT 127 1657 1658 struct { 1659 NvBool available; 1660 NvU32 value; 1661 } imageSharpening; 1662 1663 enum NvKmsDpyAttributeDigitalSignalValue digitalSignal; 1664 1665 NvU8 numberOfHardwareHeadsUsed; 1666 } NVAttributesSetEvoRec; 1667 1668 #define NV_EVO_DEFAULT_ATTRIBUTES_SET \ 1669 (NVAttributesSetEvoRec) { \ 1670 .dvc = NV_EVO_DVC_DEFAULT, \ 1671 .colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB, \ 1672 .colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL, \ 1673 .dithering = { \ 1674 .enabled = FALSE, \ 1675 .mode = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE, \ 1676 .depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE, \ 1677 }, \ 1678 .imageSharpening = { \ 1679 .value = NV_EVO_IMAGE_SHARPENING_DEFAULT, \ 1680 }, \ 1681 .numberOfHardwareHeadsUsed = 0, \ 1682 } 1683 1684 struct NvKmsVrrFramePacingInfo { 1685 /* Whether sw frame pacing is active. */ 1686 NvBool framePacingActive; 1687 1688 /* Memory handle for vidmem buffer */ 1689 NvHandle memoryHandle; 1690 1691 /* Shared data to be updated by RM */ 1692 NV0073_CTRL_RM_VRR_SHARED_DATA *pData; 1693 }; 1694 1695 typedef struct _NVEldEvoRec { 1696 NvU32 size; 1697 NvU8 buffer[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; 1698 } NVEldEvoRec; 1699 1700 /* 1701 * This structure stores information about the active per-head audio state. 1702 */ 1703 typedef struct _NVDispHeadAudioStateEvoRec { 1704 NvU32 maxFreqSupported; 1705 NVEldEvoRec eld; 1706 1707 NvBool isAudioOverHdmi : 1; 1708 NvBool supported : 1; 1709 NvBool enabled : 1; 1710 } NVDispHeadAudioStateEvoRec; 1711 1712 typedef struct _NVDispHeadInfoFrameStateEvoRec { 1713 NVT_VIDEO_INFOFRAME_CTRL ctrl; 1714 NvBool hdTimings; 1715 } NVDispHeadInfoFrameStateEvoRec; 1716 1717 typedef enum _NVEvoMergeMode { 1718 NV_EVO_MERGE_MODE_DISABLED, 1719 NV_EVO_MERGE_MODE_SETUP, 1720 NV_EVO_MERGE_MODE_PRIMARY, 1721 NV_EVO_MERGE_MODE_SECONDARY, 1722 } NVEvoMergeMode; 1723 1724 /* 1725 * This structure stores information about the active per-head display state. 1726 */ 1727 typedef struct _NVDispHeadStateEvoRec { 1728 1729 struct NvKmsVrrFramePacingInfo vrrFramePacingInfo; 1730 NvU32 displayRate; 1731 1732 /*! Cached, to preserve across modesets. */ 1733 struct NvKmsModeValidationParams modeValidationParams; 1734 1735 /* 1736 * Heads on the same NVDevEvoRec with the same non-zero 1737 * NVDispHeadStateEvoRec::allowFlipLockGroup value are eligible to 1738 * be flipLocked, from an NVKMS client point of view, if the 1739 * hardware requirements for flipLock are met. 1740 */ 1741 NvU8 allowFlipLockGroup; 1742 1743 /* 1744 * For Turing and newer, enable display composition bypass mode. 1745 * 1746 * This is intended to be used by console restore to avoid bug 2168873. 1747 */ 1748 NvBool bypassComposition : 1; 1749 1750 struct { 1751 NVT_COLOR_FORMAT colorFormat; 1752 NVT_COLORIMETRY colorimetry; 1753 NVT_COLOR_RANGE colorRange; 1754 NvU32 satCos; 1755 } procAmp; 1756 1757 /* 1758 * The activeRmId is the identifier that we use to talk to RM 1759 * about the display device(s) on this head. It is zero except 1760 * when a mode is being driven by this head. For DP MST, it is the 1761 * identifier of the displayport library group to which the driven 1762 * DP device belongs. Otherwise, it is the identifier of the connector 1763 * driven by the head. 1764 */ 1765 NvU32 activeRmId; 1766 1767 NVHwModeTimingsEvo timings; 1768 NVConnectorEvoRec *pConnectorEvo; /* NULL if the head is not active */ 1769 1770 HDMI_FRL_CONFIG hdmiFrlConfig; 1771 1772 NVDscInfoEvoRec dscInfo; 1773 1774 enum nvKmsPixelDepth pixelDepth; 1775 1776 NVDispHeadAudioStateEvoRec audio; 1777 1778 enum NvKmsOutputTf tf; 1779 1780 struct { 1781 enum NvKmsHDROutputState outputState; 1782 struct NvKmsHDRStaticMetadata staticMetadata; 1783 } hdr; 1784 1785 struct { 1786 NVLutSurfaceEvoPtr pCurrSurface; 1787 NvBool outputLutEnabled : 1; 1788 NvBool baseLutEnabled : 1; 1789 } lut; 1790 1791 /* 1792 * The api head can be mapped onto the N harware heads, a frame presented 1793 * by the api head gets split horizontally into N tiles, 'tilePosition' 1794 * describe the tile presented by this hardware head. 1795 */ 1796 NvU8 tilePosition; 1797 1798 NVEvoMergeMode mergeMode; 1799 /* 1800 * XXX[2Heads1OR] Implement per api-head frame pacing and remove 1801 * NVDispEvoRec::mergeModeVrrSecondaryHeadMask. 1802 */ 1803 NvU32 mergeModeVrrSecondaryHeadMask; 1804 } NVDispHeadStateEvoRec; 1805 1806 typedef struct _NVDispStereoParamsEvoRec { 1807 enum NvKmsStereoMode mode; 1808 NvBool isAegis; 1809 } NVDispStereoParamsEvoRec; 1810 1811 typedef struct _NVDispFlipOccurredEventDataEvoRec { 1812 NVDispEvoPtr pDispEvo; 1813 NvU32 apiHead; 1814 NvU32 layer; 1815 } NVDispFlipOccurredEventDataEvoRec; 1816 1817 typedef struct _NVDispApiHeadStateEvoRec { 1818 /* 1819 * The mask of hardware heads mapped onto this api head, 1820 * set to zero if the api head is not active. 1821 */ 1822 NvU32 hwHeadsMask; 1823 1824 NVDpyIdList activeDpys; /* Empty if the head is not active */ 1825 NVAttributesSetEvoRec attributes; 1826 1827 enum NvKmsOutputTf tf; 1828 nvkms_timer_handle_t *hdrToSdrTransitionTimer; 1829 1830 /* 1831 * Hardware timings which are split across hardware heads. 1832 * 1833 * XXX[2Heads1OR] The api-head state does not require to track full 1834 * hardware timings. Replace 'timings' by minimal per api-head hardware 1835 * timings information used in code. 1836 */ 1837 NVHwModeTimingsEvo timings; 1838 1839 NVDispStereoParamsEvoRec stereo; 1840 1841 struct NvKmsPoint viewPortPointIn; 1842 1843 NVDispHeadInfoFrameStateEvoRec infoFrame; 1844 1845 /* 1846 * Each head can have up to NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD 1847 * programmable Core semaphores. 1848 * 1849 * The numVblankSyncObjectsCreated will ideally always be equal to 1850 * NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD, but could be lower if errors 1851 * occured during syncpt allocation in nvRMSetupEvoCoreChannel(). 1852 */ 1853 NvU8 numVblankSyncObjectsCreated; 1854 NVVblankSyncObjectRec vblankSyncObjects[NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD]; 1855 1856 struct { 1857 struct nvkms_ref_ptr *ref_ptr; 1858 NVDispFlipOccurredEventDataEvoRec data; 1859 } flipOccurredEvent[NVKMS_MAX_LAYERS_PER_HEAD]; 1860 1861 NvU32 rmVBlankCallbackHandle; 1862 NVListRec vblankCallbackList; 1863 1864 NvBool hs10bpcHint : 1; 1865 } NVDispApiHeadStateEvoRec; 1866 1867 typedef struct _NVDispEvoRec { 1868 NvU8 gpuLogIndex; 1869 NVDevEvoPtr pDevEvo; 1870 NvU32 hotplugEventHandle; 1871 NvU32 DPIRQEventHandle; 1872 NVOS10_EVENT_KERNEL_CALLBACK_EX rmHotplugCallback; 1873 NVOS10_EVENT_KERNEL_CALLBACK_EX rmDPIRQCallback; 1874 1875 NVDispHeadStateEvoRec headState[NVKMS_MAX_HEADS_PER_DISP]; 1876 NVDispApiHeadStateEvoRec apiHeadState[NVKMS_MAX_HEADS_PER_DISP]; 1877 1878 NVDpyIdList vbiosDpyConfig[NVKMS_MAX_HEADS_PER_DISP]; 1879 1880 NvU32 isoBandwidthKBPS; 1881 NvU32 dramFloorKBPS; 1882 1883 /* 1884 * The list of physical connector display IDs. This is the union 1885 * of pConnectorEvo->displayId values, which is also the union of 1886 * pDpyEvo->id values for non-MST pDpys. 1887 */ 1888 NVDpyIdList connectorIds; 1889 1890 NVListRec connectorList; 1891 1892 NvU32 displayOwner; 1893 1894 NVListRec dpyList; 1895 1896 NVDpyIdList bootDisplays; 1897 NVDpyIdList validDisplays; 1898 NVDpyIdList connectedDisplays; 1899 1900 /* 1901 * displayPortMSTIds is a superset of dynamicDpyIds because not all DP MST 1902 * dpys are dynamic dpys. For example, the DP MST dpys that are driven by 1903 * a DP serializer connector are part of a fixed topology, and are static in 1904 * nature. 1905 */ 1906 NVDpyIdList displayPortMSTIds; /* DP MST dpys */ 1907 NVDpyIdList dynamicDpyIds; 1908 1909 NVDpyIdList muxDisplays; 1910 1911 struct { 1912 nvkms_timer_handle_t *unstallTimer; 1913 } vrr; 1914 1915 NVFrameLockEvoPtr pFrameLockEvo; 1916 struct { 1917 NVDpyId server; 1918 NVDpyIdList clients; 1919 NvBool syncEnabled; /* GPU is syncing to framelock */ 1920 NvU32 connectorIndex;/* NV30F1_GSYNC_CONNECTOR_* */ 1921 NvU32 currentServerHead; /* used for disabling */ 1922 NvU32 currentClientHeadsMask; /* used for disabling */ 1923 NvBool currentHouseSync; /* if state machine thinks house sync 1924 is enabled -- used for disabling */ 1925 1926 /* Framelock event-related data */ 1927 #define NV_FRAMELOCK_SYNC_LOSS 0 1928 #define NV_FRAMELOCK_SYNC_GAIN 1 1929 #define NV_FRAMELOCK_NUM_EVENTS 2 1930 1931 struct { 1932 NvU32 handle; 1933 NVOS10_EVENT_KERNEL_CALLBACK_EX callback; 1934 } gsyncEvent[NV_FRAMELOCK_NUM_EVENTS]; 1935 1936 } framelock; 1937 1938 /* NVDevEvoRec::pHsChannel[] is indexed by the api heads */ 1939 NVHsChannelEvoPtr pHsChannel[NVKMS_MAX_HEADS_PER_DISP]; 1940 1941 /* NVDevEvoRec::pSwapGroup[] is indexed by the api heads */ 1942 NVSwapGroupPtr pSwapGroup[NVKMS_MAX_HEADS_PER_DISP]; 1943 1944 /*! 1945 * ref_ptr to the structure. 1946 * 1947 * nvkms_timer_handle_t objects refer to the pDispEvo via references to 1948 * this, so that timers that fire after the pDispEvo has been freed can 1949 * detect that case and do nothing. 1950 */ 1951 struct nvkms_ref_ptr *ref_ptr; 1952 1953 /* 1954 * Indicates that NV_KMS_DISP_ATTRIBUTE_QUERY_DP_AUX_LOG has been queried at 1955 * least once on this device. If set, nvRmDestroyDisplays() will flush any 1956 * remaining AUX log messages to the system log. 1957 */ 1958 NvBool dpAuxLoggingEnabled; 1959 1960 struct nvkms_backlight_device *backlightDevice; 1961 1962 NvU32 vrrSetTimeoutEventUsageCount; 1963 NVOS10_EVENT_KERNEL_CALLBACK_EX vrrSetTimeoutCallback; 1964 NvU32 vrrSetTimeoutEventHandle; 1965 } NVDispEvoRec; 1966 1967 static inline NvU32 GetNextHwHead(NvU32 hwHeadsMask, const NvU32 prevHwHead) 1968 { 1969 if ((hwHeadsMask == 0x0) || 1970 ((prevHwHead != NV_INVALID_HEAD) && 1971 ((hwHeadsMask &= ~((1 << (prevHwHead + 1)) -1 )) == 0x0))) { 1972 return NV_INVALID_HEAD; 1973 } 1974 return BIT_IDX_32(LOWESTBIT(hwHeadsMask)); 1975 } 1976 1977 #define FOR_EACH_EVO_HW_HEAD_IN_MASK(__hwHeadsMask, __hwHead) \ 1978 for ((__hwHead) = GetNextHwHead((__hwHeadsMask), NV_INVALID_HEAD); \ 1979 (__hwHead) != NV_INVALID_HEAD; \ 1980 (__hwHead) = GetNextHwHead((__hwHeadsMask), (__hwHead))) 1981 1982 #define FOR_EACH_EVO_HW_HEAD(__pDispEvo, __apiHead, __hwHead) \ 1983 FOR_EACH_EVO_HW_HEAD_IN_MASK((__pDispEvo)->apiHeadState[(__apiHead)].hwHeadsMask, \ 1984 (__hwHead)) 1985 1986 static inline NvU32 nvGetPrimaryHwHeadFromMask(const NvU32 hwHeadsMask) 1987 { 1988 return GetNextHwHead(hwHeadsMask, NV_INVALID_HEAD); 1989 } 1990 1991 static inline NvU32 nvGetPrimaryHwHead(const NVDispEvoRec *pDispEvo, 1992 const NvU32 apiHead) 1993 { 1994 return (apiHead != NV_INVALID_HEAD) ? 1995 nvGetPrimaryHwHeadFromMask(pDispEvo->apiHeadState[apiHead].hwHeadsMask) : 1996 NV_INVALID_HEAD; 1997 } 1998 1999 typedef enum { 2000 NV_EVO_PASSIVE_DP_DONGLE_UNUSED, 2001 NV_EVO_PASSIVE_DP_DONGLE_DP2DVI, 2002 NV_EVO_PASSIVE_DP_DONGLE_DP2HDMI_TYPE_1, 2003 NV_EVO_PASSIVE_DP_DONGLE_DP2HDMI_TYPE_2, 2004 } NVEvoPassiveDpDongleType; 2005 2006 typedef struct NVEdidRec { 2007 NvU8 *buffer; 2008 size_t length; 2009 } NVEdidRec, *NVEdidPtr; 2010 2011 typedef struct _NVParsedEdidEvoRec { 2012 NvBool valid; 2013 NVT_EDID_INFO info; 2014 NVT_EDID_RANGE_LIMIT limits; 2015 char monitorName[NVT_EDID_MONITOR_NAME_STRING_LENGTH]; 2016 char serialNumberString[NVT_EDID_LDD_PAYLOAD_SIZE+1]; 2017 } NVParsedEdidEvoRec; 2018 2019 typedef void (*NVVBlankCallbackProc)(NVDispEvoRec *pDispEvo, 2020 NVVBlankCallbackPtr pCallbackData); 2021 2022 typedef struct _NVVBlankCallbackRec { 2023 NVListRec vblankCallbackListEntry; 2024 NVVBlankCallbackProc pCallback; 2025 void *pUserData; 2026 NvU32 apiHead; 2027 } NVVBlankCallbackRec; 2028 2029 typedef void (*NVRgLine1CallbackProc)(NVDispEvoRec *pDispEvo, 2030 const NvU32 head, 2031 NVRgLine1CallbackPtr pCallbackData); 2032 2033 typedef struct _NVRgLine1CallbackRec { 2034 NVRgLine1CallbackProc pCallbackProc; 2035 void *pUserData; 2036 } NVRgLine1CallbackRec; 2037 2038 typedef struct _NVDpyAttributeRequestedDitheringConfigRec { 2039 enum NvKmsDpyAttributeRequestedDitheringValue state; 2040 enum NvKmsDpyAttributeRequestedDitheringDepthValue depth; 2041 enum NvKmsDpyAttributeRequestedDitheringModeValue mode; 2042 } NVDpyAttributeRequestedDitheringConfig; 2043 2044 typedef struct _NVDpyEvoRec { 2045 NVListRec dpyListEntry; 2046 NVDpyId id; 2047 2048 char name[NVKMS_DPY_NAME_SIZE]; 2049 2050 NvU32 apiHead; 2051 2052 struct _NVDispEvoRec *pDispEvo; 2053 NVConnectorEvoPtr pConnectorEvo; 2054 2055 NvBool hasBacklightBrightness : 1; 2056 NvBool internal : 1; 2057 NvBool allowDVISpecPClkOverride : 1; 2058 2059 /* whether the connected dpy is HDMI capable */ 2060 NvBool hdmiCapable : 1; 2061 NvBool isVrHmd : 1; 2062 2063 /* 2064 * Maximum single link and total allowed pixel clock. This is first 2065 * reported by RM through DpyProbeMaxPixelClock, and then potentially 2066 * overridden by the EVO SOR capabilities for HDMI and DVI through 2067 * UpdateMaxPixelClock. 2068 */ 2069 NvU32 maxPixelClockKHz; 2070 NvU32 maxSingleLinkPixelClockKHz; 2071 2072 NVEdidRec edid; 2073 NVParsedEdidEvoRec parsedEdid; 2074 2075 NVDpyAttributeRequestedDitheringConfig requestedDithering; 2076 2077 enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace; 2078 enum NvKmsDpyAttributeColorRangeValue requestedColorRange; 2079 2080 NVAttributesSetEvoRec currentAttributes; 2081 2082 struct { 2083 char *addressString; 2084 NVDPLibDevicePtr pDpLibDevice; // DP Lib's notion of the device. 2085 NvBool inbandStereoSignaling; 2086 2087 NvU8 laneCount; // NV0073_CTRL_DP_DATA_SET_LANE_COUNT 2088 NvU8 linkRate; // NV0073_CTRL_DP_DATA_SET_LINK_BW 2089 enum NvKmsDpyAttributeDisplayportConnectorTypeValue connectorType; 2090 NvBool sinkIsAudioCapable; 2091 2092 struct { 2093 NvBool valid; 2094 NvU8 buffer[NVKMS_GUID_SIZE]; 2095 char str[NVKMS_GUID_STRING_SIZE]; 2096 } guid; 2097 2098 /* 2099 * When the DP serializer is in MST mode, this field is used to uniquely 2100 * identify each MST DPY that's connected to the DP serializer. 2101 * 2102 * This field is only valid for DP serializer DPYs, and pDpLibDevice 2103 * must be NULL in this case. 2104 */ 2105 NvU8 serializerStreamIndex; 2106 } dp; 2107 2108 struct { 2109 HDMI_SRC_CAPS srcCaps; 2110 HDMI_SINK_CAPS sinkCaps; 2111 } hdmi; 2112 2113 struct { 2114 NvBool ycbcr422Capable; 2115 NvBool ycbcr444Capable; 2116 } colorSpaceCaps; 2117 2118 struct { 2119 NvBool supported : 1; 2120 NvBool requiresModetimingPatching : 1; 2121 NvBool isDLP : 1; 2122 NvBool isAegis : 1; 2123 NvBool requiresVbiAdjustment : 1; 2124 NvU32 subType; 2125 int indexInOverrideTimings; 2126 } stereo3DVision; 2127 2128 struct { 2129 enum NvKmsDpyVRRType type; 2130 NvU32 edidTimeoutMicroseconds; 2131 NvBool needsSwFramePacing; 2132 } vrr; 2133 } NVDpyEvoRec; 2134 2135 static inline NvBool nvDpyEvoIsDPMST(const NVDpyEvoRec *pDpyEvo) 2136 { 2137 return nvDpyIdIsInDpyIdList(pDpyEvo->id, 2138 pDpyEvo->pDispEvo->displayPortMSTIds); 2139 } 2140 2141 // Return a pDpy's connector's display ID 2142 static inline NvU32 nvDpyEvoGetConnectorId(const NVDpyEvoRec *pDpyEvo) 2143 { 2144 NvU32 rmDpyId = nvDpyIdToNvU32(pDpyEvo->pConnectorEvo->displayId); 2145 2146 // This function shouldn't be used for DP MST dynamic devices. 2147 nvAssert(!nvDpyEvoIsDPMST(pDpyEvo)); 2148 nvAssert(ONEBITSET(rmDpyId)); 2149 2150 return rmDpyId; 2151 } 2152 2153 static inline 2154 NvBool nvConnectorIsInternal(const NVConnectorEvoRec *pConnectorEvo) 2155 { 2156 /* For mobile GPUs check for LVDS or embedded DisplayPort signal flag. 2157 * If found, DFP is internal*/ 2158 return (pConnectorEvo->legacyType == 2159 NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP) && 2160 (((pConnectorEvo->pDispEvo->pDevEvo->mobile) && 2161 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _SIGNAL, _LVDS, 2162 pConnectorEvo->dfpInfo))) || 2163 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _SIGNAL, _DSI, 2164 pConnectorEvo->dfpInfo)) || 2165 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _EMBEDDED_DISPLAYPORT, _TRUE, 2166 pConnectorEvo->dfpInfo))); 2167 } 2168 2169 static inline NvU32 NV_EVO_LOCK_PIN(NvU32 n) 2170 { 2171 return NV_EVO_LOCK_PIN_0 + n; 2172 } 2173 2174 static inline NvU32 NV_EVO_LOCK_PIN_INTERNAL(NvU32 n) 2175 { 2176 return NV_EVO_LOCK_PIN_INTERNAL_0 + n; 2177 } 2178 2179 static inline NvBool NV_EVO_LOCK_PIN_IS_INTERNAL(NvU32 n) 2180 { 2181 ct_assert(NV_IS_UNSIGNED(n) && NV_EVO_LOCK_PIN_INTERNAL_0 == 0); 2182 return n < NV_EVO_LOCK_PIN_0; 2183 } 2184 2185 2186 /* 2187 * Utility macro for looping over all the pConnectorsEvo on a pDispEvo. 2188 */ 2189 #define FOR_ALL_EVO_CONNECTORS(_pConnectorEvo, _pDispEvo) \ 2190 nvListForEachEntry((_pConnectorEvo), \ 2191 &(_pDispEvo)->connectorList, connectorListEntry) 2192 2193 /* 2194 * Utility macro for declaring a for loop to walk over all the 2195 * pDispEvos on a particular pDevEvo. 2196 */ 2197 #define FOR_ALL_EVO_DISPLAYS(_pDispEvo, _i, _pDevEvo) \ 2198 for ((_i) = 0, \ 2199 (_pDispEvo) = (_pDevEvo)->pDispEvo[0]; \ 2200 (_pDispEvo); \ 2201 (_i)++, (_pDispEvo) = ((_i) < (_pDevEvo)->nDispEvo) ? \ 2202 (_pDevEvo)->pDispEvo[(_i)] : NULL) 2203 2204 #define FOR_ALL_EVO_DPYS(_pDpyEvo, _dpyIdList, _pDispEvo) \ 2205 nvListForEachEntry((_pDpyEvo), &(_pDispEvo)->dpyList, dpyListEntry) \ 2206 if (nvDpyIdIsInDpyIdList((_pDpyEvo)->id, (_dpyIdList))) 2207 2208 #define FOR_ALL_EVO_FRAMELOCKS(_pFrameLockEvo) \ 2209 nvListForEachEntry(_pFrameLockEvo, &nvEvoGlobal.frameLockList, \ 2210 frameLockListEntry) 2211 2212 #define FOR_ALL_EVO_DEVS(_pDevEvo) \ 2213 nvListForEachEntry(_pDevEvo, &nvEvoGlobal.devList, devListEntry) 2214 2215 #define FOR_ALL_DEFERRED_REQUEST_FIFOS_IN_SWAP_GROUP( \ 2216 _pSwapGroup, _pDeferredRequestFifo) \ 2217 nvListForEachEntry((_pDeferredRequestFifo), \ 2218 &(_pSwapGroup)->deferredRequestFifoList, \ 2219 swapGroup.deferredRequestFifoListEntry) 2220 2221 #define FOR_EACH_SUBDEV_IN_MASK(_sd, _mask) \ 2222 FOR_EACH_INDEX_IN_MASK(32, _sd, _mask) 2223 2224 #define FOR_EACH_SUBDEV_IN_MASK_END \ 2225 FOR_EACH_INDEX_IN_MASK_END 2226 2227 static inline NVDpyEvoPtr nvGetOneArbitraryDpyEvo(NVDpyIdList dpyIdList, 2228 const NVDispEvoRec *pDispEvo) 2229 { 2230 NVDpyEvoPtr pDpyEvo; 2231 2232 nvAssert(nvDpyIdListIsASubSetofDpyIdList(dpyIdList, 2233 pDispEvo->validDisplays)); 2234 2235 FOR_ALL_EVO_DPYS(pDpyEvo, dpyIdList, pDispEvo) { 2236 return pDpyEvo; 2237 } 2238 2239 return NULL; 2240 } 2241 2242 2243 /* 2244 * Return whether or not the display devices on the connector should 2245 * be handled by the DP library. 2246 */ 2247 static inline NvBool nvConnectorUsesDPLib(const NVConnectorEvoRec 2248 *pConnectorEvo) 2249 { 2250 return (pConnectorEvo->pDpLibConnector != NULL); 2251 } 2252 2253 static inline 2254 NvBool nvConnectorIsDPSerializer(const NVConnectorEvoRec *pConnectorEvo) 2255 { 2256 return (pConnectorEvo->type == NVKMS_CONNECTOR_TYPE_DP_SERIALIZER); 2257 } 2258 2259 /* 2260 * Return whether or not the display device given is handled by the DP 2261 * library. 2262 */ 2263 static inline NvBool nvDpyUsesDPLib(const NVDpyEvoRec *pDpyEvo) 2264 { 2265 return nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo); 2266 } 2267 2268 /* 2269 * Return whether this dpy is active. The dpy is active if it is 2270 * driven by a head. 2271 */ 2272 static inline NvBool nvDpyEvoIsActive(const NVDpyEvoRec *pDpyEvo) 2273 { 2274 return (pDpyEvo->apiHead != NV_INVALID_HEAD); 2275 } 2276 2277 /* 2278 * Return true if this dpy reports an EDID supporting HDMI 3D and 2279 * isn't connected via active DisplayPort. 2280 */ 2281 static inline NvBool nvDpyEvoSupportsHdmi3D(const NVDpyEvoRec *pDpyEvo) 2282 { 2283 return (pDpyEvo->parsedEdid.valid && 2284 pDpyEvo->parsedEdid.info.HDMI3DSupported && 2285 !((pDpyEvo->pConnectorEvo->or.protocol == 2286 NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A) || 2287 (pDpyEvo->pConnectorEvo->or.protocol == 2288 NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B))); 2289 2290 } 2291 2292 static inline NvBool nvHeadIsActive(const NVDispEvoRec *pDispEvo, 2293 const NvU32 head) 2294 { 2295 return (head < ARRAY_LEN(pDispEvo->headState)) && 2296 (pDispEvo->headState[head].pConnectorEvo != NULL); 2297 } 2298 2299 static inline NvBool nvApiHeadIsActive(const NVDispEvoRec *pDispEvo, 2300 const NvU32 apiHead) 2301 { 2302 return (apiHead < ARRAY_LEN(pDispEvo->apiHeadState)) && 2303 (!nvDpyIdListIsEmpty(pDispEvo->apiHeadState[apiHead].activeDpys)); 2304 } 2305 2306 /*! 2307 * Return the mask of active heads on this pDispEvo. 2308 */ 2309 static inline NvU32 nvGetActiveHeadMask(NVDispEvoPtr pDispEvo) 2310 { 2311 NvU32 head; 2312 NvU32 headMask = 0; 2313 2314 for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { 2315 if (nvHeadIsActive(pDispEvo, head)) { 2316 headMask |= 1 << head; 2317 } 2318 } 2319 2320 return headMask; 2321 } 2322 2323 static inline NvBool nvAllHeadsInactive(const NVDevEvoRec *pDevEvo) 2324 { 2325 NVDispEvoPtr pDispEvo; 2326 NvU32 dispIndex; 2327 NvU32 head; 2328 2329 FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { 2330 for (head = 0; head < pDevEvo->numHeads; head++) { 2331 if (nvHeadIsActive(pDispEvo, head)) { 2332 return FALSE; 2333 } 2334 } 2335 } 2336 2337 return TRUE; 2338 } 2339 2340 /* 2341 * Return the list of dpys that are currently active on the given disp. 2342 */ 2343 static inline NVDpyIdList nvActiveDpysOnDispEvo(const NVDispEvoRec *pDispEvo) 2344 { 2345 NVDpyIdList dpyIdList = nvEmptyDpyIdList(); 2346 NvU32 apiHead; 2347 2348 for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { 2349 const NVDispApiHeadStateEvoRec *pApiHeadState = 2350 &pDispEvo->apiHeadState[apiHead]; 2351 2352 dpyIdList = nvAddDpyIdListToDpyIdList(dpyIdList, 2353 pApiHeadState->activeDpys); 2354 } 2355 2356 return dpyIdList; 2357 } 2358 2359 static inline NvU32 nvGpuIdOfDispEvo(const NVDispEvoRec *pDispEvo) 2360 { 2361 nvAssert(pDispEvo->displayOwner < pDispEvo->pDevEvo->numSubDevices); 2362 return pDispEvo->pDevEvo->pSubDevices[pDispEvo->displayOwner]->gpuId; 2363 } 2364 2365 static inline NvBool nvIsEmulationEvo(const NVDevEvoRec *pDevEvo) 2366 { 2367 return pDevEvo->simulationType != 2368 NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE; 2369 } 2370 2371 static inline NvBool nvIs3DVisionStereoEvo(const enum NvKmsStereoMode stereo) 2372 { 2373 return (stereo == NVKMS_STEREO_NVIDIA_3D_VISION || 2374 stereo == NVKMS_STEREO_NVIDIA_3D_VISION_PRO); 2375 } 2376 2377 /* 2378 * Utility macro for iterating over all head bits set in a head bit mask 2379 */ 2380 #define FOR_ALL_HEADS(_head, _headMask) \ 2381 for((_head) = 0; \ 2382 (_headMask) >> (_head); \ 2383 (_head)++) \ 2384 if ((_headMask) & (1 << (_head))) 2385 2386 typedef struct _NVLutSurfaceEvo { 2387 NVDevEvoPtr pDevEvo; 2388 2389 NvU32 handle; 2390 NvU32 size; 2391 2392 NvU32 dispCtxDma; 2393 2394 NvU32 allocRefCnt; /* Only used for dynamically allocated LUTs */ 2395 2396 NvU64 gpuAddress; 2397 void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; 2398 2399 /* Keep track of prefetched surfaces. */ 2400 NvU32 difrLastPrefetchPass; 2401 2402 } NVLutSurfaceEvoRec; 2403 2404 typedef struct _NVFrameLockEvo { 2405 NVListRec frameLockListEntry; 2406 2407 /* array of subdev GPU IDs */ 2408 NvU32 nGpuIds; 2409 NvU32 gpuIds[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; 2410 2411 NvU32 gsyncId; 2412 NvU32 device; /* RM device handle for this object */ 2413 2414 int fpgaIdAndRevision; /* FPGA revId (including firmware version 2415 * and board ID) */ 2416 2417 int firmwareMajorVersion; /* FPGA firmware major version */ 2418 int firmwareMinorVersion; /* FPGA firmware minor version */ 2419 NvU32 boardId; /* NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_* */ 2420 NvU32 caps; /* Various capabilities flags */ 2421 2422 NvU32 maxSyncSkew; /* Max sync skew increment */ 2423 NvU32 syncSkewResolution; /* In nanoseconds */ 2424 NvU32 maxSyncInterval; /* Max sync interval */ 2425 2426 NvU32 houseSyncUseable; 2427 2428 /* House sync mode requested by user */ 2429 enum NvKmsFrameLockAttributeHouseSyncModeValue houseSyncMode; 2430 NvU32 houseSyncModeValidValues; 2431 2432 NvBool houseSyncAssy; /* Current desired state */ 2433 NvBool houseSyncArmed; /* Current hardware state */ 2434 2435 NvU8 connectedGpuMask; /* bitmask of GPUs that are connected */ 2436 NvU8 syncReadyGpuMask; /* bitmask of GPUs that are syncReady */ 2437 2438 NvBool syncReadyLast; /* Previous NV_CTRL_FRAMELOCK_SYNC_READY 2439 * value changed either from nvctrl or 2440 * the RM, used to avoid resending events 2441 * since RM doesn't trigger a SYNC_READY 2442 * event on framelock disable */ 2443 2444 NvBool videoModeReadOnly; /* If video mode is read-only */ 2445 2446 NvU32 maxMulDivValue; /* Max sync multiply/divide value */ 2447 2448 NvBool mulDivSupported; /* Whether this board supports setting a sync 2449 * multiplier/divider; maxMulDivValue is only 2450 * valid if this is true */ 2451 2452 /* Current device state */ 2453 enum NvKmsFrameLockAttributePolarityValue polarity; 2454 NvU32 syncDelay; 2455 NvU32 syncInterval; 2456 enum NvKmsFrameLockAttributeVideoModeValue videoMode; 2457 NvU8 mulDivValue; 2458 enum NvKmsFrameLockAttributeMulDivModeValue mulDivMode; 2459 NvBool testMode; 2460 2461 } NVFrameLockEvoRec; 2462 2463 /*! 2464 * The buffer that accumulates a string with information returned to 2465 * the client. 2466 */ 2467 typedef struct _NVEvoInfoString { 2468 NvU16 length; /*! strlen(s); excludes the nul terminator */ 2469 NvU16 totalLength; /*! number of bytes in the buffer pointed to by 's' */ 2470 char *s; /*! pointer to the buffer to be written to */ 2471 } NVEvoInfoStringRec; 2472 2473 enum NvHsMapPermissions { 2474 NvHsMapPermissionsNone, 2475 NvHsMapPermissionsReadOnly, 2476 NvHsMapPermissionsReadWrite, 2477 }; 2478 2479 #define NV_HS_BAD_GPU_ADDRESS ((NvU64) -1) 2480 2481 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED1BPP ( \ 2482 NVBIT64(NvKmsSurfaceMemoryFormatI8)) 2483 2484 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED2BPP ( \ 2485 NVBIT64(NvKmsSurfaceMemoryFormatA1R5G5B5) | \ 2486 NVBIT64(NvKmsSurfaceMemoryFormatX1R5G5B5) | \ 2487 NVBIT64(NvKmsSurfaceMemoryFormatR5G6B5)) 2488 2489 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED4BPP ( \ 2490 NVBIT64(NvKmsSurfaceMemoryFormatA8R8G8B8) | \ 2491 NVBIT64(NvKmsSurfaceMemoryFormatX8R8G8B8) | \ 2492 NVBIT64(NvKmsSurfaceMemoryFormatA2B10G10R10) | \ 2493 NVBIT64(NvKmsSurfaceMemoryFormatX2B10G10R10) | \ 2494 NVBIT64(NvKmsSurfaceMemoryFormatA8B8G8R8) | \ 2495 NVBIT64(NvKmsSurfaceMemoryFormatX8B8G8R8)) 2496 2497 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED8BPP ( \ 2498 NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) | \ 2499 NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) | \ 2500 NVBIT64(NvKmsSurfaceMemoryFormatR16G16B16A16)) 2501 2502 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PACKED422 ( \ 2503 NVBIT64(NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422) | \ 2504 NVBIT64(NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422)) 2505 2506 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP420 ( \ 2507 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N420) | \ 2508 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N420)) 2509 2510 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP422 ( \ 2511 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N422) | \ 2512 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N422)) 2513 2514 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP444 ( \ 2515 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N444) | \ 2516 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N444)) 2517 2518 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP420 ( \ 2519 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N420) | \ 2520 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N420) | \ 2521 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N420) | \ 2522 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N420)) 2523 2524 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP422 ( \ 2525 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N422) | \ 2526 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N422) | \ 2527 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N422) | \ 2528 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N422)) 2529 2530 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP444 ( \ 2531 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N444) | \ 2532 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N444) | \ 2533 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N444) | \ 2534 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N444)) 2535 2536 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PLANAR444 ( \ 2537 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8___V8_N444)) 2538 2539 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PLANAR420 ( \ 2540 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8___V8_N420)) 2541 2542 struct _NVSurfaceEvoRec { 2543 /* 2544 * By default, all NVSurfaceEvoRecs will have requireCtxDma == TRUE, and 2545 * have a ctxDma allocated and placed in the display engine hash table for 2546 * each plane. 2547 * 2548 * But, if the client specified the noDisplayHardwareAccess flag, 2549 * requireCtxDma will be FALSE, and ctxDma will be 0 for all planes. 2550 * 2551 * requireCtxDma is used to remember what the client requested, so that 2552 * we correctly honor noDisplayHardwareAccess across 2553 * FreeSurfaceCtxDmasForAllOpens() / 2554 * AllocSurfaceCtxDmasForAllOpens() cycles. 2555 */ 2556 NvBool requireCtxDma; 2557 2558 struct { 2559 NvU32 rmHandle; 2560 NvU32 ctxDma; 2561 NvU32 pitch; 2562 NvU64 offset; 2563 NvU64 rmObjectSizeInBytes; 2564 } planes[NVKMS_MAX_PLANES_PER_SURFACE]; 2565 2566 struct { 2567 const struct NvKmsPerOpenDev *pOpenDev; 2568 NvKmsSurfaceHandle surfaceHandle; 2569 } owner; 2570 2571 NvU32 widthInPixels; 2572 NvU32 heightInPixels; 2573 2574 NvU32 log2GobsPerBlockY; 2575 2576 /* 2577 * GPU virtual address of the surface, in NVKMS's VA space for use by 2578 * headSurface. 2579 */ 2580 NvU64 gpuAddress; 2581 2582 /* 2583 * HeadSurface needs a CPU mapping of surfaces containing semaphores. 2584 */ 2585 void *cpuAddress[NVKMS_MAX_SUBDEVICES]; 2586 2587 enum NvKmsSurfaceMemoryLayout layout; 2588 enum NvKmsSurfaceMemoryFormat format; 2589 2590 NvKmsMemoryIsoType isoType; 2591 2592 /* 2593 * A surface has two reference counts: 2594 * 2595 * - rmRefCnt indicates how many uses of the surface reference 2596 * NVSurfaceEvoRec::planes[]::rmHandle (the surface owner who registered 2597 * the surface, EVO currently displaying the surface, an open 2598 * surface grant file descriptor). 2599 * 2600 * - structRefCnt indicates how many uses of the surface reference 2601 * the NVSurfaceEvoRec. In addition to the rmRefCnt uses, this 2602 * will also count NVKMS clients who acquired the surface 2603 * through GRANT_SURFACE/ACQUIRE_SURFACE. 2604 * 2605 * When a client registers a surface, both reference counts will 2606 * be initialized to 1. The RM surface for each plane will be unduped when 2607 * rmRefCnt reaches zero. The NVSurfaceEvoRec structure will be 2608 * freed when structRefCnt reaches zero. 2609 * 2610 * In most cases, one of the following will be true: 2611 * (rmRefCnt == 0) && (structRefCnt == 0) 2612 * (rmRefCnt != 0) && (structRefCnt != 0) 2613 * The only exception is when the owner of the surface unregisters it while 2614 * other clients still have references to it; in that case, the rmRefCnt 2615 * can drop to zero while structRefCnt is still non-zero. 2616 * 2617 * If rmRefCnt reaches zero before structRefCnt, the surface is 2618 * "orphaned": it still exists in ACQUIRE_SURFACE clients' handle 2619 * namespaces and/or granted FDs, but is not usable in subsequent API 2620 * requests (e.g., to flip, specify cursor image, etc). 2621 * 2622 * Described in a table: 2623 * 2624 * ACTION rmRefCnt structRefCnt 2625 * a) NVKMS_IOCTL_REGISTER_SURFACE =1 =1 2626 * b) flip to surface +1 +1 2627 * c) NVKMS_IOCTL_GRANT_SURFACE(grantFd) n/a +1 2628 * d) NVKMS_IOCTL_ACQUIRE_SURFACE n/a +1 2629 * e) NVKMS_IOCTL_UNREGISTER_SURFACE -1 -1 2630 * f) flip away from surface -1 -1 2631 * g) close(grantFd) n/a -1 2632 * h) NVKMS_IOCTL_RELEASE_SURFACE n/a -1 2633 * i) ..._REGISTER_DEFERRED_REQUEST_FIFO +1 +1 2634 * j) ..._UNREGISTER_DEFERRED_REQUEST_FIFO -1 -1 2635 * 2636 * (e) complements (a) 2637 * (f) complements (b) 2638 * (g) complements (c) 2639 * (h) complements (d) 2640 * (j) complements (i) 2641 */ 2642 NvU64 rmRefCnt; 2643 NvU64 structRefCnt; 2644 2645 #if NVKMS_PROCFS_ENABLE 2646 NvBool procFsFlag; 2647 #endif 2648 2649 /* 2650 * Disallow DIFR if display caching is forbidden. This will be set for 2651 * CPU accessible surfaces. 2652 */ 2653 NvBool noDisplayCaching; 2654 2655 /* Keep track of prefetched surfaces. */ 2656 NvU32 difrLastPrefetchPass; 2657 }; 2658 2659 typedef struct _NVDeferredRequestFifoRec { 2660 NVSurfaceEvoPtr pSurfaceEvo; 2661 struct NvKmsDeferredRequestFifo *fifo; 2662 2663 /* A deferred request fifo may be joined to a swapGroup. */ 2664 struct { 2665 NVSwapGroupPtr pSwapGroup; 2666 NVListRec deferredRequestFifoListEntry; 2667 NvBool ready; 2668 NvBool perEyeStereo; 2669 NvBool pendingJoined; 2670 NvBool pendingReady; 2671 NvU32 semaphoreIndex; 2672 struct NvKmsPerOpen *pOpenUnicastEvent; 2673 } swapGroup; 2674 } NVDeferredRequestFifoRec; 2675 2676 typedef struct _NVSwapGroupRec { 2677 NVListRec deferredRequestFifoList; 2678 NvBool zombie; 2679 NvBool pendingFlip; 2680 NvU32 nMembers; 2681 NvU32 nMembersReady; 2682 NvU32 nMembersPendingJoined; 2683 2684 NvU16 nClips; 2685 struct NvKmsRect *pClipList; 2686 NvBool swapGroupIsFullscreen; 2687 2688 NvU64 refCnt; 2689 } NVSwapGroupRec; 2690 2691 typedef struct { 2692 NvU32 clientHandle; 2693 2694 NVListRec devList; 2695 NVListRec frameLockList; 2696 2697 #if defined(DEBUG) 2698 NVListRec debugMemoryAllocationList; 2699 #endif 2700 2701 struct NvKmsPerOpen *nvKmsPerOpen; 2702 2703 RasterLockTopologyPtr globalTopologies; 2704 NvU32 numGlobalTopos; 2705 2706 } NVEvoGlobal; 2707 2708 extern NVEvoGlobal nvEvoGlobal; 2709 2710 /* 2711 * These enums are used during IMP validation: 2712 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE means that no changes will be made to 2713 * the current display bandwidth values. 2714 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE means that NVKMS will increase the 2715 * current display bandwidth values if required by IMP. This is typically 2716 * specified pre-modeset/flip. 2717 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST means that NVKMS may potentially 2718 * decrease the current display bandwidth values to match the current display 2719 * configuration. This is typically specified post-modeset/flip. 2720 */ 2721 typedef enum { 2722 NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE = 0, 2723 NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE = 1, 2724 NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST = 2, 2725 } NVEvoReallocateBandwidthMode; 2726 2727 typedef struct { 2728 struct { 2729 /* pTimings == NULL => this head is disabled */ 2730 const NVHwModeTimingsEvo *pTimings; 2731 NvBool enableDsc; 2732 NvBool b2Heads1Or; 2733 enum nvKmsPixelDepth pixelDepth; 2734 const struct NvKmsUsageBounds *pUsage; 2735 NvU32 displayId; 2736 NvU32 orIndex; 2737 NvU8 orType; /* NV0073_CTRL_SPECIFIC_OR_TYPE_* */ 2738 } head[NVKMS_MAX_HEADS_PER_DISP]; 2739 2740 NvBool requireBootClocks; 2741 NVEvoReallocateBandwidthMode reallocBandwidth; 2742 } NVEvoIsModePossibleDispInput; 2743 2744 typedef struct { 2745 NvBool possible; 2746 NvU32 minRequiredBandwidthKBPS; 2747 NvU32 floorBandwidthKBPS; 2748 } NVEvoIsModePossibleDispOutput; 2749 2750 /* CRC-query specific defines */ 2751 /*! 2752 * Structure that defines information about where a single variable is stored in 2753 * the CRC32NotifierEntry structure 2754 */ 2755 typedef struct _CRC32NotifierEntryRec { 2756 NvU32 field_offset; /* Var's offset from start of CRC32Notifier Struct */ 2757 NvU32 field_base_bit; /* LSB bit index for variable in entry */ 2758 NvU32 field_extent_bit; /* MSB bit index for variable in entry */ 2759 struct NvKmsDpyCRC32 *field_frame_values; /* Array to store read field values across frames */ 2760 } CRC32NotifierEntryRec; 2761 2762 /*! 2763 * Internally identifies flag read from CRC32Notifier's Status for error-checking 2764 */ 2765 enum CRC32NotifierFlagType { 2766 NVEvoCrc32NotifierFlagCount, 2767 NVEvoCrc32NotifierFlagCrcOverflow, 2768 }; 2769 2770 /*! 2771 * Structure that defines information about where a single flag is stored in 2772 * the Status of the CRC32NotifierEntry structure 2773 */ 2774 typedef struct _CRC32NotifierEntryFlags { 2775 NvU32 flag_base_bit; /* LSB bit index for flag in entry */ 2776 NvU32 flag_extent_bit; /* MSB bit index for flag in entry */ 2777 enum CRC32NotifierFlagType flag_type; /* Type of error-checking to perform on flag */ 2778 } CRC32NotifierEntryFlags; 2779 2780 /*! 2781 * Internal Crc32NotifierRead structure used to collect multiple frames of CRC 2782 * data from a QueryCRC32 call. Arrays should be allocated to match 2783 * entry_count frames. 2784 */ 2785 typedef struct _CRC32NotifierCrcOut { 2786 /*! 2787 * Array of CRCs generated from the Compositor hardware 2788 */ 2789 struct NvKmsDpyCRC32 *compositorCrc32; 2790 2791 /*! 2792 * CRCs generated from the RG hardware, if head is driving RG/SF. 2793 */ 2794 struct NvKmsDpyCRC32 *rasterGeneratorCrc32; 2795 2796 /*! 2797 * Crc values generated from the target SF/OR depending on connector's OR type 2798 */ 2799 struct NvKmsDpyCRC32 *outputCrc32; 2800 2801 } CRC32NotifierCrcOut; 2802 2803 2804 typedef const struct _nv_evo_hal { 2805 void (*SetRasterParams) (NVDevEvoPtr pDevEvo, int head, 2806 const NVHwModeTimingsEvo *pTimings, 2807 const NvU8 tilePosition, 2808 const NVDscInfoEvoRec *pDscInfo, 2809 const NVEvoColorRec *pOverscanColor, 2810 NVEvoUpdateState *updateState); 2811 void (*SetProcAmp) (NVDispEvoPtr pDispEvo, const NvU32 head, 2812 NVEvoUpdateState *updateState); 2813 void (*SetHeadControl) (NVDevEvoPtr, int sd, int head, 2814 NVEvoUpdateState *updateState); 2815 void (*SetHeadRefClk) (NVDevEvoPtr, int head, NvBool external, 2816 NVEvoUpdateState *updateState); 2817 void (*HeadSetControlOR) (NVDevEvoPtr pDevEvo, 2818 const int head, 2819 const NVHwModeTimingsEvo *pTimings, 2820 const enum nvKmsPixelDepth pixelDepth, 2821 const NvBool colorSpaceOverride, 2822 NVEvoUpdateState *updateState); 2823 void (*ORSetControl) (NVDevEvoPtr pDevEvo, 2824 const NVConnectorEvoRec *pConnectorEvo, 2825 const enum nvKmsTimingsProtocol protocol, 2826 const NvU32 orIndex, 2827 const NvU32 headMask, 2828 NVEvoUpdateState *updateState); 2829 void (*HeadSetDisplayId) (NVDevEvoPtr pDevEvo, 2830 const NvU32 head, const NvU32 displayId, 2831 NVEvoUpdateState *updateState); 2832 NvBool (*SetUsageBounds) (NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, 2833 const struct NvKmsUsageBounds *pUsage, 2834 NVEvoUpdateState *updateState); 2835 void (*Update) (NVDevEvoPtr, 2836 const NVEvoUpdateState *updateState, 2837 NvBool releaseElv); 2838 void (*IsModePossible) (NVDispEvoPtr, 2839 const NVEvoIsModePossibleDispInput *, 2840 NVEvoIsModePossibleDispOutput *); 2841 void (*PrePostIMP) (NVDispEvoPtr, NvBool isPre); 2842 void (*SetNotifier) (NVDevEvoRec *pDevEvo, 2843 const NvBool notify, 2844 const NvBool awaken, 2845 const NvU32 notifier, 2846 NVEvoUpdateState *updateState); 2847 NvBool (*GetCapabilities) (NVDevEvoPtr); 2848 void (*Flip) (NVDevEvoPtr pDevEvo, 2849 NVEvoChannelPtr pChannel, 2850 const NVFlipChannelEvoHwState *pHwState, 2851 NVEvoUpdateState *updateState, 2852 NvBool bypassComposition); 2853 void (*FlipTransitionWAR) (NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, 2854 const NVEvoSubDevHeadStateRec *pSdHeadState, 2855 const NVFlipEvoHwState *pFlipState, 2856 NVEvoUpdateState *updateState); 2857 void (*FillLUTSurface) (NVEvoLutEntryRec *pLUTBuffer, 2858 const NvU16 *red, 2859 const NvU16 *green, 2860 const NvU16 *blue, 2861 int nColorMapEntries, int depth); 2862 void (*SetLUTContextDma) (const NVDispEvoRec *pDispEvo, 2863 const int head, 2864 NVLutSurfaceEvoPtr pLutSurfEvo, 2865 NvBool enableBaseLut, 2866 NvBool enableOutputLut, 2867 NVEvoUpdateState *updateState, 2868 NvBool bypassComposition); 2869 void (*SetOutputScaler) (const NVDispEvoRec *pDispEvo, const NvU32 head, 2870 const NvU32 imageSharpeningValue, 2871 NVEvoUpdateState *updateState); 2872 void (*SetViewportPointIn) (NVDevEvoPtr pDevEvo, const int head, 2873 NvU16 x, NvU16 y, 2874 NVEvoUpdateState *updateState); 2875 void (*SetViewportInOut) (NVDevEvoPtr pDevEvo, const int head, 2876 const NVHwModeViewPortEvo *pViewPortOutMin, 2877 const NVHwModeViewPortEvo *pViewPortOut, 2878 const NVHwModeViewPortEvo *pViewPortOutMax, 2879 NVEvoUpdateState *updateState); 2880 void (*SetCursorImage) (NVDevEvoPtr pDevEvo, const int head, 2881 const NVSurfaceEvoRec *, 2882 NVEvoUpdateState *updateState, 2883 const struct NvKmsCompositionParams *pCursorCompParams); 2884 NvBool (*ValidateCursorSurface)(const NVDevEvoRec *pDevEvo, 2885 const NVSurfaceEvoRec *pSurfaceEvo); 2886 NvBool (*ValidateWindowFormat)(const enum NvKmsSurfaceMemoryFormat format, 2887 const struct NvKmsRect *sourceFetchRect, 2888 NvU32 *hwFormatOut); 2889 void (*InitCompNotifier) (const NVDispEvoRec *pDispEvo, int idx); 2890 NvBool (*IsCompNotifierComplete) (NVDispEvoPtr pDispEvo, int idx); 2891 void (*WaitForCompNotifier) (const NVDispEvoRec *pDispEvo, int idx); 2892 void (*SetDither) (NVDispEvoPtr pDispEvo, const int head, 2893 const NvBool enabled, const NvU32 type, 2894 const NvU32 algo, 2895 NVEvoUpdateState *updateState); 2896 void (*SetStallLock) (NVDispEvoPtr pDispEvo, const int head, 2897 NvBool enable, NVEvoUpdateState *updateState); 2898 void (*SetDisplayRate) (NVDispEvoPtr pDispEvo, const int head, 2899 NvBool enable, 2900 NVEvoUpdateState *updateState, 2901 NvU32 timeoutMicroseconds); 2902 void (*InitChannel) (NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel); 2903 void (*InitDefaultLut) (NVDevEvoPtr pDevEvo); 2904 void (*InitWindowMapping) (const NVDispEvoRec *pDispEvo, 2905 NVEvoModesetUpdateState *pModesetUpdateState); 2906 NvBool (*IsChannelIdle) (NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd, 2907 NvBool *result); 2908 NvBool (*IsChannelMethodPending)(NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd, 2909 NvBool *result); 2910 NvBool (*ForceIdleSatelliteChannel)(NVDevEvoPtr, 2911 const NVEvoIdleChannelState *idleChannelState); 2912 NvBool (*ForceIdleSatelliteChannelIgnoreLock)(NVDevEvoPtr, 2913 const NVEvoIdleChannelState *idleChannelState); 2914 2915 void (*AccelerateChannel)(NVDevEvoPtr pDevEvo, 2916 NVEvoChannelPtr pChannel, 2917 const NvU32 sd, 2918 const NvBool trashPendingMethods, 2919 const NvBool unblockMethodsInExecutation, 2920 NvU32 *pOldAccelerators); 2921 2922 void (*ResetChannelAccelerators)(NVDevEvoPtr pDevEvo, 2923 NVEvoChannelPtr pChannel, 2924 const NvU32 sd, 2925 const NvBool trashPendingMethods, 2926 const NvBool unblockMethodsInExecutation, 2927 NvU32 oldAccelerators); 2928 2929 NvBool (*AllocRmCtrlObject) (NVDevEvoPtr); 2930 void (*FreeRmCtrlObject) (NVDevEvoPtr); 2931 void (*SetImmPointOut) (NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd, 2932 NVEvoUpdateState *updateState, 2933 NvU16 x, NvU16 y); 2934 void (*StartCRC32Capture) (NVDevEvoPtr pDevEvo, 2935 NVEvoDmaPtr pDma, 2936 NVConnectorEvoPtr pConnectorEvo, 2937 const enum nvKmsTimingsProtocol protocol, 2938 const NvU32 orIndex, 2939 NvU32 head, 2940 NvU32 sd, 2941 NVEvoUpdateState *updateState /* out */); 2942 void (*StopCRC32Capture) (NVDevEvoPtr pDevEvo, 2943 NvU32 head, 2944 NVEvoUpdateState *updateState /* out */); 2945 NvBool (*QueryCRC32) (NVDevEvoPtr pDevEvo, 2946 NVEvoDmaPtr pDma, 2947 NvU32 sd, 2948 NvU32 entry_count, 2949 CRC32NotifierCrcOut *crc32 /* out */, 2950 NvU32 *numCRC32 /* out */); 2951 void (*GetScanLine) (const NVDispEvoRec *pDispEvo, 2952 const NvU32 head, 2953 NvU16 *pScanLine, 2954 NvBool *pInBlankingPeriod); 2955 void (*ConfigureVblankSyncObject) (NVDevEvoPtr pDevEvo, 2956 NvU16 rasterLine, 2957 NvU32 head, 2958 NvU32 semaphoreIndex, 2959 NvU32 hCtxDma, 2960 NVEvoUpdateState* pUpdateState); 2961 2962 void (*SetDscParams) (const NVDispEvoRec *pDispEvo, 2963 const NvU32 head, 2964 const NVDscInfoEvoRec *pDscInfo, 2965 const enum nvKmsPixelDepth pixelDepth); 2966 2967 void (*EnableMidFrameAndDWCFWatermark)(NVDevEvoPtr pDevEvo, 2968 NvU32 sd, 2969 NvU32 head, 2970 NvBool enable, 2971 NVEvoUpdateState *pUpdateState); 2972 2973 NvU32 (*GetActiveViewportOffset)(NVDispEvoRec *pDispEvo, NvU32 head); 2974 2975 void (*ClearSurfaceUsage) (NVDevEvoPtr pDevEvo, 2976 NVSurfaceEvoPtr pSurfaceEvo); 2977 2978 NvBool (*ComputeWindowScalingTaps)(const NVDevEvoRec *pDevEvo, 2979 const NVEvoChannel *pChannel, 2980 NVFlipChannelEvoHwState *pHwState); 2981 2982 const NVEvoScalerCaps* (*GetWindowScalingCaps)(const NVDevEvoRec *pDevEvo); 2983 2984 void (*SetMergeMode)(const NVDispEvoRec *pDispEvo, 2985 const NvU32 head, 2986 const NVEvoMergeMode mode, 2987 NVEvoUpdateState* pUpdateState); 2988 2989 struct { 2990 NvU32 supportsNonInterlockedUsageBoundsUpdate :1; 2991 NvU32 supportsDisplayRate :1; 2992 NvU32 supportsFlipLockRGStatus :1; 2993 NvU32 needDefaultLutSurface :1; 2994 NvU32 hasUnorm16OLUT :1; 2995 NvU32 supportsDigitalVibrance :1; 2996 NvU32 supportsImageSharpening :1; 2997 NvU32 supportsHDMIVRR :1; 2998 NvU32 supportsCoreChannelSurface :1; 2999 NvU32 supportsHDMIFRL :1; 3000 NvU32 supportsSetStorageMemoryLayout :1; 3001 NvU32 supportsIndependentAcqRelSemaphore :1; 3002 NvU32 supportsCoreLut :1; 3003 NvU32 supportsSynchronizedOverlayPositionUpdate :1; 3004 NvU32 supportsVblankSyncObjects :1; 3005 NvU32 requiresScalingTapsInBothDimensions :1; 3006 NvU32 supportsMergeMode :1; 3007 3008 NvU32 supportedDitheringModes; 3009 size_t impStructSize; 3010 NVEvoScalerTaps minScalerTaps; 3011 NvU64 xEmulatedSurfaceMemoryFormats; 3012 } caps; 3013 } NVEvoHAL, *NVEvoHALPtr; 3014 3015 typedef const struct _nv_evo_cursor_hal { 3016 NvU32 klass; 3017 3018 void (*MoveCursor) (NVDevEvoPtr, NvU32 sd, NvU32 head, 3019 NvS16 x, NvS16 y); 3020 void (*ReleaseElv) (NVDevEvoPtr, NvU32 sd, NvU32 head); 3021 3022 struct { 3023 NvU16 maxSize; 3024 } caps; 3025 } NVEvoCursorHAL, *NVEvoCursorHALPtr; 3026 3027 NvU32 nvEvoGetHeadSetStoragePitchValue(const NVDevEvoRec *pDevEvo, 3028 enum NvKmsSurfaceMemoryLayout layout, 3029 NvU32 pitch); 3030 3031 NvBool nvEvoGetHeadSetControlCursorValue90(const NVDevEvoRec *pDevEvo, 3032 const NVSurfaceEvoRec *pSurfaceEvo, 3033 NvU32 *pValue); 3034 3035 static inline NvBool nvEvoScalingUsageBoundsEqual( 3036 const struct NvKmsScalingUsageBounds *a, 3037 const struct NvKmsScalingUsageBounds *b) 3038 { 3039 return (a->maxVDownscaleFactor == b->maxVDownscaleFactor) && 3040 (a->maxHDownscaleFactor == b->maxHDownscaleFactor) && 3041 (a->vTaps == b->vTaps) && 3042 (a->vUpscalingAllowed == b->vUpscalingAllowed); 3043 } 3044 3045 static inline NvBool 3046 nvEvoLayerUsageBoundsEqual(const struct NvKmsUsageBounds *a, 3047 const struct NvKmsUsageBounds *b, 3048 const NvU32 layer) 3049 { 3050 return (a->layer[layer].usable == b->layer[layer].usable) && 3051 (a->layer[layer].supportedSurfaceMemoryFormats == 3052 b->layer[layer].supportedSurfaceMemoryFormats) && 3053 nvEvoScalingUsageBoundsEqual(&a->layer[layer].scaling, 3054 &b->layer[layer].scaling); 3055 } 3056 3057 static inline void nvAssignHwHeadsMaskApiHeadState( 3058 NVDispApiHeadStateEvoRec *pApiHeadState, 3059 const NvU32 hwHeadsMask) 3060 { 3061 pApiHeadState->hwHeadsMask = hwHeadsMask; 3062 pApiHeadState->attributes.numberOfHardwareHeadsUsed = 3063 nvPopCount32(hwHeadsMask); 3064 } 3065 3066 #ifdef __cplusplus 3067 }; 3068 #endif 3069 3070 #endif /* __NVKMS_TYPES_H__ */ 3071