1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef NVPCIE_H 25 #define NVPCIE_H 26 27 28 29 /**************** Resource Manager Defines and Structures ******************\ 30 * * 31 * Private PCI Express related defines and structures. * 32 * * 33 \***************************************************************************/ 34 35 #define PCI_VENDOR_ID 0x00 36 #ifndef PCI_DEVICE_ID 37 #define PCI_DEVICE_ID 0x02 38 #endif 39 #define PCI_BASE_ADDRESS_1 0x14 /* Aperture Base */ 40 #define PCI_BASE_ADDRESS_2 0x18 /* Aperture Base */ 41 #define PCI_CAPABILITY_LIST 0x34 42 #define PCI_DEVICE_SPECIFIC 0x40 43 44 #define NV_PCI_ID 0x0 45 #define NV_PCI_ID_VENDOR 15:0 46 #define NV_PCI_ID_VENDOR_NVIDIA 0x10DE 47 #define NV_PCI_ID_DEVICE 31:16 48 49 #define PCI_MAX_SLOTS 255 50 #define PCI_MAX_LANE_WIDTH 32 51 52 #define PCI_MAX_FUNCTION 8 53 #define PCI_INVALID_VENDORID 0xFFFF 54 #define PCI_INVALID_DEVICEID 0xFFFF 55 #define PCI_INVALID_SUBVENDORID 0xFFFF 56 #define PCI_INVALID_SUBDEVICEID 0xFFFF 57 58 #define PCI_IS_VENDORID_VALID(id) (((id) != 0x0000) && ((id) != 0xFFFF)) 59 60 #define PCI_CLASS_BRIDGE_DEV 0x06 61 #define PCI_SUBCLASS_BR_HOST 0x00 62 #define PCI_MULTIFUNCTION 0x80 63 64 // From PCI Local Bus Specification, Revision 3.0 65 // and PCI Express Base Specification 6.0 66 // numbers in comments to right of values indicate 67 // the referenced section in the PCIE spec 68 69 70 #define CAP_ID_MASK 0xFF 71 72 #define CAP_ID_NULL 0x00 // 7.9.28.1 73 #define CAP_ID_PMI 0x01 // 7.5.2.1 74 #define CAP_ID_AGP 0x02 75 #define CAP_ID_VPD 0x03 // 7.9.18.1 76 #define CAP_ID_SLOT_ID 0x04 77 #define CAP_ID_MSI 0x05 // 7.7.1.1 78 #define CAP_ID_HOT_SWAP 0x06 79 #define CAP_ID_PCI_X 0x07 80 #define CAP_ID_HYPER_TRANSPORT 0x08 81 #define CAP_ID_VENDOR_SPECIFIC 0x09 82 #define CAP_ID_DEBUG_PORT 0x0A 83 #define CAP_ID_CRC 0x0B 84 #define CAP_ID_HOT_PLUG 0x0C 85 #define CAP_ID_SUBSYSTEM_ID 0x0D // 7.9.23.1 86 #define CAP_ID_AGP8X 0x0E 87 #define CAP_ID_SECURE 0x0F 88 #define CAP_ID_PCI_EXPRESS 0x10 // 7.5.3.1 89 #define CAP_ID_MSI_X 0x11 // 7.7.2.1 90 #define CAP_ID_ENHANCED_ALLOCATION 0x14 // 7.8.5.1 91 #define CAP_ID_FPB 0x15 // 7.8.11.1 92 #define CAP_ID_AF 0x13 // 7.9.21.1 93 94 // 95 // sizes for static PCI capabilities structure 96 // 97 #define CAP_NULL_SIZE 0x04 // 7.9.28 98 #define CAP_PMI_SIZE 0x08 // 7.5.2 99 #define CAP_VPD_SIZE 0x08 // 7.9.18 100 #define CAP_PCI_X_SIZE 0x3C // 7.5.3 101 #define CAP_PCI_EXPRESS_SIZE 0x3C // 7.5.3 102 #define CAP_FPB_SIZE 0x08 // 7.8.11.1 103 #define CAP_AF_SIZE 0x08 // 7.9.21 104 #define CAP_SUBSYSTEM_ID_SIZE 0x08 // 7.9.23 105 106 // MSI capability size related fields 107 #define PCI_MSI_CONTROL 0x02 // 7.7.1.2 108 #define PCI_MSI_CONTROL_64BIT_CAPABLE 7:7 109 #define PCI_MSI_CONTROL_64BIT_CAPABLE_FALSE 0 110 #define PCI_MSI_CONTROL_64BIT_CAPABLE_TRUE 1 111 #define PCI_MSI_CONTROL_PVM_CAPABLE 8:8 112 #define PCI_MSI_CONTROL_PVM_CAPABLE_FALSE 0 113 #define PCI_MSI_CONTROL_PVM_CAPABLE_TRUE 1 114 #define PCI_MSI_BASE_SIZE 0x0C // 7.7.1 115 #define PCI_MSI_64BIT_ADDR_CAPABLE_ADJ_SIZE 0x04 // 7.7.1 116 #define PCI_MSI_PVM_CAPABLE_ADJ_SIZE 0x08 // 7.7.1 117 118 // MSI-X capability size related fields 119 #define PCI_MSI_X_BASE_SIZE 0x0C // 7.7.2 120 #define PCI_MSI_X_CONTROL 0x02 // 7.7.2.2 121 #define PCI_MSI_X_CONTROL_TABLE_SIZE 10:0 122 #define PCI_MSI_X_TABLE_OFFSET_BIR 0x04 // 7.7.2.3 123 #define PCI_MSI_X_TABLE_OFFSET 31:3 124 #define PCI_MSI_X_PBR_OFFSET_BIR 0x08 // 7.7.2.4 125 #define PCI_MSI_X_PBR_OFFSET 31:3 126 #define PCI_MSI_X_TABLE_ENTRY_SIZE 0x10 // 7.7.2 127 #define PCI_MSI_X_PBR_ENTRY_SIZE 0x10 // 7.7.2 128 129 // Enhanced Allocation Capability size related fields 130 #define PCI_ENHANCED_ALLOCATION_FIRST_DW 0x00 // 7.8.5.1 131 #define PCI_ENHANCED_ALLOCATION_FIRST_DW_NUM_ENTRIES 21:16 132 #define PCI_ENHANCED_ALLOCATION_TYPE_0_BASE_SIZE 0x04 // 7.8.5.1 133 #define PCI_ENHANCED_ALLOCATION_TYPE_1_BASE_SIZE 0x08 // 7.8.5.2 134 #define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER 0x00 // 7.8.5.3 135 #define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER_ENTRY_SIZE 2:0 136 137 // PCI Vendor Specific Capability size related fields 138 #define PCI_VENDOR_SPECIFIC_CAP_HEADER 0x00 // 7.9.4 139 #define PCI_VENDOR_SPECIFIC_CAP_HEADER_LENGTH 23:16 140 141 // 142 // Extended config space size is 4096 bytes. 143 // 144 #define PCI_EXTENDED_CONFIG_SPACE_LENGTH 4096 145 146 // 147 // From PCI Local Bus Specification, Revision 3.0 148 // HEADER TYPE0 Definitions - Byte offsets 149 // 150 #define PCI_HEADER_TYPE0_VENDOR_ID 0x00 151 #define PCI_HEADER_TYPE0_DEVICE_ID 0x02 152 #define PCI_HEADER_TYPE0_COMMAND 0x04 153 #define PCI_HEADER_TYPE0_STATUS 0x06 154 #define PCI_HEADER_TYPE0_REVISION_ID 0x08 155 #define PCI_HEADER_TYPE0_PROGIF 0x09 156 #define PCI_HEADER_TYPE0_SUBCLASS 0x0A 157 #define PCI_HEADER_TYPE0_BASECLASS 0x0B 158 #define PCI_HEADER_TYPE0_CACHE_LINE_SIZE 0x0C 159 #define PCI_HEADER_TYPE0_LATENCY_TIMER 0x0D 160 #define PCI_HEADER_TYPE0_HEADER_TYPE 0x0E 161 #define PCI_HEADER_TYPE0_HEADER_TYPE_0 0 162 #define PCI_HEADER_TYPE0_HEADER_TYPE_1 1 163 #define PCI_HEADER_TYPE0_BIST 0x0F 164 #define PCI_HEADER_TYPE0_BAR0 0x10 165 #define PCI_HEADER_TYPE0_BAR1 0x14 166 #define PCI_HEADER_TYPE0_BAR2 0x18 167 #define PCI_HEADER_TYPE0_BAR3 0x1C 168 #define PCI_HEADER_TYPE0_BAR4 0x20 169 #define PCI_HEADER_TYPE0_BAR5 0x24 170 #define PCI_HEADER_TYPE0_CBCIS_PTR 0x28 171 #define PCI_HEADER_TYPE0_SUBSYS_VEN_ID 0x2C 172 #define PCI_HEADER_TYPE0_SUBSYS_ID 0x2E 173 #define PCI_HEADER_TYPE0_ROMBAR 0x30 174 #define PCI_HEADER_TYPE0_CAP_PTR 0x34 175 #define PCI_HEADER_TYPE0_INT_LINE 0x3C 176 #define PCI_HEADER_TYPE0_INT_PIN 0x3D 177 #define PCI_HEADER_TYPE0_MIN_GNT 0x3E 178 #define PCI_HEADER_TYPE0_MAX_LAT 0x3F 179 180 // 181 // From PCI Express Base Specification Revision 2.0 182 // HEADER TYPE1 Definitions 183 #define PCI_HEADER_TYPE1_BRIDGE_CONTROL 0x3E 184 #define PCI_HEADER_TYPE1_BRIDGE_CONTROL_VGA_EN 0x08 185 186 #define PCIE_LINK_CAPABILITIES_2 0x000000A4 /* R--4R */ 187 #define PCIE_LINK_CAPABILITIES_2_RSVD 0:0 /* C--VF */ 188 #define PCIE_LINK_CAPABILITIES_2_RSVD_INIT 0x00000000 /* C---V */ 189 #define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */ 190 #define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4_GEN5 0x0000001F /* R---V */ 191 #define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */ 192 #define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */ 193 #define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */ 194 #define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */ 195 #define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4 0x0000000F /* R---V */ 196 #define PCIE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT 8:8 /* C--VF */ 197 #define PCIE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */ 198 #define PCIE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP 23:23 /* R-EVF */ 199 #define PCIE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */ 200 #define PCIE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP 24:24 /* R-EVF */ 201 #define PCIE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */ 202 #define PCIE_LINK_CAPABILITIES_2_RSVD1 31:25 /* C--VF */ 203 #define PCIE_LINK_CAPABILITIES_2_RSVD1_INIT 0x00000000 /* C---V */ 204 205 // 206 // PCI Express Virtual Peer-to-Peer Approval Definition 207 // 208 // These offsets are unused in hardware on existing chips and are reserved on 209 // future chips. Software has defined a virtual PCI capability that may be 210 // emulated by hypervisors at these offsets, and this capability is not tied 211 // to any specific hardware. 212 // 213 // 214 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8 215 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0 216 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8 217 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16 218 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24 219 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC 220 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0 221 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16 222 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19 223 #define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:23 224 225 #define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250 226 227 // Chipset-specific definitions. 228 // Intel SantaRosa definitions 229 #define INTEL_2A00_CONFIG_SPACE_BASE 0x60 230 231 // Intel Montevina definitions 232 #define INTEL_2A40_CONFIG_SPACE_BASE 0x60 233 #define INTEL_2A40_ASLM_CAPABLE_REVID 0x05 234 235 // Intel EagleLake definitions 236 #define INTEL_2E00_CONFIG_SPACE_BASE 0x60 237 238 // Intel Bearlake definitions 239 #define INTEL_29XX_CONFIG_SPACE_BASE 0x60 240 241 // Intel BroadWater definitions 242 #define INTEL_29A0_CONFIG_SPACE_BASE 0x60 243 244 // Intel Grantsdale definitions 245 #define INTEL_25XX_CONFIG_SPACE_BASE 0x48 246 247 // Intel Tumwater definitions 248 #define INTEL_359E_CONFIG_SPACE_BASE 0xCC 249 250 // Intel Greencreek definitions 251 #define INTEL_25E0_CONFIG_SPACE_BASE_ADDRESS 0xE0000000 252 253 // Intel Stoakley definitions 254 #define INTEL_4000_CONFIG_SPACE_BASE_ADDRESS 0xE0000000 255 256 // Intel SkullTrail definitions 257 #define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_F 0xF0000000 258 #define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_E 0xE0000000 259 #define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_F 260 #define INTEL_4003_CONFIG_SPACE_BASE 0x64 261 262 // SiS 656 263 #define SIS_656_CONFIG_SPACE_BASE 0xE0 264 #define SIS_656_CONFIG_SPACE_BASE_ADDRESS 3:0 // mapped to 31:28 265 266 // PCI/PCIE definitions 267 #define PCI_MAX_CAPS 20 // max caps to parse 268 #define PCI_MAX_DEVICES 32 // max devices on bus 269 #define PCI_MAX_FUNCTIONS 8 // max functions for a device 270 #define PCI_CAP_HEADER_ID 7:0 // PCI cap header id 271 #define PCI_CAP_HEADER_NEXT 15:8 // PCI cap header next 272 #define PCI_COMMON_CLASS_SUBCLASS 0x0a // PCI class/subclass (word) 273 #define PCI_COMMON_CLASS_SUBBASECLASS_HOST 0x0600 // Host bridge (connect PCI to CPU) [00] + Bridge Device [06] 274 #define PCI_COMMON_CLASS_SUBBASECLASS_P2P 0x0604 // PCI-to-PCI bridge (connects PCI buses) [04] + Bridge Device [06] 275 #define PCI_COMMON_CLASS_SUBBASECLASS_VGA 0x0300 276 #define PCI_COMMON_CLASS_SUBBASECLASS_3DCTRL 0x0302 277 #define PCI_COMMON_CAP_PTR 0x34 // PCI common cap ptr (byte) 278 #define PCI_TYPE_1_SECONDARY_BUS_NUMBER 0x19 // PCI type 1 sec bus (byte) 279 #define PCI_TYPE_1_SUBORDINATE_BUS_NUMBER 0x1a // PCI type 1 sub bus (byte) 280 #define PCIE_CAP_HEADER_ID 15:0 // PCIE cap header id 281 #define PCIE_CAP_HEADER_ID_INVALID 0xffff 282 #define PCIE_CAP_HEADER_NEXT 31:20 // PCIE cap header next 283 #define PCIE_BUS_SHIFT 20 // PCIE cfg space bus shift 284 #define PCIE_DEVICE_SHIFT 15 // PCIE cfg space dev shift 285 #define PCIE_FUNC_SHIFT 12 // PCIE cfg space func shift 286 #define PCIE_CAP_VERSION 19:16 // PCIE cap version 287 #define PCIE_CAP_VERSION_2P0 2 // PCIE 2.0 version 288 #define PCIE_LINK_CNTRL_STATUS_2_OFFSET 0x30 // PCIE Link Control/Status 2 offset 289 #define PCIE_LINK_STATUS_2 31:16 // PCIE Link Status 2 Register 290 #define PCIE_LINK_STATUS_2_DE_EMPHASIS 0:0 // PCIE De-Emphasis Level 291 #define PCI_COMMON_SUBSYSTEM_VENDOR_ID 0x2c // PCI subsystem Vendor Id 292 #define PCI_COMMON_SUBSYSTEM_ID 0x2e // PCI subsystem Id 293 #define PCIE_CAPABILITY_BASE 0x100 // 1st PCIE capability. 294 295 // PCI Express Capability ID in the enhanced configuration space 296 #define PCIE_CAP_ID_NULL 0x00 // 7.9.28.1 297 #define PCIE_CAP_ID_ERROR 0x01 // 7.8.4.1 298 #define PCIE_CAP_ID_VC 0x02 // 7.9.1.1 299 #define PCIE_CAP_ID_SERIAL 0x03 // 7.9.3.1 300 #define PCIE_CAP_ID_POWER 0x04 // 7.8.1.1 301 #define PCIE_CAP_ID_ROOT_COMPLEX 0x05 // 7.9.8.1 302 #define PCIE_CAP_ID_ROOT_COMPLEX_INTERNAL_LINK_CTRL 0x06 // 7.9.9.1 303 #define PCIE_CAP_ID_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT 0x07 // 7.9.10.1 304 #define PCIE_CAP_ID_PCIE_CAP_ID_MFVC 0x08 // 7.9.2.1 305 #define PCIE_CAP_ID_RCRB 0x0A // 7.9.7.1 306 #define PCIE_CAP_ID_ACS 0x0D // 7.7.11.1 307 #define PCIE_CAP_ID_ARI 0x0E // 7.8.8.1 308 #define PCIE_CAP_ID_MULTICAST 0x12 // 7.9.11.1 309 #define PCIE_CAP_ID_RESIZABLE_BAR 0x15 // 7.8.6.1 310 #define PCIE_CAP_ID_DYNAMIC_POWER_ALLOCATION 0x16 // 7.9.12.1 311 #define PCIE_CAP_ID_TPH 0x17 // 7.9.13.1 312 #define PCIE_CAP_ID_LATENCY_TOLERANCE 0x18 // 7.8.2.1 313 #define PCIE_CAP_ID_SECONDARY_PCIE_CAPABILITY 0x19 // 7.7.3.1 314 #define PCIE_CAP_ID_PASID 0x1B // 7.8.9.1 315 #define PCIE_CAP_ID_DPC 0x1D // 7.9.14.1 316 #define PCIE_CAP_ID_L1_PM_SUBSTATES 0x1E // 7.8.3.1 317 #define PCIE_CAP_ID_PTM 0x1F // 7.9.15.1 318 #define PCIE_CAP_ID_FRS_QUEUING 0x21 // 7.8.10.1 319 #define PCIE_CAP_ID_READINESS_TIME_REPORTING 0x22 // 7.9.16.1 320 #define PCIE_CAP_ID_VENDOR_SPECIFIC 0x23 // 7.9.6.1 321 #define PCIE_CAP_ID_VF_RESIZABLE_BAR 0x24 // 7.8.7.1 322 #define PCIE_CAP_ID_DATA_LINK 0x25 // 7.7.4.1 323 #define PCIE_CAP_ID_PHYSLAYER_16_GT 0x26 // 7.7.5.1 324 #define PCIE_CAP_ID_LANE_MARGINING_AT_RECEVER 0x27 // 7.7.10.1 325 #define PCIE_CAP_ID_HIERARCHY_ID 0x28 // 7.9.17.1 326 #define PCIE_CAP_ID_NPEM 0x29 // 7.9.19.1 327 #define PCIE_CAP_ID_PHYSLAYER_32_GT 0x2A // 7.7.6.1 328 #define PCIE_CAP_ID_ALTERNATE_PROTOCOL 0x2B // 7.9.20.1 329 #define PCIE_CAP_ID_SFI 0x2C // 7.9.22.1 330 #define PCIE_CAP_ID_SHADOW_FUNCTIONS 0x2D // 7.9.25.1 331 #define PCIE_CAP_ID_DATA_OBJECT_EXCHANGE 0x2E // 7.9.24.1 332 #define PCIE_CAP_ID_DEVICE_3 0x2F // 7.7.9.1 333 #define PCIE_CAP_ID_IDE 0x30 // 7.9.26.1 334 #define PCIE_CAP_ID_PHYSLAYER_64_GT 0x31 // 7.7.7.1 335 #define PCIE_CAP_ID_FLT_LOGGING 0x32 // 7.7.8.1 336 #define PCIE_CAP_ID_FLIT_PERF_MEASURMENT 0x33 // 7.8.12.1 337 #define PCIE_CAP_ID_FLIT_ERROR_INJECTION 0x34 // 7.8.13.1 338 339 // static sized structure sizes 340 #define PCIE_CAP_HEADER_SIZE 0x04 // 7.6.3 341 #define PCIE_CAP_NULL_SIZE 0x04 // 7.9.28 342 #define PCIE_CAP_ERROR_SIZE 0x48 // 7.8.4 343 #define PCIE_CAP_POWER_SIZE 0x10 // 7.8.1 344 #define PCIE_CAP_ROOT_COMPLEX_INTERNAL_LINK_CTRL_SIZE 0x0C // 7.9.9 345 #define PCIE_CAP_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT_SIZE 0x0C // 7.9.10 346 #define PCIE_CAP_SECONDARY_PCIE_SIZE 0x4C // 7.7.3.1 347 #define PCIE_CAP_DATA_LINK_SIZE 0x0C // 7.7.4 348 #define PCIE_CAP_PHYSLAYER_16_GT_SIZE 0x40 // 7.7.5 349 #define PCIE_CAP_PHYSLAYER_32_GT_SIZE 0x40 // 7.7.6 350 #define PCIE_CAP_PHYSLAYER_64_GT_SIZE 0x20 // 7.7.7 351 #define PCIE_CAP_FLT_LOGGING_SIZE 0x3C // 7.7.8 352 #define PCIE_CAP_DEVICE_3_SIZE 0x10 // 7.7.9 353 #define PCIE_CAP_LANE_MARGINING_AT_RECEVER_SIZE 0x88 // 7.7.10 354 #define PCIE_CAP_ACS_SIZE 0x10 // 7.7.11 355 #define PCIE_CAP_LATENCY_TOLERANCE_SIZE 0x08 // 7.8.2 356 #define PCIE_CAP_L1_PM_SUBSTATE_SIZE 0x14 // 7.8.3 357 #define PCIE_CAP_RESIZABLE_BAR_SIZE 0x34 // 7.8.6 358 #define PCIE_CAP_VF_RESIZABLE_BAR_SIZE 0x34 // 7.8.7 359 #define PCIE_CAP_ARI_SIZE 0x08 // 7.8.8 360 #define PCIE_CAP_PASID_SIZE 0x08 // 7.8.9 361 #define PCIE_CAP_FRS_QUEUING_SIZE 0x10 // 7.8.10 362 #define PCIE_CAP_FPB_SIZE 0x24 // 7.8.11 363 #define PCIE_CAP_FLIT_PERF_MEASURMENT_SIZE 0x24 // 7.8.12 364 #define PCIE_CAP_FLIT_ERROR_INJECTION_SIZE 0x24 // 7.8.13 365 #define PCIE_CAP_DEV_SERIAL_SIZE 0x0C // 7.9.3 366 #define PCIE_CAP_RCRB_SIZE 0x14 // 7.9.7 367 #define PCIE_CAP_MULTICAST_SIZE 0x30 // 7.9.11 368 #define PCIE_CAP_DYNAMIC_POWER_ALLOCATION_SIZE 0x30 // 7.9.12 369 #define PCIE_CAP_DPC_SIZE 0x5C // 7.9.14 370 #define PCIE_CAP_PTM_SIZE 0x0C // 7.9.15 371 #define PCIE_CAP_READINESS_TIME_REPORTING_SIZE 0x0C // 7.9.16 372 #define PCIE_CAP_HIERARCHY_ID_SIZE 0x0C // 7.9.17 373 #define PCIE_CAP_NPEM_SIZE 0x10 // 7.9.19 374 #define PCIE_CAP_ALTERNATE_PROTOCOL_SIZE 0x14 // 7.9.20 375 #define PCIE_CAP_SFI_SIZE 0x14 // 7.9.22 376 #define PCIE_CAP_DATA_OBJECT_EXCHANGE_SIZE 0x18 // 7.9.24 377 #define PCIE_CAP_SHADOW_FUNCTIONS_SIZE 0x1C // 7.9.25 378 #define PCIE_CAP_IDE_SIZE 0x34 // 7.9.26 379 380 // Virtual Channel Capability size related fields 381 #define PCIE_VC_REGISTER_1 0x04 // 7.9.1.2 382 #define PCIE_VC_REGISTER_1_EXTENDED_VC_COUNT 2:0 383 #define PCIE_VIRTUAL_CHANNELS_BASE_SIZE 0x18 // 7.9.1 384 #define PCIE_VIRTUAL_CHANNELS_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.1 385 386 // Multi Function Virtual Channel Capability size related fields 387 #define PCIE_MFVC_REGISTER_1 0x04 // 7.9.2.2 388 #define PCIE_MFVC_REGISTER_1_EXTENDED_VC_COUNT 2:0 389 #define PCIE_PCIE_CAP_ID_MFVC_BASE_SIZE 0x18 // 7.9.2 390 #define PCIE_PCIE_CAP_ID_MFVC_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.2 391 392 // Vendor Specific Capability size related fields 393 #define PCIE_VENDOR_SPECIFIC_HEADER_1 0x04 // 7.9.6.2 394 #define PCIE_VENDOR_SPECIFIC_HEADER_1_LENGTH 31:20 395 396 // Root Complex Capability size related fields 397 #define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER 0x04 // 7.9.8.2 398 #define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER_NUM_LINK_ENTRIES 15:8 399 #define PCIE_ROOT_COMPLEX_BASE_SIZE 0x0C // 7.9.8 400 #define PCIE_ROOT_COMPLEX_LINK_ENTRY_SIZE 0x10 // 7.9.8.3 401 402 // TPH capability size related fields 403 #define PCIE_TPH_REQUESTOR_REGISTER 0x04 // 7.9.13.2 404 #define PCIE_TPH_REQUESTOR_REGISTER_ST_TABLE_SIZE 26:16 405 #define PCIE_TPH_BASE_SIZE 0x0C // 7.9.13 406 #define PCIE_TPH_ST_ENTRY_SIZE 0x02 // 7.9.13.4 407 408 // Intel CPU family. 409 #define INTEL_CPU_FAMILY_06 0x06 410 #define INTEL_CPU_FAMILY_15 0x0f 411 #define INTEL_CPU_FAMILY_16 0x10 412 #define INTEL_CPU_FAMILY_21 0x15 413 414 // Intel CPU Model. Calculated as Model += (extModel << 4). 415 #define INTEL_CPU_MODEL_2A 0x2a 416 #define INTEL_CPU_MODEL_2D 0x2d 417 #define INTEL_CPU_MODEL_3A 0x3a 418 #define INTEL_CPU_MODEL_3F 0x3f 419 420 // Symbolic defines for each possible virtual channel 421 enum 422 { 423 RM_PCIE_VIRTUAL_CHANNEL_0 = 0, 424 RM_PCIE_VIRTUAL_CHANNEL_1, 425 RM_PCIE_VIRTUAL_CHANNEL_2, 426 RM_PCIE_VIRTUAL_CHANNEL_3, 427 RM_PCIE_VIRTUAL_CHANNEL_4, 428 RM_PCIE_VIRTUAL_CHANNEL_5, 429 RM_PCIE_VIRTUAL_CHANNEL_6, 430 RM_PCIE_VIRTUAL_CHANNEL_7, 431 RM_PCIE_VIRTUAL_CHANNEL_INVALID 432 }; 433 434 // Diagnostic collection actions. 435 #define RM_PCIE_ACTION_NOP 0 436 #define RM_PCIE_ACTION_COLLECT_CONFIG_SPACE 1 437 #define RM_PCIE_ACTION_COLLECT_PCI_CAP_STRUCT 2 438 #define RM_PCIE_ACTION_COLLECT_PCIE_CAP_STRUCT 3 439 #define RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS 4 440 #define RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS 5 441 #define RM_PCIE_ACTION_REPORT_PCI_CAPS_COUNT 6 442 #define RM_PCIE_ACTION_REPORT_PCIE_CAPS_COUNT 7 443 #define RM_PCIE_ACTION_EOS 0xff 444 445 446 // Diagnostic collection device Type ids 447 #define RM_PCIE_DEVICE_TYPE_NONE 0xff 448 #define RM_PCIE_DEVICE_TYPE_GPU 0 449 #define RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE 1 450 #define RM_PCIE_DEVICE_COUNT 2 451 452 // Diagnostic collection capability Type ids 453 #define RM_PCIE_DC_CAP_TYPE_NONE 0xff 454 #define RM_PCIE_DC_CAP_TYPE_PCI 0 455 #define RM_PCIE_DC_CAP_TYPE_PCIE 1 456 #define RM_PCIE_DC_CAP_TYPE_COUNT 2 457 458 typedef struct _def_bif_dc_diagnostic_collection_command 459 { 460 NvU8 action; 461 NvU8 deviceType; 462 NvU16 locator; 463 NvU16 length; 464 } CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY; 465 466 typedef struct _def_cl_pcie_dc_capability_map_entry 467 { 468 NvU16 id; 469 NvU16 blkOffset; 470 } CL_PCIE_DC_CAPABILITY_MAP_ENTRY; 471 typedef struct 472 { 473 NvU16 count; 474 CL_PCIE_DC_CAPABILITY_MAP_ENTRY entries[PCI_MAX_CAPS]; 475 } CL_PCIE_DC_CAPABILITY_MAP; 476 477 typedef struct OBJCL OBJCL; 478 typedef struct OBJGPU OBJGPU; 479 // root port setup functions 480 NV_STATUS Broadcom_HT2100_setupFunc(OBJGPU *, OBJCL*); 481 482 NV_STATUS Intel_RP25XX_setupFunc(OBJGPU *, OBJCL*); 483 NV_STATUS Intel_RP81XX_setupFunc(OBJGPU *, OBJCL*); 484 NV_STATUS Intel_RP3C0X_setupFunc(OBJGPU *, OBJCL*); 485 NV_STATUS Intel_RP2F0X_setupFunc(OBJGPU *, OBJCL*); 486 NV_STATUS Intel_RP0C0X_setupFunc(OBJGPU *, OBJCL*); 487 NV_STATUS Intel_Broadwell_setupFunc(OBJGPU *, OBJCL*); 488 NV_STATUS Intel_Skylake_setupFunc(OBJGPU *, OBJCL*); 489 NV_STATUS Intel_Skylake_U_Pch_setupFunc(OBJGPU *, OBJCL*); 490 NV_STATUS Intel_Skylake_H_Pch_setupFunc(OBJGPU *, OBJCL*); 491 NV_STATUS Intel_Kabylake_Y_setupFunc(OBJGPU *, OBJCL*); 492 493 NV_STATUS Nvidia_RPC19_setupFunc(OBJGPU *, OBJCL*); 494 NV_STATUS Nvidia_RPC51_setupFunc(OBJGPU *, OBJCL*); 495 NV_STATUS Nvidia_RPC55_setupFunc(OBJGPU *, OBJCL*); 496 497 NV_STATUS AMD_RP1480_setupFunc(OBJGPU *, OBJCL*); 498 NV_STATUS AMD_RP1630_setupFunc(OBJGPU *, OBJCL*); 499 NV_STATUS AMD_RP1483_setupFunc(OBJGPU *, OBJCL*); 500 501 // Determines if the GPU is in a multi-GPU board based on devid checks 502 NvBool gpuIsMultiGpuBoard(OBJGPU *); 503 504 #endif // NVPCIE_H 505