1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef RMLSFM_H 25 #define RMLSFM_H 26 27 /*****************************************************************************/ 28 /* This file is shared between ACR, SEC2 Binaries */ 29 /* Do not update this file without updating ACR/SEC2 */ 30 /*****************************************************************************/ 31 32 /*! 33 * @file rmlsfm.h 34 * @brief Top-level header-file that defines Light Secure Falcon Managment 35 SW shared interfaces. 36 */ 37 38 /*! 39 * READ/WRITE masks for WPR region 40 */ 41 #define LSF_WPR_REGION_RMASK (0xCU) // Readable only from level 2 and 3 client 42 #define LSF_WPR_REGION_WMASK (0xCU) // Writable only from level 2 and 3 client 43 #define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8) // Readable only from level 3 client 44 #define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8) // Writable only from level 3 client 45 #define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0) // Disallow read mis-match for all clients 46 #define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0) // Disallow write mis-match for all clients 47 48 /*! 49 * READ mask for WPR region on Tegra 50 * This is required until we update tegra binaries, Bug 200281517 51 * TODO: dgoyal - Remove this once tegra binaries are updated 52 */ 53 #define LSF_WPR_REGION_RMASK_FOR_TEGRA (0xFU) 54 55 /*! 56 * Expected REGION ID to be used for the unprotected FB region (region that 57 * does not have read or write protections) 58 */ 59 #define LSF_UNPROTECTED_REGION_ID (0x0U) 60 61 /*! 62 * Expected REGION ID to be used for the WPR region for the falcon microcode (includes data). 63 * ACR allots client requests to each region based on read/write masks and it is supposed 64 * to provide first priority to requests from LSFM. Providing first priority will naturally assign 65 * region ID 1 to LSFM and this define will provide a way for different parties to sanity check 66 * this fact. Also there are other falcons (FECS/video falcons) which depends on this define, so please 67 * be aware while modifying this. 68 */ 69 #define LSF_WPR_EXPECTED_REGION_ID (0x1U) 70 71 /*! 72 * Expected REGION ID to be used for the unused WPR region. 73 */ 74 #define LSF_WPR_UNUSED_REGION_ID (0x2U) 75 76 /*! 77 * Invalid LS falcon subWpr ID 78 */ 79 #define LSF_SUB_WPR_ID_INVALID (0xFFFFFFFFU) 80 81 /*! 82 * Expected REGION ID to be used for the VPR region. 83 */ 84 #define LSF_VPR_REGION_ID (0x3U) 85 86 /*! 87 * Expected REGION ID to be used for the CPR region with conf compute. 88 */ 89 #define LSF_CPR_REGION_ID (0x3U) 90 91 /*! 92 * Size of the separate bootloader data that could be present in WPR region. 93 */ 94 #define LSF_LS_BLDATA_EXPECTED_SIZE (0x100U) 95 96 /*! 97 * since we dont check signatures in GC6 exit, we need to hardcode the WPR offset 98 */ 99 #define LSF_WPR_EXPECTED_OFFSET (0x0U) 100 101 /*! 102 * CTXDMA to be used while loading code/data in target falcons 103 */ 104 #define LSF_BOOTSTRAP_CTX_DMA_FECS (0x0) 105 106 /*! 107 * Context DMA ID 6 is reserved for Video UCODE 108 */ 109 #define LSF_BOOTSTRAP_CTX_DMA_VIDEO (0x6) 110 #define LSF_BOOTSTRAP_CTX_DMA_BOOTSTRAP_OWNER (0x0) 111 #define LSF_BOOTSTRAP_CTX_DMA_FBFLCN (0x0) 112 113 /*! 114 * Falcon Id Defines 115 * Defines a common Light Secure Falcon identifier. 116 * Codesigning infra. assumes LSF_FALCON_ID_ prefix for units, 117 * Changes to the define needs to be reflected in path [1] 118 * For new Falcon Id adding, we need to append to the end; 119 * don't insert the new falcon Id in the middle. 120 * 121 * @note If a newly added Falcon has multiple instances sharing 122 * the same Falcon Id, the LSF_FALCON_USES_INSTANCE macro 123 * need to be updated. 124 */ 125 #define LSF_FALCON_ID_PMU (0U) 126 #define LSF_FALCON_ID_DPU (1U) 127 #define LSF_FALCON_ID_GSPLITE LSF_FALCON_ID_DPU 128 #define LSF_FALCON_ID_FECS (2U) 129 #define LSF_FALCON_ID_GPCCS (3U) 130 #define LSF_FALCON_ID_NVDEC (4U) 131 #define LSF_FALCON_ID_NVENC (5U) 132 #define LSF_FALCON_ID_NVENC0 (5U) 133 #define LSF_FALCON_ID_NVENC1 (6U) 134 #define LSF_FALCON_ID_SEC2 (7U) 135 #define LSF_FALCON_ID_NVENC2 (8U) 136 #define LSF_FALCON_ID_MINION (9U) 137 #define LSF_FALCON_ID_FBFALCON (10U) 138 #define LSF_FALCON_ID_XUSB (11U) 139 #define LSF_FALCON_ID_GSP_RISCV (12U) 140 #define LSF_FALCON_ID_PMU_RISCV (13U) 141 #define LSF_FALCON_ID_SOE (14U) 142 #define LSF_FALCON_ID_NVDEC1 (15U) 143 #define LSF_FALCON_ID_OFA (16U) 144 #define LSF_FALCON_ID_SEC2_RISCV (17U) 145 #define LSF_FALCON_ID_NVDEC_RISCV (18U) 146 #define LSF_FALCON_ID_NVDEC_RISCV_EB (19U) 147 #define LSF_FALCON_ID_NVJPG (20U) 148 #define LSF_FALCON_ID_FECS_RISCV (21U) 149 #define LSF_FALCON_ID_GPCCS_RISCV (22U) 150 #define LSF_FALCON_ID_NVJPG_RISCV_EB (23U) 151 #define LSF_FALCON_ID_OFA_RISCV_EB (24U) 152 #define LSF_FALCON_ID_NVENC_RISCV_EB (25U) 153 #define LSF_FALCON_ID_PMU_RISCV_EB (26U) 154 #define LSF_FALCON_ID_END (27U) 155 156 #define LSF_FALCON_ID_INVALID (0xFFFFFFFFU) 157 158 // 159 // TODO: Remove below Alias and add _EB Patching to macro LSF_FALCON_ID_FECS_RISCV, similarly for GPCCS, 160 // and similar cleanups in RM since RISCV based CTXSW engines are to be booted externally. 161 // Tracking in Bug 3808599 162 // 163 #define LSF_FALCON_ID_FECS_RISCV_EB (LSF_FALCON_ID_FECS_RISCV) 164 #define LSF_FALCON_ID_GPCCS_RISCV_EB (LSF_FALCON_ID_GPCCS_RISCV) 165 166 // 167 // ************************ NOTIFICATION ********************************* 168 // In case anyone needs to add new LSF falconId, please must calculate 169 // WPR header size per LSF_FALCON_ID_END. RM needs to call lsfmGetWprHeaderSizeMax_HAL 170 // to align with acrReadSubWprHeader_HAL in ACR. Otherwise, ACR can't get correct 171 // address to read sub wpr headers. 172 // We observer in case LSF_FALCON_ID_END > 32 will cause SEC2 IMEM tag missing error; 173 // but don't get the root cause yet. 174 // 175 #define LSF_FALCON_ID_END_15 (15U) 176 #define LSF_FALCON_ID_END_17 (17U) 177 #define LSF_FALCON_ID_END_18 (18U) 178 #define LSF_FALCON_ID_END_21 (21U) 179 180 #define LSF_FALCON_INSTANCE_DEFAULT_0 (0x0U) 181 #define LSF_FALCON_INSTANCE_COUNT_DEFAULT_1 (0x1U) 182 183 // Currently max supported instance is 8 for FECS/GPCCS SMC 184 #define LSF_FALCON_INSTANCE_FECS_GPCCS_MAX (0x8U) 185 #define LSF_FALCON_INSTANCE_INVALID (0xFFFFFFFFU) 186 #define LSF_FALCON_INDEX_MASK_DEFAULT_0 (0x0U) 187 188 /*! 189 * Checks if the LSF Falcon specified by falconId uses a falconInstance to uniquely identify itself. 190 * Some Falcons (eg: NVENC) use separate FalconId for each instance while some (eg: NVJPG) 191 * shares the same falconId across all instances of that engine. Those engines require a falconInstance 192 * to uniquely identify it. 193 * @note this macro should be updated as needed whenever LSF_FALCON_ID* defines are added. See Bug: 3833461 194 */ 195 #define LSF_FALCON_USES_INSTANCE(falconId) ((falconId == LSF_FALCON_ID_NVDEC_RISCV_EB) || \ 196 (falconId == LSF_FALCON_ID_NVJPG) || \ 197 (falconId == LSF_FALCON_ID_NVJPG_RISCV_EB) || \ 198 (falconId == LSF_FALCON_ID_NVENC_RISCV_EB) || \ 199 (falconId == LSF_FALCON_ID_OFA_RISCV_EB)) 200 201 /*! 202 * Size in entries of the ucode descriptor's dependency map. 203 * This used to be LSF_FALCON_ID_END, but since that had to grow and we did not want to break any 204 * existing binaries, they had to be split. 205 * 206 * Increasing this number should be done with care. 207 */ 208 #define LSF_FALCON_DEPMAP_SIZE (11) 209 210 /*! 211 * Falcon Binaries version defines 212 */ 213 #define LSF_FALCON_BIN_VERSION_INVALID (0xFFFFFFFFU) 214 215 216 /*! 217 * Light Secure Falcon Ucode Description Defines 218 * This stucture is prelim and may change as the ucode signing flow evolves. 219 */ 220 typedef struct 221 { 222 NvU8 prdKeys[2][16]; 223 NvU8 dbgKeys[2][16]; 224 NvU32 bPrdPresent; 225 NvU32 bDbgPresent; 226 NvU32 falconId; 227 NvU32 bSupportsVersioning; 228 NvU32 version; 229 NvU32 depMapCount; 230 NvU8 depMap[LSF_FALCON_DEPMAP_SIZE * 2 * 4]; 231 NvU8 kdf[16]; 232 } LSF_UCODE_DESC, *PLSF_UCODE_DESC; 233 234 /*! 235 * Light Secure WPR Header 236 * Defines state allowing Light Secure Falcon bootstrapping. 237 * 238 * falconId - LS falcon ID 239 * lsbOffset - Offset into WPR region holding LSB header 240 * bootstrapOwner - Bootstrap OWNER (either PMU or SEC2) 241 * bLazyBootstrap - Skip bootstrapping by ACR 242 * status - Bootstrapping status 243 */ 244 typedef struct 245 { 246 NvU32 falconId; 247 NvU32 lsbOffset; 248 NvU32 bootstrapOwner; 249 NvU32 bLazyBootstrap; 250 NvU32 binVersion; 251 NvU32 status; 252 } LSF_WPR_HEADER, *PLSF_WPR_HEADER; 253 254 /*! 255 * LSF shared SubWpr Header 256 * 257 * useCaseId - Shared SubWpr se case ID (updated by RM) 258 * startAddr - start address of subWpr (updated by RM) 259 * size4K - size of subWpr in 4K (updated by RM) 260 */ 261 typedef struct 262 { 263 NvU32 useCaseId; 264 NvU32 startAddr; 265 NvU32 size4K; 266 } LSF_SHARED_SUB_WPR_HEADER, *PLSF_SHARED_SUB_WPR_HEADER; 267 268 // Shared SubWpr use case IDs 269 typedef enum 270 { 271 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, 272 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2, 273 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_APM_RTS = 3 274 } LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_ENUM; 275 276 #define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_APM_RTS 277 #define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFFU) 278 279 #define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX 280 281 // 282 // Static sizes of shared subWPRs 283 // Minimum granularity supported is 4K 284 // 285 #define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100) // 1MB in 4K 286 #define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1) // 4K 287 #define LSF_SHARED_DATA_SUB_WPR_APM_RTS_SIZE_IN_4K (0x1) // 4K 288 289 /*! 290 * Bootstrap Owner Defines 291 */ 292 #define LSF_BOOTSTRAP_OWNER_PMU (LSF_FALCON_ID_PMU) 293 #define LSF_BOOTSTRAP_OWNER_SEC2 (LSF_FALCON_ID_SEC2) 294 #define LSF_BOOTSTRAP_OWNER_GSPLITE (LSF_FALCON_ID_GSPLITE) 295 #define LSF_BOOTSTRAP_OWNER_DEFAULT LSF_BOOTSTRAP_OWNER_PMU 296 297 /*! 298 * Image Status Defines 299 */ 300 #define LSF_IMAGE_STATUS_NONE (0U) 301 #define LSF_IMAGE_STATUS_COPY (1U) 302 #define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U) 303 #define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U) 304 #define LSF_IMAGE_STATUS_VALIDATION_DONE (4U) 305 #define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U) 306 #define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U) 307 #define LSF_IMAGE_STATUS_REVOCATION_CHECK_FAILED (7U) 308 309 /*! 310 * Light Secure Bootstrap Header 311 * Defines state allowing Light Secure Falcon bootstrapping. 312 * 313 * signature - Code/data signature details for this LS falcon 314 * ucodeOffset - Offset into WPR region where UCODE is located 315 * ucodeSize - Size of ucode 316 * dataSize - Size of ucode data 317 * blCodeSize - Size of bootloader that needs to be loaded by bootstrap owner 318 * blImemOffset - BL starting virtual address. Need for tagging. 319 * blDataOffset - Offset into WPR region holding the BL data 320 * blDataSize - Size of BL data 321 * appCodeOffset - Offset into WPR region where Application UCODE is located 322 * appCodeSize - Size of Application UCODE 323 * appDataOffset - Offset into WPR region where Application DATA is located 324 * appDataSize - Size of Application DATA 325 * blLoadCodeAt0 - Load BL at 0th IMEM offset 326 * bSetVACtx - Make sure to set the code/data loading CTX DMA to be virtual before exiting 327 * bDmaReqCtx - This falcon requires a ctx before issuing DMAs 328 * bForcePrivLoad- Use priv loading method instead of bootloader/DMAs 329 */ 330 331 #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0 0:0 332 #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 333 #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 334 #define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX 1:1 335 #define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX_FALSE 0 336 #define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX_TRUE 1 337 #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX 2:2 338 #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 339 #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 1 340 #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD 3:3 341 #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0 342 #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 1 343 typedef struct 344 { 345 LSF_UCODE_DESC signature; 346 NvU32 ucodeOffset; 347 NvU32 ucodeSize; 348 NvU32 dataSize; 349 NvU32 blCodeSize; 350 NvU32 blImemOffset; 351 NvU32 blDataOffset; 352 NvU32 blDataSize; 353 NvU32 appCodeOffset; 354 NvU32 appCodeSize; 355 NvU32 appDataOffset; 356 NvU32 appDataSize; 357 NvU32 flags; 358 /* 359 * TODO: Uncomment this once Sanket's changes 360 * of HALifying is done 361 NvU32 monitorCodeOffset; 362 NvU32 monitorDataOffset; 363 NvU32 manifestOffset; 364 */ 365 } LSF_LSB_HEADER, *PLSF_LSB_HEADER; 366 367 368 /*! 369 * Light Secure WPR Content Alignments 370 */ 371 #define LSF_WPR_HEADER_ALIGNMENT (256U) 372 #define LSF_SUB_WPR_HEADER_ALIGNMENT (256U) 373 #define LSF_LSB_HEADER_ALIGNMENT (256U) 374 #define LSF_BL_DATA_ALIGNMENT (256U) 375 #define LSF_BL_DATA_SIZE_ALIGNMENT (256U) 376 #define LSF_BL_CODE_SIZE_ALIGNMENT (256U) 377 #define LSF_DATA_SIZE_ALIGNMENT (256U) 378 #define LSF_CODE_SIZE_ALIGNMENT (256U) 379 380 // MMU excepts subWpr sizes in units of 4K 381 #define SUB_WPR_SIZE_ALIGNMENT (4096U) 382 383 /*! 384 * Maximum WPR Header size 385 */ 386 #define LSF_WPR_HEADERS_TOTAL_SIZE_MAX (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END), LSF_WPR_HEADER_ALIGNMENT)) 387 #define LSF_LSB_HEADER_TOTAL_SIZE_MAX (NV_ALIGN_UP(sizeof(LSF_LSB_HEADER), LSF_LSB_HEADER_ALIGNMENT)) 388 389 // 390 // PMU OBJACR_ALIGNED_256 size will vary with LSF_FALCON_ID_END. 391 // PMU could run out of DMEM in case we increase LSF_FALCON_ID_END more and more. 392 // The PMU supports the ACR task on GM20X_thru_VOLTA profiles only. 393 // In order to prevent LSF_FALCON_ID_END changes to affect older / shipped PMU ucodes (increase of DMEM footprint) 394 // adding PMU specific ***_END define capturing value covering all PMU profiles that this with the ACR task. 395 // 396 #define LSF_FALCON_ID_END_PMU (LSF_FALCON_ID_FBFALCON + 1) 397 #define LSF_WPR_HEADERS_TOTAL_SIZE_MAX_PMU (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END_PMU), LSF_WPR_HEADER_ALIGNMENT)) 398 399 // 400 // In order to prevent LSF_FALCON_ID_END changes to affect older / shipped SEC2/ACR ucodes (increase of DMEM footprint) 401 // adding SEC2/ACR specific ***_END define covering all supported falcons in pre-hopper SEC2-RTOS/ACR ucode. 402 // 403 #define LSF_FALCON_ID_END_ACR_ON_SEC2 (LSF_FALCON_ID_NVJPG + 1) 404 #define LSF_WPR_HEADERS_TOTAL_SIZE_MAX_ACR_ON_SEC2 (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END_ACR_ON_SEC2), LSF_WPR_HEADER_ALIGNMENT)) 405 406 // Maximum SUB WPR header size 407 #define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (NV_ALIGN_UP((sizeof(LSF_SHARED_SUB_WPR_HEADER) * LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), LSF_SUB_WPR_HEADER_ALIGNMENT)) 408 409 /*! 410 * For the ucode surface alignment, We align to RM_PAGE_SIZE because of 411 * busMapRmAperture issues, not because of Falcon ucode alignment requirements 412 * which currently are that it be at least 256. 413 */ 414 #define LSF_UCODE_DATA_ALIGNMENT RM_PAGE_SIZE 415 416 /*! 417 * ACR Descriptors used by ACR UC 418 */ 419 420 /*! 421 * Supporting maximum of 2 regions. 422 * This is needed to pre-allocate space in DMEM 423 */ 424 #define RM_FLCN_ACR_MAX_REGIONS (2) 425 #define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) 426 427 /*! 428 * startAddress - Starting address of region 429 * endAddress - Ending address of region 430 * regionID - Region ID 431 * readMask - Read Mask 432 * writeMask - WriteMask 433 * clientMask - Bit map of all clients currently using this region 434 * shadowMemStartAddress- FB location from where contents need to be copied to startAddress 435 */ 436 typedef struct _def_acr_dmem_region_prop 437 { 438 NvU32 startAddress; 439 NvU32 endAddress; 440 NvU32 regionID; 441 NvU32 readMask; 442 NvU32 writeMask; 443 NvU32 clientMask; 444 NvU32 shadowMemStartAddress; 445 } RM_FLCN_ACR_REGION_PROP, *PRM_FLCN_ACR_REGION_PROP; 446 447 448 /*! 449 * noOfRegions - Number of regions used by RM. 450 * regionProps - Region properties 451 */ 452 typedef struct _def_acr_regions 453 { 454 NvU32 noOfRegions; 455 RM_FLCN_ACR_REGION_PROP regionProps[RM_FLCN_ACR_MAX_REGIONS]; 456 } RM_FLCN_ACR_REGIONS, *PRM_FLCN_ACR_REGIONS; 457 458 /*! 459 * bVprEnabled : When set, ACR_LOCKDOWN phase programs VPR range. Needs to be 460 : NvU32 because of alignment 461 * vprStartAddress : Start address of VPR region. SEC2 binary updates this value 462 * vprEndAddress : End address of VPR region. SEC2 binary updates this value 463 * hdcpPolicies : VPR display policies. SEC2 binary updates this value 464 */ 465 typedef struct _def_acr_vpr_dmem_desc 466 { 467 NvU32 bVprEnabled; 468 NvU32 vprStartAddress; 469 NvU32 vprEndAddress; 470 NvU32 hdcpPolicies; 471 } ACR_BSI_VPR_DESC, *PACR_BSI_VPR_DESC; 472 473 /*! 474 * reservedDmem - When the bootstrap owner has done bootstrapping other falcons, 475 * and need to switch into LS mode, it needs to have its own actual 476 * DMEM image copied into DMEM as part of LS setup. If ACR desc is at 477 * location 0, it will definitely get overwritten causing data corruption. 478 * Hence we are reserving 0x200 bytes to give room for any loading data. 479 * NOTE: This has to be the first member always 480 * signature - Signature of ACR ucode. 481 * wprRegionID - Region ID holding the WPR header and its details 482 * wprOffset - Offset from the WPR region holding the wpr header 483 * regions - Region descriptors 484 * ucodeBlobBase- Used for Tegra, stores non-WPR start address where kernel stores ucode blob 485 * ucodeBlobSize- Used for Tegra, stores the size of the ucode blob 486 */ 487 typedef struct _def_acr_dmem_desc 488 { 489 NvU32 signatures[4]; 490 NvU32 wprRegionID; 491 NvU32 wprOffset; 492 NvU32 mmuMemoryRange; 493 RM_FLCN_ACR_REGIONS regions; 494 NvU32 ucodeBlobSize; 495 // uCodeBlobBase is moved after ucodeBlobSize to inherently align to qword (8 bytes) 496 NvU64 NV_DECLARE_ALIGNED(ucodeBlobBase, 8); 497 498 /*! 499 * Do not change the offset of this descriptor as it shared between 500 * ACR_REGION_LOCKDOWN HS binary and SEC2. Any change in this structure 501 * need recompilation of SEC2 and ACR_LOCKDOWN HS binary 502 */ 503 ACR_BSI_VPR_DESC vprDesc; 504 } RM_FLCN_ACR_DESC, *PRM_FLCN_ACR_DESC; 505 506 /*! 507 * Hub keys/nonce Structure in BSI 508 */ 509 #define MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE 4 510 511 typedef struct _def_acr_hub_scratch_data 512 { 513 NvU32 key[MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE]; 514 NvU32 nonce[MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE]; 515 } ACR_BSI_HUB_DESC, *PACR_BSI_HUB_DESC; 516 517 #define MAX_HUB_ENCRYPTION_REGION_COUNT 3 518 typedef struct _def_acr_hub_scratch_array 519 { 520 ACR_BSI_HUB_DESC entries[MAX_HUB_ENCRYPTION_REGION_COUNT]; 521 } ACR_BSI_HUB_DESC_ARRAY, *PACR_BSI_HUB_DESC_ARRAY; 522 523 typedef struct _def_acr_reserved_dmem 524 { 525 NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first.. 526 } ACR_RESERVED_DMEM, *PACR_RESERVED_DMEM; 527 528 typedef struct _def_booter_reserved_dmem 529 { 530 NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first.. 531 } BOOTER_RESERVED_DMEM; 532 533 #define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF 0:0 534 #define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0 535 #define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1 536 537 // Macro defines to be consumed by RM to get GH100 GSP Inst_in_sys FMC boot status. 538 #define GSP_INST_IN_SYS_COMPLETION_STATUS_OK 0x55 539 #define GSP_INST_IN_SYS_COMPLETION_STATUS_ERROR 0xAA 540 #define GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS 0x00 541 542 /*! 543 * Size of ACR phase in dword 544 */ 545 #define ACR_PHASE_SIZE_DWORD sizeof(RM_FLCN_ACR_DESC)/sizeof(NvU32) 546 547 /*! 548 * Falcon Mode Tokens 549 * This is the value logged to a mailbox register to indicate that the 550 * falcon isn't booted in secure mode. 551 */ 552 #define LSF_FALCON_MODE_TOKEN_FLCN_INSECURE (0xDEADDEADU) 553 554 555 // LS encryption context, to store data to decrypt LS images. 556 #define LS_ENCRYPTION_AES128_CBC_IV_SIZE_BYTE (16) 557 558 typedef struct 559 { 560 NvU8 bLsEncrypted; 561 NvU8 rsvd[3]; 562 NvU8 lsEncIV[LS_ENCRYPTION_AES128_CBC_IV_SIZE_BYTE]; 563 } LSF_ENCRYPTION_CONTEXT, *PLSF_ENCRYPTION_CONTEXT; 564 565 #endif // RMLSFM_H 566 567