1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 // 25 // This file holds Unix-specific NVIDIA driver options 26 // 27 28 #ifndef _RM_REG_H_ 29 #define _RM_REG_H_ 30 31 #include "nvtypes.h" 32 #include "nv-firmware-registry.h" 33 34 /* 35 * use NV_REG_STRING to stringify a registry key when using that registry key 36 */ 37 38 #define __NV_REG_STRING(regkey) #regkey 39 #define NV_REG_STRING(regkey) __NV_REG_STRING(regkey) 40 41 /* 42 * use NV_DEFINE_REG_ENTRY and NV_DEFINE_PARAMS_TABLE_ENTRY to simplify definition 43 * of registry keys in the kernel module source code. 44 */ 45 46 #define __NV_REG_VAR(regkey) NVreg_##regkey 47 48 #if defined(NV_MODULE_PARAMETER) 49 #define NV_DEFINE_REG_ENTRY(regkey, default_value) \ 50 static NvU32 __NV_REG_VAR(regkey) = (default_value); \ 51 NV_MODULE_PARAMETER(__NV_REG_VAR(regkey)) 52 #define NV_DEFINE_REG_ENTRY_GLOBAL(regkey, default_value) \ 53 NvU32 __NV_REG_VAR(regkey) = (default_value); \ 54 NV_MODULE_PARAMETER(__NV_REG_VAR(regkey)) 55 #else 56 #define NV_DEFINE_REG_ENTRY(regkey, default_value) \ 57 static NvU32 __NV_REG_VAR(regkey) = (default_value) 58 #define NV_DEFINE_REG_ENTRY_GLOBAL(regkey, default_value) \ 59 NvU32 __NV_REG_VAR(regkey) = (default_value) 60 #endif 61 62 #if defined(NV_MODULE_STRING_PARAMETER) 63 #define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \ 64 char *__NV_REG_VAR(regkey) = (default_value); \ 65 NV_MODULE_STRING_PARAMETER(__NV_REG_VAR(regkey)) 66 #else 67 #define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \ 68 char *__NV_REG_VAR(regkey) = (default_value) 69 #endif 70 71 #define NV_DEFINE_PARAMS_TABLE_ENTRY(regkey) \ 72 { NV_REG_STRING(regkey), &__NV_REG_VAR(regkey) } 73 74 /* 75 * Like NV_DEFINE_PARMS_TABLE_ENTRY, but allows a mismatch between the name of 76 * the regkey and the name of the module parameter. When using this macro, the 77 * name of the parameter is passed to the extra "parameter" argument, and it is 78 * this name that must be used in the NV_DEFINE_REG_ENTRY() macro. 79 */ 80 81 #define NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(regkey, parameter) \ 82 { NV_REG_STRING(regkey), &__NV_REG_VAR(parameter)} 83 84 /* 85 *----------------- registry key definitions-------------------------- 86 */ 87 88 /* 89 * Option: ModifyDeviceFiles 90 * 91 * Description: 92 * 93 * When this option is enabled, the NVIDIA driver will verify the validity 94 * of the NVIDIA device files in /dev and attempt to dynamically modify 95 * and/or (re-)create them, if necessary. If you don't wish for the NVIDIA 96 * driver to touch the device files, you can use this registry key. 97 * 98 * This module parameter is only honored by the NVIDIA GPU driver and NVIDIA 99 * capability driver. Furthermore, the NVIDIA capability driver provides 100 * modifiable /proc file entry (DeviceFileModify=0/1) to alter the behavior of 101 * this module parameter per device file. 102 * 103 * Possible Values: 104 * 0 = disable dynamic device file management 105 * 1 = enable dynamic device file management (default) 106 */ 107 108 #define __NV_MODIFY_DEVICE_FILES ModifyDeviceFiles 109 #define NV_REG_MODIFY_DEVICE_FILES NV_REG_STRING(__NV_MODIFY_DEVICE_FILES) 110 111 /* 112 * Option: DeviceFileUID 113 * 114 * Description: 115 * 116 * This registry key specifies the UID assigned to the NVIDIA device files 117 * created and/or modified by the NVIDIA driver when dynamic device file 118 * management is enabled. 119 * 120 * This module parameter is only honored by the NVIDIA GPU driver. 121 * 122 * The default UID is 0 ('root'). 123 */ 124 125 #define __NV_DEVICE_FILE_UID DeviceFileUID 126 #define NV_REG_DEVICE_FILE_UID NV_REG_STRING(__NV_DEVICE_FILE_UID) 127 128 /* 129 * Option: DeviceFileGID 130 * 131 * Description: 132 * 133 * This registry key specifies the GID assigned to the NVIDIA device files 134 * created and/or modified by the NVIDIA driver when dynamic device file 135 * management is enabled. 136 * 137 * This module parameter is only honored by the NVIDIA GPU driver. 138 * 139 * The default GID is 0 ('root'). 140 */ 141 142 #define __NV_DEVICE_FILE_GID DeviceFileGID 143 #define NV_REG_DEVICE_FILE_GID NV_REG_STRING(__NV_DEVICE_FILE_GID) 144 145 /* 146 * Option: DeviceFileMode 147 * 148 * Description: 149 * 150 * This registry key specifies the device file mode assigned to the NVIDIA 151 * device files created and/or modified by the NVIDIA driver when dynamic 152 * device file management is enabled. 153 * 154 * This module parameter is only honored by the NVIDIA GPU driver. 155 * 156 * The default mode is 0666 (octal, rw-rw-rw-). 157 */ 158 159 #define __NV_DEVICE_FILE_MODE DeviceFileMode 160 #define NV_REG_DEVICE_FILE_MODE NV_REG_STRING(__NV_DEVICE_FILE_MODE) 161 162 /* 163 * Option: ResmanDebugLevel 164 * 165 * Default value: ~0 166 */ 167 168 #define __NV_RESMAN_DEBUG_LEVEL ResmanDebugLevel 169 #define NV_REG_RESMAN_DEBUG_LEVEL NV_REG_STRING(__NV_RESMAN_DEBUG_LEVEL) 170 171 /* 172 * Option: RmLogonRC 173 * 174 * Default value: 1 175 */ 176 177 #define __NV_RM_LOGON_RC RmLogonRC 178 #define NV_REG_RM_LOGON_RC NV_REG_STRING(__NV_RM_LOGON_RC) 179 180 /* 181 * Option: InitializeSystemMemoryAllocations 182 * 183 * Description: 184 * 185 * The NVIDIA Linux driver normally clears system memory it allocates 186 * for use with GPUs or within the driver stack. This is to ensure 187 * that potentially sensitive data is not rendered accessible by 188 * arbitrary user applications. 189 * 190 * Owners of single-user systems or similar trusted configurations may 191 * choose to disable the aforementioned clears using this option and 192 * potentially improve performance. 193 * 194 * Possible values: 195 * 196 * 1 = zero out system memory allocations (default) 197 * 0 = do not perform memory clears 198 */ 199 200 #define __NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS \ 201 InitializeSystemMemoryAllocations 202 #define NV_REG_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS \ 203 NV_REG_STRING(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS) 204 205 /* 206 * Option: RegistryDwords 207 * 208 * Description: 209 * 210 * This option accepts a semicolon-separated list of key=value pairs. Each 211 * key name is checked against the table of static options; if a match is 212 * found, the static option value is overridden, but invalid options remain 213 * invalid. Pairs that do not match an entry in the static option table 214 * are passed on to the RM directly. 215 * 216 * Format: 217 * 218 * NVreg_RegistryDwords="<key=value>;<key=value>;..." 219 */ 220 221 #define __NV_REGISTRY_DWORDS RegistryDwords 222 #define NV_REG_REGISTRY_DWORDS NV_REG_STRING(__NV_REGISTRY_DWORDS) 223 224 /* 225 * Option: RegistryDwordsPerDevice 226 * 227 * Description: 228 * 229 * This option allows to specify registry keys per GPU device. It helps to 230 * control registry at GPU level of granularity. It accepts a semicolon 231 * separated list of key=value pairs. The first key value pair MUST be 232 * "pci=DDDD:BB:DD.F;" where DDDD is Domain, BB is Bus Id, DD is device slot 233 * number and F is the Function. This PCI BDF is used to identify which GPU to 234 * assign the registry keys that follows next. 235 * If a GPU corresponding to the value specified in "pci=DDDD:BB:DD.F;" is NOT 236 * found, then all the registry keys that follows are skipped, until we find next 237 * valid pci identified "pci=DDDD:BB:DD.F;". Following are the valid formats for 238 * the value of the "pci" string: 239 * 1) bus:slot : Domain and function defaults to 0. 240 * 2) domain:bus:slot : Function defaults to 0. 241 * 3) domain:bus:slot.func : Complete PCI dev id string. 242 * 243 * For each of the registry keys that follows, key name is checked against the 244 * table of static options; if a match is found, the static option value is 245 * overridden, but invalid options remain invalid. Pairs that do not match an 246 * entry in the static option table are passed on to the RM directly. 247 * 248 * Format: 249 * 250 * NVreg_RegistryDwordsPerDevice="pci=DDDD:BB:DD.F;<key=value>;<key=value>;..; \ 251 * pci=DDDD:BB:DD.F;<key=value>;..;" 252 */ 253 254 #define __NV_REGISTRY_DWORDS_PER_DEVICE RegistryDwordsPerDevice 255 #define NV_REG_REGISTRY_DWORDS_PER_DEVICE NV_REG_STRING(__NV_REGISTRY_DWORDS_PER_DEVICE) 256 257 #define __NV_RM_MSG RmMsg 258 #define NV_RM_MSG NV_REG_STRING(__NV_RM_MSG) 259 260 /* 261 * Option: UsePageAttributeTable 262 * 263 * Description: 264 * 265 * Enable/disable use of the page attribute table (PAT) available in 266 * modern x86/x86-64 processors to set the effective memory type of memory 267 * mappings to write-combining (WC). 268 * 269 * If enabled, an x86 processor with PAT support is present and the host 270 * system's Linux kernel did not configure one of the PAT entries to 271 * indicate the WC memory type, the driver will change the second entry in 272 * the PAT from its default (write-through (WT)) to WC at module load 273 * time. If the kernel did update one of the PAT entries, the driver will 274 * not modify the PAT. 275 * 276 * In both cases, the driver will honor attempts to map memory with the WC 277 * memory type by selecting the appropriate PAT entry using the correct 278 * set of PTE flags. 279 * 280 * Possible values: 281 * 282 * ~0 = use the NVIDIA driver's default logic (default) 283 * 1 = enable use of the PAT for WC mappings. 284 * 0 = disable use of the PAT for WC mappings. 285 */ 286 287 #define __NV_USE_PAGE_ATTRIBUTE_TABLE UsePageAttributeTable 288 #define NV_USE_PAGE_ATTRIBUTE_TABLE NV_REG_STRING(__NV_USE_PAGE_ATTRIBUTE_TABLE) 289 290 /* 291 * Option: EnableMSI 292 * 293 * Description: 294 * 295 * When this option is enabled and the host kernel supports the MSI feature, 296 * the NVIDIA driver will enable the PCI-E MSI capability of GPUs with the 297 * support for this feature instead of using PCI-E wired interrupt. 298 * 299 * Possible Values: 300 * 301 * 0 = disable MSI interrupt 302 * 1 = enable MSI interrupt (default) 303 * 304 */ 305 306 #define __NV_ENABLE_MSI EnableMSI 307 #define NV_REG_ENABLE_MSI NV_REG_STRING(__NV_ENABLE_MSI) 308 309 /* 310 * Option: EnablePCIeGen3 311 * 312 * Description: 313 * 314 * Due to interoperability problems seen with Kepler PCIe Gen3 capable GPUs 315 * when configured on SandyBridge E desktop platforms, NVIDIA feels that 316 * delivering a reliable, high-quality experience is not currently possible in 317 * PCIe Gen3 mode on all PCIe Gen3 platforms. Therefore, Quadro, Tesla and 318 * NVS Kepler products operate in PCIe Gen2 mode by default. You may use this 319 * option to enable PCIe Gen3 support. 320 * 321 * This is completely unsupported! 322 * 323 * Possible Values: 324 * 325 * 0: disable PCIe Gen3 support (default) 326 * 1: enable PCIe Gen3 support 327 */ 328 329 #define __NV_ENABLE_PCIE_GEN3 EnablePCIeGen3 330 #define NV_REG_ENABLE_PCIE_GEN3 NV_REG_STRING(__NV_ENABLE_PCIE_GEN3) 331 332 /* 333 * Option: MemoryPoolSize 334 * 335 * Description: 336 * 337 * When set to a non-zero value, this option specifies the size of the 338 * memory pool, given as a multiple of 1 GB, created on VMware ESXi to 339 * satisfy any system memory allocations requested by the NVIDIA kernel 340 * module. 341 */ 342 343 #define __NV_MEMORY_POOL_SIZE MemoryPoolSize 344 #define NV_REG_MEMORY_POOL_SIZE NV_REG_STRING(__NV_MEMORY_POOL_SIZE) 345 346 /* 347 * Option: KMallocHeapMaxSize 348 * 349 * Description: 350 * 351 * When set to a non-zero value, this option specifies the maximum size of the 352 * heap memory space reserved for kmalloc operations. Given as a 353 * multiple of 1 MB created on VMware ESXi to satisfy any system memory 354 * allocations requested by the NVIDIA kernel module. 355 */ 356 357 #define __NV_KMALLOC_HEAP_MAX_SIZE KMallocHeapMaxSize 358 #define NV_KMALLOC_HEAP_MAX_SIZE NV_REG_STRING(__NV_KMALLOC_HEAP_MAX_SIZE) 359 360 /* 361 * Option: VMallocHeapMaxSize 362 * 363 * Description: 364 * 365 * When set to a non-zero value, this option specifies the maximum size of the 366 * heap memory space reserved for vmalloc operations. Given as a 367 * multiple of 1 MB created on VMware ESXi to satisfy any system memory 368 * allocations requested by the NVIDIA kernel module. 369 */ 370 371 #define __NV_VMALLOC_HEAP_MAX_SIZE VMallocHeapMaxSize 372 #define NV_VMALLOC_HEAP_MAX_SIZE NV_REG_STRING(__NV_VMALLOC_HEAP_MAX_SIZE) 373 374 /* 375 * Option: IgnoreMMIOCheck 376 * 377 * Description: 378 * 379 * When this option is enabled, the NVIDIA kernel module will ignore 380 * MMIO limit check during device probe on VMWare ESXi kernel. This is 381 * typically necessary when VMware ESXi MMIO limit differs between any 382 * base version and its updates. Customer using updates can set regkey 383 * to avoid probe failure. 384 */ 385 386 #define __NV_IGNORE_MMIO_CHECK IgnoreMMIOCheck 387 #define NV_REG_IGNORE_MMIO_CHECK NV_REG_STRING(__NV_IGNORE_MMIO_CHECK) 388 389 /* 390 * Option: TCEBypassMode 391 * 392 * Description: 393 * 394 * When this option is enabled, the NVIDIA kernel module will attempt to setup 395 * all GPUs in "TCE bypass mode", in which DMA mappings of system memory bypass 396 * the IOMMU/TCE remapping hardware on IBM POWER systems. This is typically 397 * necessary for CUDA applications in which large system memory mappings may 398 * exceed the default TCE remapping capacity when operated in non-bypass mode. 399 * 400 * This option has no effect on non-POWER platforms. 401 * 402 * Possible Values: 403 * 404 * 0: system default TCE mode on all GPUs 405 * 1: enable TCE bypass mode on all GPUs 406 * 2: disable TCE bypass mode on all GPUs 407 */ 408 #define __NV_TCE_BYPASS_MODE TCEBypassMode 409 #define NV_REG_TCE_BYPASS_MODE NV_REG_STRING(__NV_TCE_BYPASS_MODE) 410 411 #define NV_TCE_BYPASS_MODE_DEFAULT 0 412 #define NV_TCE_BYPASS_MODE_ENABLE 1 413 #define NV_TCE_BYPASS_MODE_DISABLE 2 414 415 /* 416 * Option: pci 417 * 418 * Description: 419 * 420 * On Unix platforms, per GPU based registry key can be specified as: 421 * NVreg_RegistryDwordsPerDevice="pci=DDDD:BB:DD.F,<per-gpu registry keys>". 422 * where DDDD:BB:DD.F refers to Domain:Bus:Device.Function. 423 * We need this key "pci" to identify what follows next is a PCI BDF identifier, 424 * for which the registry keys are to be applied. 425 * 426 * This define is not used on non-UNIX platforms. 427 * 428 * Possible Formats for value: 429 * 430 * 1) bus:slot : Domain and function defaults to 0. 431 * 2) domain:bus:slot : Function defaults to 0. 432 * 3) domain:bus:slot.func : Complete PCI BDF identifier string. 433 */ 434 #define __NV_PCI_DEVICE_BDF pci 435 #define NV_REG_PCI_DEVICE_BDF NV_REG_STRING(__NV_PCI_DEVICE_BDF) 436 437 /* 438 * Option: EnableStreamMemOPs 439 * 440 * Description: 441 * 442 * When this option is enabled, the CUDA driver will enable support for 443 * CUDA Stream Memory Operations in user-mode applications, which are so 444 * far required to be disabled by default due to limited support in 445 * devtools. 446 * 447 * Note: this is treated as a hint. MemOPs may still be left disabled by CUDA 448 * driver for other reasons. 449 * 450 * Possible Values: 451 * 452 * 0 = disable feature (default) 453 * 1 = enable feature 454 */ 455 #define __NV_ENABLE_STREAM_MEMOPS EnableStreamMemOPs 456 #define NV_REG_ENABLE_STREAM_MEMOPS NV_REG_STRING(__NV_ENABLE_STREAM_MEMOPS) 457 458 /* 459 * Option: EnableUserNUMAManagement 460 * 461 * Description: 462 * 463 * When this option is enabled, the NVIDIA kernel module will require the 464 * user-mode NVIDIA Persistence daemon to manage the onlining and offlining 465 * of its NUMA device memory. 466 * 467 * This option has no effect on platforms that do not support onlining 468 * device memory to a NUMA node (this feature is only supported on certain 469 * POWER9 systems). 470 * 471 * Possible Values: 472 * 473 * 0: disable user-mode NUMA management 474 * 1: enable user-mode NUMA management (default) 475 */ 476 #define __NV_ENABLE_USER_NUMA_MANAGEMENT EnableUserNUMAManagement 477 #define NV_REG_ENABLE_USER_NUMA_MANAGEMENT NV_REG_STRING(__NV_ENABLE_USER_NUMA_MANAGEMENT) 478 479 /* 480 * Option: GpuBlacklist 481 * 482 * Description: 483 * 484 * This option accepts a list of blacklisted GPUs, separated by commas, that 485 * cannot be attached or used. Each blacklisted GPU is identified by a UUID in 486 * the ASCII format with leading "GPU-". An exact match is required; no partial 487 * UUIDs. This regkey is deprecated and will be removed in the future. Use 488 * NV_REG_EXCLUDED_GPUS instead. 489 */ 490 #define __NV_GPU_BLACKLIST GpuBlacklist 491 #define NV_REG_GPU_BLACKLIST NV_REG_STRING(__NV_GPU_BLACKLIST) 492 493 /* 494 * Option: ExcludedGpus 495 * 496 * Description: 497 * 498 * This option accepts a list of excluded GPUs, separated by commas, that 499 * cannot be attached or used. Each excluded GPU is identified by a UUID in 500 * the ASCII format with leading "GPU-". An exact match is required; no partial 501 * UUIDs. 502 */ 503 #define __NV_EXCLUDED_GPUS ExcludedGpus 504 #define NV_REG_EXCLUDED_GPUS NV_REG_STRING(__NV_EXCLUDED_GPUS) 505 506 /* 507 * Option: NvLinkDisable 508 * 509 * Description: 510 * 511 * When this option is enabled, the NVIDIA kernel module will not attempt to 512 * initialize or train NVLink connections for any GPUs. System reboot is required 513 * for changes to take affect. 514 * 515 * This option has no effect if no GPUs support NVLink. 516 * 517 * Possible Values: 518 * 519 * 0: Do not disable NVLink (default) 520 * 1: Disable NVLink 521 */ 522 #define __NV_NVLINK_DISABLE NvLinkDisable 523 #define NV_REG_NVLINK_DISABLE NV_REG_STRING(__NV_NVLINK_DISABLE) 524 525 /* 526 * Option: RestrictProfilingToAdminUsers 527 * 528 * Description: 529 * 530 * When this option is enabled, the NVIDIA kernel module will prevent users 531 * without administrative access (i.e., the CAP_SYS_ADMIN capability) from 532 * using GPU performance counters. 533 * 534 * Possible Values: 535 * 536 * 0: Do not restrict GPU counters (default) 537 * 1: Restrict GPU counters to system administrators only 538 */ 539 540 #define __NV_RM_PROFILING_ADMIN_ONLY RmProfilingAdminOnly 541 #define __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER RestrictProfilingToAdminUsers 542 #define NV_REG_RM_PROFILING_ADMIN_ONLY NV_REG_STRING(__NV_RM_PROFILING_ADMIN_ONLY) 543 544 /* 545 * Option: TemporaryFilePath 546 * 547 * Description: 548 * 549 * When specified, this option changes the location in which the 550 * NVIDIA kernel module will create unnamed temporary files (e.g. to 551 * save the contents of video memory in). The indicated file must 552 * be a directory. By default, temporary files are created in /tmp. 553 */ 554 #define __NV_TEMPORARY_FILE_PATH TemporaryFilePath 555 #define NV_REG_TEMPORARY_FILE_PATH NV_REG_STRING(__NV_TEMPORARY_FILE_PATH) 556 557 /* 558 * Option: PreserveVideoMemoryAllocations 559 * 560 * If enabled, this option prompts the NVIDIA kernel module to save and 561 * restore all video memory allocations across system power management 562 * cycles, i.e. suspend/resume and hibernate/restore. Otherwise, 563 * only select allocations are preserved. 564 * 565 * Possible Values: 566 * 567 * 0: Preserve only select video memory allocations (default) 568 * 1: Preserve all video memory allocations 569 */ 570 #define __NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS PreserveVideoMemoryAllocations 571 #define NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS \ 572 NV_REG_STRING(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS) 573 574 /* 575 * Option: EnableS0ixPowerManagement 576 * 577 * When this option is enabled, the NVIDIA driver will use S0ix-based 578 * power management for system suspend/resume, if both the platform and 579 * the GPU support S0ix. 580 * 581 * During system suspend, if S0ix is enabled and 582 * video memory usage is above the threshold configured by 583 * 'S0ixPowerManagementVideoMemoryThreshold', video memory will be kept 584 * in self-refresh mode while the rest of the GPU is powered down. 585 * 586 * Otherwise, the driver will copy video memory contents to system memory 587 * and power off the video memory along with the GPU. 588 * 589 * Possible Values: 590 * 591 * 0: Disable S0ix based power management (default) 592 * 1: Enable S0ix based power management 593 */ 594 595 #define __NV_ENABLE_S0IX_POWER_MANAGEMENT EnableS0ixPowerManagement 596 #define NV_REG_ENABLE_S0IX_POWER_MANAGEMENT \ 597 NV_REG_STRING(__NV_ENABLE_S0IX_POWER_MANAGEMENT) 598 599 /* 600 * Option: S0ixPowerManagementVideoMemoryThreshold 601 * 602 * This option controls the threshold that the NVIDIA driver will use during 603 * S0ix-based system power management. 604 * 605 * When S0ix is enabled and the system is suspended, the driver will 606 * compare the amount of video memory in use with this threshold, 607 * to decide whether to keep video memory in self-refresh or copy video 608 * memory content to system memory. 609 * 610 * See the 'EnableS0ixPowerManagement' option. 611 * 612 * Values are expressed in Megabytes (1048576 bytes). 613 * 614 * Default value for this option is 256MB. 615 * 616 */ 617 #define __NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ 618 S0ixPowerManagementVideoMemoryThreshold 619 #define NV_REG_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ 620 NV_REG_STRING(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD) 621 622 /* 623 * Option: DynamicPowerManagement 624 * 625 * This option controls how aggressively the NVIDIA kernel module will manage 626 * GPU power through kernel interfaces. 627 * 628 * Possible Values: 629 * 630 * 0: Never allow the GPU to be powered down (default). 631 * 1: Power down the GPU when it is not initialized. 632 * 2: Power down the GPU after it has been inactive for some time. 633 * 3: (Default) Power down the GPU after a period of inactivity (i.e., 634 * mode 2) on Ampere or later notebooks. Otherwise, do not power down 635 * the GPU. 636 */ 637 #define __NV_DYNAMIC_POWER_MANAGEMENT DynamicPowerManagement 638 #define NV_REG_DYNAMIC_POWER_MANAGEMENT \ 639 NV_REG_STRING(__NV_DYNAMIC_POWER_MANAGEMENT) 640 641 #define NV_REG_DYNAMIC_POWER_MANAGEMENT_NEVER 0 642 #define NV_REG_DYNAMIC_POWER_MANAGEMENT_COARSE 1 643 #define NV_REG_DYNAMIC_POWER_MANAGEMENT_FINE 2 644 #define NV_REG_DYNAMIC_POWER_MANAGEMENT_DEFAULT 3 645 646 /* 647 * Option: DynamicPowerManagementVideoMemoryThreshold 648 * 649 * This option controls the threshold that the NVIDIA driver will use 650 * when selecting the dynamic power management scheme. 651 * 652 * When the driver detects that the GPU is idle, it will compare the amount 653 * of video memory in use with this threshold. 654 * 655 * If the current video memory usage is less than the threshold, the 656 * driver may preserve video memory contents in system memory and power off 657 * the video memory along with the GPU itself, if supported. Otherwise, 658 * the video memory will be kept in self-refresh mode while powering down 659 * the rest of the GPU, if supported. 660 * 661 * Values are expressed in Megabytes (1048576 bytes). 662 * 663 * If the requested value is greater than 200MB (the default), then it 664 * will be capped to 200MB. 665 */ 666 #define __NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ 667 DynamicPowerManagementVideoMemoryThreshold 668 #define NV_REG_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD \ 669 NV_REG_STRING(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD) 670 671 /* 672 * Option: RegisterPCIDriver 673 * 674 * Description: 675 * 676 * When this option is enabled, the NVIDIA driver will register with 677 * PCI subsystem. 678 * 679 * Possible values: 680 * 681 * 1 - register as PCI driver (default) 682 * 0 - do not register as PCI driver 683 */ 684 685 #define __NV_REGISTER_PCI_DRIVER RegisterPCIDriver 686 #define NV_REG_REGISTER_PCI_DRIVER NV_REG_STRING(__NV_REGISTER_PCI_DRIVER) 687 688 /* 689 * Option: EnablePCIERelaxedOrderingMode 690 * 691 * Description: 692 * 693 * When this option is enabled, the registry key RmSetPCIERelaxedOrdering will 694 * be set to NV_REG_STR_RM_SET_PCIE_TLP_RELAXED_ORDERING_FORCE_ENABLE, causing 695 * every device to set the relaxed ordering bit to 1 in all outbound MWr 696 * transaction-layer packets. This is equivalent to setting the regkey to 697 * FORCE_ENABLE as a non-per-device registry key. 698 * 699 * Possible values: 700 * 0 - Do not enable PCIe TLP relaxed ordering bit-setting (default) 701 * 1 - Enable PCIe TLP relaxed ordering bit-setting 702 */ 703 #define __NV_ENABLE_PCIE_RELAXED_ORDERING_MODE EnablePCIERelaxedOrderingMode 704 #define NV_REG_ENABLE_PCIE_RELAXED_ORDERING_MODE \ 705 NV_REG_STRING(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE) 706 707 /* 708 * Option: EnableResizableBar 709 * 710 * Description: 711 * 712 * When this option is enabled, the NVIDIA driver will attempt to resize 713 * BAR1 to match framebuffer size, or the next largest available size on 714 * supported machines. This is currently only implemented for Linux. 715 * 716 * Possible values: 717 * 0 - Do not enable PCI BAR resizing 718 * 1 - Enable PCI BAR resizing 719 */ 720 #define __NV_ENABLE_RESIZABLE_BAR EnableResizableBar 721 #define NV_REG_ENABLE_RESIZABLE_BAR NV_REG_STRING(__NV_ENABLE_RESIZABLE_BAR) 722 723 /* 724 * Option: EnableGpuFirmware 725 * 726 * Description: 727 * 728 * When this option is enabled, the NVIDIA driver will enable use of GPU 729 * firmware. 730 * 731 * If this key is set globally to the system, the driver may still attempt 732 * to apply some policies to maintain uniform firmware modes across all 733 * GPUS. This may result in the driver failing initialization on some GPUs 734 * to maintain such a policy. 735 * 736 * If this key is set using NVreg_RegistryDwordsPerDevice, then the driver 737 * will attempt to honor whatever configuration is specified without applying 738 * additional policies. This may also result in failed GPU initialzations if 739 * the configuration is not possible (for example if the firmware is missing 740 * from the filesystem, or the GPU is not capable). 741 * 742 * NOTE: More details for this regkey can be found in nv-firmware-registry.h 743 */ 744 #define __NV_ENABLE_GPU_FIRMWARE EnableGpuFirmware 745 #define NV_REG_ENABLE_GPU_FIRMWARE NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE) 746 747 /* 748 * Option: EnableGpuFirmwareLogs 749 * 750 * When this option is enabled, the NVIDIA driver will send GPU firmware logs 751 * to the system log, when possible. 752 * 753 * NOTE: More details for this regkey can be found in nv-firmware-registry.h 754 */ 755 #define __NV_ENABLE_GPU_FIRMWARE_LOGS EnableGpuFirmwareLogs 756 #define NV_REG_ENABLE_GPU_FIRMWARE_LOGS NV_REG_STRING(__NV_ENABLE_GPU_FIRMWARE_LOGS) 757 758 /* 759 * Option: EnableDbgBreakpoint 760 * 761 * When this option is set to a non-zero value, and the kernel is configured 762 * appropriately, assertions within resman will trigger a CPU breakpoint (e.g., 763 * INT3 on x86_64), assumed to be caught by an attached debugger. 764 * 765 * When this option is set to the value zero (the default), assertions within 766 * resman will print to the system log, but no CPU breakpoint will be triggered. 767 */ 768 #define __NV_ENABLE_DBG_BREAKPOINT EnableDbgBreakpoint 769 770 771 /* 772 * Option: OpenRmEnableUnsupportedGpus 773 * 774 * Open nvidia.ko support for features beyond what is used on Data Center GPUs 775 * is still fairly immature, so for now require users to opt into use of open 776 * nvidia.ko with a special registry key, if not on a Data Center GPU. 777 */ 778 779 #define __NV_OPENRM_ENABLE_UNSUPPORTED_GPUS OpenRmEnableUnsupportedGpus 780 #define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS NV_REG_STRING(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS) 781 #define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE 0x00000000 782 #define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_ENABLE 0x00000001 783 #define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE 784 785 /* 786 * Option: NVreg_DmaRemapPeerMmio 787 * 788 * Description: 789 * 790 * When this option is enabled, the NVIDIA driver will use device driver 791 * APIs provided by the Linux kernel for DMA-remapping part of a device's 792 * MMIO region to another device, creating e.g., IOMMU mappings as necessary. 793 * When this option is disabled, the NVIDIA driver will instead only apply a 794 * fixed offset, which may be zero, to CPU physical addresses to produce the 795 * DMA address for the peer's MMIO region, and no IOMMU mappings will be 796 * created. 797 * 798 * This option only affects peer MMIO DMA mappings, and not system memory 799 * mappings. 800 * 801 * Possible Values: 802 * 0 = disable dynamic DMA remapping of peer MMIO regions 803 * 1 = enable dynamic DMA remapping of peer MMIO regions (default) 804 */ 805 #define __NV_DMA_REMAP_PEER_MMIO DmaRemapPeerMmio 806 #define NV_DMA_REMAP_PEER_MMIO NV_REG_STRING(__NV_DMA_REMAP_PEER_MMIO) 807 #define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 808 #define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 809 810 /* 811 * Option: NVreg_RmNvlinkBandwidth 812 * 813 * Description: 814 * 815 * This option allows user to reduce the NVLINK P2P bandwidth to save power. 816 * The option is in the string format. 817 * 818 * Possible string values: 819 * OFF: 0% bandwidth 820 * MIN: 15%-25% bandwidth depending on the system's NVLink topology 821 * HALF: 50% bandwidth 822 * 3QUARTER: 75% bandwidth 823 * FULL: 100% bandwidth (default) 824 * 825 * This option is only for Hopper+ GPU with NVLINK version 4.0. 826 */ 827 #define __NV_RM_NVLINK_BW RmNvlinkBandwidth 828 #define NV_RM_NVLINK_BW NV_REG_STRING(__NV_RM_NVLINK_BW) 829 830 #if defined(NV_DEFINE_REGISTRY_KEY_TABLE) 831 832 /* 833 *---------registry key parameter declarations-------------- 834 */ 835 836 NV_DEFINE_REG_ENTRY(__NV_RESMAN_DEBUG_LEVEL, ~0); 837 NV_DEFINE_REG_ENTRY(__NV_RM_LOGON_RC, 1); 838 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MODIFY_DEVICE_FILES, 1); 839 NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_UID, 0); 840 NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_GID, 0); 841 NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_MODE, 0666); 842 NV_DEFINE_REG_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, 1); 843 NV_DEFINE_REG_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE, ~0); 844 NV_DEFINE_REG_ENTRY(__NV_ENABLE_PCIE_GEN3, 0); 845 NV_DEFINE_REG_ENTRY(__NV_ENABLE_MSI, 1); 846 NV_DEFINE_REG_ENTRY(__NV_TCE_BYPASS_MODE, NV_TCE_BYPASS_MODE_DEFAULT); 847 NV_DEFINE_REG_ENTRY(__NV_ENABLE_STREAM_MEMOPS, 0); 848 NV_DEFINE_REG_ENTRY(__NV_RM_PROFILING_ADMIN_ONLY_PARAMETER, 1); 849 NV_DEFINE_REG_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS, 0); 850 NV_DEFINE_REG_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT, 0); 851 NV_DEFINE_REG_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 256); 852 NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT, 3); 853 NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 200); 854 NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE, NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE); 855 NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS, NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG); 856 NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT); 857 858 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_USER_NUMA_MANAGEMENT, 1); 859 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MEMORY_POOL_SIZE, 0); 860 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_KMALLOC_HEAP_MAX_SIZE, 0); 861 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_VMALLOC_HEAP_MAX_SIZE, 0); 862 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IGNORE_MMIO_CHECK, 0); 863 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0); 864 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); 865 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); 866 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_RESIZABLE_BAR, 0); 867 NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); 868 869 NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); 870 NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS_PER_DEVICE, NULL); 871 NV_DEFINE_REG_STRING_ENTRY(__NV_RM_MSG, NULL); 872 NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL); 873 NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); 874 NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); 875 NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); 876 NV_DEFINE_REG_STRING_ENTRY(__NV_RM_NVLINK_BW, NULL); 877 878 /* 879 *----------------registry database definition---------------------- 880 */ 881 882 /* 883 * You can enable any of the registry options disabled by default by 884 * editing their respective entries in the table below. The last field 885 * determines if the option is considered valid - in order for the 886 * changes to take effect, you need to recompile and reload the NVIDIA 887 * kernel module. 888 */ 889 nv_parm_t nv_parms[] = { 890 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RESMAN_DEBUG_LEVEL), 891 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_LOGON_RC), 892 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MODIFY_DEVICE_FILES), 893 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_UID), 894 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_GID), 895 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_MODE), 896 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), 897 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE), 898 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_MSI), 899 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_GEN3), 900 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MEMORY_POOL_SIZE), 901 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_KMALLOC_HEAP_MAX_SIZE), 902 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_VMALLOC_HEAP_MAX_SIZE), 903 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_IGNORE_MMIO_CHECK), 904 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_TCE_BYPASS_MODE), 905 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_STREAM_MEMOPS), 906 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_USER_NUMA_MANAGEMENT), 907 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_NVLINK_DISABLE), 908 NV_DEFINE_PARAMS_TABLE_ENTRY_CUSTOM_NAME(__NV_RM_PROFILING_ADMIN_ONLY, 909 __NV_RM_PROFILING_ADMIN_ONLY_PARAMETER), 910 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_PRESERVE_VIDEO_MEMORY_ALLOCATIONS), 911 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_S0IX_POWER_MANAGEMENT), 912 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_S0IX_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), 913 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT), 914 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), 915 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER), 916 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE), 917 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_RESIZABLE_BAR), 918 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE), 919 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), 920 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), 921 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS), 922 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DMA_REMAP_PEER_MMIO), 923 {NULL, NULL} 924 }; 925 926 #elif defined(NVRM) 927 928 extern nv_parm_t nv_parms[]; 929 930 #endif /* NV_DEFINE_REGISTRY_KEY_TABLE */ 931 932 #endif /* _RM_REG_H_ */ 933