1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <core/core.h> 25 #include <gpu/gpu.h> 26 #include <gpu/eng_desc.h> 27 #include <g_allclasses.h> 28 29 30 31 const CLASSDESCRIPTOR * 32 gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 33 { 34 static const CLASSDESCRIPTOR halTU102ClassDescriptorList[] = { 35 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 36 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 37 { FERMI_TWOD_A, ENG_GR(0) }, 38 { FERMI_VASPACE_A, ENG_DMA }, 39 { G84_PERFBUFFER, ENG_BUS }, 40 { GF100_DISP_SW, ENG_SW }, 41 { GF100_HDACODEC, ENG_HDACODEC }, 42 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 43 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 44 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 45 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 46 { GP100_UVM_SW, ENG_SW }, 47 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 48 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 49 { MMU_FAULT_BUFFER, ENG_GR(0) }, 50 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 51 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 52 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 53 { NV04_SOFTWARE_TEST, ENG_SW }, 54 { NV50_DEFERRED_API_CLASS, ENG_SW }, 55 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 56 { NV50_P2P, ENG_BUS }, 57 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 58 { NVA081_VGPU_CONFIG, ENG_GPU }, 59 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 60 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 61 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 62 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, 63 { NVC4B7_VIDEO_ENCODER, ENG_MSENC(0) }, 64 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY }, 65 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 66 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 67 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 68 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 69 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 70 { RM_USER_SHARED_DATA, ENG_GPU }, 71 { TURING_A, ENG_GR(0) }, 72 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 73 { TURING_COMPUTE_A, ENG_GR(0) }, 74 { TURING_DMA_COPY_A, ENG_CE(0) }, 75 { TURING_DMA_COPY_A, ENG_CE(1) }, 76 { TURING_DMA_COPY_A, ENG_CE(2) }, 77 { TURING_DMA_COPY_A, ENG_CE(3) }, 78 { TURING_DMA_COPY_A, ENG_CE(4) }, 79 { TURING_USERMODE_A, ENG_GPU }, 80 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 81 { VOLTA_USERMODE_A, ENG_GPU }, 82 }; 83 84 #define HALTU102_NUM_CLASS_DESCS (sizeof(halTU102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 85 86 #define HALTU102_NUM_CLASSES 52 87 88 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU102_NUM_CLASSES); 89 90 *pNumClassDescriptors = HALTU102_NUM_CLASS_DESCS; 91 return halTU102ClassDescriptorList; 92 } 93 94 95 96 const CLASSDESCRIPTOR * 97 gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 98 { 99 static const CLASSDESCRIPTOR halTU104ClassDescriptorList[] = { 100 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 101 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 102 { FERMI_TWOD_A, ENG_GR(0) }, 103 { FERMI_VASPACE_A, ENG_DMA }, 104 { G84_PERFBUFFER, ENG_BUS }, 105 { GF100_DISP_SW, ENG_SW }, 106 { GF100_HDACODEC, ENG_HDACODEC }, 107 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 108 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 109 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 110 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 111 { GP100_UVM_SW, ENG_SW }, 112 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 113 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 114 { MMU_FAULT_BUFFER, ENG_GR(0) }, 115 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 116 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 117 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 118 { NV04_SOFTWARE_TEST, ENG_SW }, 119 { NV50_DEFERRED_API_CLASS, ENG_SW }, 120 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 121 { NV50_P2P, ENG_BUS }, 122 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 123 { NVA081_VGPU_CONFIG, ENG_GPU }, 124 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 125 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 126 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 127 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, 128 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(1) }, 129 { NVC4B7_VIDEO_ENCODER, ENG_MSENC(0) }, 130 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY }, 131 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 132 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 133 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 134 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 135 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 136 { RM_USER_SHARED_DATA, ENG_GPU }, 137 { TURING_A, ENG_GR(0) }, 138 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 139 { TURING_COMPUTE_A, ENG_GR(0) }, 140 { TURING_DMA_COPY_A, ENG_CE(0) }, 141 { TURING_DMA_COPY_A, ENG_CE(1) }, 142 { TURING_DMA_COPY_A, ENG_CE(2) }, 143 { TURING_DMA_COPY_A, ENG_CE(3) }, 144 { TURING_DMA_COPY_A, ENG_CE(4) }, 145 { TURING_USERMODE_A, ENG_GPU }, 146 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 147 { VOLTA_USERMODE_A, ENG_GPU }, 148 }; 149 150 #define HALTU104_NUM_CLASS_DESCS (sizeof(halTU104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 151 152 #define HALTU104_NUM_CLASSES 52 153 154 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU104_NUM_CLASSES); 155 156 *pNumClassDescriptors = HALTU104_NUM_CLASS_DESCS; 157 return halTU104ClassDescriptorList; 158 } 159 160 161 162 const CLASSDESCRIPTOR * 163 gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 164 { 165 static const CLASSDESCRIPTOR halTU106ClassDescriptorList[] = { 166 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 167 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 168 { FERMI_TWOD_A, ENG_GR(0) }, 169 { FERMI_VASPACE_A, ENG_DMA }, 170 { G84_PERFBUFFER, ENG_BUS }, 171 { GF100_DISP_SW, ENG_SW }, 172 { GF100_HDACODEC, ENG_HDACODEC }, 173 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 174 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 175 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 176 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 177 { GP100_UVM_SW, ENG_SW }, 178 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 179 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 180 { MMU_FAULT_BUFFER, ENG_GR(0) }, 181 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 182 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 183 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 184 { NV04_SOFTWARE_TEST, ENG_SW }, 185 { NV50_DEFERRED_API_CLASS, ENG_SW }, 186 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 187 { NV50_P2P, ENG_BUS }, 188 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 189 { NVA081_VGPU_CONFIG, ENG_GPU }, 190 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 191 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 192 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 193 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, 194 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(1) }, 195 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(2) }, 196 { NVC4B7_VIDEO_ENCODER, ENG_MSENC(0) }, 197 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY }, 198 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 199 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 200 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 201 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 202 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 203 { RM_USER_SHARED_DATA, ENG_GPU }, 204 { TURING_A, ENG_GR(0) }, 205 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 206 { TURING_COMPUTE_A, ENG_GR(0) }, 207 { TURING_DMA_COPY_A, ENG_CE(0) }, 208 { TURING_DMA_COPY_A, ENG_CE(1) }, 209 { TURING_DMA_COPY_A, ENG_CE(2) }, 210 { TURING_DMA_COPY_A, ENG_CE(3) }, 211 { TURING_DMA_COPY_A, ENG_CE(4) }, 212 { TURING_USERMODE_A, ENG_GPU }, 213 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 214 { VOLTA_USERMODE_A, ENG_GPU }, 215 }; 216 217 #define HALTU106_NUM_CLASS_DESCS (sizeof(halTU106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 218 219 #define HALTU106_NUM_CLASSES 52 220 221 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU106_NUM_CLASSES); 222 223 *pNumClassDescriptors = HALTU106_NUM_CLASS_DESCS; 224 return halTU106ClassDescriptorList; 225 } 226 227 228 229 const CLASSDESCRIPTOR * 230 gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 231 { 232 static const CLASSDESCRIPTOR halTU116ClassDescriptorList[] = { 233 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 234 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 235 { FERMI_TWOD_A, ENG_GR(0) }, 236 { FERMI_VASPACE_A, ENG_DMA }, 237 { G84_PERFBUFFER, ENG_BUS }, 238 { GF100_DISP_SW, ENG_SW }, 239 { GF100_HDACODEC, ENG_HDACODEC }, 240 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 241 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 242 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 243 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 244 { GP100_UVM_SW, ENG_SW }, 245 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 246 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 247 { MMU_FAULT_BUFFER, ENG_GR(0) }, 248 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 249 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 250 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 251 { NV04_SOFTWARE_TEST, ENG_SW }, 252 { NV50_DEFERRED_API_CLASS, ENG_SW }, 253 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 254 { NV50_P2P, ENG_BUS }, 255 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 256 { NVA081_VGPU_CONFIG, ENG_GPU }, 257 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 258 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 259 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 260 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, 261 { NVC4B7_VIDEO_ENCODER, ENG_MSENC(0) }, 262 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY }, 263 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 264 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 265 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 266 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 267 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 268 { RM_USER_SHARED_DATA, ENG_GPU }, 269 { TURING_A, ENG_GR(0) }, 270 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 271 { TURING_COMPUTE_A, ENG_GR(0) }, 272 { TURING_DMA_COPY_A, ENG_CE(0) }, 273 { TURING_DMA_COPY_A, ENG_CE(1) }, 274 { TURING_DMA_COPY_A, ENG_CE(2) }, 275 { TURING_DMA_COPY_A, ENG_CE(3) }, 276 { TURING_DMA_COPY_A, ENG_CE(4) }, 277 { TURING_USERMODE_A, ENG_GPU }, 278 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 279 { VOLTA_USERMODE_A, ENG_GPU }, 280 }; 281 282 #define HALTU116_NUM_CLASS_DESCS (sizeof(halTU116ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 283 284 #define HALTU116_NUM_CLASSES 52 285 286 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU116_NUM_CLASSES); 287 288 *pNumClassDescriptors = HALTU116_NUM_CLASS_DESCS; 289 return halTU116ClassDescriptorList; 290 } 291 292 293 294 const CLASSDESCRIPTOR * 295 gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 296 { 297 static const CLASSDESCRIPTOR halTU117ClassDescriptorList[] = { 298 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 299 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 300 { FERMI_TWOD_A, ENG_GR(0) }, 301 { FERMI_VASPACE_A, ENG_DMA }, 302 { G84_PERFBUFFER, ENG_BUS }, 303 { GF100_DISP_SW, ENG_SW }, 304 { GF100_HDACODEC, ENG_HDACODEC }, 305 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 306 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 307 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 308 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 309 { GP100_UVM_SW, ENG_SW }, 310 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 311 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 312 { MMU_FAULT_BUFFER, ENG_GR(0) }, 313 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 314 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 315 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 316 { NV04_SOFTWARE_TEST, ENG_SW }, 317 { NV50_DEFERRED_API_CLASS, ENG_SW }, 318 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 319 { NV50_P2P, ENG_BUS }, 320 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 321 { NVA081_VGPU_CONFIG, ENG_GPU }, 322 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 323 { NVB4B7_VIDEO_ENCODER, ENG_MSENC(0) }, 324 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 325 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 326 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, 327 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY }, 328 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 329 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 330 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 331 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 332 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 333 { RM_USER_SHARED_DATA, ENG_GPU }, 334 { TURING_A, ENG_GR(0) }, 335 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 336 { TURING_COMPUTE_A, ENG_GR(0) }, 337 { TURING_DMA_COPY_A, ENG_CE(0) }, 338 { TURING_DMA_COPY_A, ENG_CE(1) }, 339 { TURING_DMA_COPY_A, ENG_CE(2) }, 340 { TURING_DMA_COPY_A, ENG_CE(3) }, 341 { TURING_DMA_COPY_A, ENG_CE(4) }, 342 { TURING_USERMODE_A, ENG_GPU }, 343 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 344 { VOLTA_USERMODE_A, ENG_GPU }, 345 }; 346 347 #define HALTU117_NUM_CLASS_DESCS (sizeof(halTU117ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 348 349 #define HALTU117_NUM_CLASSES 52 350 351 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU117_NUM_CLASSES); 352 353 *pNumClassDescriptors = HALTU117_NUM_CLASS_DESCS; 354 return halTU117ClassDescriptorList; 355 } 356 357 358 359 const CLASSDESCRIPTOR * 360 gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 361 { 362 static const CLASSDESCRIPTOR halGA100ClassDescriptorList[] = { 363 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 364 { AMPERE_A, ENG_GR(0) }, 365 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 366 { AMPERE_COMPUTE_A, ENG_GR(0) }, 367 { AMPERE_COMPUTE_A, ENG_GR(1) }, 368 { AMPERE_COMPUTE_A, ENG_GR(2) }, 369 { AMPERE_COMPUTE_A, ENG_GR(3) }, 370 { AMPERE_COMPUTE_A, ENG_GR(4) }, 371 { AMPERE_COMPUTE_A, ENG_GR(5) }, 372 { AMPERE_COMPUTE_A, ENG_GR(6) }, 373 { AMPERE_COMPUTE_A, ENG_GR(7) }, 374 { AMPERE_DMA_COPY_A, ENG_CE(0) }, 375 { AMPERE_DMA_COPY_A, ENG_CE(1) }, 376 { AMPERE_DMA_COPY_A, ENG_CE(2) }, 377 { AMPERE_DMA_COPY_A, ENG_CE(3) }, 378 { AMPERE_DMA_COPY_A, ENG_CE(4) }, 379 { AMPERE_DMA_COPY_A, ENG_CE(5) }, 380 { AMPERE_DMA_COPY_A, ENG_CE(6) }, 381 { AMPERE_DMA_COPY_A, ENG_CE(7) }, 382 { AMPERE_DMA_COPY_A, ENG_CE(8) }, 383 { AMPERE_DMA_COPY_A, ENG_CE(9) }, 384 { AMPERE_USERMODE_A, ENG_GPU }, 385 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 386 { FERMI_TWOD_A, ENG_GR(0) }, 387 { FERMI_VASPACE_A, ENG_DMA }, 388 { G84_PERFBUFFER, ENG_BUS }, 389 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 390 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 391 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 392 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 393 { GP100_UVM_SW, ENG_SW }, 394 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 395 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 396 { MMU_FAULT_BUFFER, ENG_GR(0) }, 397 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 398 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 399 { NV04_SOFTWARE_TEST, ENG_SW }, 400 { NV50_DEFERRED_API_CLASS, ENG_SW }, 401 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 402 { NV50_P2P, ENG_BUS }, 403 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 404 { NVA081_VGPU_CONFIG, ENG_GPU }, 405 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 406 { NVC4D1_VIDEO_NVJPG, ENG_NVJPG }, 407 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(0) }, 408 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(1) }, 409 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(2) }, 410 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(3) }, 411 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(4) }, 412 { NVC6FA_VIDEO_OFA, ENG_OFA(0) }, 413 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 414 { RM_USER_SHARED_DATA, ENG_GPU }, 415 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 416 { TURING_USERMODE_A, ENG_GPU }, 417 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 418 { VOLTA_USERMODE_A, ENG_GPU }, 419 }; 420 421 #define HALGA100_NUM_CLASS_DESCS (sizeof(halGA100ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 422 423 #define HALGA100_NUM_CLASSES 46 424 425 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA100_NUM_CLASSES); 426 427 *pNumClassDescriptors = HALGA100_NUM_CLASS_DESCS; 428 return halGA100ClassDescriptorList; 429 } 430 431 432 433 const CLASSDESCRIPTOR * 434 gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 435 { 436 static const CLASSDESCRIPTOR halGA102ClassDescriptorList[] = { 437 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 438 { AMPERE_B, ENG_GR(0) }, 439 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 440 { AMPERE_COMPUTE_B, ENG_GR(0) }, 441 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 442 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 443 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 444 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 445 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 446 { AMPERE_USERMODE_A, ENG_GPU }, 447 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 448 { FERMI_TWOD_A, ENG_GR(0) }, 449 { FERMI_VASPACE_A, ENG_DMA }, 450 { G84_PERFBUFFER, ENG_BUS }, 451 { GF100_DISP_SW, ENG_SW }, 452 { GF100_HDACODEC, ENG_HDACODEC }, 453 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 454 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 455 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 456 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 457 { GP100_UVM_SW, ENG_SW }, 458 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 459 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 460 { MMU_FAULT_BUFFER, ENG_GR(0) }, 461 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 462 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 463 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 464 { NV04_SOFTWARE_TEST, ENG_SW }, 465 { NV50_DEFERRED_API_CLASS, ENG_SW }, 466 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 467 { NV50_P2P, ENG_BUS }, 468 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 469 { NVA081_VGPU_CONFIG, ENG_GPU }, 470 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 471 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 472 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, 473 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 474 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 475 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 476 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 477 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 478 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 479 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 480 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, 481 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, 482 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, 483 { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, 484 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 485 { RM_USER_SHARED_DATA, ENG_GPU }, 486 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 487 { TURING_USERMODE_A, ENG_GPU }, 488 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 489 { VOLTA_USERMODE_A, ENG_GPU }, 490 }; 491 492 #define HALGA102_NUM_CLASS_DESCS (sizeof(halGA102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 493 494 #define HALGA102_NUM_CLASSES 58 495 496 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA102_NUM_CLASSES); 497 498 *pNumClassDescriptors = HALGA102_NUM_CLASS_DESCS; 499 return halGA102ClassDescriptorList; 500 } 501 502 503 504 const CLASSDESCRIPTOR * 505 gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 506 { 507 static const CLASSDESCRIPTOR halGA103ClassDescriptorList[] = { 508 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 509 { AMPERE_B, ENG_GR(0) }, 510 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 511 { AMPERE_COMPUTE_B, ENG_GR(0) }, 512 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 513 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 514 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 515 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 516 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 517 { AMPERE_USERMODE_A, ENG_GPU }, 518 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 519 { FERMI_TWOD_A, ENG_GR(0) }, 520 { FERMI_VASPACE_A, ENG_DMA }, 521 { G84_PERFBUFFER, ENG_BUS }, 522 { GF100_DISP_SW, ENG_SW }, 523 { GF100_HDACODEC, ENG_HDACODEC }, 524 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 525 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 526 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 527 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 528 { GP100_UVM_SW, ENG_SW }, 529 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 530 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 531 { MMU_FAULT_BUFFER, ENG_GR(0) }, 532 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 533 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 534 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 535 { NV04_SOFTWARE_TEST, ENG_SW }, 536 { NV50_DEFERRED_API_CLASS, ENG_SW }, 537 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 538 { NV50_P2P, ENG_BUS }, 539 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 540 { NVA081_VGPU_CONFIG, ENG_GPU }, 541 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 542 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 543 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, 544 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 545 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 546 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 547 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 548 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 549 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 550 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 551 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, 552 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, 553 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, 554 { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, 555 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 556 { RM_USER_SHARED_DATA, ENG_GPU }, 557 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 558 { TURING_USERMODE_A, ENG_GPU }, 559 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 560 { VOLTA_USERMODE_A, ENG_GPU }, 561 }; 562 563 #define HALGA103_NUM_CLASS_DESCS (sizeof(halGA103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 564 565 #define HALGA103_NUM_CLASSES 58 566 567 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA103_NUM_CLASSES); 568 569 *pNumClassDescriptors = HALGA103_NUM_CLASS_DESCS; 570 return halGA103ClassDescriptorList; 571 } 572 573 574 575 const CLASSDESCRIPTOR * 576 gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 577 { 578 static const CLASSDESCRIPTOR halGA104ClassDescriptorList[] = { 579 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 580 { AMPERE_B, ENG_GR(0) }, 581 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 582 { AMPERE_COMPUTE_B, ENG_GR(0) }, 583 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 584 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 585 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 586 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 587 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 588 { AMPERE_USERMODE_A, ENG_GPU }, 589 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 590 { FERMI_TWOD_A, ENG_GR(0) }, 591 { FERMI_VASPACE_A, ENG_DMA }, 592 { G84_PERFBUFFER, ENG_BUS }, 593 { GF100_DISP_SW, ENG_SW }, 594 { GF100_HDACODEC, ENG_HDACODEC }, 595 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 596 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 597 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 598 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 599 { GP100_UVM_SW, ENG_SW }, 600 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 601 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 602 { MMU_FAULT_BUFFER, ENG_GR(0) }, 603 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 604 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 605 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 606 { NV04_SOFTWARE_TEST, ENG_SW }, 607 { NV50_DEFERRED_API_CLASS, ENG_SW }, 608 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 609 { NV50_P2P, ENG_BUS }, 610 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 611 { NVA081_VGPU_CONFIG, ENG_GPU }, 612 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 613 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 614 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, 615 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 616 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 617 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 618 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 619 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 620 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 621 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 622 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, 623 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, 624 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, 625 { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, 626 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 627 { RM_USER_SHARED_DATA, ENG_GPU }, 628 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 629 { TURING_USERMODE_A, ENG_GPU }, 630 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 631 { VOLTA_USERMODE_A, ENG_GPU }, 632 }; 633 634 #define HALGA104_NUM_CLASS_DESCS (sizeof(halGA104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 635 636 #define HALGA104_NUM_CLASSES 58 637 638 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA104_NUM_CLASSES); 639 640 *pNumClassDescriptors = HALGA104_NUM_CLASS_DESCS; 641 return halGA104ClassDescriptorList; 642 } 643 644 645 646 const CLASSDESCRIPTOR * 647 gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 648 { 649 static const CLASSDESCRIPTOR halGA106ClassDescriptorList[] = { 650 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 651 { AMPERE_B, ENG_GR(0) }, 652 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 653 { AMPERE_COMPUTE_B, ENG_GR(0) }, 654 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 655 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 656 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 657 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 658 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 659 { AMPERE_USERMODE_A, ENG_GPU }, 660 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 661 { FERMI_TWOD_A, ENG_GR(0) }, 662 { FERMI_VASPACE_A, ENG_DMA }, 663 { G84_PERFBUFFER, ENG_BUS }, 664 { GF100_DISP_SW, ENG_SW }, 665 { GF100_HDACODEC, ENG_HDACODEC }, 666 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 667 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 668 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 669 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 670 { GP100_UVM_SW, ENG_SW }, 671 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 672 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 673 { MMU_FAULT_BUFFER, ENG_GR(0) }, 674 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 675 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 676 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 677 { NV04_SOFTWARE_TEST, ENG_SW }, 678 { NV50_DEFERRED_API_CLASS, ENG_SW }, 679 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 680 { NV50_P2P, ENG_BUS }, 681 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 682 { NVA081_VGPU_CONFIG, ENG_GPU }, 683 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 684 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 685 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, 686 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 687 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 688 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 689 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 690 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 691 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 692 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 693 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, 694 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, 695 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, 696 { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, 697 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 698 { RM_USER_SHARED_DATA, ENG_GPU }, 699 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 700 { TURING_USERMODE_A, ENG_GPU }, 701 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 702 { VOLTA_USERMODE_A, ENG_GPU }, 703 }; 704 705 #define HALGA106_NUM_CLASS_DESCS (sizeof(halGA106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 706 707 #define HALGA106_NUM_CLASSES 58 708 709 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA106_NUM_CLASSES); 710 711 *pNumClassDescriptors = HALGA106_NUM_CLASS_DESCS; 712 return halGA106ClassDescriptorList; 713 } 714 715 716 717 const CLASSDESCRIPTOR * 718 gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 719 { 720 static const CLASSDESCRIPTOR halGA107ClassDescriptorList[] = { 721 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 722 { AMPERE_B, ENG_GR(0) }, 723 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 724 { AMPERE_COMPUTE_B, ENG_GR(0) }, 725 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 726 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 727 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 728 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 729 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 730 { AMPERE_USERMODE_A, ENG_GPU }, 731 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 732 { FERMI_TWOD_A, ENG_GR(0) }, 733 { FERMI_VASPACE_A, ENG_DMA }, 734 { G84_PERFBUFFER, ENG_BUS }, 735 { GF100_DISP_SW, ENG_SW }, 736 { GF100_HDACODEC, ENG_HDACODEC }, 737 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 738 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 739 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 740 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 741 { GP100_UVM_SW, ENG_SW }, 742 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 743 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 744 { MMU_FAULT_BUFFER, ENG_GR(0) }, 745 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 746 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 747 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 748 { NV04_SOFTWARE_TEST, ENG_SW }, 749 { NV50_DEFERRED_API_CLASS, ENG_SW }, 750 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 751 { NV50_P2P, ENG_BUS }, 752 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 753 { NVA081_VGPU_CONFIG, ENG_GPU }, 754 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 755 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 756 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, 757 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 758 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 759 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 760 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 761 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 762 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 763 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 764 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, 765 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, 766 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, 767 { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, 768 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 769 { RM_USER_SHARED_DATA, ENG_GPU }, 770 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 771 { TURING_USERMODE_A, ENG_GPU }, 772 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 773 { VOLTA_USERMODE_A, ENG_GPU }, 774 }; 775 776 #define HALGA107_NUM_CLASS_DESCS (sizeof(halGA107ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 777 778 #define HALGA107_NUM_CLASSES 58 779 780 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA107_NUM_CLASSES); 781 782 *pNumClassDescriptors = HALGA107_NUM_CLASS_DESCS; 783 return halGA107ClassDescriptorList; 784 } 785 786 787 788 const CLASSDESCRIPTOR * 789 gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 790 { 791 static const CLASSDESCRIPTOR halAD102ClassDescriptorList[] = { 792 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 793 { ADA_A, ENG_GR(0) }, 794 { ADA_COMPUTE_A, ENG_GR(0) }, 795 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 796 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 797 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 798 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 799 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 800 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 801 { AMPERE_USERMODE_A, ENG_GPU }, 802 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 803 { FERMI_TWOD_A, ENG_GR(0) }, 804 { FERMI_VASPACE_A, ENG_DMA }, 805 { G84_PERFBUFFER, ENG_BUS }, 806 { GF100_DISP_SW, ENG_SW }, 807 { GF100_HDACODEC, ENG_HDACODEC }, 808 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 809 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 810 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 811 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 812 { GP100_UVM_SW, ENG_SW }, 813 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 814 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 815 { MMU_FAULT_BUFFER, ENG_GR(0) }, 816 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 817 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 818 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 819 { NV04_SOFTWARE_TEST, ENG_SW }, 820 { NV50_DEFERRED_API_CLASS, ENG_SW }, 821 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 822 { NV50_P2P, ENG_BUS }, 823 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 824 { NVA081_VGPU_CONFIG, ENG_GPU }, 825 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 826 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 827 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 828 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 829 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 830 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, 831 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 832 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 833 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 834 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 835 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, 836 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, 837 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, 838 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, 839 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, 840 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, 841 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, 842 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, 843 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, 844 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, 845 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, 846 { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, 847 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 848 { RM_USER_SHARED_DATA, ENG_GPU }, 849 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 850 { TURING_USERMODE_A, ENG_GPU }, 851 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 852 { VOLTA_USERMODE_A, ENG_GPU }, 853 }; 854 855 #define HALAD102_NUM_CLASS_DESCS (sizeof(halAD102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 856 857 #define HALAD102_NUM_CLASSES 59 858 859 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD102_NUM_CLASSES); 860 861 *pNumClassDescriptors = HALAD102_NUM_CLASS_DESCS; 862 return halAD102ClassDescriptorList; 863 } 864 865 866 867 const CLASSDESCRIPTOR * 868 gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 869 { 870 static const CLASSDESCRIPTOR halAD103ClassDescriptorList[] = { 871 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 872 { ADA_A, ENG_GR(0) }, 873 { ADA_COMPUTE_A, ENG_GR(0) }, 874 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 875 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 876 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 877 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 878 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 879 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 880 { AMPERE_USERMODE_A, ENG_GPU }, 881 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 882 { FERMI_TWOD_A, ENG_GR(0) }, 883 { FERMI_VASPACE_A, ENG_DMA }, 884 { G84_PERFBUFFER, ENG_BUS }, 885 { GF100_DISP_SW, ENG_SW }, 886 { GF100_HDACODEC, ENG_HDACODEC }, 887 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 888 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 889 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 890 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 891 { GP100_UVM_SW, ENG_SW }, 892 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 893 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 894 { MMU_FAULT_BUFFER, ENG_GR(0) }, 895 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 896 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 897 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 898 { NV04_SOFTWARE_TEST, ENG_SW }, 899 { NV50_DEFERRED_API_CLASS, ENG_SW }, 900 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 901 { NV50_P2P, ENG_BUS }, 902 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 903 { NVA081_VGPU_CONFIG, ENG_GPU }, 904 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 905 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 906 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 907 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 908 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 909 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, 910 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 911 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 912 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 913 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 914 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, 915 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, 916 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, 917 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, 918 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, 919 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, 920 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, 921 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, 922 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, 923 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, 924 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, 925 { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, 926 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 927 { RM_USER_SHARED_DATA, ENG_GPU }, 928 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 929 { TURING_USERMODE_A, ENG_GPU }, 930 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 931 { VOLTA_USERMODE_A, ENG_GPU }, 932 }; 933 934 #define HALAD103_NUM_CLASS_DESCS (sizeof(halAD103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 935 936 #define HALAD103_NUM_CLASSES 59 937 938 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD103_NUM_CLASSES); 939 940 *pNumClassDescriptors = HALAD103_NUM_CLASS_DESCS; 941 return halAD103ClassDescriptorList; 942 } 943 944 945 946 const CLASSDESCRIPTOR * 947 gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 948 { 949 static const CLASSDESCRIPTOR halAD104ClassDescriptorList[] = { 950 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 951 { ADA_A, ENG_GR(0) }, 952 { ADA_COMPUTE_A, ENG_GR(0) }, 953 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 954 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 955 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 956 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 957 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 958 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 959 { AMPERE_USERMODE_A, ENG_GPU }, 960 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 961 { FERMI_TWOD_A, ENG_GR(0) }, 962 { FERMI_VASPACE_A, ENG_DMA }, 963 { G84_PERFBUFFER, ENG_BUS }, 964 { GF100_DISP_SW, ENG_SW }, 965 { GF100_HDACODEC, ENG_HDACODEC }, 966 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 967 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 968 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 969 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 970 { GP100_UVM_SW, ENG_SW }, 971 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 972 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 973 { MMU_FAULT_BUFFER, ENG_GR(0) }, 974 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 975 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 976 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 977 { NV04_SOFTWARE_TEST, ENG_SW }, 978 { NV50_DEFERRED_API_CLASS, ENG_SW }, 979 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 980 { NV50_P2P, ENG_BUS }, 981 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 982 { NVA081_VGPU_CONFIG, ENG_GPU }, 983 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 984 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 985 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 986 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 987 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 988 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, 989 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 990 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 991 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 992 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 993 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, 994 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, 995 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, 996 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, 997 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, 998 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, 999 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, 1000 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, 1001 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, 1002 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, 1003 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, 1004 { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, 1005 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 1006 { RM_USER_SHARED_DATA, ENG_GPU }, 1007 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1008 { TURING_USERMODE_A, ENG_GPU }, 1009 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1010 { VOLTA_USERMODE_A, ENG_GPU }, 1011 }; 1012 1013 #define HALAD104_NUM_CLASS_DESCS (sizeof(halAD104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 1014 1015 #define HALAD104_NUM_CLASSES 59 1016 1017 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD104_NUM_CLASSES); 1018 1019 *pNumClassDescriptors = HALAD104_NUM_CLASS_DESCS; 1020 return halAD104ClassDescriptorList; 1021 } 1022 1023 1024 1025 const CLASSDESCRIPTOR * 1026 gpuGetClassDescriptorList_AD106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 1027 { 1028 static const CLASSDESCRIPTOR halAD106ClassDescriptorList[] = { 1029 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 1030 { ADA_A, ENG_GR(0) }, 1031 { ADA_COMPUTE_A, ENG_GR(0) }, 1032 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1033 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 1034 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 1035 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 1036 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 1037 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 1038 { AMPERE_USERMODE_A, ENG_GPU }, 1039 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 1040 { FERMI_TWOD_A, ENG_GR(0) }, 1041 { FERMI_VASPACE_A, ENG_DMA }, 1042 { G84_PERFBUFFER, ENG_BUS }, 1043 { GF100_DISP_SW, ENG_SW }, 1044 { GF100_HDACODEC, ENG_HDACODEC }, 1045 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 1046 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 1047 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 1048 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 1049 { GP100_UVM_SW, ENG_SW }, 1050 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 1051 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 1052 { MMU_FAULT_BUFFER, ENG_GR(0) }, 1053 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 1054 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 1055 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 1056 { NV04_SOFTWARE_TEST, ENG_SW }, 1057 { NV50_DEFERRED_API_CLASS, ENG_SW }, 1058 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 1059 { NV50_P2P, ENG_BUS }, 1060 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 1061 { NVA081_VGPU_CONFIG, ENG_GPU }, 1062 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 1063 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 1064 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 1065 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 1066 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 1067 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, 1068 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 1069 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 1070 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 1071 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 1072 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, 1073 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, 1074 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, 1075 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, 1076 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, 1077 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, 1078 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, 1079 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, 1080 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, 1081 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, 1082 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, 1083 { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, 1084 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 1085 { RM_USER_SHARED_DATA, ENG_GPU }, 1086 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1087 { TURING_USERMODE_A, ENG_GPU }, 1088 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1089 { VOLTA_USERMODE_A, ENG_GPU }, 1090 }; 1091 1092 #define HALAD106_NUM_CLASS_DESCS (sizeof(halAD106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 1093 1094 #define HALAD106_NUM_CLASSES 59 1095 1096 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD106_NUM_CLASSES); 1097 1098 *pNumClassDescriptors = HALAD106_NUM_CLASS_DESCS; 1099 return halAD106ClassDescriptorList; 1100 } 1101 1102 1103 1104 const CLASSDESCRIPTOR * 1105 gpuGetClassDescriptorList_AD107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 1106 { 1107 static const CLASSDESCRIPTOR halAD107ClassDescriptorList[] = { 1108 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 1109 { ADA_A, ENG_GR(0) }, 1110 { ADA_COMPUTE_A, ENG_GR(0) }, 1111 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1112 { AMPERE_DMA_COPY_B, ENG_CE(0) }, 1113 { AMPERE_DMA_COPY_B, ENG_CE(1) }, 1114 { AMPERE_DMA_COPY_B, ENG_CE(2) }, 1115 { AMPERE_DMA_COPY_B, ENG_CE(3) }, 1116 { AMPERE_DMA_COPY_B, ENG_CE(4) }, 1117 { AMPERE_USERMODE_A, ENG_GPU }, 1118 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 1119 { FERMI_TWOD_A, ENG_GR(0) }, 1120 { FERMI_VASPACE_A, ENG_DMA }, 1121 { G84_PERFBUFFER, ENG_BUS }, 1122 { GF100_DISP_SW, ENG_SW }, 1123 { GF100_HDACODEC, ENG_HDACODEC }, 1124 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 1125 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 1126 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 1127 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 1128 { GP100_UVM_SW, ENG_SW }, 1129 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 1130 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 1131 { MMU_FAULT_BUFFER, ENG_GR(0) }, 1132 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 1133 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 1134 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, 1135 { NV04_SOFTWARE_TEST, ENG_SW }, 1136 { NV50_DEFERRED_API_CLASS, ENG_SW }, 1137 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 1138 { NV50_P2P, ENG_BUS }, 1139 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 1140 { NVA081_VGPU_CONFIG, ENG_GPU }, 1141 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 1142 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, 1143 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, 1144 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 1145 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 1146 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, 1147 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, 1148 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, 1149 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 1150 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, 1151 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, 1152 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, 1153 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, 1154 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, 1155 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, 1156 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, 1157 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, 1158 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, 1159 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, 1160 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, 1161 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, 1162 { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, 1163 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 1164 { RM_USER_SHARED_DATA, ENG_GPU }, 1165 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1166 { TURING_USERMODE_A, ENG_GPU }, 1167 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1168 { VOLTA_USERMODE_A, ENG_GPU }, 1169 }; 1170 1171 #define HALAD107_NUM_CLASS_DESCS (sizeof(halAD107ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 1172 1173 #define HALAD107_NUM_CLASSES 59 1174 1175 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD107_NUM_CLASSES); 1176 1177 *pNumClassDescriptors = HALAD107_NUM_CLASS_DESCS; 1178 return halAD107ClassDescriptorList; 1179 } 1180 1181 1182 1183 const CLASSDESCRIPTOR * 1184 gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) 1185 { 1186 static const CLASSDESCRIPTOR halGH100ClassDescriptorList[] = { 1187 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, 1188 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1189 { AMPERE_USERMODE_A, ENG_GPU }, 1190 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, 1191 { FERMI_TWOD_A, ENG_GR(0) }, 1192 { FERMI_VASPACE_A, ENG_DMA }, 1193 { G84_PERFBUFFER, ENG_BUS }, 1194 { GF100_SUBDEVICE_INFOROM, ENG_GPU }, 1195 { GF100_SUBDEVICE_MASTER, ENG_GPU }, 1196 { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, 1197 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, 1198 { GP100_UVM_SW, ENG_SW }, 1199 { HOPPER_A, ENG_GR(0) }, 1200 { HOPPER_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1201 { HOPPER_COMPUTE_A, ENG_GR(0) }, 1202 { HOPPER_COMPUTE_A, ENG_GR(1) }, 1203 { HOPPER_COMPUTE_A, ENG_GR(2) }, 1204 { HOPPER_COMPUTE_A, ENG_GR(3) }, 1205 { HOPPER_COMPUTE_A, ENG_GR(4) }, 1206 { HOPPER_COMPUTE_A, ENG_GR(5) }, 1207 { HOPPER_COMPUTE_A, ENG_GR(6) }, 1208 { HOPPER_COMPUTE_A, ENG_GR(7) }, 1209 { HOPPER_DMA_COPY_A, ENG_CE(0) }, 1210 { HOPPER_DMA_COPY_A, ENG_CE(1) }, 1211 { HOPPER_DMA_COPY_A, ENG_CE(2) }, 1212 { HOPPER_DMA_COPY_A, ENG_CE(3) }, 1213 { HOPPER_DMA_COPY_A, ENG_CE(4) }, 1214 { HOPPER_DMA_COPY_A, ENG_CE(5) }, 1215 { HOPPER_DMA_COPY_A, ENG_CE(6) }, 1216 { HOPPER_DMA_COPY_A, ENG_CE(7) }, 1217 { HOPPER_DMA_COPY_A, ENG_CE(8) }, 1218 { HOPPER_DMA_COPY_A, ENG_CE(9) }, 1219 { HOPPER_SEC2_WORK_LAUNCH_A, ENG_SEC2 }, 1220 { HOPPER_USERMODE_A, ENG_GPU }, 1221 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, 1222 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, 1223 { MMU_FAULT_BUFFER, ENG_GR(0) }, 1224 { NV0060_SYNC_GPU_BOOST, ENG_GPU }, 1225 { NV01_MEMORY_VIRTUAL, ENG_DMA }, 1226 { NV04_SOFTWARE_TEST, ENG_SW }, 1227 { NV50_DEFERRED_API_CLASS, ENG_SW }, 1228 { NV50_MEMORY_VIRTUAL, ENG_DMA }, 1229 { NV50_P2P, ENG_BUS }, 1230 { NV50_THIRD_PARTY_P2P, ENG_BUS }, 1231 { NVA081_VGPU_CONFIG, ENG_GPU }, 1232 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, 1233 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(0) }, 1234 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(1) }, 1235 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(2) }, 1236 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(3) }, 1237 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(4) }, 1238 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(5) }, 1239 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(6) }, 1240 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(7) }, 1241 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, 1242 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, 1243 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, 1244 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, 1245 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(4) }, 1246 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(5) }, 1247 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(6) }, 1248 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(7) }, 1249 { NVB8FA_VIDEO_OFA, ENG_OFA(0) }, 1250 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, 1251 { RM_USER_SHARED_DATA, ENG_GPU }, 1252 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1253 { TURING_USERMODE_A, ENG_GPU }, 1254 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, 1255 { VOLTA_USERMODE_A, ENG_GPU }, 1256 }; 1257 1258 #define HALGH100_NUM_CLASS_DESCS (sizeof(halGH100ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) 1259 1260 #define HALGH100_NUM_CLASSES 49 1261 1262 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGH100_NUM_CLASSES); 1263 1264 *pNumClassDescriptors = HALGH100_NUM_CLASS_DESCS; 1265 return halGH100ClassDescriptorList; 1266 } 1267 1268 1269