1 #define NVOC_GPU_H_PRIVATE_ACCESS_ALLOWED 2 #include "nvoc/runtime.h" 3 #include "nvoc/rtti.h" 4 #include "nvtypes.h" 5 #include "nvport/nvport.h" 6 #include "nvport/inline/util_valist.h" 7 #include "utils/nvassert.h" 8 #include "g_gpu_nvoc.h" 9 10 #ifdef DEBUG 11 char __nvoc_class_id_uniqueness_check_0x7ef3cb = 1; 12 #endif 13 14 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; 15 16 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; 17 18 extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmHalspecOwner; 19 20 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTRACEABLE; 21 22 void __nvoc_init_OBJGPU(OBJGPU*, 23 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, 24 RM_RUNTIME_VARIANT RmVariantHal_rmVariant, 25 TEGRA_CHIP_TYPE TegraChipHal_tegraType, 26 NvU32 DispIpHal_ipver); 27 void __nvoc_init_funcTable_OBJGPU(OBJGPU*); 28 NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU*, NvU32 arg_gpuInstance); 29 void __nvoc_init_dataField_OBJGPU(OBJGPU*); 30 void __nvoc_dtor_OBJGPU(OBJGPU*); 31 extern const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGPU; 32 33 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_OBJGPU = { 34 /*pClassDef=*/ &__nvoc_class_def_OBJGPU, 35 /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_OBJGPU, 36 /*offset=*/ 0, 37 }; 38 39 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_Object = { 40 /*pClassDef=*/ &__nvoc_class_def_Object, 41 /*dtor=*/ &__nvoc_destructFromBase, 42 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_Object), 43 }; 44 45 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_RmHalspecOwner = { 46 /*pClassDef=*/ &__nvoc_class_def_RmHalspecOwner, 47 /*dtor=*/ &__nvoc_destructFromBase, 48 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_RmHalspecOwner), 49 }; 50 51 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_OBJTRACEABLE = { 52 /*pClassDef=*/ &__nvoc_class_def_OBJTRACEABLE, 53 /*dtor=*/ &__nvoc_destructFromBase, 54 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_OBJTRACEABLE), 55 }; 56 57 static const struct NVOC_CASTINFO __nvoc_castinfo_OBJGPU = { 58 /*numRelatives=*/ 4, 59 /*relatives=*/ { 60 &__nvoc_rtti_OBJGPU_OBJGPU, 61 &__nvoc_rtti_OBJGPU_OBJTRACEABLE, 62 &__nvoc_rtti_OBJGPU_RmHalspecOwner, 63 &__nvoc_rtti_OBJGPU_Object, 64 }, 65 }; 66 67 const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU = 68 { 69 /*classInfo=*/ { 70 /*size=*/ sizeof(OBJGPU), 71 /*classId=*/ classId(OBJGPU), 72 /*providerId=*/ &__nvoc_rtti_provider, 73 #if NV_PRINTF_STRINGS_ALLOWED 74 /*name=*/ "OBJGPU", 75 #endif 76 }, 77 /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_OBJGPU, 78 /*pCastInfo=*/ &__nvoc_castinfo_OBJGPU, 79 /*pExportInfo=*/ &__nvoc_export_info_OBJGPU 80 }; 81 82 const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGPU = 83 { 84 /*numEntries=*/ 0, 85 /*pExportEntries=*/ 0 86 }; 87 88 void __nvoc_dtor_Object(Object*); 89 void __nvoc_dtor_RmHalspecOwner(RmHalspecOwner*); 90 void __nvoc_dtor_OBJTRACEABLE(OBJTRACEABLE*); 91 void __nvoc_dtor_OBJGPU(OBJGPU *pThis) { 92 __nvoc_gpuDestruct(pThis); 93 __nvoc_dtor_Object(&pThis->__nvoc_base_Object); 94 __nvoc_dtor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner); 95 __nvoc_dtor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); 96 PORT_UNREFERENCED_VARIABLE(pThis); 97 } 98 99 void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { 100 ChipHal *chipHal = &staticCast(pThis, RmHalspecOwner)->chipHal; 101 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 102 RmVariantHal *rmVariantHal = &staticCast(pThis, RmHalspecOwner)->rmVariantHal; 103 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 104 PORT_UNREFERENCED_VARIABLE(pThis); 105 PORT_UNREFERENCED_VARIABLE(chipHal); 106 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 107 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 108 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 109 pThis->setProperty(pThis, PDB_PROP_GPU_IS_CONNECTED, ((NvBool)(0 == 0))); 110 111 // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY 112 // default 113 { 114 pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY, ((NvBool)(0 != 0))); 115 } 116 117 // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_IGPU 118 // default 119 { 120 pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_IGPU, ((NvBool)(0 != 0))); 121 } 122 123 // NVOC Property Hal field -- PDB_PROP_GPU_ATS_SUPPORTED 124 // default 125 { 126 pThis->setProperty(pThis, PDB_PROP_GPU_ATS_SUPPORTED, ((NvBool)(0 != 0))); 127 } 128 129 // NVOC Property Hal field -- PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE 130 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 131 { 132 pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 == 0))); 133 } 134 // default 135 else 136 { 137 pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 != 0))); 138 } 139 140 // NVOC Property Hal field -- PDB_PROP_GPU_ZERO_FB 141 // default 142 { 143 pThis->setProperty(pThis, PDB_PROP_GPU_ZERO_FB, ((NvBool)(0 != 0))); 144 } 145 146 // NVOC Property Hal field -- PDB_PROP_GPU_BAR1_BAR2_DISABLED 147 // default 148 { 149 pThis->setProperty(pThis, PDB_PROP_GPU_BAR1_BAR2_DISABLED, ((NvBool)(0 != 0))); 150 } 151 152 // NVOC Property Hal field -- PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE 153 // default 154 { 155 pThis->setProperty(pThis, PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE, ((NvBool)(0 != 0))); 156 } 157 158 // NVOC Property Hal field -- PDB_PROP_GPU_MIG_SUPPORTED 159 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 160 { 161 pThis->setProperty(pThis, PDB_PROP_GPU_MIG_SUPPORTED, ((NvBool)(0 == 0))); 162 } 163 // default 164 else 165 { 166 pThis->setProperty(pThis, PDB_PROP_GPU_MIG_SUPPORTED, ((NvBool)(0 != 0))); 167 } 168 169 // NVOC Property Hal field -- PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED 170 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 171 { 172 pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 == 0))); 173 } 174 // default 175 else 176 { 177 pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 != 0))); 178 } 179 180 // NVOC Property Hal field -- PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED 181 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 182 { 183 pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 == 0))); 184 } 185 // default 186 else 187 { 188 pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 != 0))); 189 } 190 191 // NVOC Property Hal field -- PDB_PROP_GPU_IS_COT_ENABLED 192 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 193 { 194 pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 == 0))); 195 } 196 // default 197 else 198 { 199 pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 != 0))); 200 } 201 202 // NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE 203 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 204 { 205 pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 == 0))); 206 } 207 // default 208 else 209 { 210 pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0))); 211 } 212 213 // NVOC Property Hal field -- PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED 214 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 215 { 216 pThis->setProperty(pThis, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED, ((NvBool)(0 == 0))); 217 } 218 219 // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK 220 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 221 { 222 pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 != 0))); 223 } 224 // default 225 else 226 { 227 pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0))); 228 } 229 pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0))); 230 231 // NVOC Property Hal field -- PDB_PROP_GPU_CC_FEATURE_CAPABLE 232 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 233 { 234 pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 == 0))); 235 } 236 // default 237 else 238 { 239 pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 != 0))); 240 } 241 242 // NVOC Property Hal field -- PDB_PROP_GPU_APM_FEATURE_CAPABLE 243 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 244 { 245 pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 == 0))); 246 } 247 // default 248 else 249 { 250 pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 != 0))); 251 } 252 253 // NVOC Property Hal field -- PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX 254 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 255 { 256 pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 == 0))); 257 } 258 // default 259 else 260 { 261 pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 != 0))); 262 } 263 264 // NVOC Property Hal field -- PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF 265 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 266 { 267 pThis->setProperty(pThis, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF, ((NvBool)(0 == 0))); 268 } 269 270 // NVOC Property Hal field -- PDB_PROP_GPU_IS_SOC_SDM 271 // default 272 { 273 pThis->setProperty(pThis, PDB_PROP_GPU_IS_SOC_SDM, ((NvBool)(0 != 0))); 274 } 275 276 pThis->boardId = ~0; 277 278 pThis->deviceInstance = 32; 279 280 // Hal field -- isVirtual 281 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ 282 { 283 pThis->isVirtual = ((NvBool)(0 != 0)); 284 } 285 286 // Hal field -- isGspClient 287 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ 288 { 289 pThis->isGspClient = ((NvBool)(0 == 0)); 290 } 291 292 pThis->bIsDebugModeEnabled = ((NvBool)(0 != 0)); 293 294 pThis->numOfMclkLockRequests = 0U; 295 296 pThis->bUseRegisterAccessMap = !(0); 297 298 pThis->boardInfo = ((void *)0); 299 300 // Hal field -- bUnifiedMemorySpaceEnabled 301 // default 302 { 303 pThis->bUnifiedMemorySpaceEnabled = ((NvBool)(0 != 0)); 304 } 305 306 // Hal field -- bWarBug200577889SriovHeavyEnabled 307 pThis->bWarBug200577889SriovHeavyEnabled = ((NvBool)(0 != 0)); 308 309 // Hal field -- bNonPowerOf2ChannelCountSupported 310 pThis->bNonPowerOf2ChannelCountSupported = ((NvBool)(0 != 0)); 311 312 // Hal field -- bNeed4kPageIsolation 313 // default 314 { 315 pThis->bNeed4kPageIsolation = ((NvBool)(0 != 0)); 316 } 317 318 // Hal field -- bInstLoc47bitPaWar 319 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 320 { 321 pThis->bInstLoc47bitPaWar = ((NvBool)(0 == 0)); 322 } 323 324 // Hal field -- bIsBarPteInSysmemSupported 325 // default 326 { 327 pThis->bIsBarPteInSysmemSupported = ((NvBool)(0 != 0)); 328 } 329 330 // Hal field -- bClientRmAllocatedCtxBuffer 331 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 332 { 333 pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 == 0)); 334 } 335 // default 336 else 337 { 338 pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 != 0)); 339 } 340 341 pThis->bIterativeMmuWalker = ((NvBool)(0 == 0)); 342 343 // Hal field -- bVidmemPreservationBrokenBug3172217 344 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 345 { 346 pThis->bVidmemPreservationBrokenBug3172217 = ((NvBool)(0 == 0)); 347 } 348 // default 349 else 350 { 351 pThis->bVidmemPreservationBrokenBug3172217 = ((NvBool)(0 != 0)); 352 } 353 354 // Hal field -- bInstanceMemoryAlwaysCached 355 // default 356 { 357 pThis->bInstanceMemoryAlwaysCached = ((NvBool)(0 != 0)); 358 } 359 360 pThis->bIsGeforce = ((NvBool)(0 == 0)); 361 362 // Hal field -- bComputePolicyTimesliceSupported 363 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 364 { 365 pThis->bComputePolicyTimesliceSupported = ((NvBool)(0 == 0)); 366 } 367 368 // Hal field -- bSriovCapable 369 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 370 { 371 pThis->bSriovCapable = ((NvBool)(0 == 0)); 372 } 373 374 // Hal field -- bRecheckSliSupportAtResume 375 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 376 { 377 pThis->bRecheckSliSupportAtResume = ((NvBool)(0 == 0)); 378 } 379 380 // Hal field -- bGpuNvEncAv1Supported 381 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ 382 { 383 pThis->bGpuNvEncAv1Supported = ((NvBool)(0 == 0)); 384 } 385 // default 386 else 387 { 388 pThis->bGpuNvEncAv1Supported = ((NvBool)(0 != 0)); 389 } 390 391 pThis->bIsGspOwnedFaultBuffersEnabled = ((NvBool)(0 != 0)); 392 } 393 394 NV_STATUS __nvoc_ctor_Object(Object* ); 395 NV_STATUS __nvoc_ctor_RmHalspecOwner(RmHalspecOwner* ); 396 NV_STATUS __nvoc_ctor_OBJTRACEABLE(OBJTRACEABLE* ); 397 NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU *pThis, NvU32 arg_gpuInstance) { 398 NV_STATUS status = NV_OK; 399 status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); 400 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_Object; 401 status = __nvoc_ctor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner); 402 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_RmHalspecOwner; 403 status = __nvoc_ctor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); 404 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_OBJTRACEABLE; 405 __nvoc_init_dataField_OBJGPU(pThis); 406 407 status = __nvoc_gpuConstruct(pThis, arg_gpuInstance); 408 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail__init; 409 goto __nvoc_ctor_OBJGPU_exit; // Success 410 411 __nvoc_ctor_OBJGPU_fail__init: 412 __nvoc_dtor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); 413 __nvoc_ctor_OBJGPU_fail_OBJTRACEABLE: 414 __nvoc_dtor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner); 415 __nvoc_ctor_OBJGPU_fail_RmHalspecOwner: 416 __nvoc_dtor_Object(&pThis->__nvoc_base_Object); 417 __nvoc_ctor_OBJGPU_fail_Object: 418 __nvoc_ctor_OBJGPU_exit: 419 420 return status; 421 } 422 423 static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { 424 ChipHal *chipHal = &staticCast(pThis, RmHalspecOwner)->chipHal; 425 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 426 RmVariantHal *rmVariantHal = &staticCast(pThis, RmHalspecOwner)->rmVariantHal; 427 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 428 PORT_UNREFERENCED_VARIABLE(pThis); 429 PORT_UNREFERENCED_VARIABLE(chipHal); 430 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 431 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 432 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 433 434 // Hal function -- gpuConstructDeviceInfoTable 435 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 436 { 437 pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; 438 } 439 // default 440 else 441 { 442 pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; 443 } 444 445 // Hal function -- gpuWriteBusConfigReg 446 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 447 { 448 pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GH100; 449 } 450 else 451 { 452 pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107; 453 } 454 455 // Hal function -- gpuReadBusConfigReg 456 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 457 { 458 pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100; 459 } 460 else 461 { 462 pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107; 463 } 464 465 // Hal function -- gpuReadBusConfigRegEx 466 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 467 { 468 pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_5baef9; 469 } 470 else 471 { 472 pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107; 473 } 474 475 // Hal function -- gpuReadFunctionConfigReg 476 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 477 { 478 pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9; 479 } 480 else 481 { 482 pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107; 483 } 484 485 // Hal function -- gpuWriteFunctionConfigReg 486 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 487 { 488 pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9; 489 } 490 else 491 { 492 pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107; 493 } 494 495 // Hal function -- gpuWriteFunctionConfigRegEx 496 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 497 { 498 pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9; 499 } 500 else 501 { 502 pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; 503 } 504 505 // Hal function -- gpuReadVgpuConfigReg 506 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 507 { 508 pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_GH100; 509 } 510 // default 511 else 512 { 513 pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_46f6a7; 514 } 515 516 // Hal function -- gpuGetIdInfo 517 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 518 { 519 pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100; 520 } 521 else 522 { 523 pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; 524 } 525 526 // Hal function -- gpuHandleSanityCheckRegReadError 527 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 528 { 529 pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; 530 } 531 else 532 { 533 pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; 534 } 535 536 // Hal function -- gpuHandleSecFault 537 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 538 { 539 pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_GH100; 540 } 541 // default 542 else 543 { 544 pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_b3696a; 545 } 546 547 // Hal function -- gpuGetChildrenPresent 548 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ 549 { 550 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU104; 551 } 552 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000080UL) )) /* ChipHal: TU106 */ 553 { 554 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU106; 555 } 556 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 557 { 558 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA100; 559 } 560 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 561 { 562 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100; 563 } 564 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */ 565 { 566 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU102; 567 } 568 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ 569 { 570 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA102; 571 } 572 else 573 { 574 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_AD102; 575 } 576 577 // Hal function -- gpuGetClassDescriptorList 578 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ 579 { 580 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU104; 581 } 582 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000080UL) )) /* ChipHal: TU106 */ 583 { 584 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU106; 585 } 586 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000200UL) )) /* ChipHal: TU117 */ 587 { 588 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU117; 589 } 590 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 591 { 592 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA100; 593 } 594 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 595 { 596 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100; 597 } 598 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */ 599 { 600 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU102; 601 } 602 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ 603 { 604 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA102; 605 } 606 else 607 { 608 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_AD102; 609 } 610 611 // Hal function -- gpuGetPhysAddrWidth 612 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 613 { 614 pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100; 615 } 616 else 617 { 618 pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; 619 } 620 621 // Hal function -- gpuFuseSupportsDisplay 622 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 623 { 624 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_491d52; 625 } 626 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 627 { 628 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; 629 } 630 else 631 { 632 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; 633 } 634 635 // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 636 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 637 { 638 pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100; 639 } 640 // default 641 else 642 { 643 pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; 644 } 645 646 // Hal function -- gpuReadDeviceId 647 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 648 { 649 pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; 650 } 651 else 652 { 653 pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GM107; 654 } 655 656 // Hal function -- gpuGetFlaVasSize 657 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 658 { 659 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GH100; 660 } 661 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 662 { 663 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_474d46; 664 } 665 else 666 { 667 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; 668 } 669 670 // Hal function -- gpuDetermineSelfHostedMode 671 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 672 { 673 pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_KERNEL_GH100; 674 } 675 // default 676 else 677 { 678 pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_b3696a; 679 } 680 681 // Hal function -- gpuDetermineMIGSupport 682 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 683 { 684 pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_GH100; 685 } 686 // default 687 else 688 { 689 pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a; 690 } 691 692 // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning 693 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 694 { 695 pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_GH100; 696 } 697 // default 698 else 699 { 700 pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_491d52; 701 } 702 703 // Hal function -- gpuIsSliCapableWithoutDisplay 704 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 705 { 706 pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_cbe027; 707 } 708 // default 709 else 710 { 711 pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_491d52; 712 } 713 714 // Hal function -- gpuIsCCEnabledInHw 715 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 716 { 717 pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GH100; 718 } 719 // default 720 else 721 { 722 pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52; 723 } 724 725 // Hal function -- gpuIsDevModeEnabledInHw 726 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 727 { 728 pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_GH100; 729 } 730 // default 731 else 732 { 733 pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_491d52; 734 } 735 736 // Hal function -- gpuIsCtxBufAllocInPmaSupported 737 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 738 { 739 pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_GA100; 740 } 741 // default 742 else 743 { 744 pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_491d52; 745 } 746 } 747 748 void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { 749 __nvoc_init_funcTable_OBJGPU_1(pThis); 750 } 751 752 void __nvoc_init_Object(Object*); 753 void __nvoc_init_RmHalspecOwner(RmHalspecOwner*, NvU32, NvU32, NvU32, RM_RUNTIME_VARIANT, TEGRA_CHIP_TYPE, NvU32); 754 void __nvoc_init_OBJTRACEABLE(OBJTRACEABLE*); 755 void __nvoc_init_OBJGPU(OBJGPU *pThis, 756 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, 757 RM_RUNTIME_VARIANT RmVariantHal_rmVariant, 758 TEGRA_CHIP_TYPE TegraChipHal_tegraType, 759 NvU32 DispIpHal_ipver) { 760 pThis->__nvoc_pbase_OBJGPU = pThis; 761 pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; 762 pThis->__nvoc_pbase_RmHalspecOwner = &pThis->__nvoc_base_RmHalspecOwner; 763 pThis->__nvoc_pbase_OBJTRACEABLE = &pThis->__nvoc_base_OBJTRACEABLE; 764 __nvoc_init_Object(&pThis->__nvoc_base_Object); 765 __nvoc_init_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver); 766 __nvoc_init_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); 767 __nvoc_init_funcTable_OBJGPU(pThis); 768 } 769 770 NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags, 771 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, 772 RM_RUNTIME_VARIANT RmVariantHal_rmVariant, 773 TEGRA_CHIP_TYPE TegraChipHal_tegraType, 774 NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance) { 775 NV_STATUS status; 776 Object *pParentObj; 777 OBJGPU *pThis; 778 779 status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPU), (void**)&pThis, (void**)ppThis); 780 if (status != NV_OK) 781 return status; 782 783 portMemSet(pThis, 0, sizeof(OBJGPU)); 784 785 __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPU); 786 787 pThis->__nvoc_base_Object.createFlags = createFlags; 788 789 if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) 790 { 791 pParentObj = dynamicCast(pParent, Object); 792 objAddChild(pParentObj, &pThis->__nvoc_base_Object); 793 } 794 else 795 { 796 pThis->__nvoc_base_Object.pParent = NULL; 797 } 798 799 __nvoc_init_OBJGPU(pThis, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver); 800 status = __nvoc_ctor_OBJGPU(pThis, arg_gpuInstance); 801 if (status != NV_OK) goto __nvoc_objCreate_OBJGPU_cleanup; 802 803 *ppThis = pThis; 804 805 return NV_OK; 806 807 __nvoc_objCreate_OBJGPU_cleanup: 808 // do not call destructors here since the constructor already called them 809 if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) 810 portMemSet(pThis, 0, sizeof(OBJGPU)); 811 else 812 portMemFree(pThis); 813 814 // coverity[leaked_storage:FALSE] 815 return status; 816 } 817 818 NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { 819 NV_STATUS status; 820 NvU32 ChipHal_arch = va_arg(args, NvU32); 821 NvU32 ChipHal_impl = va_arg(args, NvU32); 822 NvU32 ChipHal_hidrev = va_arg(args, NvU32); 823 RM_RUNTIME_VARIANT RmVariantHal_rmVariant = va_arg(args, RM_RUNTIME_VARIANT); 824 TEGRA_CHIP_TYPE TegraChipHal_tegraType = va_arg(args, TEGRA_CHIP_TYPE); 825 NvU32 DispIpHal_ipver = va_arg(args, NvU32); 826 NvU32 arg_gpuInstance = va_arg(args, NvU32); 827 828 status = __nvoc_objCreate_OBJGPU(ppThis, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance); 829 830 return status; 831 } 832 833