1 #define NVOC_GPU_H_PRIVATE_ACCESS_ALLOWED 2 #include "nvoc/runtime.h" 3 #include "nvoc/rtti.h" 4 #include "nvtypes.h" 5 #include "nvport/nvport.h" 6 #include "nvport/inline/util_valist.h" 7 #include "utils/nvassert.h" 8 #include "g_gpu_nvoc.h" 9 10 #ifdef DEBUG 11 char __nvoc_class_id_uniqueness_check_0x7ef3cb = 1; 12 #endif 13 14 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; 15 16 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; 17 18 extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmHalspecOwner; 19 20 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTRACEABLE; 21 22 void __nvoc_init_OBJGPU(OBJGPU*, 23 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, 24 RM_RUNTIME_VARIANT RmVariantHal_rmVariant, 25 TEGRA_CHIP_TYPE TegraChipHal_tegraType, 26 NvU32 DispIpHal_ipver); 27 void __nvoc_init_funcTable_OBJGPU(OBJGPU*); 28 NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU*, NvU32 arg_gpuInstance); 29 void __nvoc_init_dataField_OBJGPU(OBJGPU*); 30 void __nvoc_dtor_OBJGPU(OBJGPU*); 31 extern const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGPU; 32 33 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_OBJGPU = { 34 /*pClassDef=*/ &__nvoc_class_def_OBJGPU, 35 /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_OBJGPU, 36 /*offset=*/ 0, 37 }; 38 39 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_Object = { 40 /*pClassDef=*/ &__nvoc_class_def_Object, 41 /*dtor=*/ &__nvoc_destructFromBase, 42 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_Object), 43 }; 44 45 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_RmHalspecOwner = { 46 /*pClassDef=*/ &__nvoc_class_def_RmHalspecOwner, 47 /*dtor=*/ &__nvoc_destructFromBase, 48 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_RmHalspecOwner), 49 }; 50 51 static const struct NVOC_RTTI __nvoc_rtti_OBJGPU_OBJTRACEABLE = { 52 /*pClassDef=*/ &__nvoc_class_def_OBJTRACEABLE, 53 /*dtor=*/ &__nvoc_destructFromBase, 54 /*offset=*/ NV_OFFSETOF(OBJGPU, __nvoc_base_OBJTRACEABLE), 55 }; 56 57 static const struct NVOC_CASTINFO __nvoc_castinfo_OBJGPU = { 58 /*numRelatives=*/ 4, 59 /*relatives=*/ { 60 &__nvoc_rtti_OBJGPU_OBJGPU, 61 &__nvoc_rtti_OBJGPU_OBJTRACEABLE, 62 &__nvoc_rtti_OBJGPU_RmHalspecOwner, 63 &__nvoc_rtti_OBJGPU_Object, 64 }, 65 }; 66 67 const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU = 68 { 69 /*classInfo=*/ { 70 /*size=*/ sizeof(OBJGPU), 71 /*classId=*/ classId(OBJGPU), 72 /*providerId=*/ &__nvoc_rtti_provider, 73 #if NV_PRINTF_STRINGS_ALLOWED 74 /*name=*/ "OBJGPU", 75 #endif 76 }, 77 /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_OBJGPU, 78 /*pCastInfo=*/ &__nvoc_castinfo_OBJGPU, 79 /*pExportInfo=*/ &__nvoc_export_info_OBJGPU 80 }; 81 82 const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGPU = 83 { 84 /*numEntries=*/ 0, 85 /*pExportEntries=*/ 0 86 }; 87 88 void __nvoc_dtor_Object(Object*); 89 void __nvoc_dtor_RmHalspecOwner(RmHalspecOwner*); 90 void __nvoc_dtor_OBJTRACEABLE(OBJTRACEABLE*); 91 void __nvoc_dtor_OBJGPU(OBJGPU *pThis) { 92 __nvoc_gpuDestruct(pThis); 93 __nvoc_dtor_Object(&pThis->__nvoc_base_Object); 94 __nvoc_dtor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner); 95 __nvoc_dtor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); 96 PORT_UNREFERENCED_VARIABLE(pThis); 97 } 98 99 void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { 100 ChipHal *chipHal = &staticCast(pThis, RmHalspecOwner)->chipHal; 101 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 102 RmVariantHal *rmVariantHal = &staticCast(pThis, RmHalspecOwner)->rmVariantHal; 103 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 104 PORT_UNREFERENCED_VARIABLE(pThis); 105 PORT_UNREFERENCED_VARIABLE(chipHal); 106 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 107 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 108 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 109 pThis->setProperty(pThis, PDB_PROP_GPU_IS_CONNECTED, ((NvBool)(0 == 0))); 110 111 // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY 112 // default 113 { 114 pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY, ((NvBool)(0 != 0))); 115 } 116 117 // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_IGPU 118 // default 119 { 120 pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_IGPU, ((NvBool)(0 != 0))); 121 } 122 123 // NVOC Property Hal field -- PDB_PROP_GPU_ATS_SUPPORTED 124 // default 125 { 126 pThis->setProperty(pThis, PDB_PROP_GPU_ATS_SUPPORTED, ((NvBool)(0 != 0))); 127 } 128 129 // NVOC Property Hal field -- PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE 130 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 131 { 132 pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 == 0))); 133 } 134 // default 135 else 136 { 137 pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 != 0))); 138 } 139 140 // NVOC Property Hal field -- PDB_PROP_GPU_ZERO_FB 141 // default 142 { 143 pThis->setProperty(pThis, PDB_PROP_GPU_ZERO_FB, ((NvBool)(0 != 0))); 144 } 145 146 // NVOC Property Hal field -- PDB_PROP_GPU_BAR1_BAR2_DISABLED 147 // default 148 { 149 pThis->setProperty(pThis, PDB_PROP_GPU_BAR1_BAR2_DISABLED, ((NvBool)(0 != 0))); 150 } 151 152 // NVOC Property Hal field -- PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE 153 // default 154 { 155 pThis->setProperty(pThis, PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE, ((NvBool)(0 != 0))); 156 } 157 158 // NVOC Property Hal field -- PDB_PROP_GPU_MIG_SUPPORTED 159 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 160 { 161 pThis->setProperty(pThis, PDB_PROP_GPU_MIG_SUPPORTED, ((NvBool)(0 == 0))); 162 } 163 // default 164 else 165 { 166 pThis->setProperty(pThis, PDB_PROP_GPU_MIG_SUPPORTED, ((NvBool)(0 != 0))); 167 } 168 169 // NVOC Property Hal field -- PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED 170 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 171 { 172 pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 == 0))); 173 } 174 // default 175 else 176 { 177 pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 != 0))); 178 } 179 180 // NVOC Property Hal field -- PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED 181 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 182 { 183 pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 == 0))); 184 } 185 // default 186 else 187 { 188 pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 != 0))); 189 } 190 191 // NVOC Property Hal field -- PDB_PROP_GPU_IS_COT_ENABLED 192 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 193 { 194 pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 == 0))); 195 } 196 // default 197 else 198 { 199 pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 != 0))); 200 } 201 202 // NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE 203 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 204 { 205 pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 == 0))); 206 } 207 // default 208 else 209 { 210 pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0))); 211 } 212 213 // NVOC Property Hal field -- PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED 214 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 215 { 216 pThis->setProperty(pThis, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED, ((NvBool)(0 == 0))); 217 } 218 219 // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK 220 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 221 { 222 pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 != 0))); 223 } 224 // default 225 else 226 { 227 pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0))); 228 } 229 pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0))); 230 231 // NVOC Property Hal field -- PDB_PROP_GPU_CC_FEATURE_CAPABLE 232 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 233 { 234 pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 == 0))); 235 } 236 // default 237 else 238 { 239 pThis->setProperty(pThis, PDB_PROP_GPU_CC_FEATURE_CAPABLE, ((NvBool)(0 != 0))); 240 } 241 242 // NVOC Property Hal field -- PDB_PROP_GPU_APM_FEATURE_CAPABLE 243 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 244 { 245 pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 == 0))); 246 } 247 // default 248 else 249 { 250 pThis->setProperty(pThis, PDB_PROP_GPU_APM_FEATURE_CAPABLE, ((NvBool)(0 != 0))); 251 } 252 253 // NVOC Property Hal field -- PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX 254 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 255 { 256 pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 == 0))); 257 } 258 // default 259 else 260 { 261 pThis->setProperty(pThis, PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX, ((NvBool)(0 != 0))); 262 } 263 264 // NVOC Property Hal field -- PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF 265 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 266 { 267 pThis->setProperty(pThis, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF, ((NvBool)(0 == 0))); 268 } 269 270 // NVOC Property Hal field -- PDB_PROP_GPU_IS_SOC_SDM 271 // default 272 { 273 pThis->setProperty(pThis, PDB_PROP_GPU_IS_SOC_SDM, ((NvBool)(0 != 0))); 274 } 275 276 pThis->boardId = ~0; 277 278 pThis->deviceInstance = 32; 279 280 // Hal field -- isVirtual 281 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ 282 { 283 pThis->isVirtual = ((NvBool)(0 != 0)); 284 } 285 286 // Hal field -- isGspClient 287 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ 288 { 289 pThis->isGspClient = ((NvBool)(0 == 0)); 290 } 291 292 pThis->bIsDebugModeEnabled = ((NvBool)(0 != 0)); 293 294 pThis->numOfMclkLockRequests = 0U; 295 296 pThis->bUseRegisterAccessMap = !(0); 297 298 pThis->boardInfo = ((void *)0); 299 300 // Hal field -- bUnifiedMemorySpaceEnabled 301 // default 302 { 303 pThis->bUnifiedMemorySpaceEnabled = ((NvBool)(0 != 0)); 304 } 305 306 // Hal field -- bWarBug200577889SriovHeavyEnabled 307 pThis->bWarBug200577889SriovHeavyEnabled = ((NvBool)(0 != 0)); 308 309 // Hal field -- bNonPowerOf2ChannelCountSupported 310 pThis->bNonPowerOf2ChannelCountSupported = ((NvBool)(0 != 0)); 311 312 // Hal field -- bNeed4kPageIsolation 313 // default 314 { 315 pThis->bNeed4kPageIsolation = ((NvBool)(0 != 0)); 316 } 317 318 // Hal field -- bInstLoc47bitPaWar 319 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 320 { 321 pThis->bInstLoc47bitPaWar = ((NvBool)(0 == 0)); 322 } 323 324 // Hal field -- bIsBarPteInSysmemSupported 325 // default 326 { 327 pThis->bIsBarPteInSysmemSupported = ((NvBool)(0 != 0)); 328 } 329 330 // Hal field -- bClientRmAllocatedCtxBuffer 331 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 332 { 333 pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 == 0)); 334 } 335 // default 336 else 337 { 338 pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 != 0)); 339 } 340 341 pThis->bIterativeMmuWalker = ((NvBool)(0 == 0)); 342 343 // Hal field -- bVidmemPreservationBrokenBug3172217 344 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 345 { 346 pThis->bVidmemPreservationBrokenBug3172217 = ((NvBool)(0 == 0)); 347 } 348 // default 349 else 350 { 351 pThis->bVidmemPreservationBrokenBug3172217 = ((NvBool)(0 != 0)); 352 } 353 354 // Hal field -- bInstanceMemoryAlwaysCached 355 // default 356 { 357 pThis->bInstanceMemoryAlwaysCached = ((NvBool)(0 != 0)); 358 } 359 360 pThis->bIsGeforce = ((NvBool)(0 == 0)); 361 362 // Hal field -- bComputePolicyTimesliceSupported 363 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 364 { 365 pThis->bComputePolicyTimesliceSupported = ((NvBool)(0 == 0)); 366 } 367 368 // Hal field -- bSriovCapable 369 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 370 { 371 pThis->bSriovCapable = ((NvBool)(0 == 0)); 372 } 373 374 // Hal field -- bRecheckSliSupportAtResume 375 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 376 { 377 pThis->bRecheckSliSupportAtResume = ((NvBool)(0 == 0)); 378 } 379 380 // Hal field -- bGpuNvEncAv1Supported 381 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ 382 { 383 pThis->bGpuNvEncAv1Supported = ((NvBool)(0 == 0)); 384 } 385 // default 386 else 387 { 388 pThis->bGpuNvEncAv1Supported = ((NvBool)(0 != 0)); 389 } 390 391 pThis->bIsGspOwnedFaultBuffersEnabled = ((NvBool)(0 != 0)); 392 393 // Hal field -- bVideoTraceLogSupported 394 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 395 { 396 pThis->bVideoTraceLogSupported = ((NvBool)(0 == 0)); 397 } 398 } 399 400 NV_STATUS __nvoc_ctor_Object(Object* ); 401 NV_STATUS __nvoc_ctor_RmHalspecOwner(RmHalspecOwner* ); 402 NV_STATUS __nvoc_ctor_OBJTRACEABLE(OBJTRACEABLE* ); 403 NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU *pThis, NvU32 arg_gpuInstance) { 404 NV_STATUS status = NV_OK; 405 status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); 406 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_Object; 407 status = __nvoc_ctor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner); 408 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_RmHalspecOwner; 409 status = __nvoc_ctor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); 410 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_OBJTRACEABLE; 411 __nvoc_init_dataField_OBJGPU(pThis); 412 413 status = __nvoc_gpuConstruct(pThis, arg_gpuInstance); 414 if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail__init; 415 goto __nvoc_ctor_OBJGPU_exit; // Success 416 417 __nvoc_ctor_OBJGPU_fail__init: 418 __nvoc_dtor_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); 419 __nvoc_ctor_OBJGPU_fail_OBJTRACEABLE: 420 __nvoc_dtor_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner); 421 __nvoc_ctor_OBJGPU_fail_RmHalspecOwner: 422 __nvoc_dtor_Object(&pThis->__nvoc_base_Object); 423 __nvoc_ctor_OBJGPU_fail_Object: 424 __nvoc_ctor_OBJGPU_exit: 425 426 return status; 427 } 428 429 static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { 430 ChipHal *chipHal = &staticCast(pThis, RmHalspecOwner)->chipHal; 431 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 432 RmVariantHal *rmVariantHal = &staticCast(pThis, RmHalspecOwner)->rmVariantHal; 433 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 434 PORT_UNREFERENCED_VARIABLE(pThis); 435 PORT_UNREFERENCED_VARIABLE(chipHal); 436 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 437 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 438 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 439 440 // Hal function -- gpuConstructDeviceInfoTable 441 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 442 { 443 pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; 444 } 445 // default 446 else 447 { 448 pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; 449 } 450 451 // Hal function -- gpuWriteBusConfigReg 452 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 453 { 454 pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GH100; 455 } 456 else 457 { 458 pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107; 459 } 460 461 // Hal function -- gpuReadBusConfigReg 462 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 463 { 464 pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100; 465 } 466 else 467 { 468 pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107; 469 } 470 471 // Hal function -- gpuReadBusConfigRegEx 472 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 473 { 474 pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_5baef9; 475 } 476 else 477 { 478 pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107; 479 } 480 481 // Hal function -- gpuReadFunctionConfigReg 482 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 483 { 484 pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9; 485 } 486 else 487 { 488 pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107; 489 } 490 491 // Hal function -- gpuWriteFunctionConfigReg 492 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 493 { 494 pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9; 495 } 496 else 497 { 498 pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107; 499 } 500 501 // Hal function -- gpuWriteFunctionConfigRegEx 502 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 503 { 504 pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9; 505 } 506 else 507 { 508 pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; 509 } 510 511 // Hal function -- gpuReadVgpuConfigReg 512 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 513 { 514 pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_GH100; 515 } 516 // default 517 else 518 { 519 pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_46f6a7; 520 } 521 522 // Hal function -- gpuGetIdInfo 523 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 524 { 525 pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100; 526 } 527 else 528 { 529 pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; 530 } 531 532 // Hal function -- gpuHandleSanityCheckRegReadError 533 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 534 { 535 pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; 536 } 537 else 538 { 539 pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; 540 } 541 542 // Hal function -- gpuHandleSecFault 543 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 544 { 545 pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_GH100; 546 } 547 // default 548 else 549 { 550 pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_b3696a; 551 } 552 553 // Hal function -- gpuGetChildrenPresent 554 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ 555 { 556 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU104; 557 } 558 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000080UL) )) /* ChipHal: TU106 */ 559 { 560 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU106; 561 } 562 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 563 { 564 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA100; 565 } 566 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 567 { 568 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100; 569 } 570 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */ 571 { 572 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU102; 573 } 574 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ 575 { 576 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA102; 577 } 578 else 579 { 580 pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_AD102; 581 } 582 583 // Hal function -- gpuGetClassDescriptorList 584 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ 585 { 586 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU104; 587 } 588 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000080UL) )) /* ChipHal: TU106 */ 589 { 590 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU106; 591 } 592 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000200UL) )) /* ChipHal: TU117 */ 593 { 594 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU117; 595 } 596 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 597 { 598 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA100; 599 } 600 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 601 { 602 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100; 603 } 604 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */ 605 { 606 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU102; 607 } 608 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ 609 { 610 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA102; 611 } 612 else 613 { 614 pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_AD102; 615 } 616 617 // Hal function -- gpuGetPhysAddrWidth 618 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 619 { 620 pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100; 621 } 622 else 623 { 624 pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; 625 } 626 627 // Hal function -- gpuFuseSupportsDisplay 628 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 629 { 630 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_491d52; 631 } 632 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 633 { 634 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; 635 } 636 else 637 { 638 pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; 639 } 640 641 // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 642 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 643 { 644 pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100; 645 } 646 // default 647 else 648 { 649 pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; 650 } 651 652 // Hal function -- gpuReadDeviceId 653 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 654 { 655 pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; 656 } 657 else 658 { 659 pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GM107; 660 } 661 662 // Hal function -- gpuGetFlaVasSize 663 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 664 { 665 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GH100; 666 } 667 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 668 { 669 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_474d46; 670 } 671 else 672 { 673 pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; 674 } 675 676 // Hal function -- gpuDetermineSelfHostedMode 677 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 678 { 679 pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_KERNEL_GH100; 680 } 681 // default 682 else 683 { 684 pThis->__gpuDetermineSelfHostedMode__ = &gpuDetermineSelfHostedMode_b3696a; 685 } 686 687 // Hal function -- gpuDetermineMIGSupport 688 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 689 { 690 pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_GH100; 691 } 692 // default 693 else 694 { 695 pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a; 696 } 697 698 // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning 699 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 700 { 701 pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_GH100; 702 } 703 // default 704 else 705 { 706 pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_491d52; 707 } 708 709 // Hal function -- gpuIsSliCapableWithoutDisplay 710 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 711 { 712 pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_cbe027; 713 } 714 // default 715 else 716 { 717 pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_491d52; 718 } 719 720 // Hal function -- gpuIsCCEnabledInHw 721 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 722 { 723 pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GH100; 724 } 725 // default 726 else 727 { 728 pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52; 729 } 730 731 // Hal function -- gpuIsDevModeEnabledInHw 732 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 733 { 734 pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_GH100; 735 } 736 // default 737 else 738 { 739 pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_491d52; 740 } 741 742 // Hal function -- gpuIsCtxBufAllocInPmaSupported 743 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 744 { 745 pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_GA100; 746 } 747 // default 748 else 749 { 750 pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_491d52; 751 } 752 } 753 754 void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { 755 __nvoc_init_funcTable_OBJGPU_1(pThis); 756 } 757 758 void __nvoc_init_Object(Object*); 759 void __nvoc_init_RmHalspecOwner(RmHalspecOwner*, NvU32, NvU32, NvU32, RM_RUNTIME_VARIANT, TEGRA_CHIP_TYPE, NvU32); 760 void __nvoc_init_OBJTRACEABLE(OBJTRACEABLE*); 761 void __nvoc_init_OBJGPU(OBJGPU *pThis, 762 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, 763 RM_RUNTIME_VARIANT RmVariantHal_rmVariant, 764 TEGRA_CHIP_TYPE TegraChipHal_tegraType, 765 NvU32 DispIpHal_ipver) { 766 pThis->__nvoc_pbase_OBJGPU = pThis; 767 pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; 768 pThis->__nvoc_pbase_RmHalspecOwner = &pThis->__nvoc_base_RmHalspecOwner; 769 pThis->__nvoc_pbase_OBJTRACEABLE = &pThis->__nvoc_base_OBJTRACEABLE; 770 __nvoc_init_Object(&pThis->__nvoc_base_Object); 771 __nvoc_init_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver); 772 __nvoc_init_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); 773 __nvoc_init_funcTable_OBJGPU(pThis); 774 } 775 776 NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags, 777 NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, 778 RM_RUNTIME_VARIANT RmVariantHal_rmVariant, 779 TEGRA_CHIP_TYPE TegraChipHal_tegraType, 780 NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance) { 781 NV_STATUS status; 782 Object *pParentObj; 783 OBJGPU *pThis; 784 785 status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPU), (void**)&pThis, (void**)ppThis); 786 if (status != NV_OK) 787 return status; 788 789 portMemSet(pThis, 0, sizeof(OBJGPU)); 790 791 __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPU); 792 793 pThis->__nvoc_base_Object.createFlags = createFlags; 794 795 if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) 796 { 797 pParentObj = dynamicCast(pParent, Object); 798 objAddChild(pParentObj, &pThis->__nvoc_base_Object); 799 } 800 else 801 { 802 pThis->__nvoc_base_Object.pParent = NULL; 803 } 804 805 __nvoc_init_OBJGPU(pThis, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver); 806 status = __nvoc_ctor_OBJGPU(pThis, arg_gpuInstance); 807 if (status != NV_OK) goto __nvoc_objCreate_OBJGPU_cleanup; 808 809 *ppThis = pThis; 810 811 return NV_OK; 812 813 __nvoc_objCreate_OBJGPU_cleanup: 814 // do not call destructors here since the constructor already called them 815 if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) 816 portMemSet(pThis, 0, sizeof(OBJGPU)); 817 else 818 portMemFree(pThis); 819 820 // coverity[leaked_storage:FALSE] 821 return status; 822 } 823 824 NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { 825 NV_STATUS status; 826 NvU32 ChipHal_arch = va_arg(args, NvU32); 827 NvU32 ChipHal_impl = va_arg(args, NvU32); 828 NvU32 ChipHal_hidrev = va_arg(args, NvU32); 829 RM_RUNTIME_VARIANT RmVariantHal_rmVariant = va_arg(args, RM_RUNTIME_VARIANT); 830 TEGRA_CHIP_TYPE TegraChipHal_tegraType = va_arg(args, TEGRA_CHIP_TYPE); 831 NvU32 DispIpHal_ipver = va_arg(args, NvU32); 832 NvU32 arg_gpuInstance = va_arg(args, NvU32); 833 834 status = __nvoc_objCreate_OBJGPU(ppThis, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance); 835 836 return status; 837 } 838 839