1 // This file is automatically generated by rmconfig - DO NOT EDIT! 2 // 3 // HAL stubs, generated by rmconfig. 4 // 5 // Profile: shipping-gpus-openrm 6 // Template: templates/gt_hal_stubs.h 7 // 8 // Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 9 // 10 11 #ifndef _G_RMCFG_HAL_STUBS_H_ 12 #define _G_RMCFG_HAL_STUBS_H_ 13 14 // pull in private headers for each engine 15 #include "g_rpc_private.h" 16 #include "g_rpcstructurecopy_private.h" 17 18 19 #include "g_hal.h" 20 21 // HACK: a global var unique to the ipVersions _UNASSIGNED routines to ensure this function 22 // is not aliased by link-time-optimizations with a _STUB fn that might actually 23 // be assigned to a hal method as that would break the <ENG>_HAL_VERIFY_INTERFACE 24 // test. 25 NV_STATUS iGrp_ipVersions_UNIQUIFIER; 26 27 // the "_UNASSIGNED" function for all IP_VERSIONS dynamic interfaces 28 NV_STATUS iGrp_ipVersions_UNASSIGNED(void) 29 { 30 NV_ASSERT_PRECOMP(0 && "iGrp_ipVersions_UNASSIGNED"); 31 return NV_ERR_NOT_SUPPORTED + 32 iGrp_ipVersions_UNIQUIFIER; // will be 0 33 } 34 35 // 36 // generated _STUB functions 37 // 38 39 // DISP:hal:IGRP_IP_VERSIONS_GET_INFO - DISP disabled 40 NV_STATUS disp_iGrp_ipVersions_getInfo_STUB( 41 IGRP_IP_VERSIONS_TABLE_INFO *pArg1 42 ) 43 { 44 return NV_ERR_NOT_SUPPORTED; 45 } 46 47 // DPU:hal:IGRP_IP_VERSIONS_GET_INFO - DPU disabled 48 NV_STATUS dpu_iGrp_ipVersions_getInfo_STUB( 49 IGRP_IP_VERSIONS_TABLE_INFO *pArg1 50 ) 51 { 52 return NV_ERR_NOT_SUPPORTED; 53 } 54 55 // GPIO:hal:GET_SWAP_READY_FUNC_FOR_PINSET - GPIO disabled 56 NvU32 gpioGetSwapReadyFuncForPinset_STUB( 57 NvU32 pinset 58 ) 59 { 60 NV_ASSERT_PRECOMP(0 && "gpioGetSwapReadyFuncForPinset_STUB() GPIO: HAL_INTERFACES: GET_SWAP_READY_FUNC_FOR_PINSET"); 61 return (NvU32) 0; 62 } 63 64 // GPIO:hal:GET_FEATURE_STATE_HAL - GPIO disabled 65 NV_STATUS gpioGetFeatureStateHal_STUB( 66 POBJGPIO pGpio, 67 NvU32 function, 68 NvU32 feature, 69 NvBool *bState 70 ) 71 { 72 return NV_ERR_NOT_SUPPORTED; 73 } 74 75 // GPIO:hal:SET_FEATURE_STATE_HAL - GPIO disabled 76 NV_STATUS gpioSetFeatureStateHal_STUB( 77 POBJGPIO pGpio, 78 NvU32 function, 79 NvU32 feature, 80 NvBool bState 81 ) 82 { 83 return NV_ERR_NOT_SUPPORTED; 84 } 85 86 // GPIO:hal:INTERRUPT_PENDING - GPIO disabled 87 NvBool gpioInterruptPending_STUB( 88 POBJGPIO pGpio 89 ) 90 { 91 return NV_FALSE; 92 } 93 94 // GPIO:hal:DISABLE_INTERRUPTS - GPIO disabled 95 void gpioDisableInterrupts_STUB( 96 POBJGPIO pGpio 97 ) 98 { 99 } 100 101 // GPIO:hal:CLEAR_INTERRUPTS - GPIO disabled 102 void gpioClearInterrupts_STUB( 103 POBJGPIO pGpio 104 ) 105 { 106 } 107 108 // GPIO:hal:READ_INTERRUPT_STATUS - GPIO disabled 109 void gpioReadInterruptStatus_STUB( 110 POBJGPIO pGpio, 111 NvU64 *intrStatus 112 ) 113 { 114 } 115 116 // GPIO:hal:SERVICE_EVENT - GPIO disabled 117 NV_STATUS gpioServiceEvent_STUB( 118 POBJGPIO pGpio, 119 NvU64 *intrStatus 120 ) 121 { 122 return NV_OK; 123 } 124 125 // GPIO:hal:GET_INTERRUPT_HAL - GPIO disabled 126 NvBool gpioGetInterruptHal_STUB( 127 POBJGPIO pGpio, 128 NvU32 gpioFunc, 129 NvU32 direction 130 ) 131 { 132 return NV_FALSE; 133 } 134 135 // GPIO:hal:SET_INTERRUPT_HAL - GPIO disabled 136 NV_STATUS gpioSetInterruptHal_STUB( 137 POBJGPIO pGpio, 138 NvU32 gpioFunc, 139 NvU32 direction, 140 NvU32 enable 141 ) 142 { 143 return NV_ERR_NOT_SUPPORTED; 144 } 145 146 // GPIO:hal:GET_INTERRUPT_ENABLE_HAL - GPIO disabled 147 NvBool gpioGetInterruptEnableHal_STUB( 148 POBJGPIO pGpio, 149 NvU32 gpioFunc, 150 NvU32 direction 151 ) 152 { 153 return NV_FALSE; 154 } 155 156 // GPIO:hal:INIT_HW - GPIO disabled 157 NV_STATUS gpioInitHw_STUB( 158 POBJGPIO pGpio 159 ) 160 { 161 return NV_ERR_NOT_SUPPORTED; 162 } 163 164 // GPIO:hal:DESTROY_HW - GPIO disabled 165 NV_STATUS gpioDestroyHw_STUB( 166 POBJGPIO pGpio 167 ) 168 { 169 return NV_ERR_NOT_SUPPORTED; 170 } 171 172 // GPIO:hal:UPDATE_AND_PROGRAM_LCD_GPIO_ENTRIES - GPIO disabled 173 void gpioUpdateAndProgramLcdGpioEntries_STUB( 174 POBJGPIO pGpio, 175 NvU32 displayId, 176 NvBool bWriteHw 177 ) 178 { 179 } 180 181 // GPIO:hal:GET_REGISTER_FOR_FUNCTION_HAL - GPIO disabled 182 void gpioGetRegisterForFunctionHal_STUB( 183 POBJGPIO pGpio, 184 NvU32 func, 185 NvU32 *reg, 186 NvU32 *oldValue, 187 NvU32 *value_1, 188 NvU32 *value_0 189 ) 190 { 191 } 192 193 // GPIO:hal:WRITE_HW_ENUM_HAL - GPIO disabled 194 NV_STATUS gpioWriteHwEnumHal_STUB( 195 POBJGPIO pGpio, 196 NvU32 function, 197 NvU8 outHwEnum 198 ) 199 { 200 return NV_ERR_NOT_SUPPORTED; 201 } 202 203 // GPIO:hal:GET_EXCEPTION_DATA - GPIO disabled 204 NV_STATUS gpioGetExceptionData_STUB( 205 POBJGPIO pGpio 206 ) 207 { 208 return NV_ERR_NOT_SUPPORTED; 209 } 210 211 // GPIO:hal:GET_REGISTER_AND_MASK_HAL - GPIO disabled 212 NV_STATUS gpioGetRegisterAndMaskHal_STUB( 213 POBJGPIO pGpio, 214 NvU32 Function, 215 NvU32 State, 216 NvU32 *Register, 217 NvU32 *Mask, 218 NvU32 *Value 219 ) 220 { 221 return NV_ERR_NOT_SUPPORTED; 222 } 223 224 // GPIO:hal:GET_TRIGGER_REGISTER_AND_MASK_HAL - GPIO disabled 225 NV_STATUS gpioGetTriggerRegisterAndMaskHal_STUB( 226 POBJGPIO pGpio, 227 NvU32 *pRegAddr, 228 NvU32 *pAndMask, 229 NvU32 *pOrMask, 230 NvBool bDone 231 ) 232 { 233 return NV_ERR_NOT_SUPPORTED; 234 } 235 236 // GPIO:hal:GET_PIN_COUNT - GPIO disabled 237 NvU32 gpioGetPinCount_STUB( 238 POBJGPIO pGpio 239 ) 240 { 241 return (NvU32) 0; 242 } 243 244 // GPIO:hal:DUMP_RC_ERROR_REGS - GPIO disabled 245 NV_STATUS gpioDumpRCErrorRegs_STUB( 246 POBJGPU pGpu, 247 POBJGPIO pGpio, 248 PRB_ENCODER *pArg3 249 ) 250 { 251 return NV_ERR_NOT_SUPPORTED; 252 } 253 254 // GPIO:hal:INSERT_FRAME_LOCK_HEADER_LOCK_PIN_ENTRY - GPIO disabled 255 NV_STATUS gpioInsertFrameLockHeaderLockPinEntry_STUB( 256 POBJGPIO pGpio, 257 NvU32 function, 258 NvBool bIsFrameLockHeaderLockPin 259 ) 260 { 261 return NV_OK; 262 } 263 264 // GPIO:hal:GET_FRAME_LOCK_HEADER_LOCK_PINS - GPIO disabled 265 NV_STATUS gpioGetFrameLockHeaderLockPins_STUB( 266 POBJGPIO pGpio, 267 NvU32 *pFrameLockPin, 268 NvU32 *pRasterLockPin, 269 NvU32 *pFlipLockPin 270 ) 271 { 272 return NV_ERR_NOT_SUPPORTED; 273 } 274 275 // GPIO:hal:PIN_WRITE_FUNCTION_STATUS - GPIO disabled 276 NV_STATUS gpioPinWriteFunctionStatus_STUB( 277 POBJGPIO pGpio, 278 NvU32 gpioFunc, 279 NvU32 pin, 280 NvBool bEnabled 281 ) 282 { 283 return NV_ERR_NOT_SUPPORTED; 284 } 285 286 // GPIO:hal:ACTIVATE_HW_FUNCTION_HAL - GPIO disabled 287 NV_STATUS gpioActivateHwFunctionHal_STUB( 288 POBJGPIO pGpio, 289 NvU32 gpioFunc, 290 NvU32 pin 291 ) 292 { 293 return NV_ERR_NOT_SUPPORTED; 294 } 295 296 // GPIO:hal:DEACTIVATE_HW_FUNCTION_HAL - GPIO disabled 297 NV_STATUS gpioDeactivateHwFunctionHal_STUB( 298 POBJGPIO pGpio, 299 NvU32 gpioFunc, 300 NvU32 pin 301 ) 302 { 303 return NV_ERR_NOT_SUPPORTED; 304 } 305 306 // GPIO:hal:INIT_PIN_FEATURE_FLAG - GPIO disabled 307 NV_STATUS gpioInitPinFeatureFlag_STUB( 308 POBJGPIO pGpio, 309 NvU32 gpioPin, 310 NvU8 outHwEnum, 311 NvU8 inHwEnum 312 ) 313 { 314 return NV_ERR_NOT_SUPPORTED; 315 } 316 317 // GPIO:hal:PROGRAM_PIN - GPIO disabled 318 NV_STATUS gpioProgramPin_STUB( 319 POBJGPIO pGpio, 320 NvU32 gpioPinDCB, 321 NvU32 halIndex, 322 NvBool bTrigger 323 ) 324 { 325 return NV_ERR_NOT_SUPPORTED; 326 } 327 328 // GPIO:hal:RM_PMU_SYNC_STATE_INIT_HAL - GPIO disabled 329 NV_STATUS gpioRmPmuSyncStateInitHal_STUB( 330 POBJGPIO pGpio 331 ) 332 { 333 return NV_OK; 334 } 335 336 // GPIO:hal:FUNC_TO_SOR_IDX_HAL - GPIO disabled 337 NvU32 gpioFuncToSorIdxHal_STUB( 338 POBJGPIO pGpio, 339 POBJGPU pGpu, 340 NvU32 gpioFunc 341 ) 342 { 343 return NV_U32_MAX; 344 } 345 346 // GPIO:hal:OVERRIDE_GPIO_WAR_FOR_BUG_1795624 - GPIO disabled 347 void gpioOverrideGpioWarForBug1795624_STUB( 348 POBJGPIO pGpio 349 ) 350 { 351 } 352 353 // GPIO:hal:SET_SWAPRDY_FOR_BUG_200374184 - GPIO disabled 354 NV_STATUS gpioSetSwaprdyForBug200374184_STUB( 355 POBJGPU pGpu, 356 NvU32 swaprdyOutPin, 357 NvBool bEnable 358 ) 359 { 360 return NV_OK; 361 } 362 363 // GPIO:hal:OUTPUT_TRIGGER_UPDATE_UC - GPIO disabled 364 NV_STATUS gpioOutputTriggerUpdateUC_STUB( 365 POBJGPU pGpu, 366 POBJGPIO pGpio 367 ) 368 { 369 return NV_OK; 370 } 371 372 // GPIO:hal:OVERRIDE_GPIO_WAR_FOR_BUG_2701109 - GPIO disabled 373 void gpioOverrideGpioWarForBug2701109_STUB( 374 POBJGPU pGpu, 375 POBJGPIO pGpio 376 ) 377 { 378 } 379 380 // GPIO:hal:INIT_SW - GPIO disabled 381 NV_STATUS gpioInitSw_STUB( 382 POBJGPIO pGpio 383 ) 384 { 385 return NV_OK; 386 } 387 388 // GPIO:hal:DESTROY_SW - GPIO disabled 389 void gpioDestroySw_STUB( 390 POBJGPIO pGpio 391 ) 392 { 393 } 394 395 // GPIO:hal:INIT_AND_GET_PIN_NUM - GPIO disabled 396 NvU32 gpioInitAndGetPinNum_STUB( 397 POBJGPIO pGpio, 398 NvU32 arg2, 399 NvU32 *pArg3 400 ) 401 { 402 return (NvU32) 0; 403 } 404 405 // GPIO:hal:OVERRIDE_GPIO_WAR_FOR_BUG_2561134 - GPIO disabled 406 void gpioOverrideGpioWarForBug2561134_STUB( 407 POBJGPU pGpu, 408 POBJGPIO pGpio 409 ) 410 { 411 } 412 413 // GPIO:hal:SET_PROPERTIES_LIST - GPIO disabled 414 void gpioSetPropertiesList_STUB( 415 POBJGPU pGpu, 416 POBJGPIO pGpio 417 ) 418 { 419 } 420 421 // GPIO:hal:READ_INPUT - GPIO disabled 422 NV_STATUS gpioReadInput_MISSING( 423 POBJGPIO pGpio, 424 NvU32 gpioPin, 425 NvU32 halIndex, 426 NvU32 *pValue 427 ) 428 { 429 return NV_ERR_NOT_SUPPORTED; 430 } 431 432 // GPIO:hal:PROGRAM_OUTPUT - GPIO disabled 433 void gpioProgramOutput_MISSING( 434 POBJGPIO pGpio, 435 NvU32 gpioPin, 436 NvU32 value, 437 NvU32 halIndex 438 ) 439 { 440 } 441 442 // GPIO:hal:READ_OUTPUT - GPIO disabled 443 NvBool gpioReadOutput_MISSING( 444 POBJGPIO pGpio, 445 NvU32 gpioPin 446 ) 447 { 448 return NV_FALSE; 449 } 450 451 // GPIO:hal:PROGRAM_DIRECTION - GPIO disabled 452 void gpioProgramDirection_MISSING( 453 POBJGPIO pGpio, 454 NvU32 gpioPin, 455 NvBool input, 456 NvU32 halIndex 457 ) 458 { 459 } 460 461 // GPIO:hal:READ_DIRECTION - GPIO disabled 462 NvBool gpioReadDirection_MISSING( 463 POBJGPIO pGpio, 464 NvU32 gpioPin, 465 NvU32 halIndex 466 ) 467 { 468 return NV_FALSE; 469 } 470 471 // GPIO:hal:INIT_DEFAULT_ENTRIES - GPIO disabled 472 void gpioInitDefaultEntries_MISSING( 473 POBJGPIO pGpio 474 ) 475 { 476 } 477 478 // GPIO:hal:SET_STATE_LIST_HAL - GPIO disabled 479 void gpioSetStateListHal_MISSING( 480 POBJGPIO pGpio, 481 PGPIO_FUNC_LIST_ITEM pList, 482 NvU32 count 483 ) 484 { 485 } 486 487 // GPIO:hal:IS_FEATURE_AVAILABLE_HAL - GPIO disabled 488 NvBool gpioIsFeatureAvailableHal_MISSING( 489 POBJGPIO pGpio, 490 NvU32 function, 491 NvU32 feature 492 ) 493 { 494 return NV_FALSE; 495 } 496 497 // GPIO:hal:GET_FUNC_PWM_SENSE - GPIO disabled 498 NvU32 gpioGetFuncPwmSense_MISSING( 499 POBJGPIO pGpio, 500 NvU32 func 501 ) 502 { 503 return (NvU32) 0; 504 } 505 506 // GPIO:hal:WRITE_PIN_HW_ENUM - GPIO disabled 507 NV_STATUS gpioWritePinHwEnum_MISSING( 508 POBJGPIO pGpio, 509 NvU32 gpioPin, 510 NvU8 outHwEnum 511 ) 512 { 513 return NV_ERR_NOT_SUPPORTED; 514 } 515 516 // GPIO:hal:OUTPUT_CNTL_CHECK_PROTECTION - GPIO disabled 517 NV_STATUS gpioOutputCntlCheckProtection_MISSING( 518 POBJGPU pGpu, 519 POBJGPIO pGpio, 520 NvU32 gpioPin, 521 NvBool *pbIsProtected 522 ) 523 { 524 return NV_ERR_NOT_SUPPORTED; 525 } 526 527 // GPIO:hal:INPUT_CNTL_CHECK_PROTECTION - GPIO disabled 528 NV_STATUS gpioInputCntlCheckProtection_MISSING( 529 POBJGPU pGpu, 530 POBJGPIO pGpio, 531 NvU32 inputHwEnum, 532 NvBool *pbIsProtected 533 ) 534 { 535 return NV_ERR_NOT_SUPPORTED; 536 } 537 538 // GPIO:hal:READ_INPUT - GPIO disabled 539 NV_STATUS gpioReadInput_FWCLIENT( 540 POBJGPIO pGpio, 541 NvU32 gpioPin, 542 NvU32 halIndex, 543 NvU32 *pValue 544 ) 545 { 546 return NV_OK; 547 } 548 549 // GPIO:hal:PROGRAM_OUTPUT - GPIO disabled 550 void gpioProgramOutput_FWCLIENT( 551 POBJGPIO pGpio, 552 NvU32 gpioPin, 553 NvU32 value, 554 NvU32 halIndex 555 ) 556 { 557 } 558 559 // GPIO:hal:READ_OUTPUT - GPIO disabled 560 NvBool gpioReadOutput_FWCLIENT( 561 POBJGPIO pGpio, 562 NvU32 gpioPin 563 ) 564 { 565 return NV_FALSE; 566 } 567 568 // GPIO:hal:PROGRAM_DIRECTION - GPIO disabled 569 void gpioProgramDirection_FWCLIENT( 570 POBJGPIO pGpio, 571 NvU32 gpioPin, 572 NvBool input, 573 NvU32 halIndex 574 ) 575 { 576 } 577 578 // GPIO:hal:READ_DIRECTION - GPIO disabled 579 NvBool gpioReadDirection_FWCLIENT( 580 POBJGPIO pGpio, 581 NvU32 gpioPin, 582 NvU32 halIndex 583 ) 584 { 585 return NV_FALSE; 586 } 587 588 // GPIO:hal:GET_INTERRUPT_HAL - GPIO disabled 589 NvBool gpioGetInterruptHal_FWCLIENT( 590 POBJGPIO pGpio, 591 NvU32 gpioFunc, 592 NvU32 direction 593 ) 594 { 595 return NV_FALSE; 596 } 597 598 // GPIO:hal:SET_INTERRUPT_HAL - GPIO disabled 599 NV_STATUS gpioSetInterruptHal_FWCLIENT( 600 POBJGPIO pGpio, 601 NvU32 gpioFunc, 602 NvU32 direction, 603 NvU32 enable 604 ) 605 { 606 return NV_OK; 607 } 608 609 // GPIO:hal:GET_EXCEPTION_DATA - GPIO disabled 610 NV_STATUS gpioGetExceptionData_FWCLIENT( 611 POBJGPIO pGpio 612 ) 613 { 614 return NV_OK; 615 } 616 617 // GPIO:hal:INIT_SW - GPIO disabled 618 NV_STATUS gpioInitSw_FWCLIENT( 619 POBJGPIO pGpio 620 ) 621 { 622 return NV_OK; 623 } 624 625 // GPIO:hal:DESTROY_SW - GPIO disabled 626 void gpioDestroySw_FWCLIENT( 627 POBJGPIO pGpio 628 ) 629 { 630 } 631 632 // GPIO:hal:INIT_AND_GET_PIN_NUM - GPIO disabled 633 NvU32 gpioInitAndGetPinNum_FWCLIENT( 634 POBJGPIO pGpio, 635 NvU32 arg2, 636 NvU32 *pArg3 637 ) 638 { 639 return (NvU32) 0; 640 } 641 642 // RPC:hal:CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 643 NV_STATUS rpcCtrlFifoSetupVfZombieSubctxPdb_STUB( 644 POBJGPU pGpu, 645 POBJRPC pRpc, 646 NvHandle arg3, 647 NvHandle arg4, 648 void *pArg5 649 ) 650 { 651 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 652 } 653 654 // RPC:hal:VGPU_PF_REG_READ32 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 655 NV_STATUS rpcVgpuPfRegRead32_STUB( 656 POBJGPU pGpu, 657 POBJRPC pRpc, 658 NvU64 arg3, 659 NvU32 *pArg4, 660 NvU32 arg5 661 ) 662 { 663 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 664 } 665 666 // RPC:hal:CTRL_BUS_UNSET_P2P_MAPPING - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 667 NV_STATUS rpcCtrlBusUnsetP2pMapping_STUB( 668 POBJGPU pGpu, 669 POBJRPC pRpc, 670 NvHandle arg3, 671 NvHandle arg4, 672 void *pArg5 673 ) 674 { 675 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 676 } 677 678 // RPC:hal:DUMP_PROTOBUF_COMPONENT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 679 NV_STATUS rpcDumpProtobufComponent_STUB( 680 POBJGPU pGpu, 681 POBJRPC pRpc, 682 PRB_ENCODER *pPrbEnc, 683 NVD_STATE *pNvDumpState, 684 NVDUMP_COMPONENT component 685 ) 686 { 687 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 688 } 689 690 // RPC:hal:ECC_NOTIFIER_WRITE_ACK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 691 NV_STATUS rpcEccNotifierWriteAck_STUB( 692 POBJGPU pGpu, 693 POBJRPC pRpc 694 ) 695 { 696 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 697 } 698 699 // RPC:hal:ALLOC_MEMORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 700 NV_STATUS rpcAllocMemory_STUB( 701 POBJGPU pGpu, 702 POBJRPC pRpc, 703 NvHandle arg3, 704 NvHandle arg4, 705 NvHandle arg5, 706 NvU32 arg6, 707 NvU32 arg7, 708 MEMORY_DESCRIPTOR *pArg8 709 ) 710 { 711 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 712 } 713 714 // RPC:hal:CTRL_DBG_READ_SINGLE_SM_ERROR_STATE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 715 NV_STATUS rpcCtrlDbgReadSingleSmErrorState_STUB( 716 POBJGPU pGpu, 717 POBJRPC pRpc, 718 NvHandle arg3, 719 NvHandle arg4, 720 void *pArg5 721 ) 722 { 723 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 724 } 725 726 // RPC:hal:DISABLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 727 NV_STATUS rpcDisableChannels_STUB( 728 POBJGPU pGpu, 729 POBJRPC pRpc, 730 NvU32 arg3 731 ) 732 { 733 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 734 } 735 736 // RPC:hal:GPU_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 737 NV_STATUS rpcGpuExecRegOps_STUB( 738 POBJGPU pGpu, 739 POBJRPC pRpc, 740 NvHandle arg3, 741 NvHandle arg4, 742 NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS *pArg5, 743 NV2080_CTRL_GPU_REG_OP *pArg6 744 ) 745 { 746 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 747 } 748 749 // RPC:hal:CTRL_GPU_PROMOTE_CTX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 750 NV_STATUS rpcCtrlGpuPromoteCtx_STUB( 751 POBJGPU pGpu, 752 POBJRPC pRpc, 753 NvHandle arg3, 754 NvHandle arg4, 755 void *pArg5 756 ) 757 { 758 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 759 } 760 761 // RPC:hal:CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 762 NV_STATUS rpcCtrlDbgSetNextStopTriggerType_STUB( 763 POBJGPU pGpu, 764 POBJRPC pRpc, 765 NvHandle arg3, 766 NvHandle arg4, 767 void *pArg5 768 ) 769 { 770 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 771 } 772 773 // RPC:hal:ALLOC_SHARE_DEVICE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 774 NV_STATUS rpcAllocShareDevice_STUB( 775 POBJGPU pGpu, 776 POBJRPC pRpc, 777 NvHandle arg3, 778 NvHandle arg4, 779 NvHandle arg5, 780 NvHandle arg6, 781 NvHandle arg7, 782 NvU32 arg8, 783 NvU32 arg9, 784 NvU64 arg10, 785 NvU32 arg11 786 ) 787 { 788 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 789 } 790 791 // RPC:hal:CTRL_PREEMPT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 792 NV_STATUS rpcCtrlPreempt_STUB( 793 POBJGPU pGpu, 794 POBJRPC pRpc, 795 NvHandle arg3, 796 NvHandle arg4, 797 void *pArg5 798 ) 799 { 800 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 801 } 802 803 // RPC:hal:CTRL_GPU_INITIALIZE_CTX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 804 NV_STATUS rpcCtrlGpuInitializeCtx_STUB( 805 POBJGPU pGpu, 806 POBJRPC pRpc, 807 NvHandle arg3, 808 NvHandle arg4, 809 void *pArg5 810 ) 811 { 812 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 813 } 814 815 // RPC:hal:CTRL_RESERVE_PM_AREA_SMPC - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 816 NV_STATUS rpcCtrlReservePmAreaSmpc_STUB( 817 POBJGPU pGpu, 818 POBJRPC pRpc, 819 NvHandle arg3, 820 NvHandle arg4, 821 void *pArg5 822 ) 823 { 824 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 825 } 826 827 // RPC:hal:CTRL_GPU_MIGRATABLE_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 828 NV_STATUS rpcCtrlGpuMigratableOps_STUB( 829 POBJGPU pGpu, 830 POBJRPC pRpc, 831 NvHandle arg3, 832 NvHandle arg4, 833 void *pArg5 834 ) 835 { 836 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 837 } 838 839 // RPC:hal:CTRL_DBG_SET_MODE_ERRBAR_DEBUG - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 840 NV_STATUS rpcCtrlDbgSetModeErrbarDebug_STUB( 841 POBJGPU pGpu, 842 POBJRPC pRpc, 843 NvHandle arg3, 844 NvHandle arg4, 845 void *pArg5 846 ) 847 { 848 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 849 } 850 851 // RPC:hal:CTRL_PMA_STREAM_UPDATE_GET_PUT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 852 NV_STATUS rpcCtrlPmaStreamUpdateGetPut_STUB( 853 POBJGPU pGpu, 854 POBJRPC pRpc, 855 NvHandle arg3, 856 NvHandle arg4, 857 void *pArg5 858 ) 859 { 860 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 861 } 862 863 // RPC:hal:CTRL_FABRIC_MEMORY_DESCRIBE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 864 NV_STATUS rpcCtrlFabricMemoryDescribe_STUB( 865 POBJGPU pGpu, 866 POBJRPC pRpc, 867 NvHandle arg3, 868 NvHandle arg4, 869 void *pArg5 870 ) 871 { 872 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 873 } 874 875 // RPC:hal:ALLOC_CHANNEL_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 876 NV_STATUS rpcAllocChannelDma_STUB( 877 POBJGPU pGpu, 878 POBJRPC pRpc, 879 NvHandle arg3, 880 NvHandle arg4, 881 NvHandle arg5, 882 NvU32 arg6, 883 NV_CHANNEL_ALLOC_PARAMS *pArg7, 884 NvU32 *pArg8 885 ) 886 { 887 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 888 } 889 890 // RPC:hal:CTRL_SET_ZBC_DEPTH_CLEAR - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 891 NV_STATUS rpcCtrlSetZbcDepthClear_STUB( 892 POBJGPU pGpu, 893 POBJRPC pRpc, 894 NvHandle arg3, 895 NvHandle arg4, 896 void *pArg5 897 ) 898 { 899 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 900 } 901 902 // RPC:hal:CTRL_RESET_ISOLATED_CHANNEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 903 NV_STATUS rpcCtrlResetIsolatedChannel_STUB( 904 POBJGPU pGpu, 905 POBJRPC pRpc, 906 NvHandle arg3, 907 NvHandle arg4, 908 void *pArg5 909 ) 910 { 911 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 912 } 913 914 // RPC:hal:CTRL_DMA_SET_DEFAULT_VASPACE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 915 NV_STATUS rpcCtrlDmaSetDefaultVaspace_STUB( 916 POBJGPU pGpu, 917 POBJRPC pRpc, 918 NvHandle arg3, 919 NvHandle arg4, 920 void *pArg5 921 ) 922 { 923 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 924 } 925 926 // RPC:hal:ALLOC_SUBDEVICE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 927 NV_STATUS rpcAllocSubdevice_STUB( 928 POBJGPU pGpu, 929 POBJRPC pRpc, 930 NvHandle arg3, 931 NvHandle arg4, 932 NvHandle arg5, 933 NvU32 arg6, 934 NvU32 arg7 935 ) 936 { 937 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 938 } 939 940 // RPC:hal:FREE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 941 NV_STATUS rpcFree_STUB( 942 POBJGPU pGpu, 943 POBJRPC pRpc, 944 NvHandle arg3, 945 NvHandle arg4, 946 NvHandle arg5 947 ) 948 { 949 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 950 } 951 952 // RPC:hal:DMA_CONTROL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 953 NV_STATUS rpcDmaControl_STUB( 954 POBJGPU pGpu, 955 POBJRPC pRpc, 956 NvHandle arg3, 957 NvHandle arg4, 958 NvU32 arg5, 959 void *pArg6, 960 NvU32 arg7 961 ) 962 { 963 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 964 } 965 966 // RPC:hal:CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 967 NV_STATUS rpcCtrlDbgClearSingleSmErrorState_STUB( 968 POBJGPU pGpu, 969 POBJRPC pRpc, 970 NvHandle arg3, 971 NvHandle arg4, 972 void *pArg5 973 ) 974 { 975 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 976 } 977 978 // RPC:hal:UNSET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 979 NV_STATUS rpcUnsetPageDirectory_STUB( 980 POBJGPU pGpu, 981 POBJRPC pRpc, 982 NvHandle arg3, 983 NvHandle arg4, 984 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pArg5 985 ) 986 { 987 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 988 } 989 990 // RPC:hal:GET_GSP_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 991 NV_STATUS rpcGetGspStaticInfo_STUB( 992 POBJGPU pGpu, 993 POBJRPC pRpc 994 ) 995 { 996 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 997 } 998 999 // RPC:hal:SAVE_HIBERNATION_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1000 NV_STATUS rpcSaveHibernationData_STUB( 1001 POBJGPU pGpu, 1002 POBJRPC pRpc 1003 ) 1004 { 1005 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1006 } 1007 1008 // RPC:hal:DUP_OBJECT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1009 NV_STATUS rpcDupObject_STUB( 1010 POBJGPU pGpu, 1011 POBJRPC pRpc, 1012 NvHandle arg3, 1013 NvHandle arg4, 1014 NvHandle arg5, 1015 NvHandle arg6, 1016 NvHandle arg7, 1017 NvU32 arg8 1018 ) 1019 { 1020 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1021 } 1022 1023 // RPC:hal:GSP_SET_SYSTEM_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1024 NV_STATUS rpcGspSetSystemInfo_STUB( 1025 POBJGPU pGpu, 1026 POBJRPC pRpc 1027 ) 1028 { 1029 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1030 } 1031 1032 // RPC:hal:CTRL_PM_AREA_PC_SAMPLER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1033 NV_STATUS rpcCtrlPmAreaPcSampler_STUB( 1034 POBJGPU pGpu, 1035 POBJRPC pRpc, 1036 NvHandle arg3, 1037 NvHandle arg4, 1038 NvU32 arg5, 1039 void *pArg6 1040 ) 1041 { 1042 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1043 } 1044 1045 // RPC:hal:CTRL_DBG_SET_EXCEPTION_MASK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1046 NV_STATUS rpcCtrlDbgSetExceptionMask_STUB( 1047 POBJGPU pGpu, 1048 POBJRPC pRpc, 1049 NvHandle arg3, 1050 NvHandle arg4, 1051 void *pArg5 1052 ) 1053 { 1054 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1055 } 1056 1057 // RPC:hal:CTRL_VASPACE_COPY_SERVER_RESERVED_PDES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1058 NV_STATUS rpcCtrlVaspaceCopyServerReservedPdes_STUB( 1059 POBJGPU pGpu, 1060 POBJRPC pRpc, 1061 NvHandle arg3, 1062 NvHandle arg4, 1063 void *pArg5 1064 ) 1065 { 1066 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1067 } 1068 1069 // RPC:hal:CTRL_GR_CTXSW_PREEMPTION_BIND - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1070 NV_STATUS rpcCtrlGrCtxswPreemptionBind_STUB( 1071 POBJGPU pGpu, 1072 POBJRPC pRpc, 1073 NvHandle arg3, 1074 NvHandle arg4, 1075 void *pArg5 1076 ) 1077 { 1078 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1079 } 1080 1081 // RPC:hal:CTRL_ALLOC_PMA_STREAM - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1082 NV_STATUS rpcCtrlAllocPmaStream_STUB( 1083 POBJGPU pGpu, 1084 POBJRPC pRpc, 1085 NvHandle arg3, 1086 NvHandle arg4, 1087 void *pArg5 1088 ) 1089 { 1090 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1091 } 1092 1093 // RPC:hal:CTRL_RESERVE_HWPM_LEGACY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1094 NV_STATUS rpcCtrlReserveHwpmLegacy_STUB( 1095 POBJGPU pGpu, 1096 POBJRPC pRpc, 1097 NvHandle arg3, 1098 NvHandle arg4, 1099 void *pArg5 1100 ) 1101 { 1102 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1103 } 1104 1105 // RPC:hal:CTRL_INTERNAL_QUIESCE_PMA_CHANNEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1106 NV_STATUS rpcCtrlInternalQuiescePmaChannel_STUB( 1107 POBJGPU pGpu, 1108 POBJRPC pRpc, 1109 NvHandle arg3, 1110 NvHandle arg4, 1111 void *pArg5 1112 ) 1113 { 1114 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1115 } 1116 1117 // RPC:hal:CTRL_PERF_RATED_TDP_GET_STATUS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1118 NV_STATUS rpcCtrlPerfRatedTdpGetStatus_STUB( 1119 POBJGPU pGpu, 1120 POBJRPC pRpc, 1121 NvHandle arg3, 1122 NvHandle arg4, 1123 void *pArg5 1124 ) 1125 { 1126 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1127 } 1128 1129 // RPC:hal:CTRL_BUS_SET_P2P_MAPPING - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1130 NV_STATUS rpcCtrlBusSetP2pMapping_STUB( 1131 POBJGPU pGpu, 1132 POBJRPC pRpc, 1133 NvHandle arg3, 1134 NvHandle arg4, 1135 void *pArg5 1136 ) 1137 { 1138 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1139 } 1140 1141 // RPC:hal:CTRL_GPU_GET_INFO_V2 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1142 NV_STATUS rpcCtrlGpuGetInfoV2_STUB( 1143 POBJGPU pGpu, 1144 POBJRPC pRpc, 1145 NvHandle arg3, 1146 NvHandle arg4, 1147 void *pArg5 1148 ) 1149 { 1150 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1151 } 1152 1153 // RPC:hal:CTRL_GET_HS_CREDITS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1154 NV_STATUS rpcCtrlGetHsCredits_STUB( 1155 POBJGPU pGpu, 1156 POBJRPC pRpc, 1157 NvHandle arg3, 1158 NvHandle arg4, 1159 void *pArg5 1160 ) 1161 { 1162 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1163 } 1164 1165 // RPC:hal:CTRL_GR_SET_CTXSW_PREEMPTION_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1166 NV_STATUS rpcCtrlGrSetCtxswPreemptionMode_STUB( 1167 POBJGPU pGpu, 1168 POBJRPC pRpc, 1169 NvHandle arg3, 1170 NvHandle arg4, 1171 void *pArg5 1172 ) 1173 { 1174 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1175 } 1176 1177 // RPC:hal:CTRL_B0CC_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1178 NV_STATUS rpcCtrlB0ccExecRegOps_STUB( 1179 POBJGPU pGpu, 1180 POBJRPC pRpc, 1181 NvHandle arg3, 1182 NvHandle arg4, 1183 void *pArg5 1184 ) 1185 { 1186 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1187 } 1188 1189 // RPC:hal:CTRL_GRMGR_GET_GR_FS_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1190 NV_STATUS rpcCtrlGrmgrGetGrFsInfo_STUB( 1191 POBJGPU pGpu, 1192 POBJRPC pRpc, 1193 NvHandle arg3, 1194 NvHandle arg4, 1195 void *pArg5 1196 ) 1197 { 1198 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1199 } 1200 1201 // RPC:hal:CTRL_GET_ZBC_CLEAR_TABLE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1202 NV_STATUS rpcCtrlGetZbcClearTable_STUB( 1203 POBJGPU pGpu, 1204 POBJRPC pRpc, 1205 NvHandle arg3, 1206 NvHandle arg4, 1207 void *pArg5 1208 ) 1209 { 1210 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1211 } 1212 1213 // RPC:hal:CLEANUP_SURFACE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1214 NV_STATUS rpcCleanupSurface_STUB( 1215 POBJGPU pGpu, 1216 POBJRPC pRpc, 1217 NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pArg3 1218 ) 1219 { 1220 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1221 } 1222 1223 // RPC:hal:CTRL_SET_TIMESLICE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1224 NV_STATUS rpcCtrlSetTimeslice_STUB( 1225 POBJGPU pGpu, 1226 POBJRPC pRpc, 1227 NvHandle arg3, 1228 NvHandle arg4, 1229 void *pArg5 1230 ) 1231 { 1232 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1233 } 1234 1235 // RPC:hal:CTRL_GPU_QUERY_ECC_STATUS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1236 NV_STATUS rpcCtrlGpuQueryEccStatus_STUB( 1237 POBJGPU pGpu, 1238 POBJRPC pRpc, 1239 NvHandle arg3, 1240 NvHandle arg4, 1241 void *pArg5 1242 ) 1243 { 1244 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1245 } 1246 1247 // RPC:hal:CTRL_DBG_GET_MODE_MMU_DEBUG - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1248 NV_STATUS rpcCtrlDbgGetModeMmuDebug_STUB( 1249 POBJGPU pGpu, 1250 POBJRPC pRpc, 1251 NvHandle arg3, 1252 NvHandle arg4, 1253 void *pArg5 1254 ) 1255 { 1256 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1257 } 1258 1259 // RPC:hal:CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1260 NV_STATUS rpcCtrlDbgClearAllSmErrorStates_STUB( 1261 POBJGPU pGpu, 1262 POBJRPC pRpc, 1263 NvHandle arg3, 1264 NvHandle arg4, 1265 void *pArg5 1266 ) 1267 { 1268 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1269 } 1270 1271 // RPC:hal:VGPU_GSP_RING_DOORBELL - TU10X, GA100 1272 NV_STATUS rpcVgpuGspRingDoorbell_STUB( 1273 POBJGPU pGpu, 1274 NvU32 arg2 1275 ) 1276 { 1277 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1278 } 1279 1280 // RPC:hal:CTRL_GR_SET_TPC_PARTITION_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1281 NV_STATUS rpcCtrlGrSetTpcPartitionMode_STUB( 1282 POBJGPU pGpu, 1283 POBJRPC pRpc, 1284 NvHandle arg3, 1285 NvHandle arg4, 1286 void *pArg5 1287 ) 1288 { 1289 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1290 } 1291 1292 // RPC:hal:CTRL_GET_TOTAL_HS_CREDITS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1293 NV_STATUS rpcCtrlGetTotalHsCredits_STUB( 1294 POBJGPU pGpu, 1295 POBJRPC pRpc, 1296 NvHandle arg3, 1297 NvHandle arg4, 1298 void *pArg5 1299 ) 1300 { 1301 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1302 } 1303 1304 // RPC:hal:CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1305 NV_STATUS rpcCtrlInternalPromoteFaultMethodBuffers_STUB( 1306 OBJGPU *pArg1, 1307 POBJRPC pRpc, 1308 NvHandle arg3, 1309 NvHandle arg4, 1310 void *pArg5 1311 ) 1312 { 1313 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1314 } 1315 1316 // RPC:hal:CTRL_FB_GET_INFO_V2 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1317 NV_STATUS rpcCtrlFbGetInfoV2_STUB( 1318 POBJGPU pGpu, 1319 POBJRPC pRpc, 1320 NvHandle arg3, 1321 NvHandle arg4, 1322 void *pArg5 1323 ) 1324 { 1325 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1326 } 1327 1328 // RPC:hal:VGPU_GSP_WRITE_SCRATCH_REGISTER - TU10X, GA100 1329 NV_STATUS rpcVgpuGspWriteScratchRegister_STUB( 1330 POBJGPU pGpu, 1331 NvU64 arg2 1332 ) 1333 { 1334 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1335 } 1336 1337 // RPC:hal:SET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1338 NV_STATUS rpcSetPageDirectory_STUB( 1339 POBJGPU pGpu, 1340 POBJRPC pRpc, 1341 NvHandle arg3, 1342 NvHandle arg4, 1343 NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pArg5 1344 ) 1345 { 1346 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1347 } 1348 1349 // RPC:hal:CTRL_GET_P2P_CAPS_V2 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1350 NV_STATUS rpcCtrlGetP2pCapsV2_STUB( 1351 POBJGPU pGpu, 1352 POBJRPC pRpc, 1353 void *pArg3 1354 ) 1355 { 1356 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1357 } 1358 1359 // RPC:hal:CTRL_NVLINK_GET_INBAND_RECEIVED_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1360 NV_STATUS rpcCtrlNvlinkGetInbandReceivedData_STUB( 1361 POBJGPU pGpu, 1362 POBJRPC pRpc, 1363 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pArg3, 1364 NvU16 arg4, 1365 NvBool *pArg5 1366 ) 1367 { 1368 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1369 } 1370 1371 // RPC:hal:CTRL_GET_CE_PCE_MASK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1372 NV_STATUS rpcCtrlGetCePceMask_STUB( 1373 POBJGPU pGpu, 1374 POBJRPC pRpc, 1375 NvHandle arg3, 1376 NvHandle arg4, 1377 void *pArg5 1378 ) 1379 { 1380 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1381 } 1382 1383 // RPC:hal:CTRL_GET_NVLINK_PEER_ID_MASK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1384 NV_STATUS rpcCtrlGetNvlinkPeerIdMask_STUB( 1385 POBJGPU pGpu, 1386 POBJRPC pRpc, 1387 NvHandle arg3, 1388 NvHandle arg4, 1389 void *pArg5 1390 ) 1391 { 1392 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1393 } 1394 1395 // RPC:hal:CTRL_GPU_EVICT_CTX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1396 NV_STATUS rpcCtrlGpuEvictCtx_STUB( 1397 POBJGPU pGpu, 1398 POBJRPC pRpc, 1399 NvHandle arg3, 1400 NvHandle arg4, 1401 void *pArg5 1402 ) 1403 { 1404 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1405 } 1406 1407 // RPC:hal:CTRL_GET_MMU_DEBUG_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1408 NV_STATUS rpcCtrlGetMmuDebugMode_STUB( 1409 POBJGPU pGpu, 1410 POBJRPC pRpc, 1411 NvHandle arg3, 1412 NvHandle arg4, 1413 void *pArg5 1414 ) 1415 { 1416 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1417 } 1418 1419 // RPC:hal:INVALIDATE_TLB - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1420 NV_STATUS rpcInvalidateTlb_STUB( 1421 POBJGPU pGpu, 1422 POBJRPC pRpc, 1423 NvU64 arg3, 1424 NvU32 arg4 1425 ) 1426 { 1427 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1428 } 1429 1430 // RPC:hal:CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1431 NV_STATUS rpcCtrlDbgSetSingleSmSingleStep_STUB( 1432 POBJGPU pGpu, 1433 POBJRPC pRpc, 1434 NvHandle arg3, 1435 NvHandle arg4, 1436 void *pArg5 1437 ) 1438 { 1439 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1440 } 1441 1442 // RPC:hal:UNLOADING_GUEST_DRIVER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1443 NV_STATUS rpcUnloadingGuestDriver_STUB( 1444 POBJGPU pGpu, 1445 POBJRPC pRpc, 1446 NvBool arg3, 1447 NvBool arg4, 1448 NvU32 arg5 1449 ) 1450 { 1451 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1452 } 1453 1454 // RPC:hal:GET_CONSOLIDATED_GR_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1455 NV_STATUS rpcGetConsolidatedGrStaticInfo_STUB( 1456 POBJGPU pGpu, 1457 POBJRPC pRpc 1458 ) 1459 { 1460 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1461 } 1462 1463 // RPC:hal:SWITCH_TO_VGA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1464 NV_STATUS rpcSwitchToVga_STUB( 1465 POBJGPU pGpu, 1466 POBJRPC pRpc 1467 ) 1468 { 1469 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1470 } 1471 1472 // RPC:hal:CTRL_RESET_CHANNEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1473 NV_STATUS rpcCtrlResetChannel_STUB( 1474 POBJGPU pGpu, 1475 POBJRPC pRpc, 1476 NvHandle arg3, 1477 NvHandle arg4, 1478 void *pArg5 1479 ) 1480 { 1481 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1482 } 1483 1484 // RPC:hal:CTRL_GPFIFO_SCHEDULE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1485 NV_STATUS rpcCtrlGpfifoSchedule_STUB( 1486 POBJGPU pGpu, 1487 POBJRPC pRpc, 1488 NvHandle arg3, 1489 NvHandle arg4, 1490 NvU32 arg5, 1491 void *pArg6 1492 ) 1493 { 1494 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1495 } 1496 1497 // RPC:hal:SET_REGISTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1498 NV_STATUS rpcSetRegistry_STUB( 1499 POBJGPU pGpu, 1500 POBJRPC pRpc 1501 ) 1502 { 1503 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1504 } 1505 1506 // RPC:hal:CTRL_GET_NVLINK_STATUS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1507 NV_STATUS rpcCtrlGetNvlinkStatus_STUB( 1508 POBJGPU pGpu, 1509 POBJRPC pRpc, 1510 NvHandle arg3, 1511 NvHandle arg4, 1512 void *pArg5 1513 ) 1514 { 1515 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1516 } 1517 1518 // RPC:hal:GET_STATIC_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1519 NV_STATUS rpcGetStaticData_STUB( 1520 POBJGPU pGpu, 1521 POBJRPC pRpc 1522 ) 1523 { 1524 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1525 } 1526 1527 // RPC:hal:CTRL_GR_GET_TPC_PARTITION_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1528 NV_STATUS rpcCtrlGrGetTpcPartitionMode_STUB( 1529 POBJGPU pGpu, 1530 POBJRPC pRpc, 1531 NvHandle arg3, 1532 NvHandle arg4, 1533 void *pArg5 1534 ) 1535 { 1536 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1537 } 1538 1539 // RPC:hal:CTRL_STOP_CHANNEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1540 NV_STATUS rpcCtrlStopChannel_STUB( 1541 POBJGPU pGpu, 1542 POBJRPC pRpc, 1543 NvHandle arg3, 1544 NvHandle arg4, 1545 void *pArg5 1546 ) 1547 { 1548 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1549 } 1550 1551 // RPC:hal:SET_SURFACE_PROPERTIES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1552 NV_STATUS rpcSetSurfaceProperties_STUB( 1553 POBJGPU pGpu, 1554 POBJRPC pRpc, 1555 NvHandle arg3, 1556 NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES *pArg4, 1557 NvBool arg5 1558 ) 1559 { 1560 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1561 } 1562 1563 // RPC:hal:CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1564 NV_STATUS rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_STUB( 1565 POBJGPU pGpu, 1566 POBJRPC pRpc, 1567 NvHandle arg3, 1568 NvHandle arg4, 1569 void *pArg5 1570 ) 1571 { 1572 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1573 } 1574 1575 // RPC:hal:CTRL_TIMER_SET_GR_TICK_FREQ - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1576 NV_STATUS rpcCtrlTimerSetGrTickFreq_STUB( 1577 POBJGPU pGpu, 1578 POBJRPC pRpc, 1579 NvHandle arg3, 1580 NvHandle arg4, 1581 void *pArg5 1582 ) 1583 { 1584 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1585 } 1586 1587 // RPC:hal:ALLOC_EVENT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1588 NV_STATUS rpcAllocEvent_STUB( 1589 POBJGPU pGpu, 1590 POBJRPC pRpc, 1591 NvHandle arg3, 1592 NvHandle arg4, 1593 NvHandle arg5, 1594 NvHandle arg6, 1595 NvHandle arg7, 1596 NvU32 arg8, 1597 NvU32 arg9 1598 ) 1599 { 1600 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1601 } 1602 1603 // RPC:hal:CTRL_GR_PC_SAMPLING_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1604 NV_STATUS rpcCtrlGrPcSamplingMode_STUB( 1605 POBJGPU pGpu, 1606 POBJRPC pRpc, 1607 NvHandle arg3, 1608 NvHandle arg4, 1609 void *pArg5 1610 ) 1611 { 1612 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1613 } 1614 1615 // RPC:hal:CTRL_MC_SERVICE_INTERRUPTS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1616 NV_STATUS rpcCtrlMcServiceInterrupts_STUB( 1617 POBJGPU pGpu, 1618 POBJRPC pRpc, 1619 NvHandle arg3, 1620 NvHandle arg4, 1621 void *pArg5 1622 ) 1623 { 1624 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1625 } 1626 1627 // RPC:hal:CTRL_DBG_READ_ALL_SM_ERROR_STATES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1628 NV_STATUS rpcCtrlDbgReadAllSmErrorStates_STUB( 1629 POBJGPU pGpu, 1630 POBJRPC pRpc, 1631 NvHandle arg3, 1632 NvHandle arg4, 1633 void *pArg5 1634 ) 1635 { 1636 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1637 } 1638 1639 // RPC:hal:CTRL_SET_ZBC_COLOR_CLEAR - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1640 NV_STATUS rpcCtrlSetZbcColorClear_STUB( 1641 POBJGPU pGpu, 1642 POBJRPC pRpc, 1643 NvHandle arg3, 1644 NvHandle arg4, 1645 void *pArg5 1646 ) 1647 { 1648 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1649 } 1650 1651 // RPC:hal:GET_ENCODER_CAPACITY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1652 NV_STATUS rpcGetEncoderCapacity_STUB( 1653 POBJGPU pGpu, 1654 POBJRPC pRpc, 1655 NvHandle arg3, 1656 NvHandle arg4, 1657 NvU32 *pArg5 1658 ) 1659 { 1660 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1661 } 1662 1663 // RPC:hal:CTRL_GET_P2P_CAPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1664 NV_STATUS rpcCtrlGetP2pCaps_STUB( 1665 POBJGPU pGpu, 1666 POBJRPC pRpc, 1667 NvHandle arg3, 1668 NvHandle arg4, 1669 void *pArg5 1670 ) 1671 { 1672 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1673 } 1674 1675 // RPC:hal:PERF_GET_LEVEL_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1676 NV_STATUS rpcPerfGetLevelInfo_STUB( 1677 POBJGPU pGpu, 1678 POBJRPC pRpc, 1679 NvHandle arg3, 1680 NvHandle arg4, 1681 NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS *pArg5, 1682 NV2080_CTRL_PERF_GET_CLK_INFO *pArg6 1683 ) 1684 { 1685 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1686 } 1687 1688 // RPC:hal:ALLOC_OBJECT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1689 NV_STATUS rpcAllocObject_STUB( 1690 POBJGPU pGpu, 1691 POBJRPC pRpc, 1692 NvHandle arg3, 1693 NvHandle arg4, 1694 NvHandle arg5, 1695 NvU32 arg6, 1696 void *pArg7 1697 ) 1698 { 1699 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1700 } 1701 1702 // RPC:hal:CTRL_GPU_HANDLE_VF_PRI_FAULT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1703 NV_STATUS rpcCtrlGpuHandleVfPriFault_STUB( 1704 POBJGPU pGpu, 1705 POBJRPC pRpc, 1706 NvHandle arg3, 1707 NvHandle arg4, 1708 void *pArg5 1709 ) 1710 { 1711 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1712 } 1713 1714 // RPC:hal:RM_API_CONTROL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1715 NV_STATUS rpcRmApiControl_STUB( 1716 POBJGPU pGpu, 1717 POBJRPC pRpc, 1718 NvHandle arg3, 1719 NvHandle arg4, 1720 NvU32 arg5, 1721 void *pArg6, 1722 NvU32 arg7 1723 ) 1724 { 1725 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1726 } 1727 1728 // RPC:hal:CTRL_FABRIC_MEM_STATS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1729 NV_STATUS rpcCtrlFabricMemStats_STUB( 1730 POBJGPU pGpu, 1731 POBJRPC pRpc, 1732 NvHandle arg3, 1733 NvHandle arg4, 1734 void *pArg5 1735 ) 1736 { 1737 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1738 } 1739 1740 // RPC:hal:CTRL_GR_CTXSW_ZCULL_BIND - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1741 NV_STATUS rpcCtrlGrCtxswZcullBind_STUB( 1742 POBJGPU pGpu, 1743 POBJRPC pRpc, 1744 NvHandle arg3, 1745 NvHandle arg4, 1746 void *pArg5 1747 ) 1748 { 1749 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1750 } 1751 1752 // RPC:hal:CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1753 NV_STATUS rpcCtrlInternalMemsysSetZbcReferenced_STUB( 1754 POBJGPU pGpu, 1755 POBJRPC pRpc, 1756 NvHandle arg3, 1757 NvHandle arg4, 1758 void *pArg5 1759 ) 1760 { 1761 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1762 } 1763 1764 // RPC:hal:CTRL_PERF_RATED_TDP_SET_CONTROL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1765 NV_STATUS rpcCtrlPerfRatedTdpSetControl_STUB( 1766 POBJGPU pGpu, 1767 POBJRPC pRpc, 1768 NvHandle arg3, 1769 NvHandle arg4, 1770 void *pArg5 1771 ) 1772 { 1773 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1774 } 1775 1776 // RPC:hal:CTRL_EXEC_PARTITIONS_CREATE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1777 NV_STATUS rpcCtrlExecPartitionsCreate_STUB( 1778 POBJGPU pGpu, 1779 POBJRPC pRpc, 1780 NvHandle arg3, 1781 NvHandle arg4, 1782 void *pArg5 1783 ) 1784 { 1785 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1786 } 1787 1788 // RPC:hal:CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1789 NV_STATUS rpcCtrlGpfifoGetWorkSubmitToken_STUB( 1790 POBJGPU pGpu, 1791 POBJRPC pRpc, 1792 NvHandle arg3, 1793 NvHandle arg4, 1794 void *pArg5 1795 ) 1796 { 1797 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1798 } 1799 1800 // RPC:hal:IDLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1801 NV_STATUS rpcIdleChannels_STUB( 1802 OBJGPU *pArg1, 1803 POBJRPC pRpc, 1804 NvHandle *phclients, 1805 NvHandle *phdevices, 1806 NvHandle *phchannels, 1807 NvU32 nentries, 1808 NvU32 flags, 1809 NvU32 timeout 1810 ) 1811 { 1812 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1813 } 1814 1815 // RPC:hal:CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1816 NV_STATUS rpcCtrlCmdInternalGpuStartFabricProbe_STUB( 1817 POBJGPU pGpu, 1818 POBJRPC pRpc, 1819 NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS *pArg3 1820 ) 1821 { 1822 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1823 } 1824 1825 // RPC:hal:GET_BRAND_CAPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1826 NV_STATUS rpcGetBrandCaps_STUB( 1827 POBJGPU pGpu, 1828 POBJRPC pRpc, 1829 NvHandle arg3, 1830 NvHandle arg4, 1831 NvU32 arg5, 1832 void *pArg6, 1833 NvU32 arg7 1834 ) 1835 { 1836 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1837 } 1838 1839 // RPC:hal:RESTORE_HIBERNATION_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1840 NV_STATUS rpcRestoreHibernationData_STUB( 1841 POBJGPU pGpu, 1842 POBJRPC pRpc 1843 ) 1844 { 1845 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1846 } 1847 1848 // RPC:hal:CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1849 NV_STATUS rpcCtrlFlaSetupInstanceMemBlock_STUB( 1850 POBJGPU pGpu, 1851 POBJRPC pRpc, 1852 NvHandle arg3, 1853 NvHandle arg4, 1854 void *pArg5 1855 ) 1856 { 1857 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1858 } 1859 1860 // RPC:hal:CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1861 NV_STATUS rpcCtrlInternalSriovPromotePmaStream_STUB( 1862 POBJGPU pGpu, 1863 POBJRPC pRpc, 1864 NvHandle arg3, 1865 NvHandle arg4, 1866 void *pArg5 1867 ) 1868 { 1869 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1870 } 1871 1872 // RPC:hal:CTRL_FB_GET_FS_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1873 NV_STATUS rpcCtrlFbGetFsInfo_STUB( 1874 POBJGPU pGpu, 1875 POBJRPC pRpc, 1876 NvHandle arg3, 1877 NvHandle arg4, 1878 void *pArg5 1879 ) 1880 { 1881 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1882 } 1883 1884 // RPC:hal:CTRL_SET_CHANNEL_INTERLEAVE_LEVEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1885 NV_STATUS rpcCtrlSetChannelInterleaveLevel_STUB( 1886 POBJGPU pGpu, 1887 POBJRPC pRpc, 1888 NvHandle arg3, 1889 NvHandle arg4, 1890 void *pArg5 1891 ) 1892 { 1893 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1894 } 1895 1896 // RPC:hal:CTRL_DBG_RESUME_CONTEXT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1897 NV_STATUS rpcCtrlDbgResumeContext_STUB( 1898 POBJGPU pGpu, 1899 POBJRPC pRpc, 1900 NvHandle arg3, 1901 NvHandle arg4 1902 ) 1903 { 1904 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1905 } 1906 1907 // RPC:hal:ALLOC_ROOT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1908 NV_STATUS rpcAllocRoot_STUB( 1909 POBJGPU pGpu, 1910 POBJRPC pRpc, 1911 NvHandle arg3 1912 ) 1913 { 1914 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1915 } 1916 1917 // RPC:hal:CTRL_FIFO_DISABLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1918 NV_STATUS rpcCtrlFifoDisableChannels_STUB( 1919 POBJGPU pGpu, 1920 POBJRPC pRpc, 1921 NvHandle arg3, 1922 NvHandle arg4, 1923 void *pArg5 1924 ) 1925 { 1926 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1927 } 1928 1929 // RPC:hal:CTRL_SET_HS_CREDITS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1930 NV_STATUS rpcCtrlSetHsCredits_STUB( 1931 POBJGPU pGpu, 1932 POBJRPC pRpc, 1933 NvHandle arg3, 1934 NvHandle arg4, 1935 void *pArg5 1936 ) 1937 { 1938 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1939 } 1940 1941 // RPC:hal:GET_ENGINE_UTILIZATION - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1942 NV_STATUS rpcGetEngineUtilization_STUB( 1943 POBJGPU pGpu, 1944 POBJRPC pRpc, 1945 NvHandle arg3, 1946 NvHandle arg4, 1947 NvU32 arg5, 1948 void *pArg6, 1949 NvU32 arg7 1950 ) 1951 { 1952 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1953 } 1954 1955 // RPC:hal:CTRL_GET_ZBC_CLEAR_TABLE_ENTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1956 NV_STATUS rpcCtrlGetZbcClearTableEntry_STUB( 1957 POBJGPU pGpu, 1958 POBJRPC pRpc, 1959 NvHandle arg3, 1960 NvHandle arg4, 1961 void *pArg5 1962 ) 1963 { 1964 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1965 } 1966 1967 // RPC:hal:CTRL_NVENC_SW_SESSION_UPDATE_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1968 NV_STATUS rpcCtrlNvencSwSessionUpdateInfo_STUB( 1969 POBJGPU pGpu, 1970 POBJRPC pRpc, 1971 NvHandle arg3, 1972 NvHandle arg4, 1973 void *pArg5 1974 ) 1975 { 1976 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1977 } 1978 1979 // RPC:hal:CTRL_DBG_SUSPEND_CONTEXT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1980 NV_STATUS rpcCtrlDbgSuspendContext_STUB( 1981 POBJGPU pGpu, 1982 POBJRPC pRpc, 1983 NvHandle arg3, 1984 NvHandle arg4, 1985 void *pArg5 1986 ) 1987 { 1988 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 1989 } 1990 1991 // RPC:hal:CTRL_GET_P2P_CAPS_MATRIX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 1992 NV_STATUS rpcCtrlGetP2pCapsMatrix_STUB( 1993 POBJGPU pGpu, 1994 POBJRPC pRpc, 1995 NvHandle arg3, 1996 NvHandle arg4, 1997 void *pArg5 1998 ) 1999 { 2000 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2001 } 2002 2003 // RPC:hal:CTRL_DBG_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2004 NV_STATUS rpcCtrlDbgExecRegOps_STUB( 2005 POBJGPU pGpu, 2006 POBJRPC pRpc, 2007 NvHandle arg3, 2008 NvHandle arg4, 2009 void *pArg5 2010 ) 2011 { 2012 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2013 } 2014 2015 // RPC:hal:CTRL_FREE_PMA_STREAM - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2016 NV_STATUS rpcCtrlFreePmaStream_STUB( 2017 POBJGPU pGpu, 2018 POBJRPC pRpc, 2019 NvHandle arg3, 2020 NvHandle arg4, 2021 void *pArg5 2022 ) 2023 { 2024 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2025 } 2026 2027 // RPC:hal:CTRL_SET_TSG_INTERLEAVE_LEVEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2028 NV_STATUS rpcCtrlSetTsgInterleaveLevel_STUB( 2029 POBJGPU pGpu, 2030 POBJRPC pRpc, 2031 NvHandle arg3, 2032 NvHandle arg4, 2033 void *pArg5 2034 ) 2035 { 2036 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2037 } 2038 2039 // RPC:hal:CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2040 NV_STATUS rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_STUB( 2041 POBJGPU pGpu, 2042 POBJRPC pRpc, 2043 NvHandle arg3, 2044 NvHandle arg4, 2045 void *pArg5 2046 ) 2047 { 2048 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2049 } 2050 2051 // RPC:hal:LOG - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2052 NV_STATUS rpcLog_STUB( 2053 POBJGPU pGpu, 2054 POBJRPC pRpc, 2055 const char *pArg3, 2056 NvU32 arg4 2057 ) 2058 { 2059 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2060 } 2061 2062 // RPC:hal:CTRL_EXEC_PARTITIONS_DELETE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2063 NV_STATUS rpcCtrlExecPartitionsDelete_STUB( 2064 POBJGPU pGpu, 2065 POBJRPC pRpc, 2066 NvHandle arg3, 2067 NvHandle arg4, 2068 void *pArg5 2069 ) 2070 { 2071 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2072 } 2073 2074 // RPC:hal:CTRL_PERF_BOOST - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2075 NV_STATUS rpcCtrlPerfBoost_STUB( 2076 POBJGPU pGpu, 2077 POBJRPC pRpc, 2078 NvHandle arg3, 2079 NvHandle arg4, 2080 void *pArg5 2081 ) 2082 { 2083 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2084 } 2085 2086 // RPC:hal:CTRL_DBG_SET_MODE_MMU_DEBUG - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2087 NV_STATUS rpcCtrlDbgSetModeMmuDebug_STUB( 2088 POBJGPU pGpu, 2089 POBJRPC pRpc, 2090 NvHandle arg3, 2091 NvHandle arg4, 2092 void *pArg5 2093 ) 2094 { 2095 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2096 } 2097 2098 // RPC:hal:CTRL_FIFO_SET_CHANNEL_PROPERTIES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2099 NV_STATUS rpcCtrlFifoSetChannelProperties_STUB( 2100 POBJGPU pGpu, 2101 POBJRPC pRpc, 2102 NvHandle arg3, 2103 NvHandle arg4, 2104 void *pArg5 2105 ) 2106 { 2107 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2108 } 2109 2110 // RPC:hal:CTRL_SUBDEVICE_GET_P2P_CAPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2111 NV_STATUS rpcCtrlSubdeviceGetP2pCaps_STUB( 2112 POBJGPU pGpu, 2113 POBJRPC pRpc, 2114 NvHandle arg3, 2115 NvHandle arg4, 2116 void *pArg5 2117 ) 2118 { 2119 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2120 } 2121 2122 // RPC:hal:UPDATE_BAR_PDE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2123 NV_STATUS rpcUpdateBarPde_STUB( 2124 POBJGPU pGpu, 2125 POBJRPC pRpc, 2126 NV_RPC_UPDATE_PDE_BAR_TYPE arg3, 2127 NvU64 arg4, 2128 NvU64 arg5 2129 ) 2130 { 2131 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2132 } 2133 2134 // RPC:hal:CTRL_BIND_PM_RESOURCES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2135 NV_STATUS rpcCtrlBindPmResources_STUB( 2136 POBJGPU pGpu, 2137 POBJRPC pRpc, 2138 NvHandle arg3, 2139 NvHandle arg4 2140 ) 2141 { 2142 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2143 } 2144 2145 // RPC:hal:MAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2146 NV_STATUS rpcMapMemoryDma_STUB( 2147 POBJGPU pGpu, 2148 POBJRPC pRpc, 2149 NvHandle arg3, 2150 NvHandle arg4, 2151 NvHandle arg5, 2152 NvHandle arg6, 2153 NvU64 arg7, 2154 NvU64 arg8, 2155 NvU32 arg9, 2156 NvU64 *pArg10 2157 ) 2158 { 2159 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2160 } 2161 2162 // RPC:hal:UNMAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2163 NV_STATUS rpcUnmapMemoryDma_STUB( 2164 POBJGPU pGpu, 2165 POBJRPC pRpc, 2166 NvHandle arg3, 2167 NvHandle arg4, 2168 NvHandle arg5, 2169 NvHandle arg6, 2170 NvU32 arg7, 2171 NvU64 arg8 2172 ) 2173 { 2174 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2175 } 2176 2177 // RPC:hal:SET_GUEST_SYSTEM_INFO_EXT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2178 NV_STATUS rpcSetGuestSystemInfoExt_STUB( 2179 POBJGPU pGpu, 2180 POBJRPC pRpc 2181 ) 2182 { 2183 return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; 2184 } 2185 2186 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2187 NV_STATUS deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB( 2188 NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *data, 2189 NvU8 *stream, 2190 NvU32 streamSize, 2191 NvU32 *offset 2192 ) 2193 { 2194 return NV_OK; 2195 } 2196 2197 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2198 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB( 2199 NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *data, 2200 NvU8 *stream, 2201 NvU32 streamSize, 2202 NvU32 *offset 2203 ) 2204 { 2205 return NV_OK; 2206 } 2207 2208 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2209 NV_STATUS deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB( 2210 NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *data, 2211 NvU8 *stream, 2212 NvU32 streamSize, 2213 NvU32 *offset 2214 ) 2215 { 2216 return NV_OK; 2217 } 2218 2219 // RPCSTRUCTURECOPY:hal:VGPU_P2P_CAPABILITY_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2220 NV_STATUS deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB( 2221 VGPU_P2P_CAPABILITY_PARAMS *data, 2222 NvU8 *stream, 2223 NvU32 streamSize, 2224 NvU32 *offset 2225 ) 2226 { 2227 return NV_OK; 2228 } 2229 2230 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2231 NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB( 2232 NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *data, 2233 NvU8 *stream, 2234 NvU32 streamSize, 2235 NvU32 *offset 2236 ) 2237 { 2238 return NV_OK; 2239 } 2240 2241 // RPCSTRUCTURECOPY:hal:NVA080_CTRL_VGPU_GET_CONFIG_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2242 NV_STATUS deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB( 2243 NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *data, 2244 NvU8 *stream, 2245 NvU32 streamSize, 2246 NvU32 *offset 2247 ) 2248 { 2249 return NV_OK; 2250 } 2251 2252 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2253 NV_STATUS deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB( 2254 NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS *data, 2255 NvU8 *stream, 2256 NvU32 streamSize, 2257 NvU32 *offset 2258 ) 2259 { 2260 return NV_OK; 2261 } 2262 2263 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2264 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB( 2265 NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS *data, 2266 NvU8 *stream, 2267 NvU32 streamSize, 2268 NvU32 *offset 2269 ) 2270 { 2271 return NV_OK; 2272 } 2273 2274 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2275 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB( 2276 NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *data, 2277 NvU8 *stream, 2278 NvU32 streamSize, 2279 NvU32 *offset 2280 ) 2281 { 2282 return NV_OK; 2283 } 2284 2285 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2286 NV_STATUS deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB( 2287 NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *data, 2288 NvU8 *stream, 2289 NvU32 streamSize, 2290 NvU32 *offset 2291 ) 2292 { 2293 return NV_OK; 2294 } 2295 2296 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_GPU_GET_GID_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2297 NV_STATUS deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB( 2298 NV2080_CTRL_GPU_GET_GID_INFO_PARAMS *data, 2299 NvU8 *stream, 2300 NvU32 streamSize, 2301 NvU32 *offset 2302 ) 2303 { 2304 return NV_OK; 2305 } 2306 2307 // RPCSTRUCTURECOPY:hal:NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2308 NV_STATUS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB( 2309 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *data, 2310 NvU8 *stream, 2311 NvU32 streamSize, 2312 NvU32 *offset 2313 ) 2314 { 2315 return NV_OK; 2316 } 2317 2318 // RPCSTRUCTURECOPY:hal:NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2319 NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB( 2320 NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *data, 2321 NvU8 *stream, 2322 NvU32 streamSize, 2323 NvU32 *offset 2324 ) 2325 { 2326 return NV_OK; 2327 } 2328 2329 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2330 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB( 2331 NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS *data, 2332 NvU8 *stream, 2333 NvU32 streamSize, 2334 NvU32 *offset 2335 ) 2336 { 2337 return NV_OK; 2338 } 2339 2340 // RPCSTRUCTURECOPY:hal:VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2341 NV_STATUS deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB( 2342 VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES *data, 2343 NvU8 *stream, 2344 NvU32 streamSize, 2345 NvU32 *offset 2346 ) 2347 { 2348 return NV_OK; 2349 } 2350 2351 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2352 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB( 2353 NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *data, 2354 NvU8 *stream, 2355 NvU32 streamSize, 2356 NvU32 *offset 2357 ) 2358 { 2359 return NV_OK; 2360 } 2361 2362 // RPCSTRUCTURECOPY:hal:VGPU_FB_GET_LTC_INFO_FOR_FBP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2363 NV_STATUS deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB( 2364 VGPU_FB_GET_LTC_INFO_FOR_FBP *data, 2365 NvU8 *stream, 2366 NvU32 streamSize, 2367 NvU32 *offset 2368 ) 2369 { 2370 return NV_OK; 2371 } 2372 2373 // RPCSTRUCTURECOPY:hal:VGPU_STATIC_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2374 NV_STATUS deserialize_VGPU_STATIC_DATA_STUB( 2375 VGPU_STATIC_DATA *data, 2376 NvU8 *stream, 2377 NvU32 streamSize, 2378 NvU32 *offset 2379 ) 2380 { 2381 return NV_OK; 2382 } 2383 2384 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2385 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB( 2386 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS *data, 2387 NvU8 *stream, 2388 NvU32 streamSize, 2389 NvU32 *offset 2390 ) 2391 { 2392 return NV_OK; 2393 } 2394 2395 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2396 NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB( 2397 NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *data, 2398 NvU8 *stream, 2399 NvU32 streamSize, 2400 NvU32 *offset 2401 ) 2402 { 2403 return NV_OK; 2404 } 2405 2406 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2407 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB( 2408 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS *data, 2409 NvU8 *stream, 2410 NvU32 streamSize, 2411 NvU32 *offset 2412 ) 2413 { 2414 return NV_OK; 2415 } 2416 2417 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2418 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB( 2419 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS *data, 2420 NvU8 *stream, 2421 NvU32 streamSize, 2422 NvU32 *offset 2423 ) 2424 { 2425 return NV_OK; 2426 } 2427 2428 // RPCSTRUCTURECOPY:hal:NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2429 NV_STATUS deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB( 2430 NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *data, 2431 NvU8 *stream, 2432 NvU32 streamSize, 2433 NvU32 *offset 2434 ) 2435 { 2436 return NV_OK; 2437 } 2438 2439 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2440 NV_STATUS deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB( 2441 NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *data, 2442 NvU8 *stream, 2443 NvU32 streamSize, 2444 NvU32 *offset 2445 ) 2446 { 2447 return NV_OK; 2448 } 2449 2450 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2451 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB( 2452 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS *data, 2453 NvU8 *stream, 2454 NvU32 streamSize, 2455 NvU32 *offset 2456 ) 2457 { 2458 return NV_OK; 2459 } 2460 2461 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2462 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB( 2463 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS *data, 2464 NvU8 *stream, 2465 NvU32 streamSize, 2466 NvU32 *offset 2467 ) 2468 { 2469 return NV_OK; 2470 } 2471 2472 // RPCSTRUCTURECOPY:hal:VGPU_FIFO_GET_DEVICE_INFO_TABLE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2473 NV_STATUS deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB( 2474 VGPU_FIFO_GET_DEVICE_INFO_TABLE *data, 2475 NvU8 *stream, 2476 NvU32 streamSize, 2477 NvU32 *offset 2478 ) 2479 { 2480 return NV_OK; 2481 } 2482 2483 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2484 NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB( 2485 NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *data, 2486 NvU8 *stream, 2487 NvU32 streamSize, 2488 NvU32 *offset 2489 ) 2490 { 2491 return NV_OK; 2492 } 2493 2494 // RPCSTRUCTURECOPY:hal:VGPU_BSP_GET_CAPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2495 NV_STATUS deserialize_VGPU_BSP_GET_CAPS_STUB( 2496 VGPU_BSP_GET_CAPS *data, 2497 NvU8 *stream, 2498 NvU32 streamSize, 2499 NvU32 *offset 2500 ) 2501 { 2502 return NV_OK; 2503 } 2504 2505 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2506 NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB( 2507 NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *data, 2508 NvU8 *stream, 2509 NvU32 streamSize, 2510 NvU32 *offset 2511 ) 2512 { 2513 return NV_OK; 2514 } 2515 2516 // RPCSTRUCTURECOPY:hal:GPU_PARTITION_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2517 NV_STATUS deserialize_GPU_PARTITION_INFO_STUB( 2518 GPU_PARTITION_INFO *data, 2519 NvU8 *stream, 2520 NvU32 streamSize, 2521 NvU32 *offset 2522 ) 2523 { 2524 return NV_OK; 2525 } 2526 2527 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2528 NV_STATUS deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB( 2529 NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *data, 2530 NvU8 *stream, 2531 NvU32 streamSize, 2532 NvU32 *offset 2533 ) 2534 { 2535 return NV_OK; 2536 } 2537 2538 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2539 NV_STATUS deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB( 2540 NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *data, 2541 NvU8 *stream, 2542 NvU32 streamSize, 2543 NvU32 *offset 2544 ) 2545 { 2546 return NV_OK; 2547 } 2548 2549 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2550 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB( 2551 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS *data, 2552 NvU8 *stream, 2553 NvU32 streamSize, 2554 NvU32 *offset 2555 ) 2556 { 2557 return NV_OK; 2558 } 2559 2560 // RPCSTRUCTURECOPY:hal:NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2561 NV_STATUS deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB( 2562 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *data, 2563 NvU8 *stream, 2564 NvU32 streamSize, 2565 NvU32 *offset 2566 ) 2567 { 2568 return NV_OK; 2569 } 2570 2571 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2572 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB( 2573 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS *data, 2574 NvU8 *stream, 2575 NvU32 streamSize, 2576 NvU32 *offset 2577 ) 2578 { 2579 return NV_OK; 2580 } 2581 2582 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2583 NV_STATUS deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB( 2584 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *data, 2585 NvU8 *stream, 2586 NvU32 streamSize, 2587 NvU32 *offset 2588 ) 2589 { 2590 return NV_OK; 2591 } 2592 2593 // RPCSTRUCTURECOPY:hal:VGPU_STATIC_PROPERTIES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2594 NV_STATUS deserialize_VGPU_STATIC_PROPERTIES_STUB( 2595 VGPU_STATIC_PROPERTIES *data, 2596 NvU8 *stream, 2597 NvU32 streamSize, 2598 NvU32 *offset 2599 ) 2600 { 2601 return NV_OK; 2602 } 2603 2604 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_BUS_GET_INFO_V2_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2605 NV_STATUS deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB( 2606 NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *data, 2607 NvU8 *stream, 2608 NvU32 streamSize, 2609 NvU32 *offset 2610 ) 2611 { 2612 return NV_OK; 2613 } 2614 2615 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2616 NV_STATUS deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB( 2617 NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *data, 2618 NvU8 *stream, 2619 NvU32 streamSize, 2620 NvU32 *offset 2621 ) 2622 { 2623 return NV_OK; 2624 } 2625 2626 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2627 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB( 2628 NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *data, 2629 NvU8 *stream, 2630 NvU32 streamSize, 2631 NvU32 *offset 2632 ) 2633 { 2634 return NV_OK; 2635 } 2636 2637 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_FLA_GET_RANGE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2638 NV_STATUS deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB( 2639 NV2080_CTRL_FLA_GET_RANGE_PARAMS *data, 2640 NvU8 *stream, 2641 NvU32 streamSize, 2642 NvU32 *offset 2643 ) 2644 { 2645 return NV_OK; 2646 } 2647 2648 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2649 NV_STATUS deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB( 2650 NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *data, 2651 NvU8 *stream, 2652 NvU32 streamSize, 2653 NvU32 *offset 2654 ) 2655 { 2656 return NV_OK; 2657 } 2658 2659 // RPCSTRUCTURECOPY:hal:NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2660 NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB( 2661 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *data, 2662 NvU8 *stream, 2663 NvU32 streamSize, 2664 NvU32 *offset 2665 ) 2666 { 2667 return NV_OK; 2668 } 2669 2670 // RPCSTRUCTURECOPY:hal:VGPU_CE_GET_CAPS_V2 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2671 NV_STATUS deserialize_VGPU_CE_GET_CAPS_V2_STUB( 2672 VGPU_CE_GET_CAPS_V2 *data, 2673 NvU8 *stream, 2674 NvU32 streamSize, 2675 NvU32 *offset 2676 ) 2677 { 2678 return NV_OK; 2679 } 2680 2681 // RPCSTRUCTURECOPY:hal:VGPU_GET_LATENCY_BUFFER_SIZE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2682 NV_STATUS deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB( 2683 VGPU_GET_LATENCY_BUFFER_SIZE *data, 2684 NvU8 *stream, 2685 NvU32 streamSize, 2686 NvU32 *offset 2687 ) 2688 { 2689 return NV_OK; 2690 } 2691 2692 // RPCSTRUCTURECOPY:hal:NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 2693 NV_STATUS deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB( 2694 NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *data, 2695 NvU8 *stream, 2696 NvU32 streamSize, 2697 NvU32 *offset 2698 ) 2699 { 2700 return NV_OK; 2701 } 2702 2703 2704 2705 2706 // 2707 // "missing engine" setup sequences, if any 2708 // 2709 2710 // Install the _MISSING overrides for GPIO: HAL_INTERFACES 2711 void gpioHalIfacesSetup_MISSING(GPIO_HAL_IFACES *pGpioHal) 2712 { 2713 // GPIO disabled by rmconfig; no additional MISSING support needed 2714 } 2715 2716 2717 2718 2719 2720 2721 #endif // _G_RMCFG_HAL_STUBS_H_ 2722