1 #define NVOC_INTR_H_PRIVATE_ACCESS_ALLOWED
2 #include "nvoc/runtime.h"
3 #include "nvoc/rtti.h"
4 #include "nvtypes.h"
5 #include "nvport/nvport.h"
6 #include "nvport/inline/util_valist.h"
7 #include "utils/nvassert.h"
8 #include "g_intr_nvoc.h"
9
10 #ifdef DEBUG
11 char __nvoc_class_id_uniqueness_check_0xc06e44 = 1;
12 #endif
13
14 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Intr;
15
16 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object;
17
18 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE;
19
20 void __nvoc_init_Intr(Intr*, RmHalspecOwner* );
21 void __nvoc_init_funcTable_Intr(Intr*, RmHalspecOwner* );
22 NV_STATUS __nvoc_ctor_Intr(Intr*, RmHalspecOwner* );
23 void __nvoc_init_dataField_Intr(Intr*, RmHalspecOwner* );
24 void __nvoc_dtor_Intr(Intr*);
25 extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Intr;
26
27 static const struct NVOC_RTTI __nvoc_rtti_Intr_Intr = {
28 /*pClassDef=*/ &__nvoc_class_def_Intr,
29 /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_Intr,
30 /*offset=*/ 0,
31 };
32
33 static const struct NVOC_RTTI __nvoc_rtti_Intr_Object = {
34 /*pClassDef=*/ &__nvoc_class_def_Object,
35 /*dtor=*/ &__nvoc_destructFromBase,
36 /*offset=*/ NV_OFFSETOF(Intr, __nvoc_base_OBJENGSTATE.__nvoc_base_Object),
37 };
38
39 static const struct NVOC_RTTI __nvoc_rtti_Intr_OBJENGSTATE = {
40 /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE,
41 /*dtor=*/ &__nvoc_destructFromBase,
42 /*offset=*/ NV_OFFSETOF(Intr, __nvoc_base_OBJENGSTATE),
43 };
44
45 static const struct NVOC_CASTINFO __nvoc_castinfo_Intr = {
46 /*numRelatives=*/ 3,
47 /*relatives=*/ {
48 &__nvoc_rtti_Intr_Intr,
49 &__nvoc_rtti_Intr_OBJENGSTATE,
50 &__nvoc_rtti_Intr_Object,
51 },
52 };
53
54 const struct NVOC_CLASS_DEF __nvoc_class_def_Intr =
55 {
56 /*classInfo=*/ {
57 /*size=*/ sizeof(Intr),
58 /*classId=*/ classId(Intr),
59 /*providerId=*/ &__nvoc_rtti_provider,
60 #if NV_PRINTF_STRINGS_ALLOWED
61 /*name=*/ "Intr",
62 #endif
63 },
64 /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_Intr,
65 /*pCastInfo=*/ &__nvoc_castinfo_Intr,
66 /*pExportInfo=*/ &__nvoc_export_info_Intr
67 };
68
__nvoc_thunk_Intr_engstateConstructEngine(OBJGPU * pGpu,struct OBJENGSTATE * pIntr,ENGDESCRIPTOR arg0)69 static NV_STATUS __nvoc_thunk_Intr_engstateConstructEngine(OBJGPU *pGpu, struct OBJENGSTATE *pIntr, ENGDESCRIPTOR arg0) {
70 return intrConstructEngine(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0);
71 }
72
__nvoc_thunk_Intr_engstateStateInitUnlocked(OBJGPU * pGpu,struct OBJENGSTATE * pIntr)73 static NV_STATUS __nvoc_thunk_Intr_engstateStateInitUnlocked(OBJGPU *pGpu, struct OBJENGSTATE *pIntr) {
74 return intrStateInitUnlocked(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset));
75 }
76
__nvoc_thunk_Intr_engstateStateInitLocked(OBJGPU * pGpu,struct OBJENGSTATE * pIntr)77 static NV_STATUS __nvoc_thunk_Intr_engstateStateInitLocked(OBJGPU *pGpu, struct OBJENGSTATE *pIntr) {
78 return intrStateInitLocked(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset));
79 }
80
__nvoc_thunk_Intr_engstateStateDestroy(OBJGPU * pGpu,struct OBJENGSTATE * pIntr)81 static void __nvoc_thunk_Intr_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pIntr) {
82 intrStateDestroy(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset));
83 }
84
__nvoc_thunk_Intr_engstateStateLoad(OBJGPU * pGpu,struct OBJENGSTATE * pIntr,NvU32 arg0)85 static NV_STATUS __nvoc_thunk_Intr_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pIntr, NvU32 arg0) {
86 return intrStateLoad(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0);
87 }
88
__nvoc_thunk_Intr_engstateStateUnload(OBJGPU * pGpu,struct OBJENGSTATE * pIntr,NvU32 arg0)89 static NV_STATUS __nvoc_thunk_Intr_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pIntr, NvU32 arg0) {
90 return intrStateUnload(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0);
91 }
92
__nvoc_thunk_OBJENGSTATE_intrStatePreLoad(POBJGPU pGpu,struct Intr * pEngstate,NvU32 arg0)93 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreLoad(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) {
94 return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0);
95 }
96
__nvoc_thunk_OBJENGSTATE_intrStatePostUnload(POBJGPU pGpu,struct Intr * pEngstate,NvU32 arg0)97 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePostUnload(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) {
98 return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0);
99 }
100
__nvoc_thunk_OBJENGSTATE_intrStatePreUnload(POBJGPU pGpu,struct Intr * pEngstate,NvU32 arg0)101 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreUnload(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) {
102 return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0);
103 }
104
__nvoc_thunk_OBJENGSTATE_intrInitMissing(POBJGPU pGpu,struct Intr * pEngstate)105 static void __nvoc_thunk_OBJENGSTATE_intrInitMissing(POBJGPU pGpu, struct Intr *pEngstate) {
106 engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset));
107 }
108
__nvoc_thunk_OBJENGSTATE_intrStatePreInitLocked(POBJGPU pGpu,struct Intr * pEngstate)109 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreInitLocked(POBJGPU pGpu, struct Intr *pEngstate) {
110 return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset));
111 }
112
__nvoc_thunk_OBJENGSTATE_intrStatePreInitUnlocked(POBJGPU pGpu,struct Intr * pEngstate)113 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreInitUnlocked(POBJGPU pGpu, struct Intr *pEngstate) {
114 return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset));
115 }
116
__nvoc_thunk_OBJENGSTATE_intrStatePostLoad(POBJGPU pGpu,struct Intr * pEngstate,NvU32 arg0)117 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePostLoad(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) {
118 return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0);
119 }
120
__nvoc_thunk_OBJENGSTATE_intrIsPresent(POBJGPU pGpu,struct Intr * pEngstate)121 static NvBool __nvoc_thunk_OBJENGSTATE_intrIsPresent(POBJGPU pGpu, struct Intr *pEngstate) {
122 return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset));
123 }
124
125 const struct NVOC_EXPORT_INFO __nvoc_export_info_Intr =
126 {
127 /*numEntries=*/ 0,
128 /*pExportEntries=*/ 0
129 };
130
131 void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*);
__nvoc_dtor_Intr(Intr * pThis)132 void __nvoc_dtor_Intr(Intr *pThis) {
133 __nvoc_intrDestruct(pThis);
134 __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE);
135 PORT_UNREFERENCED_VARIABLE(pThis);
136 }
137
__nvoc_init_dataField_Intr(Intr * pThis,RmHalspecOwner * pRmhalspecowner)138 void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) {
139 ChipHal *chipHal = &pRmhalspecowner->chipHal;
140 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
141 RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
142 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
143 PORT_UNREFERENCED_VARIABLE(pThis);
144 PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
145 PORT_UNREFERENCED_VARIABLE(chipHal);
146 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
147 PORT_UNREFERENCED_VARIABLE(rmVariantHal);
148 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
149
150 // NVOC Property Hal field -- PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC
151 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
152 {
153 pThis->setProperty(pThis, PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC, ((NvBool)(0 == 0)));
154 }
155
156 // NVOC Property Hal field -- PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS
157 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
158 {
159 pThis->setProperty(pThis, PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS, ((NvBool)(0 == 0)));
160 }
161 // default
162 else
163 {
164 pThis->setProperty(pThis, PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS, ((NvBool)(0 != 0)));
165 }
166
167 // NVOC Property Hal field -- PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET
168 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
169 {
170 pThis->setProperty(pThis, PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET, ((NvBool)(0 == 0)));
171 }
172 // default
173 else
174 {
175 pThis->setProperty(pThis, PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET, ((NvBool)(0 != 0)));
176 }
177
178 // NVOC Property Hal field -- PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE
179 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
180 {
181 pThis->setProperty(pThis, PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE, ((NvBool)(0 == 0)));
182 }
183
184 // NVOC Property Hal field -- PDB_PROP_INTR_MASK_SUPPORTED
185 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
186 {
187 pThis->setProperty(pThis, PDB_PROP_INTR_MASK_SUPPORTED, ((NvBool)(0 == 0)));
188 }
189
190 // Hal field -- bDefaultNonstallNotify
191 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
192 {
193 pThis->bDefaultNonstallNotify = ((NvBool)(0 == 0));
194 }
195
196 // Hal field -- bUseLegacyVectorAssignment
197 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
198 {
199 pThis->bUseLegacyVectorAssignment = ((NvBool)(0 == 0));
200 }
201 // default
202 else
203 {
204 pThis->bUseLegacyVectorAssignment = ((NvBool)(0 == 0));
205 }
206 }
207
208 NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* );
__nvoc_ctor_Intr(Intr * pThis,RmHalspecOwner * pRmhalspecowner)209 NV_STATUS __nvoc_ctor_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) {
210 NV_STATUS status = NV_OK;
211 status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE);
212 if (status != NV_OK) goto __nvoc_ctor_Intr_fail_OBJENGSTATE;
213 __nvoc_init_dataField_Intr(pThis, pRmhalspecowner);
214 goto __nvoc_ctor_Intr_exit; // Success
215
216 __nvoc_ctor_Intr_fail_OBJENGSTATE:
217 __nvoc_ctor_Intr_exit:
218
219 return status;
220 }
221
__nvoc_init_funcTable_Intr_1(Intr * pThis,RmHalspecOwner * pRmhalspecowner)222 static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspecowner) {
223 ChipHal *chipHal = &pRmhalspecowner->chipHal;
224 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
225 RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
226 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
227 PORT_UNREFERENCED_VARIABLE(pThis);
228 PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
229 PORT_UNREFERENCED_VARIABLE(chipHal);
230 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
231 PORT_UNREFERENCED_VARIABLE(rmVariantHal);
232 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
233
234 pThis->__intrConstructEngine__ = &intrConstructEngine_IMPL;
235
236 pThis->__intrStateInitUnlocked__ = &intrStateInitUnlocked_IMPL;
237
238 pThis->__intrStateInitLocked__ = &intrStateInitLocked_IMPL;
239
240 pThis->__intrStateDestroy__ = &intrStateDestroy_IMPL;
241
242 // Hal function -- intrDecodeStallIntrEn
243 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
244 {
245 pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_TU102;
246 }
247 else
248 {
249 pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_4a4dee;
250 }
251
252 // Hal function -- intrServiceVirtual
253 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
254 {
255 pThis->__intrServiceVirtual__ = &intrServiceVirtual_f2d351;
256 }
257 else
258 {
259 pThis->__intrServiceVirtual__ = &intrServiceVirtual_TU102;
260 }
261
262 // Hal function -- intrTriggerPrivDoorbell
263 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
264 {
265 pThis->__intrTriggerPrivDoorbell__ = &intrTriggerPrivDoorbell_5baef9;
266 }
267 else
268 {
269 pThis->__intrTriggerPrivDoorbell__ = &intrTriggerPrivDoorbell_TU102;
270 }
271
272 // Hal function -- intrGetUvmSharedLeafEnDisableMask
273 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
274 {
275 pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_TU102;
276 }
277 else
278 {
279 pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_GA100;
280 }
281
282 // Hal function -- intrSetDisplayInterruptEnable
283 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
284 {
285 pThis->__intrSetDisplayInterruptEnable__ = &intrSetDisplayInterruptEnable_TU102;
286 }
287 // default
288 else
289 {
290 pThis->__intrSetDisplayInterruptEnable__ = &intrSetDisplayInterruptEnable_b3696a;
291 }
292
293 // Hal function -- intrReadRegTopEnSet
294 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
295 {
296 pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_CPU_TU102;
297 }
298 else
299 {
300 pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_CPU_GA102;
301 }
302
303 // Hal function -- intrWriteRegTopEnSet
304 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
305 {
306 pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_CPU_TU102;
307 }
308 else
309 {
310 pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_CPU_GA102;
311 }
312
313 // Hal function -- intrWriteRegTopEnClear
314 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */
315 {
316 pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_CPU_TU102;
317 }
318 else
319 {
320 pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_CPU_GA102;
321 }
322
323 // Hal function -- intrGetNumLeaves
324 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
325 {
326 pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_GH100;
327 }
328 else
329 {
330 pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_TU102;
331 }
332
333 // Hal function -- intrGetLeafSize
334 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
335 {
336 pThis->__intrGetLeafSize__ = &intrGetLeafSize_GH100;
337 }
338 else
339 {
340 pThis->__intrGetLeafSize__ = &intrGetLeafSize_TU102;
341 }
342
343 // Hal function -- intrGetIntrTopNonStallMask
344 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
345 {
346 pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_GH100;
347 }
348 else
349 {
350 pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_TU102;
351 }
352
353 // Hal function -- intrSanityCheckEngineIntrStallVector
354 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
355 {
356 pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GH100;
357 }
358 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
359 {
360 pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GA100;
361 }
362 // default
363 else
364 {
365 pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_b3696a;
366 }
367
368 // Hal function -- intrSanityCheckEngineIntrNotificationVector
369 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
370 {
371 pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GH100;
372 }
373 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
374 {
375 pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GA100;
376 }
377 // default
378 else
379 {
380 pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_b3696a;
381 }
382
383 // Hal function -- intrStateLoad
384 pThis->__intrStateLoad__ = &intrStateLoad_TU102;
385
386 // Hal function -- intrStateUnload
387 pThis->__intrStateUnload__ = &intrStateUnload_TU102;
388
389 // Hal function -- intrInitSubtreeMap
390 if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ && (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ ))
391 {
392 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
393 {
394 pThis->__intrInitSubtreeMap__ = &intrInitSubtreeMap_GH100;
395 }
396 else
397 {
398 pThis->__intrInitSubtreeMap__ = &intrInitSubtreeMap_TU102;
399 }
400 }
401 else
402 {
403 pThis->__intrInitSubtreeMap__ = &intrInitSubtreeMap_395e98;
404 }
405
406 // Hal function -- intrInitInterruptTable
407 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
408 {
409 pThis->__intrInitInterruptTable__ = &intrInitInterruptTable_VIRTUAL;
410 }
411 else
412 {
413 pThis->__intrInitInterruptTable__ = &intrInitInterruptTable_KERNEL;
414 }
415
416 // Hal function -- intrSetIntrMask
417 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
418 {
419 pThis->__intrSetIntrMask__ = &intrSetIntrMask_GP100;
420 }
421 else
422 {
423 pThis->__intrSetIntrMask__ = &intrSetIntrMask_46f6a7;
424 }
425
426 // Hal function -- intrSetIntrEnInHw
427 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
428 {
429 pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_GP100;
430 }
431 else
432 {
433 pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_d44104;
434 }
435
436 // Hal function -- intrGetIntrEnFromHw
437 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */
438 {
439 pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_GP100;
440 }
441 else
442 {
443 pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_b2b553;
444 }
445
446 pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_Intr_engstateConstructEngine;
447
448 pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitUnlocked__ = &__nvoc_thunk_Intr_engstateStateInitUnlocked;
449
450 pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_Intr_engstateStateInitLocked;
451
452 pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_Intr_engstateStateDestroy;
453
454 pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_Intr_engstateStateLoad;
455
456 pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_Intr_engstateStateUnload;
457
458 pThis->__intrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreLoad;
459
460 pThis->__intrStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_intrStatePostUnload;
461
462 pThis->__intrStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreUnload;
463
464 pThis->__intrInitMissing__ = &__nvoc_thunk_OBJENGSTATE_intrInitMissing;
465
466 pThis->__intrStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreInitLocked;
467
468 pThis->__intrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreInitUnlocked;
469
470 pThis->__intrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_intrStatePostLoad;
471
472 pThis->__intrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_intrIsPresent;
473 }
474
__nvoc_init_funcTable_Intr(Intr * pThis,RmHalspecOwner * pRmhalspecowner)475 void __nvoc_init_funcTable_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) {
476 __nvoc_init_funcTable_Intr_1(pThis, pRmhalspecowner);
477 }
478
479 void __nvoc_init_OBJENGSTATE(OBJENGSTATE*);
__nvoc_init_Intr(Intr * pThis,RmHalspecOwner * pRmhalspecowner)480 void __nvoc_init_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) {
481 pThis->__nvoc_pbase_Intr = pThis;
482 pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object;
483 pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE;
484 __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE);
485 __nvoc_init_funcTable_Intr(pThis, pRmhalspecowner);
486 }
487
__nvoc_objCreate_Intr(Intr ** ppThis,Dynamic * pParent,NvU32 createFlags)488 NV_STATUS __nvoc_objCreate_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFlags)
489 {
490 NV_STATUS status;
491 Object *pParentObj = NULL;
492 Intr *pThis;
493 RmHalspecOwner *pRmhalspecowner;
494
495 // Assign `pThis`, allocating memory unless suppressed by flag.
496 status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Intr), (void**)&pThis, (void**)ppThis);
497 if (status != NV_OK)
498 return status;
499
500 // Zero is the initial value for everything.
501 portMemSet(pThis, 0, sizeof(Intr));
502
503 // Initialize runtime type information.
504 __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Intr);
505
506 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags;
507
508 // pParent must be a valid object that derives from a halspec owner class.
509 NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT);
510
511 // Link the child into the parent unless flagged not to do so.
512 if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY))
513 {
514 pParentObj = dynamicCast(pParent, Object);
515 objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object);
516 }
517 else
518 {
519 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL;
520 }
521
522 if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL)
523 pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent);
524 NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT);
525
526 __nvoc_init_Intr(pThis, pRmhalspecowner);
527 status = __nvoc_ctor_Intr(pThis, pRmhalspecowner);
528 if (status != NV_OK) goto __nvoc_objCreate_Intr_cleanup;
529
530 // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set.
531 *ppThis = pThis;
532
533 return NV_OK;
534
535 __nvoc_objCreate_Intr_cleanup:
536
537 // Unlink the child from the parent if it was linked above.
538 if (pParentObj != NULL)
539 objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object);
540
541 // Do not call destructors here since the constructor already called them.
542 if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT)
543 portMemSet(pThis, 0, sizeof(Intr));
544 else
545 {
546 portMemFree(pThis);
547 *ppThis = NULL;
548 }
549
550 // coverity[leaked_storage:FALSE]
551 return status;
552 }
553
__nvoc_objCreateDynamic_Intr(Intr ** ppThis,Dynamic * pParent,NvU32 createFlags,va_list args)554 NV_STATUS __nvoc_objCreateDynamic_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) {
555 NV_STATUS status;
556
557 status = __nvoc_objCreate_Intr(ppThis, pParent, createFlags);
558
559 return status;
560 }
561
562