1 #define NVOC_INTR_H_PRIVATE_ACCESS_ALLOWED 2 #include "nvoc/runtime.h" 3 #include "nvoc/rtti.h" 4 #include "nvtypes.h" 5 #include "nvport/nvport.h" 6 #include "nvport/inline/util_valist.h" 7 #include "utils/nvassert.h" 8 #include "g_intr_nvoc.h" 9 10 #ifdef DEBUG 11 char __nvoc_class_id_uniqueness_check_0xc06e44 = 1; 12 #endif 13 14 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Intr; 15 16 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; 17 18 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; 19 20 void __nvoc_init_Intr(Intr*, RmHalspecOwner* ); 21 void __nvoc_init_funcTable_Intr(Intr*, RmHalspecOwner* ); 22 NV_STATUS __nvoc_ctor_Intr(Intr*, RmHalspecOwner* ); 23 void __nvoc_init_dataField_Intr(Intr*, RmHalspecOwner* ); 24 void __nvoc_dtor_Intr(Intr*); 25 extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Intr; 26 27 static const struct NVOC_RTTI __nvoc_rtti_Intr_Intr = { 28 /*pClassDef=*/ &__nvoc_class_def_Intr, 29 /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_Intr, 30 /*offset=*/ 0, 31 }; 32 33 static const struct NVOC_RTTI __nvoc_rtti_Intr_Object = { 34 /*pClassDef=*/ &__nvoc_class_def_Object, 35 /*dtor=*/ &__nvoc_destructFromBase, 36 /*offset=*/ NV_OFFSETOF(Intr, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), 37 }; 38 39 static const struct NVOC_RTTI __nvoc_rtti_Intr_OBJENGSTATE = { 40 /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, 41 /*dtor=*/ &__nvoc_destructFromBase, 42 /*offset=*/ NV_OFFSETOF(Intr, __nvoc_base_OBJENGSTATE), 43 }; 44 45 static const struct NVOC_CASTINFO __nvoc_castinfo_Intr = { 46 /*numRelatives=*/ 3, 47 /*relatives=*/ { 48 &__nvoc_rtti_Intr_Intr, 49 &__nvoc_rtti_Intr_OBJENGSTATE, 50 &__nvoc_rtti_Intr_Object, 51 }, 52 }; 53 54 const struct NVOC_CLASS_DEF __nvoc_class_def_Intr = 55 { 56 /*classInfo=*/ { 57 /*size=*/ sizeof(Intr), 58 /*classId=*/ classId(Intr), 59 /*providerId=*/ &__nvoc_rtti_provider, 60 #if NV_PRINTF_STRINGS_ALLOWED 61 /*name=*/ "Intr", 62 #endif 63 }, 64 /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_Intr, 65 /*pCastInfo=*/ &__nvoc_castinfo_Intr, 66 /*pExportInfo=*/ &__nvoc_export_info_Intr 67 }; 68 69 static NV_STATUS __nvoc_thunk_Intr_engstateConstructEngine(OBJGPU *pGpu, struct OBJENGSTATE *pIntr, ENGDESCRIPTOR arg0) { 70 return intrConstructEngine(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); 71 } 72 73 static NV_STATUS __nvoc_thunk_Intr_engstateStateInitUnlocked(OBJGPU *pGpu, struct OBJENGSTATE *pIntr) { 74 return intrStateInitUnlocked(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset)); 75 } 76 77 static NV_STATUS __nvoc_thunk_Intr_engstateStateInitLocked(OBJGPU *pGpu, struct OBJENGSTATE *pIntr) { 78 return intrStateInitLocked(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset)); 79 } 80 81 static void __nvoc_thunk_Intr_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pIntr) { 82 intrStateDestroy(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset)); 83 } 84 85 static NV_STATUS __nvoc_thunk_Intr_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pIntr, NvU32 arg0) { 86 return intrStateLoad(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); 87 } 88 89 static NV_STATUS __nvoc_thunk_Intr_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pIntr, NvU32 arg0) { 90 return intrStateUnload(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); 91 } 92 93 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreLoad(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { 94 return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); 95 } 96 97 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePostUnload(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { 98 return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); 99 } 100 101 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreUnload(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { 102 return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); 103 } 104 105 static void __nvoc_thunk_OBJENGSTATE_intrInitMissing(POBJGPU pGpu, struct Intr *pEngstate) { 106 engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset)); 107 } 108 109 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreInitLocked(POBJGPU pGpu, struct Intr *pEngstate) { 110 return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset)); 111 } 112 113 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreInitUnlocked(POBJGPU pGpu, struct Intr *pEngstate) { 114 return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset)); 115 } 116 117 static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePostLoad(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { 118 return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); 119 } 120 121 static NvBool __nvoc_thunk_OBJENGSTATE_intrIsPresent(POBJGPU pGpu, struct Intr *pEngstate) { 122 return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset)); 123 } 124 125 const struct NVOC_EXPORT_INFO __nvoc_export_info_Intr = 126 { 127 /*numEntries=*/ 0, 128 /*pExportEntries=*/ 0 129 }; 130 131 void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); 132 void __nvoc_dtor_Intr(Intr *pThis) { 133 __nvoc_intrDestruct(pThis); 134 __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 135 PORT_UNREFERENCED_VARIABLE(pThis); 136 } 137 138 void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { 139 ChipHal *chipHal = &pRmhalspecowner->chipHal; 140 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 141 RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; 142 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 143 PORT_UNREFERENCED_VARIABLE(pThis); 144 PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); 145 PORT_UNREFERENCED_VARIABLE(chipHal); 146 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 147 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 148 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 149 150 // NVOC Property Hal field -- PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC 151 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 152 { 153 pThis->setProperty(pThis, PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC, ((NvBool)(0 == 0))); 154 } 155 156 // NVOC Property Hal field -- PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS 157 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 158 { 159 pThis->setProperty(pThis, PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS, ((NvBool)(0 == 0))); 160 } 161 // default 162 else 163 { 164 pThis->setProperty(pThis, PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS, ((NvBool)(0 != 0))); 165 } 166 167 // NVOC Property Hal field -- PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET 168 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 169 { 170 pThis->setProperty(pThis, PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET, ((NvBool)(0 == 0))); 171 } 172 // default 173 else 174 { 175 pThis->setProperty(pThis, PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET, ((NvBool)(0 != 0))); 176 } 177 178 // NVOC Property Hal field -- PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE 179 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 180 { 181 pThis->setProperty(pThis, PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE, ((NvBool)(0 == 0))); 182 } 183 184 // NVOC Property Hal field -- PDB_PROP_INTR_MASK_SUPPORTED 185 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 186 { 187 pThis->setProperty(pThis, PDB_PROP_INTR_MASK_SUPPORTED, ((NvBool)(0 == 0))); 188 } 189 190 // Hal field -- bDefaultNonstallNotify 191 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ 192 { 193 pThis->bDefaultNonstallNotify = ((NvBool)(0 == 0)); 194 } 195 196 // Hal field -- bUseLegacyVectorAssignment 197 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 198 { 199 pThis->bUseLegacyVectorAssignment = ((NvBool)(0 == 0)); 200 } 201 // default 202 else 203 { 204 pThis->bUseLegacyVectorAssignment = ((NvBool)(0 == 0)); 205 } 206 } 207 208 NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); 209 NV_STATUS __nvoc_ctor_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { 210 NV_STATUS status = NV_OK; 211 status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 212 if (status != NV_OK) goto __nvoc_ctor_Intr_fail_OBJENGSTATE; 213 __nvoc_init_dataField_Intr(pThis, pRmhalspecowner); 214 goto __nvoc_ctor_Intr_exit; // Success 215 216 __nvoc_ctor_Intr_fail_OBJENGSTATE: 217 __nvoc_ctor_Intr_exit: 218 219 return status; 220 } 221 222 static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { 223 ChipHal *chipHal = &pRmhalspecowner->chipHal; 224 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 225 RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; 226 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 227 PORT_UNREFERENCED_VARIABLE(pThis); 228 PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); 229 PORT_UNREFERENCED_VARIABLE(chipHal); 230 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 231 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 232 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 233 234 pThis->__intrConstructEngine__ = &intrConstructEngine_IMPL; 235 236 pThis->__intrStateInitUnlocked__ = &intrStateInitUnlocked_IMPL; 237 238 pThis->__intrStateInitLocked__ = &intrStateInitLocked_IMPL; 239 240 pThis->__intrStateDestroy__ = &intrStateDestroy_IMPL; 241 242 // Hal function -- intrDecodeStallIntrEn 243 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 244 { 245 pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_TU102; 246 } 247 else 248 { 249 pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_4a4dee; 250 } 251 252 // Hal function -- intrGetNonStallBaseVector 253 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 254 { 255 pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_TU102; 256 } 257 else 258 { 259 pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_c067f9; 260 } 261 262 // Hal function -- intrGetUvmSharedLeafEnDisableMask 263 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 264 { 265 pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_TU102; 266 } 267 else 268 { 269 pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_GA100; 270 } 271 272 // Hal function -- intrSetDisplayInterruptEnable 273 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 274 { 275 pThis->__intrSetDisplayInterruptEnable__ = &intrSetDisplayInterruptEnable_TU102; 276 } 277 // default 278 else 279 { 280 pThis->__intrSetDisplayInterruptEnable__ = &intrSetDisplayInterruptEnable_b3696a; 281 } 282 283 // Hal function -- intrReadRegTopEnSet 284 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 285 { 286 pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_TU102; 287 } 288 else 289 { 290 pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_GA102; 291 } 292 293 // Hal function -- intrWriteRegTopEnSet 294 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 295 { 296 pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_TU102; 297 } 298 else 299 { 300 pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_GA102; 301 } 302 303 // Hal function -- intrWriteRegTopEnClear 304 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 305 { 306 pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_TU102; 307 } 308 else 309 { 310 pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_GA102; 311 } 312 313 // Hal function -- intrGetNumLeaves 314 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 315 { 316 pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_GH100; 317 } 318 else 319 { 320 pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_TU102; 321 } 322 323 // Hal function -- intrGetLeafSize 324 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 325 { 326 pThis->__intrGetLeafSize__ = &intrGetLeafSize_GH100; 327 } 328 else 329 { 330 pThis->__intrGetLeafSize__ = &intrGetLeafSize_TU102; 331 } 332 333 // Hal function -- intrGetIntrTopNonStallMask 334 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 335 { 336 pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_GH100; 337 } 338 else 339 { 340 pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_TU102; 341 } 342 343 // Hal function -- intrSanityCheckEngineIntrStallVector 344 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 345 { 346 pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GH100; 347 } 348 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 349 { 350 pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GA100; 351 } 352 // default 353 else 354 { 355 pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_b3696a; 356 } 357 358 // Hal function -- intrSanityCheckEngineIntrNotificationVector 359 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 360 { 361 pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GH100; 362 } 363 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 364 { 365 pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GA100; 366 } 367 // default 368 else 369 { 370 pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_b3696a; 371 } 372 373 // Hal function -- intrStateLoad 374 pThis->__intrStateLoad__ = &intrStateLoad_TU102; 375 376 // Hal function -- intrStateUnload 377 pThis->__intrStateUnload__ = &intrStateUnload_TU102; 378 379 // Hal function -- intrSetIntrMask 380 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 381 { 382 pThis->__intrSetIntrMask__ = &intrSetIntrMask_GP100; 383 } 384 else 385 { 386 pThis->__intrSetIntrMask__ = &intrSetIntrMask_46f6a7; 387 } 388 389 // Hal function -- intrSetIntrEnInHw 390 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 391 { 392 pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_GP100; 393 } 394 else 395 { 396 pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_d44104; 397 } 398 399 // Hal function -- intrGetIntrEnFromHw 400 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 401 { 402 pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_GP100; 403 } 404 else 405 { 406 pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_b2b553; 407 } 408 409 pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_Intr_engstateConstructEngine; 410 411 pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitUnlocked__ = &__nvoc_thunk_Intr_engstateStateInitUnlocked; 412 413 pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_Intr_engstateStateInitLocked; 414 415 pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_Intr_engstateStateDestroy; 416 417 pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_Intr_engstateStateLoad; 418 419 pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_Intr_engstateStateUnload; 420 421 pThis->__intrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreLoad; 422 423 pThis->__intrStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_intrStatePostUnload; 424 425 pThis->__intrStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreUnload; 426 427 pThis->__intrInitMissing__ = &__nvoc_thunk_OBJENGSTATE_intrInitMissing; 428 429 pThis->__intrStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreInitLocked; 430 431 pThis->__intrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreInitUnlocked; 432 433 pThis->__intrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_intrStatePostLoad; 434 435 pThis->__intrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_intrIsPresent; 436 } 437 438 void __nvoc_init_funcTable_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { 439 __nvoc_init_funcTable_Intr_1(pThis, pRmhalspecowner); 440 } 441 442 void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); 443 void __nvoc_init_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { 444 pThis->__nvoc_pbase_Intr = pThis; 445 pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; 446 pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; 447 __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 448 __nvoc_init_funcTable_Intr(pThis, pRmhalspecowner); 449 } 450 451 NV_STATUS __nvoc_objCreate_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFlags) { 452 NV_STATUS status; 453 Object *pParentObj; 454 Intr *pThis; 455 RmHalspecOwner *pRmhalspecowner; 456 457 status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Intr), (void**)&pThis, (void**)ppThis); 458 if (status != NV_OK) 459 return status; 460 461 portMemSet(pThis, 0, sizeof(Intr)); 462 463 __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Intr); 464 465 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; 466 467 if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) 468 { 469 pParentObj = dynamicCast(pParent, Object); 470 objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); 471 } 472 else 473 { 474 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; 475 } 476 477 if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) 478 pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); 479 NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); 480 481 __nvoc_init_Intr(pThis, pRmhalspecowner); 482 status = __nvoc_ctor_Intr(pThis, pRmhalspecowner); 483 if (status != NV_OK) goto __nvoc_objCreate_Intr_cleanup; 484 485 *ppThis = pThis; 486 487 return NV_OK; 488 489 __nvoc_objCreate_Intr_cleanup: 490 // do not call destructors here since the constructor already called them 491 if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) 492 portMemSet(pThis, 0, sizeof(Intr)); 493 else 494 portMemFree(pThis); 495 496 // coverity[leaked_storage:FALSE] 497 return status; 498 } 499 500 NV_STATUS __nvoc_objCreateDynamic_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { 501 NV_STATUS status; 502 503 status = __nvoc_objCreate_Intr(ppThis, pParent, createFlags); 504 505 return status; 506 } 507 508