1 #define NVOC_KERNEL_CE_H_PRIVATE_ACCESS_ALLOWED 2 #include "nvoc/runtime.h" 3 #include "nvoc/rtti.h" 4 #include "nvtypes.h" 5 #include "nvport/nvport.h" 6 #include "nvport/inline/util_valist.h" 7 #include "utils/nvassert.h" 8 #include "g_kernel_ce_nvoc.h" 9 10 #ifdef DEBUG 11 char __nvoc_class_id_uniqueness_check_0x242aca = 1; 12 #endif 13 14 extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCE; 15 16 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; 17 18 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; 19 20 extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; 21 22 void __nvoc_init_KernelCE(KernelCE*, RmHalspecOwner* ); 23 void __nvoc_init_funcTable_KernelCE(KernelCE*, RmHalspecOwner* ); 24 NV_STATUS __nvoc_ctor_KernelCE(KernelCE*, RmHalspecOwner* ); 25 void __nvoc_init_dataField_KernelCE(KernelCE*, RmHalspecOwner* ); 26 void __nvoc_dtor_KernelCE(KernelCE*); 27 extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCE; 28 29 static const struct NVOC_RTTI __nvoc_rtti_KernelCE_KernelCE = { 30 /*pClassDef=*/ &__nvoc_class_def_KernelCE, 31 /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelCE, 32 /*offset=*/ 0, 33 }; 34 35 static const struct NVOC_RTTI __nvoc_rtti_KernelCE_Object = { 36 /*pClassDef=*/ &__nvoc_class_def_Object, 37 /*dtor=*/ &__nvoc_destructFromBase, 38 /*offset=*/ NV_OFFSETOF(KernelCE, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), 39 }; 40 41 static const struct NVOC_RTTI __nvoc_rtti_KernelCE_OBJENGSTATE = { 42 /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, 43 /*dtor=*/ &__nvoc_destructFromBase, 44 /*offset=*/ NV_OFFSETOF(KernelCE, __nvoc_base_OBJENGSTATE), 45 }; 46 47 static const struct NVOC_RTTI __nvoc_rtti_KernelCE_IntrService = { 48 /*pClassDef=*/ &__nvoc_class_def_IntrService, 49 /*dtor=*/ &__nvoc_destructFromBase, 50 /*offset=*/ NV_OFFSETOF(KernelCE, __nvoc_base_IntrService), 51 }; 52 53 static const struct NVOC_CASTINFO __nvoc_castinfo_KernelCE = { 54 /*numRelatives=*/ 4, 55 /*relatives=*/ { 56 &__nvoc_rtti_KernelCE_KernelCE, 57 &__nvoc_rtti_KernelCE_IntrService, 58 &__nvoc_rtti_KernelCE_OBJENGSTATE, 59 &__nvoc_rtti_KernelCE_Object, 60 }, 61 }; 62 63 const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCE = 64 { 65 /*classInfo=*/ { 66 /*size=*/ sizeof(KernelCE), 67 /*classId=*/ classId(KernelCE), 68 /*providerId=*/ &__nvoc_rtti_provider, 69 #if NV_PRINTF_STRINGS_ALLOWED 70 /*name=*/ "KernelCE", 71 #endif 72 }, 73 /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelCE, 74 /*pCastInfo=*/ &__nvoc_castinfo_KernelCE, 75 /*pExportInfo=*/ &__nvoc_export_info_KernelCE 76 }; 77 78 static NV_STATUS __nvoc_thunk_KernelCE_engstateConstructEngine(OBJGPU *pGpu, struct OBJENGSTATE *pKCe, ENGDESCRIPTOR arg0) { 79 return kceConstructEngine(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); 80 } 81 82 static NvBool __nvoc_thunk_KernelCE_engstateIsPresent(OBJGPU *pGpu, struct OBJENGSTATE *pKCe) { 83 return kceIsPresent(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); 84 } 85 86 static NV_STATUS __nvoc_thunk_KernelCE_engstateStateInitLocked(OBJGPU *arg0, struct OBJENGSTATE *arg1) { 87 return kceStateInitLocked(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); 88 } 89 90 static NV_STATUS __nvoc_thunk_KernelCE_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKCe, NvU32 flags) { 91 return kceStateUnload(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), flags); 92 } 93 94 static NV_STATUS __nvoc_thunk_KernelCE_engstateStateLoad(OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { 95 return kceStateLoad(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg2); 96 } 97 98 static void __nvoc_thunk_KernelCE_engstateStateDestroy(OBJGPU *arg0, struct OBJENGSTATE *arg1) { 99 kceStateDestroy(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); 100 } 101 102 static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[171]) { 103 kceRegisterIntrService(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); 104 } 105 106 static NV_STATUS __nvoc_thunk_KernelCE_intrservServiceNotificationInterrupt(OBJGPU *arg0, struct IntrService *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) { 107 return kceServiceNotificationInterrupt(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); 108 } 109 110 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreLoad(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { 111 return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); 112 } 113 114 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePostUnload(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { 115 return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); 116 } 117 118 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreUnload(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { 119 return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); 120 } 121 122 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateInitUnlocked(POBJGPU pGpu, struct KernelCE *pEngstate) { 123 return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); 124 } 125 126 static void __nvoc_thunk_OBJENGSTATE_kceInitMissing(POBJGPU pGpu, struct KernelCE *pEngstate) { 127 engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); 128 } 129 130 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreInitLocked(POBJGPU pGpu, struct KernelCE *pEngstate) { 131 return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); 132 } 133 134 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreInitUnlocked(POBJGPU pGpu, struct KernelCE *pEngstate) { 135 return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); 136 } 137 138 static NvBool __nvoc_thunk_IntrService_kceClearInterrupt(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceClearInterruptArguments *pParams) { 139 return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelCE_IntrService.offset), pParams); 140 } 141 142 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePostLoad(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { 143 return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); 144 } 145 146 static NvU32 __nvoc_thunk_IntrService_kceServiceInterrupt(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceServiceInterruptArguments *pParams) { 147 return intrservServiceInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelCE_IntrService.offset), pParams); 148 } 149 150 const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCE = 151 { 152 /*numEntries=*/ 0, 153 /*pExportEntries=*/ 0 154 }; 155 156 void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); 157 void __nvoc_dtor_IntrService(IntrService*); 158 void __nvoc_dtor_KernelCE(KernelCE *pThis) { 159 __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 160 __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); 161 PORT_UNREFERENCED_VARIABLE(pThis); 162 } 163 164 void __nvoc_init_dataField_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) { 165 ChipHal *chipHal = &pRmhalspecowner->chipHal; 166 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 167 RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; 168 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 169 PORT_UNREFERENCED_VARIABLE(pThis); 170 PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); 171 PORT_UNREFERENCED_VARIABLE(chipHal); 172 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 173 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 174 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 175 176 // Hal field -- bCcFipsSelfTestRequired 177 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 178 { 179 pThis->bCcFipsSelfTestRequired = ((NvBool)(0 == 0)); 180 } 181 // default 182 else 183 { 184 pThis->bCcFipsSelfTestRequired = ((NvBool)(0 != 0)); 185 } 186 } 187 188 NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); 189 NV_STATUS __nvoc_ctor_IntrService(IntrService* ); 190 NV_STATUS __nvoc_ctor_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) { 191 NV_STATUS status = NV_OK; 192 status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 193 if (status != NV_OK) goto __nvoc_ctor_KernelCE_fail_OBJENGSTATE; 194 status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService); 195 if (status != NV_OK) goto __nvoc_ctor_KernelCE_fail_IntrService; 196 __nvoc_init_dataField_KernelCE(pThis, pRmhalspecowner); 197 goto __nvoc_ctor_KernelCE_exit; // Success 198 199 __nvoc_ctor_KernelCE_fail_IntrService: 200 __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 201 __nvoc_ctor_KernelCE_fail_OBJENGSTATE: 202 __nvoc_ctor_KernelCE_exit: 203 204 return status; 205 } 206 207 static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) { 208 ChipHal *chipHal = &pRmhalspecowner->chipHal; 209 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 210 RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; 211 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 212 PORT_UNREFERENCED_VARIABLE(pThis); 213 PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); 214 PORT_UNREFERENCED_VARIABLE(chipHal); 215 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 216 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 217 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 218 219 pThis->__kceConstructEngine__ = &kceConstructEngine_IMPL; 220 221 // Hal function -- kceIsPresent 222 pThis->__kceIsPresent__ = &kceIsPresent_IMPL; 223 224 pThis->__kceStateInitLocked__ = &kceStateInitLocked_IMPL; 225 226 // Hal function -- kceStateUnload 227 // default 228 pThis->__kceStateUnload__ = &kceStateUnload_56cd7a; 229 230 // Hal function -- kceStateLoad 231 pThis->__kceStateLoad__ = &kceStateLoad_GP100; 232 233 pThis->__kceStateDestroy__ = &kceStateDestroy_IMPL; 234 235 pThis->__kceRegisterIntrService__ = &kceRegisterIntrService_IMPL; 236 237 pThis->__kceServiceNotificationInterrupt__ = &kceServiceNotificationInterrupt_IMPL; 238 239 // Hal function -- kceGetP2PCes 240 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 241 { 242 pThis->__kceGetP2PCes__ = &kceGetP2PCes_GH100; 243 } 244 else 245 { 246 pThis->__kceGetP2PCes__ = &kceGetP2PCes_GV100; 247 } 248 249 // Hal function -- kceGetNvlinkAutoConfigCeValues 250 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 251 { 252 pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_TU102; 253 } 254 else 255 { 256 pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_GA100; 257 } 258 259 // Hal function -- kceGetNvlinkMaxTopoForTable 260 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 261 { 262 pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_GP100; 263 } 264 else 265 { 266 pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_491d52; 267 } 268 269 // Hal function -- kceIsCurrentMaxTopology 270 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 271 { 272 pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_491d52; 273 } 274 else 275 { 276 pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_GA100; 277 } 278 279 // Hal function -- kceGetAutoConfigTableEntry 280 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 281 { 282 pThis->__kceGetAutoConfigTableEntry__ = &kceGetAutoConfigTableEntry_GH100; 283 } 284 else 285 { 286 pThis->__kceGetAutoConfigTableEntry__ = &kceGetAutoConfigTableEntry_GV100; 287 } 288 289 // Hal function -- kceGetPce2lceConfigSize1 290 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 291 { 292 pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA100; 293 } 294 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 295 { 296 pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GH100; 297 } 298 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 299 { 300 pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_TU102; 301 } 302 else 303 { 304 pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA102; 305 } 306 307 // Hal function -- kceGetMappings 308 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 309 { 310 pThis->__kceGetMappings__ = &kceGetMappings_GH100; 311 } 312 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 313 { 314 pThis->__kceGetMappings__ = &kceGetMappings_46f6a7; 315 } 316 else 317 { 318 pThis->__kceGetMappings__ = &kceGetMappings_GA100; 319 } 320 321 // Hal function -- kceMapPceLceForC2C 322 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 323 { 324 pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_GH100; 325 } 326 else 327 { 328 pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_46f6a7; 329 } 330 331 // Hal function -- kceMapPceLceForGRCE 332 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 333 { 334 pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_GH100; 335 } 336 // default 337 else 338 { 339 pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_b3696a; 340 } 341 342 // Hal function -- kceMapPceLceForSysmemLinks 343 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 344 { 345 pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA100; 346 } 347 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ 348 { 349 pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_46f6a7; 350 } 351 else 352 { 353 pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA102; 354 } 355 356 // Hal function -- kceMapPceLceForNvlinkPeers 357 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 358 { 359 pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GH100; 360 } 361 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 362 { 363 pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_46f6a7; 364 } 365 else 366 { 367 pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GA100; 368 } 369 370 // Hal function -- kceGetSysmemSupportedLceMask 371 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 372 { 373 pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA100; 374 } 375 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ 376 { 377 pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_4a4dee; 378 } 379 else 380 { 381 pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA102; 382 } 383 384 // Hal function -- kceMapAsyncLceDefault 385 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 386 { 387 pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GH100; 388 } 389 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 390 { 391 pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_46f6a7; 392 } 393 else 394 { 395 pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GA100; 396 } 397 398 // Hal function -- kceGetNvlinkPeerSupportedLceMask 399 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 400 { 401 pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA100; 402 } 403 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 404 { 405 pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_4a4dee; 406 } 407 else 408 { 409 pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA102; 410 } 411 412 // Hal function -- kceGetGrceSupportedLceMask 413 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 414 { 415 pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA100; 416 } 417 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 418 { 419 pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_4a4dee; 420 } 421 else 422 { 423 pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA102; 424 } 425 426 // Hal function -- kceIsGenXorHigherSupported 427 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 428 { 429 pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GA100; 430 } 431 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 432 { 433 pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GH100; 434 } 435 else 436 { 437 pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_cbe027; 438 } 439 440 // Hal function -- kceApplyGen4orHigherMapping 441 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 442 { 443 pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_GA100; 444 } 445 else 446 { 447 pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_b3696a; 448 } 449 450 pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelCE_engstateConstructEngine; 451 452 pThis->__nvoc_base_OBJENGSTATE.__engstateIsPresent__ = &__nvoc_thunk_KernelCE_engstateIsPresent; 453 454 pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelCE_engstateStateInitLocked; 455 456 pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelCE_engstateStateUnload; 457 458 pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelCE_engstateStateLoad; 459 460 pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelCE_engstateStateDestroy; 461 462 pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelCE_intrservRegisterIntrService; 463 464 pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelCE_intrservServiceNotificationInterrupt; 465 466 pThis->__kceStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreLoad; 467 468 pThis->__kceStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kceStatePostUnload; 469 470 pThis->__kceStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreUnload; 471 472 pThis->__kceStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kceStateInitUnlocked; 473 474 pThis->__kceInitMissing__ = &__nvoc_thunk_OBJENGSTATE_kceInitMissing; 475 476 pThis->__kceStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreInitLocked; 477 478 pThis->__kceStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreInitUnlocked; 479 480 pThis->__kceClearInterrupt__ = &__nvoc_thunk_IntrService_kceClearInterrupt; 481 482 pThis->__kceStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePostLoad; 483 484 pThis->__kceServiceInterrupt__ = &__nvoc_thunk_IntrService_kceServiceInterrupt; 485 } 486 487 void __nvoc_init_funcTable_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) { 488 __nvoc_init_funcTable_KernelCE_1(pThis, pRmhalspecowner); 489 } 490 491 void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); 492 void __nvoc_init_IntrService(IntrService*); 493 void __nvoc_init_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) { 494 pThis->__nvoc_pbase_KernelCE = pThis; 495 pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; 496 pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; 497 pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; 498 __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 499 __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); 500 __nvoc_init_funcTable_KernelCE(pThis, pRmhalspecowner); 501 } 502 503 NV_STATUS __nvoc_objCreate_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 createFlags) 504 { 505 NV_STATUS status; 506 Object *pParentObj = NULL; 507 KernelCE *pThis; 508 RmHalspecOwner *pRmhalspecowner; 509 510 // Assign `pThis`, allocating memory unless suppressed by flag. 511 status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCE), (void**)&pThis, (void**)ppThis); 512 if (status != NV_OK) 513 return status; 514 515 // Zero is the initial value for everything. 516 portMemSet(pThis, 0, sizeof(KernelCE)); 517 518 // Initialize runtime type information. 519 __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCE); 520 521 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; 522 523 // pParent must be a valid object that derives from a halspec owner class. 524 NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); 525 526 // Link the child into the parent unless flagged not to do so. 527 if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) 528 { 529 pParentObj = dynamicCast(pParent, Object); 530 objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); 531 } 532 else 533 { 534 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; 535 } 536 537 if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) 538 pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); 539 NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); 540 541 __nvoc_init_KernelCE(pThis, pRmhalspecowner); 542 status = __nvoc_ctor_KernelCE(pThis, pRmhalspecowner); 543 if (status != NV_OK) goto __nvoc_objCreate_KernelCE_cleanup; 544 545 // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. 546 *ppThis = pThis; 547 548 return NV_OK; 549 550 __nvoc_objCreate_KernelCE_cleanup: 551 552 // Unlink the child from the parent if it was linked above. 553 if (pParentObj != NULL) 554 objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); 555 556 // Do not call destructors here since the constructor already called them. 557 if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) 558 portMemSet(pThis, 0, sizeof(KernelCE)); 559 else 560 { 561 portMemFree(pThis); 562 *ppThis = NULL; 563 } 564 565 // coverity[leaked_storage:FALSE] 566 return status; 567 } 568 569 NV_STATUS __nvoc_objCreateDynamic_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { 570 NV_STATUS status; 571 572 status = __nvoc_objCreate_KernelCE(ppThis, pParent, createFlags); 573 574 return status; 575 } 576 577