1 #define NVOC_KERNEL_GSP_H_PRIVATE_ACCESS_ALLOWED 2 #include "nvoc/runtime.h" 3 #include "nvoc/rtti.h" 4 #include "nvtypes.h" 5 #include "nvport/nvport.h" 6 #include "nvport/inline/util_valist.h" 7 #include "utils/nvassert.h" 8 #include "g_kernel_gsp_nvoc.h" 9 10 #ifdef DEBUG 11 char __nvoc_class_id_uniqueness_check_0x311d4e = 1; 12 #endif 13 14 extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelGsp; 15 16 extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; 17 18 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; 19 20 extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; 21 22 extern const struct NVOC_CLASS_DEF __nvoc_class_def_CrashCatEngine; 23 24 extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelCrashCatEngine; 25 26 extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon; 27 28 void __nvoc_init_KernelGsp(KernelGsp*, RmHalspecOwner* ); 29 void __nvoc_init_funcTable_KernelGsp(KernelGsp*, RmHalspecOwner* ); 30 NV_STATUS __nvoc_ctor_KernelGsp(KernelGsp*, RmHalspecOwner* ); 31 void __nvoc_init_dataField_KernelGsp(KernelGsp*, RmHalspecOwner* ); 32 void __nvoc_dtor_KernelGsp(KernelGsp*); 33 extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelGsp; 34 35 static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_KernelGsp = { 36 /*pClassDef=*/ &__nvoc_class_def_KernelGsp, 37 /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelGsp, 38 /*offset=*/ 0, 39 }; 40 41 static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_Object = { 42 /*pClassDef=*/ &__nvoc_class_def_Object, 43 /*dtor=*/ &__nvoc_destructFromBase, 44 /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), 45 }; 46 47 static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_OBJENGSTATE = { 48 /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, 49 /*dtor=*/ &__nvoc_destructFromBase, 50 /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_OBJENGSTATE), 51 }; 52 53 static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_IntrService = { 54 /*pClassDef=*/ &__nvoc_class_def_IntrService, 55 /*dtor=*/ &__nvoc_destructFromBase, 56 /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_IntrService), 57 }; 58 59 static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_CrashCatEngine = { 60 /*pClassDef=*/ &__nvoc_class_def_CrashCatEngine, 61 /*dtor=*/ &__nvoc_destructFromBase, 62 /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine), 63 }; 64 65 static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_KernelCrashCatEngine = { 66 /*pClassDef=*/ &__nvoc_class_def_KernelCrashCatEngine, 67 /*dtor=*/ &__nvoc_destructFromBase, 68 /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine), 69 }; 70 71 static const struct NVOC_RTTI __nvoc_rtti_KernelGsp_KernelFalcon = { 72 /*pClassDef=*/ &__nvoc_class_def_KernelFalcon, 73 /*dtor=*/ &__nvoc_destructFromBase, 74 /*offset=*/ NV_OFFSETOF(KernelGsp, __nvoc_base_KernelFalcon), 75 }; 76 77 static const struct NVOC_CASTINFO __nvoc_castinfo_KernelGsp = { 78 /*numRelatives=*/ 7, 79 /*relatives=*/ { 80 &__nvoc_rtti_KernelGsp_KernelGsp, 81 &__nvoc_rtti_KernelGsp_KernelFalcon, 82 &__nvoc_rtti_KernelGsp_KernelCrashCatEngine, 83 &__nvoc_rtti_KernelGsp_CrashCatEngine, 84 &__nvoc_rtti_KernelGsp_IntrService, 85 &__nvoc_rtti_KernelGsp_OBJENGSTATE, 86 &__nvoc_rtti_KernelGsp_Object, 87 }, 88 }; 89 90 const struct NVOC_CLASS_DEF __nvoc_class_def_KernelGsp = 91 { 92 /*classInfo=*/ { 93 /*size=*/ sizeof(KernelGsp), 94 /*classId=*/ classId(KernelGsp), 95 /*providerId=*/ &__nvoc_rtti_provider, 96 #if NV_PRINTF_STRINGS_ALLOWED 97 /*name=*/ "KernelGsp", 98 #endif 99 }, 100 /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelGsp, 101 /*pCastInfo=*/ &__nvoc_castinfo_KernelGsp, 102 /*pExportInfo=*/ &__nvoc_export_info_KernelGsp 103 }; 104 105 static NV_STATUS __nvoc_thunk_KernelGsp_engstateConstructEngine(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelGsp, ENGDESCRIPTOR arg0) { 106 return kgspConstructEngine(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); 107 } 108 109 static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[168]) { 110 kgspRegisterIntrService(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_IntrService.offset), pRecords); 111 } 112 113 static NvU32 __nvoc_thunk_KernelGsp_intrservServiceInterrupt(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceServiceInterruptArguments *pParams) { 114 return kgspServiceInterrupt(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_IntrService.offset), pParams); 115 } 116 117 static NV_STATUS __nvoc_thunk_KernelGsp_kflcnResetHw(struct OBJGPU *pGpu, struct KernelFalcon *pKernelGsp) { 118 return kgspResetHw(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelFalcon.offset)); 119 } 120 121 static NvBool __nvoc_thunk_KernelCrashCatEngine_kgspConfigured(struct KernelGsp *arg0) { 122 return kcrashcatEngineConfigured((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset)); 123 } 124 125 static NvU32 __nvoc_thunk_KernelCrashCatEngine_kgspPriRead(struct KernelGsp *arg0, NvU32 offset) { 126 return kcrashcatEnginePriRead((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset); 127 } 128 129 static void __nvoc_thunk_KernelFalcon_kgspRegWrite(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 offset, NvU32 data) { 130 kflcnRegWrite(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelGsp_KernelFalcon.offset), offset, data); 131 } 132 133 static NvU32 __nvoc_thunk_KernelFalcon_kgspMaskDmemAddr(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 addr) { 134 return kflcnMaskDmemAddr(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelGsp_KernelFalcon.offset), addr); 135 } 136 137 static void __nvoc_thunk_OBJENGSTATE_kgspStateDestroy(POBJGPU pGpu, struct KernelGsp *pEngstate) { 138 engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); 139 } 140 141 static void __nvoc_thunk_KernelCrashCatEngine_kgspVprintf(struct KernelGsp *arg0, NvBool bReportStart, const char *fmt, va_list args) { 142 kcrashcatEngineVprintf((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), bReportStart, fmt, args); 143 } 144 145 static NvBool __nvoc_thunk_IntrService_kgspClearInterrupt(struct OBJGPU *pGpu, struct KernelGsp *pIntrService, IntrServiceClearInterruptArguments *pParams) { 146 return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGsp_IntrService.offset), pParams); 147 } 148 149 static void __nvoc_thunk_KernelCrashCatEngine_kgspPriWrite(struct KernelGsp *arg0, NvU32 offset, NvU32 data) { 150 kcrashcatEnginePriWrite((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, data); 151 } 152 153 static void *__nvoc_thunk_KernelCrashCatEngine_kgspMapBufferDescriptor(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc) { 154 return kcrashcatEngineMapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), pBufDesc); 155 } 156 157 static void __nvoc_thunk_KernelCrashCatEngine_kgspSyncBufferDescriptor(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc, NvU32 offset, NvU32 size) { 158 kcrashcatEngineSyncBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), pBufDesc, offset, size); 159 } 160 161 static NvU32 __nvoc_thunk_KernelFalcon_kgspRegRead(struct OBJGPU *pGpu, struct KernelGsp *pKernelFlcn, NvU32 offset) { 162 return kflcnRegRead(pGpu, (struct KernelFalcon *)(((unsigned char *)pKernelFlcn) + __nvoc_rtti_KernelGsp_KernelFalcon.offset), offset); 163 } 164 165 static NvBool __nvoc_thunk_OBJENGSTATE_kgspIsPresent(POBJGPU pGpu, struct KernelGsp *pEngstate) { 166 return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); 167 } 168 169 static void __nvoc_thunk_KernelCrashCatEngine_kgspReadEmem(struct KernelGsp *arg0, NvU64 offset, NvU64 size, void *pBuf) { 170 kcrashcatEngineReadEmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, size, pBuf); 171 } 172 173 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateLoad(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { 174 return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); 175 } 176 177 static const NvU32 *__nvoc_thunk_KernelCrashCatEngine_kgspGetScratchOffsets(struct KernelGsp *arg0, NV_CRASHCAT_SCRATCH_GROUP_ID scratchGroupId) { 178 return kcrashcatEngineGetScratchOffsets((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), scratchGroupId); 179 } 180 181 static void __nvoc_thunk_KernelCrashCatEngine_kgspUnload(struct KernelGsp *arg0) { 182 kcrashcatEngineUnload((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset)); 183 } 184 185 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateUnload(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { 186 return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); 187 } 188 189 static NV_STATUS __nvoc_thunk_IntrService_kgspServiceNotificationInterrupt(struct OBJGPU *pGpu, struct KernelGsp *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { 190 return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGsp_IntrService.offset), pParams); 191 } 192 193 static NvU32 __nvoc_thunk_KernelCrashCatEngine_kgspGetWFL0Offset(struct KernelGsp *arg0) { 194 return kcrashcatEngineGetWFL0Offset((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset)); 195 } 196 197 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateInitLocked(POBJGPU pGpu, struct KernelGsp *pEngstate) { 198 return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); 199 } 200 201 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePreLoad(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { 202 return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); 203 } 204 205 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePostUnload(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { 206 return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); 207 } 208 209 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePreUnload(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { 210 return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); 211 } 212 213 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateInitUnlocked(POBJGPU pGpu, struct KernelGsp *pEngstate) { 214 return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); 215 } 216 217 static void __nvoc_thunk_OBJENGSTATE_kgspInitMissing(POBJGPU pGpu, struct KernelGsp *pEngstate) { 218 engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); 219 } 220 221 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePreInitLocked(POBJGPU pGpu, struct KernelGsp *pEngstate) { 222 return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); 223 } 224 225 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePreInitUnlocked(POBJGPU pGpu, struct KernelGsp *pEngstate) { 226 return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); 227 } 228 229 static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePostLoad(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { 230 return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); 231 } 232 233 static void __nvoc_thunk_KernelCrashCatEngine_kgspUnmapBufferDescriptor(struct KernelGsp *arg0, CrashCatBufferDescriptor *pBufDesc) { 234 kcrashcatEngineUnmapBufferDescriptor((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), pBufDesc); 235 } 236 237 static void __nvoc_thunk_KernelCrashCatEngine_kgspReadDmem(struct KernelGsp *arg0, NvU32 offset, NvU32 size, void *pBuf) { 238 kcrashcatEngineReadDmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, size, pBuf); 239 } 240 241 const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelGsp = 242 { 243 /*numEntries=*/ 0, 244 /*pExportEntries=*/ 0 245 }; 246 247 void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); 248 void __nvoc_dtor_IntrService(IntrService*); 249 void __nvoc_dtor_KernelFalcon(KernelFalcon*); 250 void __nvoc_dtor_KernelGsp(KernelGsp *pThis) { 251 __nvoc_kgspDestruct(pThis); 252 __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 253 __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); 254 __nvoc_dtor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon); 255 PORT_UNREFERENCED_VARIABLE(pThis); 256 } 257 258 void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { 259 ChipHal *chipHal = &pRmhalspecowner->chipHal; 260 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 261 RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; 262 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 263 PORT_UNREFERENCED_VARIABLE(pThis); 264 PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); 265 PORT_UNREFERENCED_VARIABLE(chipHal); 266 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 267 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 268 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 269 270 // Hal field -- bIsTaskIsrQueueRequired 271 pThis->bIsTaskIsrQueueRequired = ((NvBool)(0 != 0)); 272 273 // Hal field -- bPartitionedFmc 274 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 275 { 276 pThis->bPartitionedFmc = ((NvBool)(0 == 0)); 277 } 278 // default 279 else 280 { 281 pThis->bPartitionedFmc = ((NvBool)(0 != 0)); 282 } 283 284 // Hal field -- bScrubberUcodeSupported 285 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ 286 { 287 pThis->bScrubberUcodeSupported = ((NvBool)(0 == 0)); 288 } 289 // default 290 else 291 { 292 pThis->bScrubberUcodeSupported = ((NvBool)(0 != 0)); 293 } 294 295 // Hal field -- fwHeapParamBaseSize 296 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 297 { 298 pThis->fwHeapParamBaseSize = (8 << 20); 299 } 300 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 301 { 302 pThis->fwHeapParamBaseSize = (14 << 20); 303 } 304 305 // Hal field -- bBootGspRmWithBoostClocks 306 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ 307 { 308 pThis->bBootGspRmWithBoostClocks = ((NvBool)(0 == 0)); 309 } 310 // default 311 else 312 { 313 pThis->bBootGspRmWithBoostClocks = ((NvBool)(0 != 0)); 314 } 315 } 316 317 NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); 318 NV_STATUS __nvoc_ctor_IntrService(IntrService* ); 319 NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon* , RmHalspecOwner* ); 320 NV_STATUS __nvoc_ctor_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { 321 NV_STATUS status = NV_OK; 322 status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 323 if (status != NV_OK) goto __nvoc_ctor_KernelGsp_fail_OBJENGSTATE; 324 status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService); 325 if (status != NV_OK) goto __nvoc_ctor_KernelGsp_fail_IntrService; 326 status = __nvoc_ctor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); 327 if (status != NV_OK) goto __nvoc_ctor_KernelGsp_fail_KernelFalcon; 328 __nvoc_init_dataField_KernelGsp(pThis, pRmhalspecowner); 329 goto __nvoc_ctor_KernelGsp_exit; // Success 330 331 __nvoc_ctor_KernelGsp_fail_KernelFalcon: 332 __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); 333 __nvoc_ctor_KernelGsp_fail_IntrService: 334 __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 335 __nvoc_ctor_KernelGsp_fail_OBJENGSTATE: 336 __nvoc_ctor_KernelGsp_exit: 337 338 return status; 339 } 340 341 static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { 342 ChipHal *chipHal = &pRmhalspecowner->chipHal; 343 const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; 344 RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; 345 const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; 346 PORT_UNREFERENCED_VARIABLE(pThis); 347 PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); 348 PORT_UNREFERENCED_VARIABLE(chipHal); 349 PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); 350 PORT_UNREFERENCED_VARIABLE(rmVariantHal); 351 PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); 352 353 pThis->__kgspConstructEngine__ = &kgspConstructEngine_IMPL; 354 355 pThis->__kgspRegisterIntrService__ = &kgspRegisterIntrService_IMPL; 356 357 pThis->__kgspServiceInterrupt__ = &kgspServiceInterrupt_IMPL; 358 359 // Hal function -- kgspConfigureFalcon 360 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 361 { 362 pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; 363 } 364 else 365 { 366 pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; 367 } 368 369 // Hal function -- kgspIsDebugModeEnabled 370 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 371 { 372 pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; 373 } 374 else 375 { 376 pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; 377 } 378 379 // Hal function -- kgspAllocBootArgs 380 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 381 { 382 pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; 383 } 384 else 385 { 386 pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; 387 } 388 389 // Hal function -- kgspFreeBootArgs 390 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 391 { 392 pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; 393 } 394 else 395 { 396 pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; 397 } 398 399 // Hal function -- kgspBootstrapRiscvOSEarly 400 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 401 { 402 pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GH100; 403 } 404 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 405 { 406 pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_TU102; 407 } 408 else 409 { 410 pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GA102; 411 } 412 413 // Hal function -- kgspGetGspRmBootUcodeStorage 414 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 415 { 416 pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GH100; 417 } 418 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 419 { 420 pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; 421 } 422 else 423 { 424 pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; 425 } 426 427 // Hal function -- kgspGetBinArchiveGspRmBoot 428 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 429 { 430 pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA100; 431 } 432 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 433 { 434 pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; 435 } 436 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 437 { 438 pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_TU102; 439 } 440 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ 441 { 442 pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; 443 } 444 else 445 { 446 pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; 447 } 448 449 // Hal function -- kgspGetBinArchiveConcatenatedFMCDesc 450 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 451 { 452 pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_GH100; 453 } 454 else 455 { 456 pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_80f438; 457 } 458 459 // Hal function -- kgspGetBinArchiveConcatenatedFMC 460 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 461 { 462 pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_GH100; 463 } 464 else 465 { 466 pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_80f438; 467 } 468 469 // Hal function -- kgspGetBinArchiveGspRmFmcGfwDebugSigned 470 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 471 { 472 pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; 473 } 474 // default 475 else 476 { 477 pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; 478 } 479 480 // Hal function -- kgspGetBinArchiveGspRmFmcGfwProdSigned 481 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 482 { 483 pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; 484 } 485 // default 486 else 487 { 488 pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; 489 } 490 491 // Hal function -- kgspGetBinArchiveGspRmCcFmcGfwProdSigned 492 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 493 { 494 pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100; 495 } 496 // default 497 else 498 { 499 pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_80f438; 500 } 501 502 // Hal function -- kgspCalculateFbLayout 503 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 504 { 505 pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; 506 } 507 else 508 { 509 pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; 510 } 511 512 // Hal function -- kgspGetNonWprHeapSize 513 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 514 { 515 pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; 516 } 517 else 518 { 519 pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; 520 } 521 522 // Hal function -- kgspExecuteSequencerCommand 523 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 524 { 525 pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; 526 } 527 else 528 { 529 pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; 530 } 531 532 // Hal function -- kgspReadUcodeFuseVersion 533 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ 534 { 535 pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; 536 } 537 else 538 { 539 pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; 540 } 541 542 // Hal function -- kgspResetHw 543 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 544 { 545 pThis->__kgspResetHw__ = &kgspResetHw_GH100; 546 } 547 else 548 { 549 pThis->__kgspResetHw__ = &kgspResetHw_TU102; 550 } 551 552 // Hal function -- kgspIsWpr2Up 553 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 554 { 555 pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_GH100; 556 } 557 else 558 { 559 pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_TU102; 560 } 561 562 // Hal function -- kgspGetFrtsSize 563 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 564 { 565 pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; 566 } 567 else 568 { 569 pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; 570 } 571 572 // Hal function -- kgspGetPrescrubbedTopFbSize 573 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 574 { 575 pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_604eb7; 576 } 577 else 578 { 579 pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623; 580 } 581 582 // Hal function -- kgspExtractVbiosFromRom 583 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 584 { 585 pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; 586 } 587 else 588 { 589 pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; 590 } 591 592 // Hal function -- kgspExecuteFwsecFrts 593 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ 594 { 595 pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_5baef9; 596 } 597 else 598 { 599 pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_TU102; 600 } 601 602 // Hal function -- kgspExecuteFwsecSb 603 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 604 { 605 pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_ac1694; 606 } 607 else 608 { 609 pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_TU102; 610 } 611 612 // Hal function -- kgspExecuteScrubberIfNeeded 613 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ 614 { 615 pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102; 616 } 617 else 618 { 619 pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9; 620 } 621 622 // Hal function -- kgspExecuteBooterLoad 623 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 624 { 625 pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; 626 } 627 else 628 { 629 pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; 630 } 631 632 // Hal function -- kgspExecuteBooterUnloadIfNeeded 633 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 634 { 635 pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; 636 } 637 else 638 { 639 pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; 640 } 641 642 // Hal function -- kgspExecuteHsFalcon 643 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 644 { 645 pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; 646 } 647 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 648 { 649 pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; 650 } 651 else 652 { 653 pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; 654 } 655 656 // Hal function -- kgspWaitForGfwBootOk 657 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 658 { 659 pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; 660 } 661 else 662 { 663 pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; 664 } 665 666 // Hal function -- kgspGetBinArchiveBooterLoadUcode 667 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 668 { 669 pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA100; 670 } 671 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 672 { 673 pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; 674 } 675 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ 676 { 677 pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU116; 678 } 679 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ 680 { 681 pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU102; 682 } 683 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ 684 { 685 pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; 686 } 687 else 688 { 689 pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; 690 } 691 692 // Hal function -- kgspGetBinArchiveBooterUnloadUcode 693 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ 694 { 695 pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA100; 696 } 697 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 698 { 699 pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; 700 } 701 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ 702 { 703 pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU116; 704 } 705 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ 706 { 707 pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU102; 708 } 709 else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ 710 { 711 pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; 712 } 713 else 714 { 715 pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; 716 } 717 718 // Hal function -- kgspGetMinWprHeapSizeMB 719 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 720 { 721 pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_7185bf; 722 } 723 else 724 { 725 pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_cc88c3; 726 } 727 728 // Hal function -- kgspGetMaxWprHeapSizeMB 729 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 730 { 731 pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_ad4e6a; 732 } 733 else 734 { 735 pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_55728f; 736 } 737 738 // Hal function -- kgspGetFwHeapParamOsCarveoutSize 739 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 740 { 741 pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_397f70; 742 } 743 else 744 { 745 pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_4b5307; 746 } 747 748 // Hal function -- kgspInitVgpuPartitionLogging 749 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 750 { 751 pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; 752 } 753 else 754 { 755 pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; 756 } 757 758 // Hal function -- kgspFreeVgpuPartitionLogging 759 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ 760 { 761 pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; 762 } 763 else 764 { 765 pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; 766 } 767 768 // Hal function -- kgspGetSignatureSectionNamePrefix 769 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 770 { 771 pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_GH100; 772 } 773 // default 774 else 775 { 776 pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_789efb; 777 } 778 779 // Hal function -- kgspSetupGspFmcArgs 780 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 781 { 782 pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; 783 } 784 // default 785 else 786 { 787 pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; 788 } 789 790 pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGsp_engstateConstructEngine; 791 792 pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelGsp_intrservRegisterIntrService; 793 794 pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelGsp_intrservServiceInterrupt; 795 796 pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelGsp_kflcnResetHw; 797 798 pThis->__kgspConfigured__ = &__nvoc_thunk_KernelCrashCatEngine_kgspConfigured; 799 800 pThis->__kgspPriRead__ = &__nvoc_thunk_KernelCrashCatEngine_kgspPriRead; 801 802 pThis->__kgspRegWrite__ = &__nvoc_thunk_KernelFalcon_kgspRegWrite; 803 804 pThis->__kgspMaskDmemAddr__ = &__nvoc_thunk_KernelFalcon_kgspMaskDmemAddr; 805 806 pThis->__kgspStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kgspStateDestroy; 807 808 pThis->__kgspVprintf__ = &__nvoc_thunk_KernelCrashCatEngine_kgspVprintf; 809 810 pThis->__kgspClearInterrupt__ = &__nvoc_thunk_IntrService_kgspClearInterrupt; 811 812 pThis->__kgspPriWrite__ = &__nvoc_thunk_KernelCrashCatEngine_kgspPriWrite; 813 814 pThis->__kgspMapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kgspMapBufferDescriptor; 815 816 pThis->__kgspSyncBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kgspSyncBufferDescriptor; 817 818 pThis->__kgspRegRead__ = &__nvoc_thunk_KernelFalcon_kgspRegRead; 819 820 pThis->__kgspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgspIsPresent; 821 822 pThis->__kgspReadEmem__ = &__nvoc_thunk_KernelCrashCatEngine_kgspReadEmem; 823 824 pThis->__kgspStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStateLoad; 825 826 pThis->__kgspGetScratchOffsets__ = &__nvoc_thunk_KernelCrashCatEngine_kgspGetScratchOffsets; 827 828 pThis->__kgspUnload__ = &__nvoc_thunk_KernelCrashCatEngine_kgspUnload; 829 830 pThis->__kgspStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStateUnload; 831 832 pThis->__kgspServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_kgspServiceNotificationInterrupt; 833 834 pThis->__kgspGetWFL0Offset__ = &__nvoc_thunk_KernelCrashCatEngine_kgspGetWFL0Offset; 835 836 pThis->__kgspStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kgspStateInitLocked; 837 838 pThis->__kgspStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreLoad; 839 840 pThis->__kgspStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePostUnload; 841 842 pThis->__kgspStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreUnload; 843 844 pThis->__kgspStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgspStateInitUnlocked; 845 846 pThis->__kgspInitMissing__ = &__nvoc_thunk_OBJENGSTATE_kgspInitMissing; 847 848 pThis->__kgspStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreInitLocked; 849 850 pThis->__kgspStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreInitUnlocked; 851 852 pThis->__kgspStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePostLoad; 853 854 pThis->__kgspUnmapBufferDescriptor__ = &__nvoc_thunk_KernelCrashCatEngine_kgspUnmapBufferDescriptor; 855 856 pThis->__kgspReadDmem__ = &__nvoc_thunk_KernelCrashCatEngine_kgspReadDmem; 857 } 858 859 void __nvoc_init_funcTable_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { 860 __nvoc_init_funcTable_KernelGsp_1(pThis, pRmhalspecowner); 861 } 862 863 void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); 864 void __nvoc_init_IntrService(IntrService*); 865 void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); 866 void __nvoc_init_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { 867 pThis->__nvoc_pbase_KernelGsp = pThis; 868 pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; 869 pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; 870 pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; 871 pThis->__nvoc_pbase_CrashCatEngine = &pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__nvoc_base_CrashCatEngine; 872 pThis->__nvoc_pbase_KernelCrashCatEngine = &pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine; 873 pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; 874 __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); 875 __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); 876 __nvoc_init_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); 877 __nvoc_init_funcTable_KernelGsp(pThis, pRmhalspecowner); 878 } 879 880 NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp **ppThis, Dynamic *pParent, NvU32 createFlags) { 881 NV_STATUS status; 882 Object *pParentObj; 883 KernelGsp *pThis; 884 RmHalspecOwner *pRmhalspecowner; 885 886 status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGsp), (void**)&pThis, (void**)ppThis); 887 if (status != NV_OK) 888 return status; 889 890 portMemSet(pThis, 0, sizeof(KernelGsp)); 891 892 __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGsp); 893 894 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; 895 896 if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) 897 { 898 pParentObj = dynamicCast(pParent, Object); 899 objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); 900 } 901 else 902 { 903 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; 904 } 905 906 if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) 907 pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); 908 NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); 909 910 __nvoc_init_KernelGsp(pThis, pRmhalspecowner); 911 status = __nvoc_ctor_KernelGsp(pThis, pRmhalspecowner); 912 if (status != NV_OK) goto __nvoc_objCreate_KernelGsp_cleanup; 913 914 *ppThis = pThis; 915 916 return NV_OK; 917 918 __nvoc_objCreate_KernelGsp_cleanup: 919 // do not call destructors here since the constructor already called them 920 if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) 921 portMemSet(pThis, 0, sizeof(KernelGsp)); 922 else 923 portMemFree(pThis); 924 925 // coverity[leaked_storage:FALSE] 926 return status; 927 } 928 929 NV_STATUS __nvoc_objCreateDynamic_KernelGsp(KernelGsp **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { 930 NV_STATUS status; 931 932 status = __nvoc_objCreate_KernelGsp(ppThis, pParent, createFlags); 933 934 return status; 935 } 936 937