1 #ifndef _G_OS_NVOC_H_ 2 #define _G_OS_NVOC_H_ 3 #include "nvoc/runtime.h" 4 5 #ifdef __cplusplus 6 extern "C" { 7 #endif 8 9 /* 10 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 11 * SPDX-License-Identifier: MIT 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 28 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 29 * DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include "g_os_nvoc.h" 33 34 35 #ifndef _OS_H_ 36 #define _OS_H_ 37 38 /*! 39 * @file os.h 40 * @brief Interface for Operating System module 41 */ 42 43 /* ------------------------ Core & Library Includes ------------------------- */ 44 #include "core/core.h" 45 #include "containers/btree.h" 46 #include "ctrl/ctrl0073/ctrl0073dfp.h" 47 48 /* ------------------------ SDK & Interface Includes ------------------------ */ 49 #include "nvsecurityinfo.h" 50 #include "nvacpitypes.h" 51 #include "nvimpshared.h" // TODO - should move from sdk to resman/interface 52 #include "nvi2c.h" // TODO - should move from sdk to resman/interface 53 54 /* ------------------------ OS Includes ------------------------------------- */ 55 #include "os/nv_memory_type.h" 56 #include "os/capability.h" 57 58 /* ------------------------ Forward Declarations ---------------------------- */ 59 struct OBJOS; 60 61 #ifndef __NVOC_CLASS_OBJOS_TYPEDEF__ 62 #define __NVOC_CLASS_OBJOS_TYPEDEF__ 63 typedef struct OBJOS OBJOS; 64 #endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */ 65 66 #ifndef __nvoc_class_id_OBJOS 67 #define __nvoc_class_id_OBJOS 0xaa1d70 68 #endif /* __nvoc_class_id_OBJOS */ 69 70 71 72 // 73 // The OS module should NOT depend on RM modules. The only exception is 74 // core/core.h. 75 // 76 // DO NOT ADD INCLUDES TO RM MODULE HEADERS FROM THIS FILE. OS module should be 77 // a leaf module. Dependencies on RM headers in this files results in circular 78 // dependencies as most modules depend on the OS module. 79 // 80 // Ideally, all types used by the OS module's interface are from the SDK, 81 // resman/interface or self-contained within the OS module header. For now, 82 // since the OS module depends on a few RM internal types we forward declare to 83 // avoid the need to pull in headers from across RM. 84 // 85 typedef struct SYS_STATIC_CONFIG SYS_STATIC_CONFIG; 86 typedef struct MEMORY_DESCRIPTOR MEMORY_DESCRIPTOR; 87 typedef struct IOVAMAPPING *PIOVAMAPPING; 88 typedef struct OBJGPUMGR OBJGPUMGR; 89 typedef struct EVENTNOTIFICATION EVENTNOTIFICATION, *PEVENTNOTIFICATION; 90 typedef struct DEVICE_MAPPING DEVICE_MAPPING; 91 typedef void *PUID_TOKEN; 92 typedef struct OBJTMR OBJTMR; 93 typedef struct OBJCL OBJCL; 94 typedef struct _GUID *LPGUID; 95 96 // 97 // Forward declare OS_GPU_INFO type 98 // 99 // TODO - We shouldn't need a special definition per-OS. OS implementations 100 // should use a consistent type 101 // 102 typedef struct nv_state_t OS_GPU_INFO; 103 104 /* ------------------------ OS Interface ------------------------------------ */ 105 106 typedef struct os_wait_queue OS_WAIT_QUEUE; 107 108 // 109 // Defines and Typedefs used by the OS 110 // 111 typedef NvU64 OS_THREAD_HANDLE; 112 113 // 114 // Forward references for OS1HZTIMERENTRY symbols 115 // 116 typedef struct OS1HZTIMERENTRY *POS1HZTIMERENTRY; 117 typedef struct OS1HZTIMERENTRY OS1HZTIMERENTRY; 118 119 // 120 // Simple 1 second callback facility. Schedules the given routine to be called with the supplied data 121 // in approximately 1 second. Might be called from an elevated IRQL. 122 // Unlike the tmr facilities (tmrScheduleCallbackXXX), this does not rely on the hardware. 123 // 124 typedef void (*OS1HZPROC)(OBJGPU *, void *); 125 126 #define NV_OS_1HZ_ONESHOT 0x00000000 127 #define NV_OS_1HZ_REPEAT 0x00000001 128 129 struct OS1HZTIMERENTRY 130 { 131 OS1HZPROC callback; 132 void* data; 133 NvU32 flags; 134 POS1HZTIMERENTRY next; 135 }; 136 137 typedef struct RM_PAGEABLE_SECTION { 138 void *osHandle; // handle returned from OS API 139 void *pDataSection; // pointer to a date inside the target data/bss/const segment 140 } RM_PAGEABLE_SECTION; 141 142 143 // OSSetVideoSource defines 144 #define NV_OS_VIDEO_SOURCE_MCE 0x0 145 #define NV_OS_VIDEO_SOURCE_WINDVR 0x1 146 #define NV_OS_VIDEO_SOURCE_WMP9 0x2 147 #define NV_OS_VIDEO_SOURCE_VMR9 0x3 148 #define NV_OS_VIDEO_SOURCE_WINDVD 0x4 149 150 // OSPollHotkeyState return values 151 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE 0:0 152 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE_NOT_FOUND 0x00000000 153 #define NV_OS_HOTKEY_STATE_DISPLAY_CHANGE_FOUND 0x00000001 154 #define NV_OS_HOTKEY_STATE_SCALE_EVENT 1:1 155 #define NV_OS_HOTKEY_STATE_SCALE_EVENT_NOT_FOUND 0x00000000 156 #define NV_OS_HOTKEY_STATE_SCALE_EVENT_FOUND 0x00000001 157 #define NV_OS_HOTKEY_STATE_LID_EVENT 2:2 158 #define NV_OS_HOTKEY_STATE_LID_EVENT_NOT_FOUND 0x00000000 159 #define NV_OS_HOTKEY_STATE_LID_EVENT_FOUND 0x00000001 160 #define NV_OS_HOTKEY_STATE_POWER_EVENT 3:3 161 #define NV_OS_HOTKEY_STATE_POWER_EVENT_NOT_FOUND 0x00000000 162 #define NV_OS_HOTKEY_STATE_POWER_EVENT_FOUND 0x00000001 163 #define NV_OS_HOTKEY_STATE_DOCK_EVENT 4:4 164 #define NV_OS_HOTKEY_STATE_DOCK_EVENT_NOT_FOUND 0x00000000 165 #define NV_OS_HOTKEY_STATE_DOCK_EVENT_FOUND 0x00000001 166 167 #define MAX_BRIGHTNESS_BCL_ELEMENTS 103 168 169 // ACPI _DOD Bit defines 170 // These bits are defined in the Hybrid SAS 171 #define NV_ACPI_DOD_DISPLAY_OWNER 20:18 172 #define NV_ACPI_DOD_DISPLAY_OWNER_ALL 0x00000000 173 #define NV_ACPI_DOD_DISPLAY_OWNER_MGPU 0x00000001 174 #define NV_ACPI_DOD_DISPLAY_OWNER_DGPU1 0x00000002 175 176 #define NV_OS_ALLOCFLAGS_LOCKPAGES NVBIT(0) 177 #define NV_OS_ALLOCFLAGS_PAGEDPOOL NVBIT(1) 178 #define NV_OS_ALLOCFLAGS_NONPAGEDPOOL 0 179 180 // ACPI 3.0a definitions for requested data length 181 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_128B 0x00000001 182 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_256B 0x00000002 183 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_384B 0x00000003 184 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_512B 0x00000004 185 #define NV_ACPI_DDC_REQUESTED_DATA_LENGTH_DEFAULT 0x00000001 186 187 typedef enum _OS_PEX_RECOVERY_STATUS 188 { 189 OS_PEX_RECOVERY_GPU_RESET_PENDING = 0, 190 OS_PEX_RECOVERY_GPU_RESTORED, 191 OS_PEX_RECOVERY_GPU_REMOVED 192 } OS_PEX_RECOVERY_STATUS; 193 194 // osBugCheck bugcode defines 195 #define OS_BUG_CHECK_BUGCODE_UNKNOWN (0) 196 #define OS_BUG_CHECK_BUGCODE_INTERNAL_TEST (1) 197 #define OS_BUG_CHECK_BUGCODE_BUS (2) 198 #define OS_BUG_CHECK_BUGCODE_ECC_DBE (3) 199 #define OS_BUG_CHECK_BUGCODE_NVLINK_TL_ERR (4) 200 #define OS_BUG_CHECK_BUGCODE_PAGED_SEGMENT (5) 201 #define OS_BUG_CHECK_BUGCODE_BSOD_ON_ASSERT (6) 202 #define OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW (7) 203 #define OS_BUG_CHECK_BUGCODE_LAST OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW 204 205 #define OS_BUG_CHECK_BUGCODE_STR \ 206 { \ 207 "Unknown Error", \ 208 "Nv Internal Testing", \ 209 "Bus Error", \ 210 "Double Bit Error", \ 211 "NVLink TL Error", \ 212 "Invalid Bindata Access", \ 213 "BSOD on Assert or Breakpoint", \ 214 "Display Underflow" \ 215 } 216 217 // Flags needed by OSAllocPagesNode 218 #define OS_ALLOC_PAGES_NODE_NONE 0x0 219 #define OS_ALLOC_PAGES_NODE_SKIP_RECLAIM 0x1 220 221 // 222 // Structures for osPackageRegistry and osUnpackageRegistry 223 // 224 typedef struct PACKED_REGISTRY_ENTRY 225 { 226 NvU32 nameOffset; 227 NvU8 type; 228 NvU32 data; 229 NvU32 length; 230 } PACKED_REGISTRY_ENTRY; 231 232 typedef struct PACKED_REGISTRY_TABLE 233 { 234 NvU32 size; 235 NvU32 numEntries; 236 PACKED_REGISTRY_ENTRY entries[0]; 237 } PACKED_REGISTRY_TABLE; 238 239 // TODO: Merge with NV_REGISTRY_ENTRY_TYPE 240 // 241 // Values for PACKED_REGISTRY_ENTRY::type 242 // 243 #define REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN 0 244 #define REGISTRY_TABLE_ENTRY_TYPE_DWORD 1 245 #define REGISTRY_TABLE_ENTRY_TYPE_BINARY 2 246 #define REGISTRY_TABLE_ENTRY_TYPE_STRING 3 247 248 typedef enum 249 { 250 NV_REGISTRY_ENTRY_TYPE_UNKNOWN = 0, 251 NV_REGISTRY_ENTRY_TYPE_DWORD, 252 NV_REGISTRY_ENTRY_TYPE_BINARY, 253 NV_REGISTRY_ENTRY_TYPE_STRING 254 } nv_reg_type_t; 255 256 /* 257 * nv_reg_entry_t 258 * 259 * regParmStr/regName 260 * Name of key 261 * type 262 * One of nv_reg_type_t enum 263 * data 264 * Integer data of key. Only used with DWORD type 265 * pdata 266 * Pointer to data of key. Only used with BINARY or STRING type 267 * len 268 * Length of pdata buffer. Only used with BINARY or STRING type 269 * next 270 * Next entry in linked list 271 */ 272 typedef struct nv_reg_entry_s 273 { 274 char *regParmStr; 275 NvU32 type; 276 NvU32 data; 277 NvU8 *pdata; 278 NvU32 len; 279 struct nv_reg_entry_s *next; 280 } nv_reg_entry_t; 281 282 /* 283 * OS_DRIVER_BLOCK 284 * 285 * driverStart 286 * CPU VA of where the driver is loaded 287 * unique_id 288 * Debug GUID of the Driver. Used to match with Pdb 289 * age 290 * Additional GUID information 291 * offset 292 * Offset from VA to start of text 293 */ 294 typedef struct { 295 NvP64 driverStart NV_ALIGN_BYTES(8); 296 NvU8 unique_id[16]; 297 NvU32 age; 298 NvU32 offset; 299 } OS_DRIVER_BLOCK; 300 301 // Basic OS interface functions 302 typedef NvU32 OSSetEvent(OBJGPU *, NvP64); 303 typedef NV_STATUS OSEventNotification(OBJGPU *, PEVENTNOTIFICATION, NvU32, void *, NvU32); 304 typedef NV_STATUS OSEventNotificationWithInfo(OBJGPU *, PEVENTNOTIFICATION, NvU32, NvU32, NvU16, void *, NvU32); 305 typedef NV_STATUS OSObjectEventNotification(NvHandle, NvHandle, NvU32, PEVENTNOTIFICATION, NvU32, void *, NvU32); 306 typedef NV_STATUS NV_FORCERESULTCHECK OSAllocPages(MEMORY_DESCRIPTOR *); 307 typedef NV_STATUS NV_FORCERESULTCHECK OSAllocPagesInternal(MEMORY_DESCRIPTOR *); 308 typedef void OSFreePages(MEMORY_DESCRIPTOR *); 309 typedef void OSFreePagesInternal(MEMORY_DESCRIPTOR *); 310 typedef NV_STATUS NV_FORCERESULTCHECK OSLockMem(MEMORY_DESCRIPTOR *); 311 typedef NV_STATUS OSUnlockMem(MEMORY_DESCRIPTOR *); 312 typedef NV_STATUS NV_FORCERESULTCHECK OSMapGPU(OBJGPU *, RS_PRIV_LEVEL, NvU64, NvU64, NvU32, NvP64 *, NvP64 *); 313 typedef void OSUnmapGPU(OS_GPU_INFO *, RS_PRIV_LEVEL, NvP64, NvU64, NvP64); 314 typedef NV_STATUS NV_FORCERESULTCHECK OSNotifyEvent(OBJGPU *, PEVENTNOTIFICATION, NvU32, NvU32, NV_STATUS); 315 typedef NV_STATUS OSReadRegistryString(OBJGPU *, const char *, NvU8 *, NvU32 *); 316 typedef NV_STATUS OSWriteRegistryBinary(OBJGPU *, const char *, NvU8 *, NvU32); 317 typedef NV_STATUS OSWriteRegistryVolatile(OBJGPU *, const char *, NvU8 *, NvU32); 318 typedef NV_STATUS OSReadRegistryVolatile(OBJGPU *, const char *, NvU8 *, NvU32); 319 typedef NV_STATUS OSReadRegistryVolatileSize(OBJGPU *, const char *, NvU32 *); 320 typedef NV_STATUS OSReadRegistryBinary(OBJGPU *, const char *, NvU8 *, NvU32 *); 321 typedef NV_STATUS OSWriteRegistryDword(OBJGPU *, const char *, NvU32); 322 typedef NV_STATUS OSReadRegistryDword(OBJGPU *, const char *, NvU32 *); 323 typedef NV_STATUS OSReadRegistryDwordBase(OBJGPU *, const char *, NvU32 *); 324 typedef NV_STATUS OSReadRegistryStringBase(OBJGPU *, const char *, NvU8 *, NvU32 *); 325 typedef NV_STATUS OSPackageRegistry(OBJGPU *, PACKED_REGISTRY_TABLE *, NvU32 *); 326 typedef NV_STATUS OSUnpackageRegistry(PACKED_REGISTRY_TABLE *); 327 typedef NvBool OSQueueDpc(OBJGPU *); 328 typedef void OSFlushCpuWriteCombineBuffer(void); 329 typedef NV_STATUS OSNumaMemblockSize(NvU64 *); 330 typedef NvBool OSNumaOnliningEnabled(OS_GPU_INFO *); 331 typedef NV_STATUS OSAllocPagesNode(NvS32, NvLength, NvU32, NvU64 *); 332 typedef void OSAllocAcquirePage(NvU64, NvU32); 333 typedef void OSAllocReleasePage(NvU64, NvU32); 334 typedef NvU32 OSGetPageRefcount(NvU64); 335 typedef NvU32 OSCountTailPages(NvU64); 336 typedef NvU64 OSGetPageSize(void); 337 typedef NvU8 OSGetPageShift(void); 338 339 340 // We use osAcquireRmSema to catch "unported" sema code to new lock model 341 typedef NV_STATUS NV_FORCERESULTCHECK OSAcquireRmSema(void *); 342 typedef NvBool NV_FORCERESULTCHECK OSIsRmSemaOwner(void *); 343 344 #define DPC_RELEASE_ALL_GPU_LOCKS (1) 345 #define DPC_RELEASE_SINGLE_GPU_LOCK (2) 346 347 typedef NV_STATUS OSGpuLocksQueueRelease(OBJGPU *pGpu, NvU32 dpcGpuLockRelease); 348 typedef NvU32 OSApiLockAcquireConfigureFlags(NvU32 flags); 349 typedef NV_STATUS NV_FORCERESULTCHECK OSCondAcquireRmSema(void *); 350 typedef NvU32 OSReleaseRmSema(void *, OBJGPU *); 351 352 typedef NvU32 OSGetCpuCount(void); 353 typedef NvU32 OSGetMaximumCoreCount(void); 354 typedef NvU32 OSGetCurrentProcessorNumber(void); 355 typedef NV_STATUS OSDelay(NvU32); 356 typedef NV_STATUS OSDelayUs(NvU32); 357 typedef NV_STATUS OSDelayNs(NvU32); 358 typedef void OSSpinLoop(void); 359 typedef NvU64 OSGetMaxUserVa(void); 360 typedef NvU32 OSGetCpuVaAddrShift(void); 361 typedef NvU32 OSGetCurrentProcess(void); 362 typedef void OSGetCurrentProcessName(char *, NvU32); 363 typedef NvU32 OSGetCurrentPasid(void); 364 typedef NV_STATUS OSGetCurrentThread(OS_THREAD_HANDLE *); 365 typedef NV_STATUS OSAttachToProcess(void **, NvU32); 366 typedef void OSDetachFromProcess(void*); 367 typedef NV_STATUS OSVirtualToPhysicalAddr(MEMORY_DESCRIPTOR *, NvP64, RmPhysAddr *); 368 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryUser(OS_GPU_INFO *, RmPhysAddr, NvU64, NvU32, NvP64 *, NvP64 *, NvU32); 369 typedef void OSUnmapPciMemoryUser(OS_GPU_INFO *, NvP64, NvU64, NvP64); 370 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryKernelOld(OBJGPU *, RmPhysAddr, NvU64, NvU32, void **, NvU32); 371 typedef void OSUnmapPciMemoryKernelOld(OBJGPU *, void *); 372 typedef NV_STATUS NV_FORCERESULTCHECK OSMapPciMemoryKernel64(OBJGPU *, RmPhysAddr, NvU64, NvU32, NvP64 *, NvU32); 373 typedef void OSUnmapPciMemoryKernel64(OBJGPU *, NvP64); 374 typedef NV_STATUS NV_FORCERESULTCHECK OSMapSystemMemory(MEMORY_DESCRIPTOR *, NvU64, NvU64, NvBool, NvU32, NvP64*, NvP64*); 375 typedef void OSUnmapSystemMemory(MEMORY_DESCRIPTOR *, NvBool, NvU32, NvP64, NvP64); 376 typedef NvBool OSLockShouldToggleInterrupts(OBJGPU *); 377 typedef NV_STATUS OSGetPerformanceCounter(NvU64 *); 378 NvBool osDbgBreakpointEnabled(void); 379 typedef NV_STATUS OSAttachGpu(OBJGPU *, void *); 380 typedef NV_STATUS OSDpcAttachGpu(OBJGPU *, void *); 381 typedef void OSDpcDetachGpu(OBJGPU *); 382 typedef NV_STATUS OSHandleGpuLost(OBJGPU *); 383 typedef void OSHandleGpuSurpriseRemoval(OBJGPU *); 384 typedef void OSInitScalabilityOptions(OBJGPU *, void *); 385 typedef void OSHandleDeferredRecovery(OBJGPU *); 386 typedef NvBool OSIsSwPreInitOnly(OS_GPU_INFO *); 387 388 #define NVRM_MAX_FILE_NAME_LENGTH (128) 389 #define NVRM_FILE_ACCESS_READ NVBIT(0) 390 #define NVRM_FILE_ACCESS_WRITE NVBIT(1) 391 392 typedef void OSGetTimeoutParams(OBJGPU *, NvU32 *, NvU32 *, NvU32 *); 393 typedef NvBool OSIsRaisedIRQL(void); 394 typedef NvBool OSIsISR(void); 395 typedef NV_STATUS OSGetDriverBlock(OS_GPU_INFO *, OS_DRIVER_BLOCK *); 396 typedef NvBool OSIsEqualGUID(void *, void *); 397 398 #define OS_QUEUE_WORKITEM_FLAGS_NONE 0x00000000 399 #define OS_QUEUE_WORKITEM_FLAGS_DONT_FREE_PARAMS NVBIT(0) 400 #define OS_QUEUE_WORKITEM_FLAGS_FALLBACK_TO_DPC NVBIT(1) 401 // 402 // Lock flags: 403 // Only one of the LOCK_GPU flags should be provided. If multiple are, 404 // the priority ordering should be GPUS > GROUP_DEVICE > GROUP_SUBDEVICE 405 // 406 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA NVBIT(8) 407 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW NVBIT(9) 408 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RO NVBIT(10) 409 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW NVBIT(11) 410 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RO NVBIT(12) 411 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW NVBIT(13) 412 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RO NVBIT(14) 413 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW NVBIT(15) 414 #define OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RO NVBIT(16) 415 // 416 // Perform a GPU full power sanity after getting GPU locks. 417 // One of the above LOCK_GPU flags must be provided when using this flag. 418 // 419 #define OS_QUEUE_WORKITEM_FLAGS_FULL_GPU_SANITY NVBIT(17) 420 #define OS_QUEUE_WORKITEM_FLAGS_FOR_PM_RESUME NVBIT(18) 421 typedef void OSWorkItemFunction(NvU32 gpuInstance, void *); 422 typedef void OSSystemWorkItemFunction(void *); 423 NV_STATUS osQueueWorkItemWithFlags(OBJGPU *, OSWorkItemFunction, void *, NvU32); 424 425 static NV_INLINE NV_STATUS osQueueWorkItem(OBJGPU *pGpu, OSWorkItemFunction pFunction, void *pParams) 426 { 427 return osQueueWorkItemWithFlags(pGpu, pFunction, pParams, OS_QUEUE_WORKITEM_FLAGS_NONE); 428 } 429 430 NV_STATUS osQueueSystemWorkItem(OSSystemWorkItemFunction, void *); 431 432 // MXM ACPI calls 433 NV_STATUS osCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *); 434 NV_STATUS osCallACPI_DDC(OBJGPU *, NvU32, NvU8*,NvU32*, NvBool); 435 NV_STATUS osCallACPI_BCL(OBJGPU *, NvU32, NvU32 *, NvU16 *); 436 437 // Display MUX ACPI calls 438 NV_STATUS osCallACPI_MXDS(OBJGPU *, NvU32, NvU32 *); 439 NV_STATUS osCallACPI_MXDM(OBJGPU *, NvU32, NvU32 *); 440 NV_STATUS osCallACPI_MXID(OBJGPU *, NvU32, NvU32 *); 441 NV_STATUS osCallACPI_LRST(OBJGPU *, NvU32, NvU32 *); 442 443 // Hybrid GPU ACPI calls 444 NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *, NvU32 *); 445 NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *, NvU32 *); 446 NV_STATUS osCallACPI_NVHG_GPUSTA(OBJGPU *, NvU32 *); 447 NV_STATUS osCallACPI_NVHG_MXDS(OBJGPU *, NvU32, NvU32 *); 448 NV_STATUS osCallACPI_NVHG_MXMX(OBJGPU *, NvU32, NvU32 *); 449 NV_STATUS osCallACPI_NVHG_DOS(OBJGPU *, NvU32, NvU32 *); 450 NV_STATUS osCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *); 451 NV_STATUS osCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *); 452 NV_STATUS osCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *); 453 454 // Tegra ACPI calls 455 NV_STATUS osCallACPI_ON(OBJGPU *, NvU32); 456 NV_STATUS osCallACPI_OFF(OBJGPU *, NvU32); 457 458 // Optimus WMI ACPI calls 459 NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *); 460 461 // Generic ACPI _DSM call 462 NV_STATUS osCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, 463 NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size); 464 465 // UEFI variable calls 466 NV_STATUS osGetUefiVariable(const char *, LPGUID, NvU8 *, NvU32 *); 467 468 // The following functions are also implemented in WinNT 469 void osQADbgRegistryInit(void); 470 typedef NV_STATUS OSGetVersionDump(void *); 471 // End of WinNT 472 473 // OS functions typically only implemented for MacOS core 474 // These next functions also appear on UNIX 475 typedef NvU32 OSnv_rdcr4(struct OBJOS *); 476 typedef NvU64 OSnv_rdxcr0(struct OBJOS *); 477 typedef int OSnv_cpuid(struct OBJOS *, int, int, NvU32 *, NvU32 *, NvU32 *, NvU32 *); 478 // end of functions shared between MacOSX and UNIX 479 480 // These next functions also appear on UNIX 481 typedef NvU32 OSnv_rdmsr(struct OBJOS *, NvU32, NvU32 *, NvU32 *); 482 typedef NvU32 OSnv_wrmsr(struct OBJOS *, NvU32, NvU32, NvU32); 483 // end functions shared by MacOS and UNIX 484 485 // NOTE: The following functions are also implemented in MODS 486 NV_STATUS osSimEscapeWrite(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 Value); 487 NV_STATUS osSimEscapeWriteBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); 488 NV_STATUS osSimEscapeRead(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value); 489 NV_STATUS osSimEscapeReadBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); 490 NvU32 osGetSimulationMode(void); 491 typedef void OSLogString(const char*, ...); 492 typedef void OSFlushLog(void); 493 typedef void OSSetSurfaceName(void *pDescriptor, char *name); 494 495 // End of MODS functions 496 497 //Vista Specific Functions 498 499 NV_STATUS osSetupVBlank(OBJGPU *pGpu, void * pProc, 500 void * pParm1, void * pParm2, NvU32 Head, void * pParm3); 501 502 // Heap reserve tracking functions 503 typedef void OSInternalReserveAllocCallback(NvU64 offset, NvU64 size, NvU32 gpuId); 504 typedef void OSInternalReserveFreeCallback(NvU64 offset, NvU32 gpuId); 505 506 507 // 508 // SPB_GPS (Vista) specific defines 509 // 510 typedef struct 511 { 512 NvU64 cpuFPCounter1; // CPU Fixed Performance Counter 1 513 NvU64 cpuFPCounter2; // CPU Fixed Performance Counter 2 514 NvU64 cpuC0Counter; // C0 Counter 515 NvU64 cpuCoreTSC; // per core Time Stamp Counter value 516 NvU8 cpuCoreC0Value; // average C0 residency per core 517 NvU8 cpuCoreAperf; // CPU Aperf value per core 518 519 }OS_CPU_CORE_PERF_COUNTERS, *POS_CPU_CORE_PERF_COUNTERS; 520 521 typedef NV_STATUS OsGetSystemCpuLogicalCoreCounts(NvU32 *pCpuCoreCount); 522 typedef NV_STATUS OsGetSystemCpuC0AndAPerfCounters(NvU32 coreIndex, POS_CPU_CORE_PERF_COUNTERS pCpuPerfData); 523 typedef void OsEnableCpuPerformanceCounters(struct OBJOS *pOS); 524 typedef NV_STATUS OsCpuDpcObjInit(void **ppCpuDpcObj, OBJGPU *pGpu, NvU32 coreCount); 525 typedef void OsCpuDpcObjQueue(void **ppCpuDpcObj, NvU32 coreCount, POS_CPU_CORE_PERF_COUNTERS pCpuPerfData); 526 typedef void OsCpuDpcObjFree(void **ppCpuDpcObj); 527 typedef NV_STATUS OsSystemGetBatteryDrain(NvS32 *pChargeRate); 528 529 // OSDRIVERERROR structure 530 typedef struct 531 { 532 enum { 533 OS_DRIVER_ERROR_CODE_NONE = 0, 534 OS_DRIVER_ERROR_CODE_HP_GT216_VBIOS_BUG_587560, 535 OS_DRIVER_ERROR_CODE_COUNT, // Must always be last 536 } code; 537 538 union 539 { 540 void *osDriverErrorContextNone; 541 542 } context; 543 544 } OSDRIVERERROR, * POSDRIVERERROR; 545 546 typedef NV_STATUS OSPexRecoveryCallback(OS_GPU_INFO *, OS_PEX_RECOVERY_STATUS); 547 548 // 549 // Function pointer typedef for use as callback prototype when filtering 550 // address ranges in os memory access routines 551 // 552 typedef NV_STATUS (OSMemFilterCb)(void *pPriv, NvU64 addr, void *pData, NvU64 size, NvBool bRead); 553 554 // Structure typedef for storing the callback pointer and priv data 555 typedef struct 556 { 557 NODE node; 558 OSMemFilterCb *pFilterCb; 559 void *pPriv; 560 } OSMEMFILTERDATA, *POSMEMFILTERDATA; 561 562 // 563 // OS Functions typically only implemented for MODS 564 // Note: See comments above for other functions that 565 // are also implemented on MODS as well as other 566 // OS's. 567 // 568 569 typedef NvBool OSRmInitRm(struct OBJOS *); 570 typedef NV_STATUS OSGetPanelStrapAndIndex(struct OBJOS *, OBJGPU *, NvU32 *, NvU32 *); 571 typedef NV_STATUS OSNotifySbiosDisplayChangeEnd(OBJGPU *, NvU32); 572 typedef NvU32 OSGetDfpScalerFromSbios(OBJGPU *); 573 typedef NvU32 OSPollHotkeyState(OBJGPU *); 574 575 typedef NV_STATUS OSInitGpuMgr(OBJGPUMGR *); 576 typedef void OSSyncWithRmDestroy(void); 577 typedef void OSSyncWithGpuDestroy(NvBool); 578 579 typedef void OSModifyGpuSwStatePersistence(OS_GPU_INFO *, NvBool); 580 581 typedef NV_STATUS OSMemAddFilter(NvU64, NvU64, OSMemFilterCb*, void *); 582 typedef NV_STATUS OSMemRemoveFilter(NvU64); 583 typedef POSMEMFILTERDATA OSMemGetFilter(NvUPtr); 584 585 typedef NV_STATUS OSGetCarveoutInfo(NvU64*, NvU64*); 586 typedef NV_STATUS OSGetVPRInfo(NvU64*, NvU64*); 587 typedef NV_STATUS OSAllocInVPR(MEMORY_DESCRIPTOR*); 588 typedef NV_STATUS OSGetGenCarveout(NvU64*, NvU64 *, NvU32, NvU64); 589 590 typedef NvU32 OSPepReadReg(OBJGPU *, NvU32); 591 typedef void OSPepWriteReg(OBJGPU *, NvU32, NvU32); 592 593 typedef NV_STATUS OSI2CClosePorts(OS_GPU_INFO *, NvU32); 594 typedef NV_STATUS OSWriteI2CBufferDirect(OBJGPU *, NvU32, NvU8, void *, NvU32, void *, NvU32); 595 typedef NV_STATUS OSReadI2CBufferDirect(OBJGPU *, NvU32, NvU8, void *, NvU32, void *, NvU32); 596 typedef NV_STATUS OSI2CTransfer(OBJGPU *, NvU32, NvU8, nv_i2c_msg_t *, NvU32); 597 typedef NV_STATUS OSSetGpuRailVoltage(OBJGPU *, NvU32, NvU32*); 598 typedef NV_STATUS OSGetGpuRailVoltage(OBJGPU *, NvU32*); 599 typedef NV_STATUS OSGetGpuRailVoltageInfo(OBJGPU *, NvU32 *, NvU32 *, NvU32 *); 600 typedef NV_STATUS OSTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *); 601 typedef NV_STATUS OSTegraSocEnableDisableRfl(OS_GPU_INFO *, NvBool); 602 typedef NV_STATUS OSTegraAllocateDisplayBandwidth(OS_GPU_INFO *, NvU32, NvU32); 603 604 typedef NV_STATUS OSMemdrvQueryInterface(OS_GPU_INFO *); 605 typedef void OSMemdrvReleaseInterface(void); 606 typedef NV_STATUS OSMemdrvGetAsid(NvU32, NvU32 *); 607 typedef NV_STATUS OSMemdrvGetStreamId(NvU32, NvU32 *); 608 609 typedef NV_STATUS OSGC6PowerControl(OBJGPU *, NvU32, NvU32 *); 610 611 typedef RmPhysAddr OSPageArrayGetPhysAddr(OS_GPU_INFO *pOsGpuInfo, void* pPageData, NvU32 pageIndex); 612 typedef NV_STATUS OSGetChipInfo(OBJGPU *, NvU32*, NvU32*, NvU32*, NvU32*); 613 typedef NV_STATUS OSGetCurrentIrqPrivData(OS_GPU_INFO *, NvU32*); 614 615 typedef enum 616 { 617 RC_CALLBACK_IGNORE, 618 RC_CALLBACK_ISOLATE, 619 RC_CALLBACK_ISOLATE_NO_RESET, 620 } RC_CALLBACK_STATUS; 621 RC_CALLBACK_STATUS osRCCallback(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvU32 *, void *); 622 NvBool osCheckCallback(OBJGPU *); 623 RC_CALLBACK_STATUS osRCCallback_v2(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvBool, NvU32 *, void *); 624 NvBool osCheckCallback_v2(OBJGPU *); 625 typedef NV_STATUS OSReadPFPciConfigInVF(NvU32, NvU32*); 626 627 // Actual definition of the OBJOS structure 628 #ifdef NVOC_OS_H_PRIVATE_ACCESS_ALLOWED 629 #define PRIVATE_FIELD(x) x 630 #else 631 #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) 632 #endif 633 struct OBJOS { 634 const struct NVOC_RTTI *__nvoc_rtti; 635 struct Object __nvoc_base_Object; 636 struct Object *__nvoc_pbase_Object; 637 struct OBJOS *__nvoc_pbase_OBJOS; 638 NvBool PDB_PROP_OS_PAT_UNSUPPORTED; 639 NvBool PDB_PROP_OS_SLI_ALLOWED; 640 NvBool PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED; 641 NvBool PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT; 642 NvBool PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM; 643 NvBool PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED; 644 NvBool PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE; 645 NvBool PDB_PROP_OS_LIMIT_GPU_RESET; 646 NvBool PDB_PROP_OS_SUPPORTS_TDR; 647 NvBool PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI; 648 NvBool PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER; 649 NvBool PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS; 650 NvBool PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS; 651 OSnv_rdcr4 *osNv_rdcr4; 652 OSnv_rdxcr0 *osNv_rdxcr0; 653 OSnv_cpuid *osNv_cpuid; 654 OSnv_rdmsr *osNv_rdmsr; 655 OSnv_wrmsr *osNv_wrmsr; 656 OSRmInitRm *osRmInitRm; 657 OSPexRecoveryCallback *osPexRecoveryCallback; 658 OSInternalReserveAllocCallback *osInternalReserveAllocCallback; 659 OSInternalReserveFreeCallback *osInternalReserveFreeCallback; 660 NvU32 SystemMemorySize; 661 OSPageArrayGetPhysAddr *osPageArrayGetPhysAddr; 662 NvU32 dynamicPowerSupportGpuMask; 663 NvBool bIsSimMods; 664 }; 665 666 #ifndef __NVOC_CLASS_OBJOS_TYPEDEF__ 667 #define __NVOC_CLASS_OBJOS_TYPEDEF__ 668 typedef struct OBJOS OBJOS; 669 #endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */ 670 671 #ifndef __nvoc_class_id_OBJOS 672 #define __nvoc_class_id_OBJOS 0xaa1d70 673 #endif /* __nvoc_class_id_OBJOS */ 674 675 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJOS; 676 677 #define __staticCast_OBJOS(pThis) \ 678 ((pThis)->__nvoc_pbase_OBJOS) 679 680 #ifdef __nvoc_os_h_disabled 681 #define __dynamicCast_OBJOS(pThis) ((OBJOS*)NULL) 682 #else //__nvoc_os_h_disabled 683 #define __dynamicCast_OBJOS(pThis) \ 684 ((OBJOS*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJOS))) 685 #endif //__nvoc_os_h_disabled 686 687 #define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_CAST 688 #define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_NAME PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER 689 #define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_CAST 690 #define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_NAME PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS 691 #define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_CAST 692 #define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_NAME PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM 693 #define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_CAST 694 #define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_NAME PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED 695 #define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_CAST 696 #define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_NAME PDB_PROP_OS_LIMIT_GPU_RESET 697 #define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_CAST 698 #define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_NAME PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT 699 #define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_CAST 700 #define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_NAME PDB_PROP_OS_PAT_UNSUPPORTED 701 #define PDB_PROP_OS_SLI_ALLOWED_BASE_CAST 702 #define PDB_PROP_OS_SLI_ALLOWED_BASE_NAME PDB_PROP_OS_SLI_ALLOWED 703 #define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_CAST 704 #define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_NAME PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS 705 #define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_CAST 706 #define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_NAME PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE 707 #define PDB_PROP_OS_SUPPORTS_TDR_BASE_CAST 708 #define PDB_PROP_OS_SUPPORTS_TDR_BASE_NAME PDB_PROP_OS_SUPPORTS_TDR 709 #define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_CAST 710 #define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_NAME PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI 711 #define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_CAST 712 #define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_NAME PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED 713 714 NV_STATUS __nvoc_objCreateDynamic_OBJOS(OBJOS**, Dynamic*, NvU32, va_list); 715 716 NV_STATUS __nvoc_objCreate_OBJOS(OBJOS**, Dynamic*, NvU32); 717 #define __objCreate_OBJOS(ppNewObj, pParent, createFlags) \ 718 __nvoc_objCreate_OBJOS((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) 719 720 #undef PRIVATE_FIELD 721 722 723 NV_STATUS addProbe(OBJGPU *, NvU32); 724 725 726 typedef NV_STATUS OSFlushCpuCache(void); 727 typedef void OSAddRecordForCrashLog(void *, NvU32); 728 typedef void OSDeleteRecordForCrashLog(void *); 729 730 OSFlushCpuCache osFlushCpuCache; 731 OSAddRecordForCrashLog osAddRecordForCrashLog; 732 OSDeleteRecordForCrashLog osDeleteRecordForCrashLog; 733 734 735 // 736 // This file should only contain the most common OS functions that provide 737 // direct call. Ex. osDelay, osIsAdministrator 738 // 739 NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo); 740 NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo); 741 NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo); 742 NV_STATUS osTegraSocBpmpSendMrq(OS_GPU_INFO *pOsGpuInfo, 743 NvU32 mrq, 744 const void *pRequestData, 745 NvU32 requestDataSize, 746 void *pResponseData, 747 NvU32 responseDataSize, 748 NvS32 *pRet, 749 NvS32 *pApiRet); 750 NV_STATUS osTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *pTegraImpImportData); 751 NV_STATUS osTegraSocEnableDisableRfl(OS_GPU_INFO *pOsGpuInfo, NvBool bEnable); 752 NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo, 753 NvU32 averageBandwidthKBPS, 754 NvU32 floorBandwidthKBPS); 755 756 NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid); 757 NvBool osIsAdministrator(void); 758 NvBool osAllowPriorityOverride(void); 759 NV_STATUS osGetCurrentTime(NvU32 *pSec,NvU32 *puSec); 760 NV_STATUS osGetCurrentTick(NvU64 *pTimeInNs); 761 NvU64 osGetTickResolution(void); 762 NvU64 osGetTimestamp(void); 763 NvU64 osGetTimestampFreq(void); 764 765 NV_STATUS osDeferredIsr(OBJGPU *pGpu); 766 767 void osEnableInterrupts(OBJGPU *pGpu); 768 769 void osDisableInterrupts(OBJGPU *pGpu, 770 NvBool bIsr); 771 772 void osBugCheck(NvU32 bugCode); 773 void osAssertFailed(void); 774 775 // OS PCI R/W functions 776 void *osPciInitHandle(NvU32 domain, NvU8 bus, NvU8 slot, NvU8 function, 777 NvU16 *pVendor, NvU16 *pDevice); 778 NvU32 osPciReadDword(void *pHandle, NvU32 offset); 779 NvU16 osPciReadWord(void *pHandle, NvU32 offset); 780 NvU8 osPciReadByte(void *pHandle, NvU32 offset); 781 void osPciWriteDword(void *pHandle, NvU32 offset, NvU32 value); 782 void osPciWriteWord(void *pHandle, NvU32 offset, NvU16 value); 783 void osPciWriteByte(void *pHandle, NvU32 offset, NvU8 value); 784 785 // OS RM capabilities calls 786 787 void osRmCapInitDescriptor(NvU64 *pCapDescriptor); 788 NV_STATUS osRmCapAcquire(OS_RM_CAPS *pOsRmCaps, NvU32 rmCap, 789 NvU64 capDescriptor, 790 NvU64 *dupedCapDescriptor); 791 void osRmCapRelease(NvU64 dupedCapDescriptor); 792 NV_STATUS osRmCapRegisterGpu(OS_GPU_INFO *pOsGpuInfo, OS_RM_CAPS **ppOsRmCaps); 793 void osRmCapUnregister(OS_RM_CAPS **ppOsRmCaps); 794 NV_STATUS osRmCapRegisterSmcPartition(OS_RM_CAPS *pGpuOsRmCaps, 795 OS_RM_CAPS **ppPartitionOsRmCaps, 796 NvU32 partitionId); 797 NV_STATUS osRmCapRegisterSmcExecutionPartition( 798 OS_RM_CAPS *pPartitionOsRmCaps, 799 OS_RM_CAPS **ppExecPartitionOsRmCaps, 800 NvU32 execPartitionId); 801 NV_STATUS osRmCapRegisterSys(OS_RM_CAPS **ppOsRmCaps); 802 803 NV_STATUS osGetRandomBytes(NvU8 *pBytes, NvU16 numBytes); 804 805 NV_STATUS osAllocWaitQueue(OS_WAIT_QUEUE **ppWq); 806 void osFreeWaitQueue(OS_WAIT_QUEUE *pWq); 807 void osWaitUninterruptible(OS_WAIT_QUEUE *pWq); 808 void osWaitInterruptible(OS_WAIT_QUEUE *pWq); 809 void osWakeUp(OS_WAIT_QUEUE *pWq); 810 811 NvU32 osGetDynamicPowerSupportMask(void); 812 813 void osUnrefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo); 814 NV_STATUS osRefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo); 815 816 NV_STATUS osIovaMap(PIOVAMAPPING pIovaMapping); 817 void osIovaUnmap(PIOVAMAPPING pIovaMapping); 818 NV_STATUS osGetAtsTargetAddressRange(OBJGPU *pGpu, 819 NvU64 *pAddr, 820 NvU32 *pAddrWidth, 821 NvU32 *pMask, 822 NvU32 *pMaskWidth, 823 NvBool bIsPeer, 824 NvU32 peerIndex); 825 NV_STATUS osGetFbNumaInfo(OBJGPU *pGpu, 826 NvU64 *pAddrPhys, 827 NvS32 *pNodeId); 828 NV_STATUS osGetEgmInfo(OBJGPU *pGpu, 829 NvU64 *pPhysAddr, 830 NvU64 *pSize, 831 NvS32 *pNodeId); 832 NV_STATUS osGetForcedNVLinkConnection(OBJGPU *pGpu, 833 NvU32 maxLinks, 834 NvU32 *pLinkConnection); 835 NV_STATUS osGetForcedC2CConnection(OBJGPU *pGpu, 836 NvU32 maxLinks, 837 NvU32 *pLinkConnection); 838 void osSetNVLinkSysmemLinkState(OBJGPU *pGpu,NvBool enabled); 839 NV_STATUS osGetPlatformNvlinkLinerate(OBJGPU *pGpu,NvU32 *lineRate); 840 const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void); 841 842 void osRemoveGpu(NvU32 domain, NvU8 bus, NvU8 device); 843 NvBool osRemoveGpuSupported(void); 844 845 void initVGXSpecificRegistry(OBJGPU *); 846 847 NV_STATUS osVgpuVfioWake(void *waitQueue); 848 NV_STATUS osVgpuInjectInterrupt(void *pArg1); 849 NV_STATUS osVgpuRegisterMdev(OS_GPU_INFO *pArg1); 850 NV_STATUS osIsVgpuVfioPresent(void); 851 NV_STATUS osIsVfioPciCorePresent(void); 852 NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1); 853 NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection); 854 NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection); 855 856 void osFlushGpuCoherentCpuCacheRange(OS_GPU_INFO *pOsGpuInfo, 857 NvU64 cpuVirtual, 858 NvU64 size); 859 NvBool osUidTokensEqual(PUID_TOKEN arg1, PUID_TOKEN arg2); 860 861 NV_STATUS osValidateClientTokens(PSECURITY_TOKEN arg1, 862 PSECURITY_TOKEN arg2); 863 PUID_TOKEN osGetCurrentUidToken(void); 864 PSECURITY_TOKEN osGetSecurityToken(void); 865 866 NV_STATUS osIsKernelBuffer(void *pArg1, NvU32 arg2); 867 868 NV_STATUS osMapViewToSection(OS_GPU_INFO *pArg1, 869 void *pSectionHandle, 870 void **ppAddress, 871 NvU64 actualSize, 872 NvU64 sectionOffset, 873 NvBool bIommuEnabled); 874 NV_STATUS osUnmapViewFromSection(OS_GPU_INFO *pArg1, 875 void *pAddress, 876 NvBool bIommuEnabled); 877 878 NV_STATUS osOpenTemporaryFile(void **ppFile); 879 void osCloseFile(void *pFile); 880 NV_STATUS osWriteToFile(void *pFile, NvU8 *buffer, 881 NvU64 size, NvU64 offset); 882 NV_STATUS osReadFromFile(void *pFile, NvU8 *buffer, 883 NvU64 size, NvU64 offset); 884 885 NV_STATUS osSrPinSysmem(OS_GPU_INFO *pArg1, 886 NvU64 commitSize, 887 void *pMdl); 888 NV_STATUS osSrUnpinSysmem(OS_GPU_INFO *pArg1); 889 890 void osPagedSegmentAccessCheck(void); 891 892 NV_STATUS osCreateMemFromOsDescriptorInternal(OBJGPU *pGpu, void *pAddress, 893 NvU32 flags, NvU64 size, 894 MEMORY_DESCRIPTOR **ppMemDesc, 895 NvBool bCachedKernel, 896 RS_PRIV_LEVEL privilegeLevel); 897 898 NV_STATUS osReserveCpuAddressSpaceUpperBound(void **ppSectionHandle, 899 NvU64 maxSectionSize); 900 void osReleaseCpuAddressSpaceUpperBound(void *pSectionHandle); 901 902 void* osGetPidInfo(void); 903 void osPutPidInfo(void *pOsPidInfo); 904 NV_STATUS osFindNsPid(void *pOsPidInfo, NvU32 *pNsPid); 905 906 // OS Tegra IPC functions 907 NV_STATUS osTegraDceRegisterIpcClient(NvU32 interfaceType, void *usrCtx, 908 NvU32 *clientId); 909 NV_STATUS osTegraDceClientIpcSendRecv(NvU32 clientId, void *msg, 910 NvU32 msgLength); 911 NV_STATUS osTegraDceUnregisterIpcClient(NvU32 clientId); 912 913 // 914 // Define OS-layer specific type instead of #include "clk_domains.h" for 915 // CLKWHICH, avoids upwards dependency from OS interface on higher level 916 // RM modules 917 // 918 typedef NvU32 OS_CLKWHICH; 919 920 NV_STATUS osTegraSocEnableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM); 921 NV_STATUS osTegraSocDisableClk(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM); 922 NV_STATUS osTegraSocGetCurrFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pCurrFreqKHz); 923 NV_STATUS osTegraSocGetMaxFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pMaxFreqKHz); 924 NV_STATUS osTegraSocGetMinFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 *pMinFreqKHz); 925 NV_STATUS osTegraSocSetFreqKHz(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRM, NvU32 reqFreqKHz); 926 NV_STATUS osTegraSocSetParent(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRMsource, OS_CLKWHICH whichClkRMparent); 927 NV_STATUS osTegraSocGetParent(OS_GPU_INFO *pOsGpuInfo, OS_CLKWHICH whichClkRMsource, OS_CLKWHICH *pWhichClkRMparent); 928 929 NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo); 930 NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo); 931 NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo); 932 NV_STATUS osGetSyncpointAperture(OS_GPU_INFO *pOsGpuInfo, 933 NvU32 syncpointId, 934 NvU64 *physAddr, 935 NvU64 *limit, 936 NvU32 *offset); 937 NV_STATUS osTegraI2CGetBusState(OS_GPU_INFO *pOsGpuInfo, NvU32 port, NvS32 *scl, NvS32 *sda); 938 NV_STATUS osTegraSocParseFixedModeTimings(OS_GPU_INFO *pOsGpuInfo, 939 NvU32 dcbIndex, 940 NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pTimingsPerStream, 941 NvU8 *pNumTimings); 942 943 NV_STATUS osGetVersion(NvU32 *pMajorVer, 944 NvU32 *pMinorVer, 945 NvU32 *pBuildNum, 946 NvU16 *pServicePackMaj, 947 NvU16 *pProductType); 948 949 NvBool osGrService(OS_GPU_INFO *pOsGpuInfo, NvU32 grIdx, NvU32 intr, NvU32 nstatus, NvU32 addr, NvU32 dataLo); 950 951 NvBool osDispService(NvU32 Intr0, NvU32 Intr1); 952 953 NV_STATUS osReferenceObjectCount(void *pEvent); 954 955 NV_STATUS osDereferenceObjectCount(void *pEvent); 956 957 // 958 // Perform OS-specific error logging. 959 // Like libc's vsnprintf(), osErrorLogV() invalidates its va_list argument. The va_list argument 960 // may not be reused after osErrorLogV() returns. If the va_list is needed after the 961 // osErrorLogV() call, create a copy of the va_list using va_copy(). 962 // The caller controls the lifetime of the va_list argument, and should free it using va_end. 963 // 964 void osErrorLogV(OBJGPU *pGpu, NvU32 num, const char * pFormat, va_list arglist); 965 void osErrorLog(OBJGPU *pGpu, NvU32 num, const char* pFormat, ...); 966 967 NV_STATUS osNvifInitialize(OBJGPU *pGpu); 968 969 NV_STATUS osNvifMethod(OBJGPU *pGpu, NvU32 func, 970 NvU32 subFunc, void *pInParam, 971 NvU16 inParamSize, NvU32 *pOutStatus, 972 void *pOutData, NvU16 *pOutDataSize); 973 974 NV_STATUS osCreateMemFromOsDescriptor(OBJGPU *pGpu, NvP64 pDescriptor, 975 NvHandle hClient, NvU32 flags, 976 NvU64 *pLimit, 977 MEMORY_DESCRIPTOR **ppMemDesc, 978 NvU32 descriptorType, 979 RS_PRIV_LEVEL privilegeLevel); 980 981 void* osMapKernelSpace(RmPhysAddr Start, 982 NvU64 Size, 983 NvU32 Mode, 984 NvU32 Protect); 985 986 void osUnmapKernelSpace(void *addr, NvU64 size); 987 988 989 void *osMapIOSpace(RmPhysAddr start, 990 NvU64 size_bytes, 991 void ** priv, 992 NvU32 user, 993 NvU32 mode, 994 NvU32 Protect); 995 996 void osUnmapIOSpace(void *pAddress, 997 NvU64 Size, 998 void *pData, 999 NvU32 User); 1000 1001 NvBool osTestPcieExtendedConfigAccess(void *handle, NvU32 offset); 1002 1003 NvU32 osGetCpuFrequency(void); 1004 1005 void osIoWriteByte(NvU32 Address, NvU8 Value); 1006 1007 NvU8 osIoReadByte(NvU32 Address); 1008 1009 void osIoWriteWord(NvU32 Address, NvU16 Value); 1010 1011 NvU16 osIoReadWord(NvU32 Address); 1012 1013 void osIoWriteDword(NvU32 port, NvU32 data); 1014 1015 NvU32 osIoReadDword(NvU32 port); 1016 1017 // OS functions to get memory pages 1018 1019 NV_STATUS osGetNumMemoryPages (MEMORY_DESCRIPTOR *pMemDesc, NvU32 *pNumPages); 1020 NV_STATUS osGetMemoryPages (MEMORY_DESCRIPTOR *pMemDesc, void *pPages, NvU32 *pNumPages); 1021 1022 NV_STATUS osGetAcpiTable(NvU32 tableSignature, 1023 void **ppTable, 1024 NvU32 tableSize, 1025 NvU32 *retSize); 1026 1027 NV_STATUS osInitGetAcpiTable(void); 1028 1029 // Read NvGlobal regkey 1030 NV_STATUS osGetNvGlobalRegistryDword(OBJGPU *, const char *pRegParmStr, NvU32 *pData); 1031 1032 NV_STATUS osGetIbmnpuGenregInfo(OS_GPU_INFO *pArg1, 1033 NvU64 *pArg2, 1034 NvU64 *pArg3); 1035 1036 NV_STATUS osGetIbmnpuRelaxedOrderingMode(OS_GPU_INFO *pArg1, 1037 NvBool *pArg2); 1038 1039 void osWaitForIbmnpuRsync(OS_GPU_INFO *pArg1); 1040 1041 NV_STATUS osGetAcpiRsdpFromUefi(NvU32 *pRsdpAddr); 1042 1043 NV_STATUS osCreateNanoTimer(OS_GPU_INFO *pArg1, 1044 void *tmrEvent, 1045 void **tmrUserData); 1046 1047 NV_STATUS osStartNanoTimer(OS_GPU_INFO *pArg1, 1048 void *pTimer, 1049 NvU64 timeNs); 1050 1051 NV_STATUS osCancelNanoTimer(OS_GPU_INFO *pArg1, 1052 void *pArg2); 1053 1054 NV_STATUS osDestroyNanoTimer(OS_GPU_INFO *pArg1, 1055 void *pArg2); 1056 1057 NV_STATUS osGetValidWindowHeadMask(OS_GPU_INFO *pArg1, 1058 NvU64 *pWindowHeadMask); 1059 1060 NV_STATUS osSchedule(void); 1061 1062 NV_STATUS osDmaMapPages(OS_GPU_INFO *pArg1, 1063 MEMORY_DESCRIPTOR *pMemDesc); 1064 1065 NV_STATUS osDmaUnmapPages(OS_GPU_INFO *pArg1, 1066 MEMORY_DESCRIPTOR *pMemDesc); 1067 1068 void osDmaSetAddressSize(OS_GPU_INFO *pArg1, 1069 NvU32 bits); 1070 1071 void osClientGcoffDisallowRefcount(OS_GPU_INFO *pArg1, 1072 NvBool arg2); 1073 1074 NV_STATUS osTegraSocGpioGetPinState(OS_GPU_INFO *pArg1, 1075 NvU32 arg2, 1076 NvU32 *pArg3); 1077 1078 void osTegraSocGpioSetPinState(OS_GPU_INFO *pArg1, 1079 NvU32 arg2, 1080 NvU32 arg3); 1081 1082 NV_STATUS osTegraSocGpioSetPinDirection(OS_GPU_INFO *pArg1, 1083 NvU32 arg2, 1084 NvU32 arg3); 1085 1086 NV_STATUS osTegraSocGpioGetPinDirection(OS_GPU_INFO *pArg1, 1087 NvU32 arg2, 1088 NvU32 *pArg3); 1089 1090 NV_STATUS osTegraSocGpioGetPinNumber(OS_GPU_INFO *pArg1, 1091 NvU32 arg2, 1092 NvU32 *pArg3); 1093 1094 NV_STATUS osTegraSocGpioGetPinInterruptStatus(OS_GPU_INFO *pArg1, 1095 NvU32 arg2, 1096 NvU32 arg3, 1097 NvBool *pArg4); 1098 1099 NV_STATUS osTegraSocGpioSetPinInterrupt(OS_GPU_INFO *pArg1, 1100 NvU32 arg2, 1101 NvU32 arg3); 1102 1103 NV_STATUS osTegraSocDsiParsePanelProps(OS_GPU_INFO *pArg1, 1104 void *pArg2); 1105 1106 NvBool osTegraSocIsDsiPanelConnected(OS_GPU_INFO *pArg1); 1107 1108 NV_STATUS osTegraSocDsiPanelEnable(OS_GPU_INFO *pArg1, 1109 void *pArg2); 1110 1111 NV_STATUS osTegraSocDsiPanelReset(OS_GPU_INFO *pArg1, 1112 void *pArg2); 1113 1114 void osTegraSocDsiPanelDisable(OS_GPU_INFO *pArg1, 1115 void *pArg2); 1116 1117 void osTegraSocDsiPanelCleanup(OS_GPU_INFO *pArg1, 1118 void *pArg2); 1119 1120 NV_STATUS osTegraSocResetMipiCal(OS_GPU_INFO *pArg1); 1121 1122 NV_STATUS osGetTegraNumDpAuxInstances(OS_GPU_INFO *pArg1, 1123 NvU32 *pArg2); 1124 1125 NvU32 osTegraSocFuseRegRead(NvU32 addr); 1126 1127 typedef void (*osTegraTsecCbFunc)(void*, void*); 1128 1129 NvU32 osTegraSocTsecSendCmd(void* cmd, osTegraTsecCbFunc cbFunc, void* cbContext); 1130 1131 NvU32 osTegraSocTsecEventRegister(osTegraTsecCbFunc cbFunc, void* cbContext, NvBool isInitEvent); 1132 1133 NvU32 osTegraSocTsecEventUnRegister(NvBool isInitEvent); 1134 1135 void* osTegraSocTsecAllocMemDesc(NvU32 numBytes, NvU32 *flcnAddr); 1136 1137 void osTegraSocTsecFreeMemDesc(void *memDesc); 1138 1139 NV_STATUS osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout); 1140 1141 NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pArg1, NvU32, NvU32); 1142 1143 NV_STATUS osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pArg1); 1144 1145 NV_STATUS osGetCurrentIrqPrivData(OS_GPU_INFO *pArg1, 1146 NvU32 *pArg2); 1147 1148 NV_STATUS osGetTegraBrightnessLevel(OS_GPU_INFO *pArg1, 1149 NvU32 *pArg2); 1150 1151 NV_STATUS osSetTegraBrightnessLevel(OS_GPU_INFO *pArg1, 1152 NvU32 arg2); 1153 1154 NvBool osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo); 1155 1156 NvBool osIsVga(OS_GPU_INFO *pArg1, 1157 NvBool bIsGpuPrimaryDevice); 1158 1159 void osInitOSHwInfo(OBJGPU *pGpu); 1160 1161 void osDestroyOSHwInfo(OBJGPU *pGpu); 1162 1163 NV_STATUS osUserHandleToKernelPtr(NvU32 hClient, 1164 NvP64 Handle, 1165 NvP64 *pHandle); 1166 1167 NV_STATUS osGetSmbiosTable(void **pBaseVAddr, NvU64 *pLength, 1168 NvU64 *pNumSubTypes, NvU32 *pVersion); 1169 1170 void osPutSmbiosTable(void *pBaseVAddr, NvU64 length); 1171 1172 NvBool osIsNvswitchPresent(void); 1173 1174 void osQueueMMUFaultHandler(OBJGPU *); 1175 1176 NvBool osIsGpuAccessible(OBJGPU *pGpu); 1177 NvBool osIsGpuShutdown(OBJGPU *pGpu); 1178 1179 NvBool osMatchGpuOsInfo(OBJGPU *pGpu, void *pOsInfo); 1180 1181 void osReleaseGpuOsInfo(void *pOsInfo); 1182 1183 void osGpuWriteReg008(OBJGPU *pGpu, 1184 NvU32 thisAddress, 1185 NvV8 thisValue); 1186 1187 void osDevWriteReg008(OBJGPU *pGpu, 1188 DEVICE_MAPPING *pMapping, 1189 NvU32 thisAddress, 1190 NvV8 thisValue); 1191 1192 NvU8 osGpuReadReg008(OBJGPU *pGpu, 1193 NvU32 thisAddress); 1194 1195 NvU8 osDevReadReg008(OBJGPU *pGpu, 1196 DEVICE_MAPPING *pMapping, 1197 NvU32 thisAddress); 1198 1199 void osGpuWriteReg016(OBJGPU *pGpu, 1200 NvU32 thisAddress, 1201 NvV16 thisValue); 1202 1203 void osDevWriteReg016(OBJGPU *pGpu, 1204 DEVICE_MAPPING *pMapping, 1205 NvU32 thisAddress, 1206 NvV16 thisValue); 1207 1208 NvU16 osGpuReadReg016(OBJGPU *pGpu, 1209 NvU32 thisAddress); 1210 1211 NvU16 osDevReadReg016(OBJGPU *pGpu, 1212 DEVICE_MAPPING *pMapping, 1213 NvU32 thisAddress); 1214 1215 void osGpuWriteReg032(OBJGPU *pGpu, 1216 NvU32 thisAddress, 1217 NvV32 thisValue); 1218 1219 void osDevWriteReg032(OBJGPU *pGpu, 1220 DEVICE_MAPPING *pMapping, 1221 NvU32 thisAddress, 1222 NvV32 thisValue); 1223 1224 NvU32 osGpuReadReg032(OBJGPU *pGpu, 1225 NvU32 thisAddress); 1226 1227 NvU32 osDevReadReg032(OBJGPU *pGpu, 1228 DEVICE_MAPPING *pMapping, 1229 NvU32 thisAddress); 1230 1231 NV_STATUS osIsr(OBJGPU *pGpu); 1232 1233 NV_STATUS osSanityTestIsr(OBJGPU *pGpu); 1234 1235 NV_STATUS osInitMapping(OBJGPU *pGpu); 1236 1237 NV_STATUS osVerifySystemEnvironment(OBJGPU *pGpu); 1238 1239 NV_STATUS osSanityTestIsr(OBJGPU *pGpu); 1240 1241 void osAllocatedRmClient(void* pOSInfo); 1242 1243 NV_STATUS osConfigurePcieReqAtomics(OS_GPU_INFO *pOsGpuInfo, NvU32 *pMask); 1244 1245 NvBool osDmabufIsSupported(void); 1246 1247 static NV_INLINE NV_STATUS isrWrapper(NvBool testIntr, OBJGPU *pGpu) 1248 { 1249 // 1250 // If pGpu->testIntr is not true then use original osIsr function. 1251 // On VMware Esxi 6.0, both rm isr and dpc handlers are called from Esxi 6.0 1252 // dpc handler. Because of this when multiple GPU are present in the system, 1253 // we may get a call to rm_isr routine for a hw interrupt corresponding to a 1254 // previously initialized GPU. In that case we need to call original osIsr 1255 // function. 1256 // 1257 1258 NV_STATUS status = NV_OK; 1259 1260 if (testIntr) 1261 { 1262 status = osSanityTestIsr(pGpu); 1263 } 1264 else 1265 { 1266 status = osIsr(pGpu); 1267 } 1268 1269 return status; 1270 } 1271 1272 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_32 NVBIT(0) 1273 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_64 NVBIT(1) 1274 #define OS_PCIE_CAP_MASK_REQ_ATOMICS_128 NVBIT(2) 1275 1276 void osGetNumaMemoryUsage(NvS32 numaId, NvU64 *free_memory_bytes, NvU64 *total_memory_bytes); 1277 1278 NV_STATUS osNumaAddGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, 1279 NvU64 size, NvU32 *pNumaNodeId); 1280 void osNumaRemoveGpuMemory(OS_GPU_INFO *pOsGpuInfo, NvU64 offset, 1281 NvU64 size, NvU32 numaNodeId); 1282 1283 NV_STATUS osOfflinePageAtAddress(NvU64 address); 1284 1285 // Os 1Hz timer callback functions 1286 NV_STATUS osInit1HzCallbacks(OBJTMR *pTmr); 1287 NV_STATUS osDestroy1HzCallbacks(OBJTMR *pTmr); 1288 NV_STATUS osSchedule1SecondCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData, NvU32 flags); 1289 void osRemove1SecondRepeatingCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData); 1290 NvBool osRun1HzCallbacksNow(OBJGPU *pGpu); 1291 NV_STATUS osDoFunctionLevelReset(OBJGPU *pGpu); 1292 1293 void vgpuDevWriteReg032( 1294 OBJGPU *pGpu, 1295 NvU32 thisAddress, 1296 NvV32 thisValue, 1297 NvBool *vgpuHandled 1298 ); 1299 1300 NvU32 vgpuDevReadReg032( 1301 OBJGPU *pGpu, 1302 NvU32 thisAddress, 1303 NvBool *vgpuHandled 1304 ); 1305 1306 void osInitSystemStaticConfig(SYS_STATIC_CONFIG *); 1307 1308 void osDbgBugCheckOnAssert(void); 1309 1310 NvBool osBugCheckOnTimeoutEnabled(void); 1311 1312 // 1313 // TODO: to clean-up the rest of the list 1314 // 1315 OSAttachGpu osAttachGpu; 1316 OSDpcAttachGpu osDpcAttachGpu; 1317 OSDpcDetachGpu osDpcDetachGpu; 1318 OSHandleGpuLost osHandleGpuLost; 1319 OSHandleGpuSurpriseRemoval osHandleGpuSurpriseRemoval; 1320 OSInitScalabilityOptions osInitScalabilityOptions; 1321 OSQueueDpc osQueueDpc; 1322 OSRmInitRm osRmInitRm; 1323 OSSetEvent osSetEvent; 1324 OSEventNotification osEventNotification; 1325 OSEventNotificationWithInfo osEventNotificationWithInfo; 1326 OSObjectEventNotification osObjectEventNotification; 1327 OSNotifyEvent osNotifyEvent; 1328 OSFlushCpuWriteCombineBuffer osFlushCpuWriteCombineBuffer; 1329 OSDelay osDelay; 1330 OSSpinLoop osSpinLoop; 1331 OSDelayUs osDelayUs; 1332 OSDelayNs osDelayNs; 1333 OSGetCpuCount osGetCpuCount; 1334 OSGetMaximumCoreCount osGetMaximumCoreCount; 1335 OSGetCurrentProcessorNumber osGetCurrentProcessorNumber; 1336 OSGetVersionDump osGetVersionDump; 1337 1338 OSGetMaxUserVa osGetMaxUserVa; 1339 OSGetCpuVaAddrShift osGetCpuVaAddrShift; 1340 OSMemAddFilter osMemAddFilter; 1341 OSMemRemoveFilter osMemRemoveFilter; 1342 OSMemGetFilter osMemGetFilter; 1343 1344 OSAllocPagesInternal osAllocPagesInternal; 1345 OSFreePagesInternal osFreePagesInternal; 1346 1347 OSGetPageSize osGetPageSize; 1348 OSGetPageShift osGetPageShift; 1349 OSNumaMemblockSize osNumaMemblockSize; 1350 OSNumaOnliningEnabled osNumaOnliningEnabled; 1351 OSAllocPagesNode osAllocPagesNode; 1352 OSAllocAcquirePage osAllocAcquirePage; 1353 OSAllocReleasePage osAllocReleasePage; 1354 OSGetPageRefcount osGetPageRefcount; 1355 OSCountTailPages osCountTailPages; 1356 OSVirtualToPhysicalAddr osKernVirtualToPhysicalAddr; 1357 OSLockMem osLockMem; 1358 OSUnlockMem osUnlockMem; 1359 OSMapSystemMemory osMapSystemMemory; 1360 OSUnmapSystemMemory osUnmapSystemMemory; 1361 OSWriteRegistryDword osWriteRegistryDword; 1362 OSReadRegistryDword osReadRegistryDword; 1363 OSReadRegistryString osReadRegistryString; 1364 OSWriteRegistryBinary osWriteRegistryBinary; 1365 OSWriteRegistryVolatile osWriteRegistryVolatile; 1366 OSReadRegistryVolatile osReadRegistryVolatile; 1367 OSReadRegistryVolatileSize osReadRegistryVolatileSize; 1368 OSReadRegistryBinary osReadRegistryBinary; 1369 OSReadRegistryDwordBase osReadRegistryDwordBase; 1370 OSReadRegistryStringBase osReadRegistryStringBase; 1371 OSPackageRegistry osPackageRegistry; 1372 OSUnpackageRegistry osUnpackageRegistry; 1373 NV_STATUS osDestroyRegistry(void); 1374 nv_reg_entry_t* osGetRegistryList(void); 1375 NV_STATUS osSetRegistryList(nv_reg_entry_t *pRegList); 1376 OSMapPciMemoryUser osMapPciMemoryUser; 1377 OSUnmapPciMemoryUser osUnmapPciMemoryUser; 1378 OSMapPciMemoryKernelOld osMapPciMemoryKernelOld; 1379 OSMapPciMemoryKernel64 osMapPciMemoryKernel64; 1380 OSUnmapPciMemoryKernelOld osUnmapPciMemoryKernelOld; 1381 OSUnmapPciMemoryKernel64 osUnmapPciMemoryKernel64; 1382 OSMapGPU osMapGPU; 1383 OSUnmapGPU osUnmapGPU; 1384 OSLockShouldToggleInterrupts osLockShouldToggleInterrupts; 1385 1386 OSGetPerformanceCounter osGetPerformanceCounter; 1387 1388 OSI2CClosePorts osI2CClosePorts; 1389 OSWriteI2CBufferDirect osWriteI2CBufferDirect; 1390 OSReadI2CBufferDirect osReadI2CBufferDirect; 1391 OSI2CTransfer osI2CTransfer; 1392 OSSetGpuRailVoltage osSetGpuRailVoltage; 1393 OSGetGpuRailVoltage osGetGpuRailVoltage; 1394 OSGetChipInfo osGetChipInfo; 1395 OSGetGpuRailVoltageInfo osGetGpuRailVoltageInfo; 1396 1397 OSGetCurrentProcess osGetCurrentProcess; 1398 OSGetCurrentProcessName osGetCurrentProcessName; 1399 OSGetCurrentThread osGetCurrentThread; 1400 OSAttachToProcess osAttachToProcess; 1401 OSDetachFromProcess osDetachFromProcess; 1402 OSPollHotkeyState osPollHotkeyState; 1403 1404 OSIsRaisedIRQL osIsRaisedIRQL; 1405 OSIsISR osIsISR; 1406 OSGetDriverBlock osGetDriverBlock; 1407 1408 OSInitGpuMgr osInitGpuMgr; 1409 1410 OSSyncWithRmDestroy osSyncWithRmDestroy; 1411 OSSyncWithGpuDestroy osSyncWithGpuDestroy; 1412 1413 OSModifyGpuSwStatePersistence osModifyGpuSwStatePersistence; 1414 1415 OSPexRecoveryCallback osPexRecoveryCallback; 1416 OSHandleDeferredRecovery osHandleDeferredRecovery; 1417 OSIsSwPreInitOnly osIsSwPreInitOnly; 1418 OSGetCarveoutInfo osGetCarveoutInfo; 1419 OSGetVPRInfo osGetVPRInfo; 1420 OSAllocInVPR osAllocInVPR; 1421 OSGetGenCarveout osGetGenCarveout; 1422 OsGetSystemCpuLogicalCoreCounts osGetSystemCpuLogicalCoreCounts; 1423 OsGetSystemCpuC0AndAPerfCounters osGetSystemCpuC0AndAPerfCounters; 1424 OsEnableCpuPerformanceCounters osEnableCpuPerformanceCounters; 1425 OsCpuDpcObjInit osCpuDpcObjInit; 1426 OsCpuDpcObjQueue osCpuDpcObjQueue; 1427 OsCpuDpcObjFree osCpuDpcObjFree; 1428 OsSystemGetBatteryDrain osSystemGetBatteryDrain; 1429 OSGC6PowerControl osGC6PowerControl; 1430 OSReadPFPciConfigInVF osReadPFPciConfigInVF; 1431 1432 // 1433 // When the new basic lock model is enabled then the following legacy RM 1434 // system semaphore routines are stubbed. 1435 // 1436 #define osAllocRmSema(s) (NV_OK) 1437 #define osFreeRmSema(s) 1438 #define osIsAcquiredRmSema(s) (NV_TRUE) 1439 #define osIsRmSemaOwner(s) (NV_TRUE) 1440 #define osCondReleaseRmSema(s) (NV_TRUE) 1441 #define osAcquireRmSemaForced(s) osAcquireRmSema(s) 1442 #define osGpuLockSetOwner(s,t) (NV_OK) 1443 1444 // 1445 // This version of osAcquireRmSema asserts that the GPUs lock is held when the 1446 // basic lock model is enabled. This should help catch newly introduced 1447 // dependencies on the legacy RM system semaphore that do not have 1448 // corresponding corresponding basic lock model support. 1449 // 1450 OSAcquireRmSema osAcquireRmSema; 1451 OSAcquireRmSema osAcquireRmSemaForced; 1452 1453 OSApiLockAcquireConfigureFlags osApiLockAcquireConfigureFlags; 1454 OSGpuLocksQueueRelease osGpuLocksQueueRelease; 1455 OSCondAcquireRmSema osCondAcquireRmSema; 1456 OSReleaseRmSema osReleaseRmSema; 1457 1458 OSFlushLog osFlushLog; 1459 OSSetSurfaceName osSetSurfaceName; 1460 1461 #define MODS_ARCH_ERROR_PRINTF(format, ...) 1462 #define MODS_ARCH_INFO_PRINTF(format, ...) 1463 #define MODS_ARCH_REPORT(event, format, ...) 1464 1465 1466 #define osAllocPages(a) osAllocPagesInternal(a) 1467 #define osFreePages(a) osFreePagesInternal(a) 1468 1469 extern NV_STATUS constructObjOS(struct OBJOS *); 1470 extern void osInitObjOS(struct OBJOS *); 1471 1472 extern OSGetTimeoutParams osGetTimeoutParams; 1473 1474 // 1475 // NV OS simulation mode defines 1476 // Keep in sync with gpu.h SIM MODE defines until osGetSimulationMode is deprecated. 1477 // 1478 #ifndef NV_SIM_MODE_DEFS 1479 #define NV_SIM_MODE_DEFS 1480 #define NV_SIM_MODE_HARDWARE 0U 1481 #define NV_SIM_MODE_RTL 1U 1482 #define NV_SIM_MODE_CMODEL 2U 1483 #define NV_SIM_MODE_MODS_AMODEL 3U 1484 #define NV_SIM_MODE_TEGRA_FPGA 4U 1485 #define NV_SIM_MODE_INVALID (~0x0U) 1486 #endif 1487 1488 // 1489 // NV Heap control defines 1490 // 1491 #define NV_HEAP_CONTROL_INTERNAL 0 1492 #define NV_HEAP_CONTROL_EXTERNAL 1 1493 1494 // osDelayUs flags 1495 #define OSDELAYUS_FLAGS_USE_TMR_DELAY NVBIT(0) 1496 1497 // osEventNotification notifyIndex all value 1498 #define OS_EVENT_NOTIFICATION_INDEX_ALL (0xffffffff) 1499 1500 // tells osEventNotification to only issue notifies/events on this subdev 1501 #define OS_EVENT_NOTIFICATION_INDEX_MATCH_SUBDEV (0x10000000) 1502 1503 // Notify callback action 1504 #define NV_OS_WRITE_THEN_AWAKEN 0x00000001 1505 1506 // 1507 // Include per-OS definitions 1508 // 1509 // #ifdef out for nvoctrans, this hides include to system headers which 1510 // breaks the tool. 1511 // 1512 // TODO - we should delete the per-OS os_custom.h files exposed to 1513 // OS-agnostic code. Cross-OS code shouldn't pull in per-OS headers or 1514 // per-OS definitions. 1515 // 1516 #include "os_custom.h" 1517 1518 #define NV_SEMA_RELEASE_SUCCEED 0 // lock released, no waiting thread to notify 1519 #define NV_SEMA_RELEASE_FAILED 1 // failed to lock release 1520 #define NV_SEMA_RELEASE_NOTIFIED 2 // lock released, notify waiting thread 1521 #define NV_SEMA_RELEASE_DPC_QUEUED 3 // lock released, queue DPC to notify waiting thread 1522 #define NV_SEMA_RELEASE_DPC_FAILED 4 // lock released, but failed to queue a DPC to notify waiting thread 1523 1524 #define ADD_PROBE(pGpu, probeId) 1525 1526 #define IS_SIM_MODS(pOS) (pOS->bIsSimMods) 1527 1528 #endif // _OS_H_ 1529 1530 #ifdef __cplusplus 1531 } // extern "C" 1532 #endif 1533 1534 #endif // _G_OS_NVOC_H_ 1535