1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 /* 24 * WARNING: This is an autogenerated file. DO NOT EDIT. 25 * This file is generated using below files: 26 * template file: kernel/inc/vgpu/gt_rpc-structures.h 27 * definition file: kernel/inc/vgpu/rpc-structures.def 28 */ 29 30 31 #ifdef RPC_STRUCTURES 32 // These structures will be used for the communication between the vmioplugin & guest RM. 33 #define SDK_STRUCTURES 34 #include "g_sdk-structures.h" 35 #undef SDK_STRUCTURES 36 typedef struct rpc_set_guest_system_info_v03_00 37 { 38 NvU32 vgxVersionMajorNum; 39 NvU32 vgxVersionMinorNum; 40 NvU32 guestDriverVersionBufferLength; 41 NvU32 guestVersionBufferLength; 42 NvU32 guestTitleBufferLength; 43 NvU32 guestClNum; 44 char guestDriverVersion[0x100]; 45 char guestVersion[0x100]; 46 char guestTitle[0x100]; 47 } rpc_set_guest_system_info_v03_00; 48 49 typedef rpc_set_guest_system_info_v03_00 rpc_set_guest_system_info_v; 50 51 typedef struct rpc_alloc_memory_v13_01 52 { 53 NvHandle hClient; 54 NvHandle hDevice; 55 NvHandle hMemory; 56 NvU32 hClass; 57 NvU32 flags; 58 NvU32 pteAdjust; 59 NvU32 format; 60 NvU64 length NV_ALIGN_BYTES(8); 61 NvU32 pageCount; 62 struct pte_desc pteDesc; 63 } rpc_alloc_memory_v13_01; 64 65 typedef rpc_alloc_memory_v13_01 rpc_alloc_memory_v; 66 67 typedef struct rpc_free_v03_00 68 { 69 NVOS00_PARAMETERS_v03_00 params; 70 } rpc_free_v03_00; 71 72 typedef rpc_free_v03_00 rpc_free_v; 73 74 typedef struct rpc_map_memory_dma_v03_00 75 { 76 NVOS46_PARAMETERS_v03_00 params; 77 } rpc_map_memory_dma_v03_00; 78 79 typedef rpc_map_memory_dma_v03_00 rpc_map_memory_dma_v; 80 81 typedef struct rpc_unmap_memory_dma_v03_00 82 { 83 NVOS47_PARAMETERS_v03_00 params; 84 } rpc_unmap_memory_dma_v03_00; 85 86 typedef rpc_unmap_memory_dma_v03_00 rpc_unmap_memory_dma_v; 87 88 typedef struct rpc_dup_object_v03_00 89 { 90 NVOS55_PARAMETERS_v03_00 params; 91 } rpc_dup_object_v03_00; 92 93 typedef rpc_dup_object_v03_00 rpc_dup_object_v; 94 95 typedef struct rpc_idle_channels_v03_00 96 { 97 NvU32 flags; 98 NvU32 timeout; 99 NvU32 nchannels; 100 idle_channel_list_v03_00 channel_list[]; 101 } rpc_idle_channels_v03_00; 102 103 typedef rpc_idle_channels_v03_00 rpc_idle_channels_v; 104 105 typedef struct rpc_unloading_guest_driver_v1F_07 106 { 107 NvBool bInPMTransition; 108 NvBool bGc6Entering; 109 NvU32 newLevel; 110 } rpc_unloading_guest_driver_v1F_07; 111 112 typedef rpc_unloading_guest_driver_v1F_07 rpc_unloading_guest_driver_v; 113 114 typedef struct rpc_gpu_exec_reg_ops_v12_01 115 { 116 NvHandle hClient; 117 NvHandle hObject; 118 gpu_exec_reg_ops_v12_01 params; 119 } rpc_gpu_exec_reg_ops_v12_01; 120 121 typedef rpc_gpu_exec_reg_ops_v12_01 rpc_gpu_exec_reg_ops_v; 122 123 typedef struct rpc_set_page_directory_v03_00 124 { 125 NvHandle hClient; 126 NvHandle hDevice; 127 NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00 params; 128 } rpc_set_page_directory_v03_00; 129 130 typedef struct rpc_set_page_directory_v1E_05 131 { 132 NvHandle hClient; 133 NvHandle hDevice; 134 NvU32 pasid; 135 NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 params; 136 } rpc_set_page_directory_v1E_05; 137 138 typedef rpc_set_page_directory_v1E_05 rpc_set_page_directory_v; 139 140 typedef struct rpc_unset_page_directory_v03_00 141 { 142 NvHandle hClient; 143 NvHandle hDevice; 144 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00 params; 145 } rpc_unset_page_directory_v03_00; 146 147 typedef struct rpc_unset_page_directory_v1E_05 148 { 149 NvHandle hClient; 150 NvHandle hDevice; 151 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 params; 152 } rpc_unset_page_directory_v1E_05; 153 154 typedef rpc_unset_page_directory_v1E_05 rpc_unset_page_directory_v; 155 156 typedef struct rpc_get_gsp_static_info_v14_00 157 { 158 NvU32 data; 159 } rpc_get_gsp_static_info_v14_00; 160 161 typedef rpc_get_gsp_static_info_v14_00 rpc_get_gsp_static_info_v; 162 163 typedef struct rpc_update_bar_pde_v15_00 164 { 165 UpdateBarPde_v15_00 info; 166 } rpc_update_bar_pde_v15_00; 167 168 typedef rpc_update_bar_pde_v15_00 rpc_update_bar_pde_v; 169 170 typedef struct rpc_vgpu_pf_reg_read32_v15_00 171 { 172 NvU64 address NV_ALIGN_BYTES(8); 173 NvU32 value; 174 NvU32 grEngId; 175 } rpc_vgpu_pf_reg_read32_v15_00; 176 177 typedef rpc_vgpu_pf_reg_read32_v15_00 rpc_vgpu_pf_reg_read32_v; 178 179 typedef struct rpc_ctrl_subdevice_get_p2p_caps_v21_02 180 { 181 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 ctrlParams; 182 } rpc_ctrl_subdevice_get_p2p_caps_v21_02; 183 184 typedef rpc_ctrl_subdevice_get_p2p_caps_v21_02 rpc_ctrl_subdevice_get_p2p_caps_v; 185 186 typedef struct rpc_ctrl_bus_set_p2p_mapping_v21_03 187 { 188 NvHandle hClient; 189 NvHandle hObject; 190 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 params; 191 } rpc_ctrl_bus_set_p2p_mapping_v21_03; 192 193 typedef rpc_ctrl_bus_set_p2p_mapping_v21_03 rpc_ctrl_bus_set_p2p_mapping_v; 194 195 typedef struct rpc_ctrl_bus_unset_p2p_mapping_v21_03 196 { 197 NvHandle hClient; 198 NvHandle hObject; 199 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 params; 200 } rpc_ctrl_bus_unset_p2p_mapping_v21_03; 201 202 typedef rpc_ctrl_bus_unset_p2p_mapping_v21_03 rpc_ctrl_bus_unset_p2p_mapping_v; 203 204 typedef struct rpc_rmfs_init_v15_00 205 { 206 NvU64 statusQueuePhysAddr NV_ALIGN_BYTES(8); 207 } rpc_rmfs_init_v15_00; 208 209 typedef rpc_rmfs_init_v15_00 rpc_rmfs_init_v; 210 211 typedef struct rpc_rmfs_test_v15_00 212 { 213 NvU32 numReps; 214 NvU32 flags; 215 NvU32 testData1; 216 NvU32 testData2; 217 } rpc_rmfs_test_v15_00; 218 219 typedef rpc_rmfs_test_v15_00 rpc_rmfs_test_v; 220 221 typedef struct rpc_gsp_set_system_info_v17_00 222 { 223 NvU32 data; 224 } rpc_gsp_set_system_info_v17_00; 225 226 typedef rpc_gsp_set_system_info_v17_00 rpc_gsp_set_system_info_v; 227 228 typedef struct rpc_gsp_rm_alloc_v03_00 229 { 230 NvHandle hClient; 231 NvHandle hParent; 232 NvHandle hObject; 233 NvU32 hClass; 234 NvU32 status; 235 NvU32 paramsSize; 236 NvU8 params[]; 237 } rpc_gsp_rm_alloc_v03_00; 238 239 typedef rpc_gsp_rm_alloc_v03_00 rpc_gsp_rm_alloc_v; 240 241 typedef struct rpc_gsp_rm_control_v03_00 242 { 243 NvHandle hClient; 244 NvHandle hObject; 245 NvU32 cmd; 246 NvU32 status; 247 NvU32 paramsSize; 248 NvBool serialized; 249 NvBool copyOutOnError; 250 NvU8 reserved[2]; 251 NvU8 params[]; 252 } rpc_gsp_rm_control_v03_00; 253 254 typedef rpc_gsp_rm_control_v03_00 rpc_gsp_rm_control_v; 255 256 typedef struct rpc_dump_protobuf_component_v18_12 257 { 258 NvU16 component; 259 NvU8 nvDumpType; 260 NvBool countOnly; 261 NvU32 bugCheckCode; 262 NvU32 internalCode; 263 NvU32 bufferSize; 264 NvU8 blob[]; 265 } rpc_dump_protobuf_component_v18_12; 266 267 typedef rpc_dump_protobuf_component_v18_12 rpc_dump_protobuf_component_v; 268 269 typedef struct rpc_run_cpu_sequencer_v17_00 270 { 271 NvU32 bufferSizeDWord; 272 NvU32 cmdIndex; 273 NvU32 regSaveArea[8]; 274 NvU32 commandBuffer[]; 275 } rpc_run_cpu_sequencer_v17_00; 276 277 typedef rpc_run_cpu_sequencer_v17_00 rpc_run_cpu_sequencer_v; 278 279 typedef struct rpc_post_event_v17_00 280 { 281 NvHandle hClient; 282 NvHandle hEvent; 283 NvU32 notifyIndex; 284 NvU32 data; 285 NvU32 status; 286 NvU32 eventDataSize; 287 NvBool bNotifyList; 288 NvU8 eventData[]; 289 } rpc_post_event_v17_00; 290 291 typedef rpc_post_event_v17_00 rpc_post_event_v; 292 293 typedef struct rpc_rc_triggered_v17_02 294 { 295 NvU32 nv2080EngineType; 296 NvU32 chid; 297 NvU32 exceptType; 298 NvU32 scope; 299 NvU16 partitionAttributionId; 300 } rpc_rc_triggered_v17_02; 301 302 typedef rpc_rc_triggered_v17_02 rpc_rc_triggered_v; 303 304 typedef struct rpc_os_error_log_v17_00 305 { 306 NvU32 exceptType; 307 NvU32 runlistId; 308 NvU32 chid; 309 char errString[0x100]; 310 } rpc_os_error_log_v17_00; 311 312 typedef rpc_os_error_log_v17_00 rpc_os_error_log_v; 313 314 typedef struct rpc_rg_line_intr_v17_00 315 { 316 NvU32 head; 317 NvU32 rgIntr; 318 } rpc_rg_line_intr_v17_00; 319 320 typedef rpc_rg_line_intr_v17_00 rpc_rg_line_intr_v; 321 322 typedef struct rpc_display_modeset_v01_00 323 { 324 NvBool bModesetStart; 325 NvU32 minRequiredIsoBandwidthKBPS; 326 NvU32 minRequiredFloorBandwidthKBPS; 327 } rpc_display_modeset_v01_00; 328 329 typedef rpc_display_modeset_v01_00 rpc_display_modeset_v; 330 331 typedef struct rpc_gpuacct_perfmon_util_samples_v17_00 332 { 333 NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00 params; 334 } rpc_gpuacct_perfmon_util_samples_v17_00; 335 336 typedef rpc_gpuacct_perfmon_util_samples_v17_00 rpc_gpuacct_perfmon_util_samples_v; 337 338 typedef struct rpc_vgpu_gsp_plugin_triggered_v17_00 339 { 340 NvU32 gfid; 341 NvU32 notifyIndex; 342 } rpc_vgpu_gsp_plugin_triggered_v17_00; 343 344 typedef rpc_vgpu_gsp_plugin_triggered_v17_00 rpc_vgpu_gsp_plugin_triggered_v; 345 346 typedef struct rpc_vgpu_config_event_v17_00 347 { 348 NvU32 notifyIndex; 349 } rpc_vgpu_config_event_v17_00; 350 351 typedef rpc_vgpu_config_event_v17_00 rpc_vgpu_config_event_v; 352 353 typedef struct rpc_dce_rm_init_v01_00 354 { 355 NvBool bInit; 356 } rpc_dce_rm_init_v01_00; 357 358 typedef rpc_dce_rm_init_v01_00 rpc_dce_rm_init_v; 359 360 typedef struct rpc_sim_read_v1E_01 361 { 362 char path[0x100]; 363 NvU32 index; 364 NvU32 count; 365 } rpc_sim_read_v1E_01; 366 367 typedef rpc_sim_read_v1E_01 rpc_sim_read_v; 368 369 typedef struct rpc_sim_write_v1E_01 370 { 371 char path[0x100]; 372 NvU32 index; 373 NvU32 count; 374 NvU32 data; 375 } rpc_sim_write_v1E_01; 376 377 typedef rpc_sim_write_v1E_01 rpc_sim_write_v; 378 379 typedef struct rpc_ucode_libos_print_v1E_08 380 { 381 NvU32 ucodeEngDesc; 382 NvU32 libosPrintBufSize; 383 NvU8 libosPrintBuf[]; 384 } rpc_ucode_libos_print_v1E_08; 385 386 typedef rpc_ucode_libos_print_v1E_08 rpc_ucode_libos_print_v; 387 388 typedef struct rpc_init_done_v17_00 389 { 390 NvU32 not_used; 391 } rpc_init_done_v17_00; 392 393 typedef rpc_init_done_v17_00 rpc_init_done_v; 394 395 typedef struct rpc_semaphore_schedule_callback_v17_00 396 { 397 NvU64 GPUVA NV_ALIGN_BYTES(8); 398 NvU32 hVASpace; 399 NvU32 ReleaseValue; 400 NvU32 Flags; 401 NvU32 completionStatus; 402 NvHandle hClient; 403 NvHandle hEvent; 404 } rpc_semaphore_schedule_callback_v17_00; 405 406 typedef rpc_semaphore_schedule_callback_v17_00 rpc_semaphore_schedule_callback_v; 407 408 typedef struct rpc_timed_semaphore_release_v01_00 409 { 410 NvU64 semaphoreVA NV_ALIGN_BYTES(8); 411 NvU64 notifierVA NV_ALIGN_BYTES(8); 412 NvU32 hVASpace; 413 NvU32 releaseValue; 414 NvU32 completionStatus; 415 NvHandle hClient; 416 } rpc_timed_semaphore_release_v01_00; 417 418 typedef rpc_timed_semaphore_release_v01_00 rpc_timed_semaphore_release_v; 419 420 typedef struct rpc_perf_gpu_boost_sync_limits_callback_v17_00 421 { 422 NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 params; 423 } rpc_perf_gpu_boost_sync_limits_callback_v17_00; 424 425 typedef rpc_perf_gpu_boost_sync_limits_callback_v17_00 rpc_perf_gpu_boost_sync_limits_callback_v; 426 427 typedef struct rpc_perf_bridgeless_info_update_v17_00 428 { 429 NvU64 bBridgeless NV_ALIGN_BYTES(8); 430 } rpc_perf_bridgeless_info_update_v17_00; 431 432 typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v; 433 434 typedef struct rpc_nvlink_fault_up_v17_00 435 { 436 NvU32 linkId; 437 } rpc_nvlink_fault_up_v17_00; 438 439 typedef rpc_nvlink_fault_up_v17_00 rpc_nvlink_fault_up_v; 440 441 typedef struct rpc_nvlink_inband_received_data_256_v17_00 442 { 443 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 params; 444 } rpc_nvlink_inband_received_data_256_v17_00; 445 446 typedef rpc_nvlink_inband_received_data_256_v17_00 rpc_nvlink_inband_received_data_256_v; 447 448 typedef struct rpc_nvlink_inband_received_data_512_v17_00 449 { 450 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 params; 451 } rpc_nvlink_inband_received_data_512_v17_00; 452 453 typedef rpc_nvlink_inband_received_data_512_v17_00 rpc_nvlink_inband_received_data_512_v; 454 455 typedef struct rpc_nvlink_inband_received_data_1024_v17_00 456 { 457 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 params; 458 } rpc_nvlink_inband_received_data_1024_v17_00; 459 460 typedef rpc_nvlink_inband_received_data_1024_v17_00 rpc_nvlink_inband_received_data_1024_v; 461 462 typedef struct rpc_nvlink_inband_received_data_2048_v17_00 463 { 464 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 params; 465 } rpc_nvlink_inband_received_data_2048_v17_00; 466 467 typedef rpc_nvlink_inband_received_data_2048_v17_00 rpc_nvlink_inband_received_data_2048_v; 468 469 typedef struct rpc_nvlink_inband_received_data_4096_v17_00 470 { 471 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 params; 472 } rpc_nvlink_inband_received_data_4096_v17_00; 473 474 typedef rpc_nvlink_inband_received_data_4096_v17_00 rpc_nvlink_inband_received_data_4096_v; 475 476 typedef struct rpc_nvlink_is_gpu_degraded_v17_00 477 { 478 NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 params; 479 } rpc_nvlink_is_gpu_degraded_v17_00; 480 481 typedef rpc_nvlink_is_gpu_degraded_v17_00 rpc_nvlink_is_gpu_degraded_v; 482 483 typedef struct rpc_gsp_send_user_shared_data_v17_00 484 { 485 NvU32 data; 486 } rpc_gsp_send_user_shared_data_v17_00; 487 488 typedef rpc_gsp_send_user_shared_data_v17_00 rpc_gsp_send_user_shared_data_v; 489 490 typedef struct rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 491 { 492 NvU32 sysmemPfnBitmapRing; 493 NvU32 sysmemPfnBitmapRingHi; 494 NvU32 sysmemPfnBitmap; 495 } rpc_set_sysmem_dirty_page_tracking_buffer_v20_00; 496 497 typedef rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 rpc_set_sysmem_dirty_page_tracking_buffer_v; 498 499 typedef struct rpc_extdev_intr_service_v17_00 500 { 501 NvU8 lossRegStatus; 502 NvU8 gainRegStatus; 503 NvU8 miscRegStatus; 504 NvBool rmStatus; 505 } rpc_extdev_intr_service_v17_00; 506 507 typedef rpc_extdev_intr_service_v17_00 rpc_extdev_intr_service_v; 508 509 typedef struct rpc_pfm_req_hndlr_state_sync_callback_v21_04 510 { 511 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 params; 512 } rpc_pfm_req_hndlr_state_sync_callback_v21_04; 513 514 typedef rpc_pfm_req_hndlr_state_sync_callback_v21_04 rpc_pfm_req_hndlr_state_sync_callback_v; 515 516 typedef struct rpc_gsp_lockdown_notice_v17_00 517 { 518 NvBool bLockdownEngaging; 519 } rpc_gsp_lockdown_notice_v17_00; 520 521 typedef rpc_gsp_lockdown_notice_v17_00 rpc_gsp_lockdown_notice_v; 522 523 524 #endif 525 526 #ifdef RPC_DEBUG_PRINT_STRUCTURES 527 // These are printable definitions of above structures. These will be used for RPC logging in the vmioplugin. 528 #define SDK_DEBUG_PRINT_STRUCTURES 529 #include "g_sdk-structures.h" 530 #undef SDK_DEBUG_PRINT_STRUCTURES 531 532 #ifndef SKIP_PRINT_rpc_nop_v03_00 533 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nop_v03_00[] = { 534 { 535 .vtype = vt_end 536 } 537 }; 538 539 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nop_v03_00 = { 540 .name = "rpc_nop", 541 .fdesc = vmiopd_fdesc_t_rpc_nop_v03_00 542 }; 543 #endif 544 545 #ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00 546 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00[] = { 547 { 548 .vtype = vtype_NvU32, 549 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMajorNum), 550 .name = "vgxVersionMajorNum" 551 }, 552 { 553 .vtype = vtype_NvU32, 554 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMinorNum), 555 .name = "vgxVersionMinorNum" 556 }, 557 { 558 .vtype = vtype_NvU32, 559 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersionBufferLength), 560 .name = "guestDriverVersionBufferLength" 561 }, 562 { 563 .vtype = vtype_NvU32, 564 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersionBufferLength), 565 .name = "guestVersionBufferLength" 566 }, 567 { 568 .vtype = vtype_NvU32, 569 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitleBufferLength), 570 .name = "guestTitleBufferLength" 571 }, 572 { 573 .vtype = vtype_NvU32, 574 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestClNum), 575 .name = "guestClNum" 576 }, 577 { 578 .vtype = vtype_char_array, 579 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersion), 580 .array_length = 0x100, 581 .name = "guestDriverVersion" 582 }, 583 { 584 .vtype = vtype_char_array, 585 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersion), 586 .array_length = 0x100, 587 .name = "guestVersion" 588 }, 589 { 590 .vtype = vtype_char_array, 591 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitle), 592 .array_length = 0x100, 593 .name = "guestTitle" 594 }, 595 { 596 .vtype = vt_end 597 } 598 }; 599 600 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00 = { 601 .name = "rpc_set_guest_system_info", 602 .header_length = NV_SIZEOF32(rpc_set_guest_system_info_v03_00), 603 .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00 604 }; 605 #endif 606 607 #ifndef SKIP_PRINT_rpc_alloc_memory_v13_01 608 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_memory_v13_01[] = { 609 { 610 .vtype = vtype_NvHandle, 611 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClient), 612 .name = "hClient" 613 }, 614 { 615 .vtype = vtype_NvHandle, 616 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hDevice), 617 .name = "hDevice" 618 }, 619 { 620 .vtype = vtype_NvHandle, 621 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hMemory), 622 .name = "hMemory" 623 }, 624 { 625 .vtype = vtype_NvU32, 626 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClass), 627 .name = "hClass" 628 }, 629 { 630 .vtype = vtype_NvU32, 631 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, flags), 632 .name = "flags" 633 }, 634 { 635 .vtype = vtype_NvU32, 636 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteAdjust), 637 .name = "pteAdjust" 638 }, 639 { 640 .vtype = vtype_NvU32, 641 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, format), 642 .name = "format" 643 }, 644 { 645 .vtype = vtype_NvU64, 646 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, length), 647 .name = "length" 648 }, 649 { 650 .vtype = vtype_NvU32, 651 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pageCount), 652 .name = "pageCount" 653 }, 654 { 655 .vtype = vtype_struct_pte_desc, 656 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteDesc), 657 .name = "pteDesc" 658 }, 659 { 660 .vtype = vt_end 661 } 662 }; 663 664 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_memory_v13_01 = { 665 .name = "rpc_alloc_memory", 666 .header_length = NV_SIZEOF32(rpc_alloc_memory_v13_01), 667 .fdesc = vmiopd_fdesc_t_rpc_alloc_memory_v13_01 668 }; 669 #endif 670 671 #ifndef SKIP_PRINT_rpc_free_v03_00 672 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_free_v03_00[] = { 673 { 674 .vtype = vtype_NVOS00_PARAMETERS_v03_00, 675 .offset = NV_OFFSETOF(rpc_free_v03_00, params), 676 .name = "params" 677 }, 678 { 679 .vtype = vt_end 680 } 681 }; 682 683 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_free_v03_00 = { 684 .name = "rpc_free", 685 .header_length = NV_SIZEOF32(rpc_free_v03_00), 686 .fdesc = vmiopd_fdesc_t_rpc_free_v03_00 687 }; 688 #endif 689 690 #ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00 691 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_map_memory_dma_v03_00[] = { 692 { 693 .vtype = vtype_NVOS46_PARAMETERS_v03_00, 694 .offset = NV_OFFSETOF(rpc_map_memory_dma_v03_00, params), 695 .name = "params" 696 }, 697 { 698 .vtype = vt_end 699 } 700 }; 701 702 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_map_memory_dma_v03_00 = { 703 .name = "rpc_map_memory_dma", 704 .header_length = NV_SIZEOF32(rpc_map_memory_dma_v03_00), 705 .fdesc = vmiopd_fdesc_t_rpc_map_memory_dma_v03_00 706 }; 707 #endif 708 709 #ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00 710 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00[] = { 711 { 712 .vtype = vtype_NVOS47_PARAMETERS_v03_00, 713 .offset = NV_OFFSETOF(rpc_unmap_memory_dma_v03_00, params), 714 .name = "params" 715 }, 716 { 717 .vtype = vt_end 718 } 719 }; 720 721 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00 = { 722 .name = "rpc_unmap_memory_dma", 723 .header_length = NV_SIZEOF32(rpc_unmap_memory_dma_v03_00), 724 .fdesc = vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00 725 }; 726 #endif 727 728 #ifndef SKIP_PRINT_rpc_dup_object_v03_00 729 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dup_object_v03_00[] = { 730 { 731 .vtype = vtype_NVOS55_PARAMETERS_v03_00, 732 .offset = NV_OFFSETOF(rpc_dup_object_v03_00, params), 733 .name = "params" 734 }, 735 { 736 .vtype = vt_end 737 } 738 }; 739 740 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dup_object_v03_00 = { 741 .name = "rpc_dup_object", 742 .header_length = NV_SIZEOF32(rpc_dup_object_v03_00), 743 .fdesc = vmiopd_fdesc_t_rpc_dup_object_v03_00 744 }; 745 #endif 746 747 #ifndef SKIP_PRINT_rpc_idle_channels_v03_00 748 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_idle_channels_v03_00[] = { 749 { 750 .vtype = vtype_NvU32, 751 .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, flags), 752 .name = "flags" 753 }, 754 { 755 .vtype = vtype_NvU32, 756 .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, timeout), 757 .name = "timeout" 758 }, 759 { 760 .vtype = vtype_NvU32, 761 .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels), 762 .name = "nchannels" 763 }, 764 { 765 .vtype = vtype_idle_channel_list_v03_00_array, 766 .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, channel_list), 767 .array_length = 0, 768 .array_length_fn = get_array_length_rpc_idle_channels_v03_00_channel_list, 769 .name = "channel_list" 770 }, 771 { 772 .vtype = vt_end 773 } 774 }; 775 776 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_idle_channels_v03_00 = { 777 .name = "rpc_idle_channels", 778 .header_length = NV_SIZEOF32(rpc_idle_channels_v03_00), 779 .fdesc = vmiopd_fdesc_t_rpc_idle_channels_v03_00 780 }; 781 #endif 782 783 #ifndef SKIP_PRINT_rpc_unloading_guest_driver_v03_00 784 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v03_00[] = { 785 { 786 .vtype = vt_end 787 } 788 }; 789 790 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v03_00 = { 791 .name = "rpc_unloading_guest_driver", 792 .fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v03_00 793 }; 794 #endif 795 796 #ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07 797 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = { 798 { 799 .vtype = vtype_NvBool, 800 .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bInPMTransition), 801 .name = "bInPMTransition" 802 }, 803 { 804 .vtype = vtype_NvBool, 805 .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bGc6Entering), 806 .name = "bGc6Entering" 807 }, 808 { 809 .vtype = vtype_NvU32, 810 .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, newLevel), 811 .name = "newLevel" 812 }, 813 { 814 .vtype = vt_end 815 } 816 }; 817 818 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07 = { 819 .name = "rpc_unloading_guest_driver", 820 .header_length = NV_SIZEOF32(rpc_unloading_guest_driver_v1F_07), 821 .fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07 822 }; 823 #endif 824 825 #ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01 826 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01[] = { 827 { 828 .vtype = vtype_NvHandle, 829 .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hClient), 830 .name = "hClient" 831 }, 832 { 833 .vtype = vtype_NvHandle, 834 .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hObject), 835 .name = "hObject" 836 }, 837 { 838 .vtype = vtype_gpu_exec_reg_ops_v12_01, 839 .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, params), 840 .name = "params" 841 }, 842 { 843 .vtype = vt_end 844 } 845 }; 846 847 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01 = { 848 .name = "rpc_gpu_exec_reg_ops", 849 .header_length = NV_SIZEOF32(rpc_gpu_exec_reg_ops_v12_01), 850 .fdesc = vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01 851 }; 852 #endif 853 854 #ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05 855 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v1E_05[] = { 856 { 857 .vtype = vtype_NvHandle, 858 .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hClient), 859 .name = "hClient" 860 }, 861 { 862 .vtype = vtype_NvHandle, 863 .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hDevice), 864 .name = "hDevice" 865 }, 866 { 867 .vtype = vtype_NvU32, 868 .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, pasid), 869 .name = "pasid" 870 }, 871 { 872 .vtype = vtype_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05, 873 .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, params), 874 .name = "params" 875 }, 876 { 877 .vtype = vt_end 878 } 879 }; 880 881 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v1E_05 = { 882 .name = "rpc_set_page_directory", 883 .header_length = NV_SIZEOF32(rpc_set_page_directory_v1E_05), 884 .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v1E_05 885 }; 886 #endif 887 888 #ifndef SKIP_PRINT_rpc_set_page_directory_v03_00 889 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v03_00[] = { 890 { 891 .vtype = vtype_NvHandle, 892 .offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, hClient), 893 .name = "hClient" 894 }, 895 { 896 .vtype = vtype_NvHandle, 897 .offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, hDevice), 898 .name = "hDevice" 899 }, 900 { 901 .vtype = vtype_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00, 902 .offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, params), 903 .name = "params" 904 }, 905 { 906 .vtype = vt_end 907 } 908 }; 909 910 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v03_00 = { 911 .name = "rpc_set_page_directory", 912 .header_length = NV_SIZEOF32(rpc_set_page_directory_v03_00), 913 .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v03_00 914 }; 915 #endif 916 917 #ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05 918 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05[] = { 919 { 920 .vtype = vtype_NvHandle, 921 .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hClient), 922 .name = "hClient" 923 }, 924 { 925 .vtype = vtype_NvHandle, 926 .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hDevice), 927 .name = "hDevice" 928 }, 929 { 930 .vtype = vtype_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05, 931 .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, params), 932 .name = "params" 933 }, 934 { 935 .vtype = vt_end 936 } 937 }; 938 939 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05 = { 940 .name = "rpc_unset_page_directory", 941 .header_length = NV_SIZEOF32(rpc_unset_page_directory_v1E_05), 942 .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05 943 }; 944 #endif 945 946 #ifndef SKIP_PRINT_rpc_unset_page_directory_v03_00 947 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v03_00[] = { 948 { 949 .vtype = vtype_NvHandle, 950 .offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, hClient), 951 .name = "hClient" 952 }, 953 { 954 .vtype = vtype_NvHandle, 955 .offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, hDevice), 956 .name = "hDevice" 957 }, 958 { 959 .vtype = vtype_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00, 960 .offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, params), 961 .name = "params" 962 }, 963 { 964 .vtype = vt_end 965 } 966 }; 967 968 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v03_00 = { 969 .name = "rpc_unset_page_directory", 970 .header_length = NV_SIZEOF32(rpc_unset_page_directory_v03_00), 971 .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v03_00 972 }; 973 #endif 974 975 #ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00 976 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00[] = { 977 { 978 .vtype = vtype_NvU32, 979 .offset = NV_OFFSETOF(rpc_get_gsp_static_info_v14_00, data), 980 .name = "data" 981 }, 982 { 983 .vtype = vt_end 984 } 985 }; 986 987 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00 = { 988 .name = "rpc_get_gsp_static_info", 989 .header_length = NV_SIZEOF32(rpc_get_gsp_static_info_v14_00), 990 .fdesc = vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00 991 }; 992 #endif 993 994 #ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00 995 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_update_bar_pde_v15_00[] = { 996 { 997 .vtype = vtype_UpdateBarPde_v15_00, 998 .offset = NV_OFFSETOF(rpc_update_bar_pde_v15_00, info), 999 .name = "info" 1000 }, 1001 { 1002 .vtype = vt_end 1003 } 1004 }; 1005 1006 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_update_bar_pde_v15_00 = { 1007 .name = "rpc_update_bar_pde", 1008 .header_length = NV_SIZEOF32(rpc_update_bar_pde_v15_00), 1009 .fdesc = vmiopd_fdesc_t_rpc_update_bar_pde_v15_00 1010 }; 1011 #endif 1012 1013 #ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00 1014 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00[] = { 1015 { 1016 .vtype = vtype_NvU64, 1017 .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, address), 1018 .name = "address" 1019 }, 1020 { 1021 .vtype = vtype_NvU32, 1022 .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, value), 1023 .name = "value" 1024 }, 1025 { 1026 .vtype = vtype_NvU32, 1027 .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, grEngId), 1028 .name = "grEngId" 1029 }, 1030 { 1031 .vtype = vt_end 1032 } 1033 }; 1034 1035 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00 = { 1036 .name = "rpc_vgpu_pf_reg_read32", 1037 .header_length = NV_SIZEOF32(rpc_vgpu_pf_reg_read32_v15_00), 1038 .fdesc = vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00 1039 }; 1040 #endif 1041 1042 #ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02 1043 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02[] = { 1044 { 1045 .vtype = vtype_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02, 1046 .offset = NV_OFFSETOF(rpc_ctrl_subdevice_get_p2p_caps_v21_02, ctrlParams), 1047 .name = "ctrlParams" 1048 }, 1049 { 1050 .vtype = vt_end 1051 } 1052 }; 1053 1054 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 = { 1055 .name = "rpc_ctrl_subdevice_get_p2p_caps", 1056 .header_length = NV_SIZEOF32(rpc_ctrl_subdevice_get_p2p_caps_v21_02), 1057 .fdesc = vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 1058 }; 1059 #endif 1060 1061 #ifndef SKIP_PRINT_rpc_ctrl_bus_set_p2p_mapping_v21_03 1062 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03[] = { 1063 { 1064 .vtype = vtype_NvHandle, 1065 .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hClient), 1066 .name = "hClient" 1067 }, 1068 { 1069 .vtype = vtype_NvHandle, 1070 .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hObject), 1071 .name = "hObject" 1072 }, 1073 { 1074 .vtype = vtype_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03, 1075 .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, params), 1076 .name = "params" 1077 }, 1078 { 1079 .vtype = vt_end 1080 } 1081 }; 1082 1083 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 = { 1084 .name = "rpc_ctrl_bus_set_p2p_mapping", 1085 .header_length = NV_SIZEOF32(rpc_ctrl_bus_set_p2p_mapping_v21_03), 1086 .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 1087 }; 1088 #endif 1089 1090 #ifndef SKIP_PRINT_rpc_ctrl_bus_unset_p2p_mapping_v21_03 1091 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03[] = { 1092 { 1093 .vtype = vtype_NvHandle, 1094 .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hClient), 1095 .name = "hClient" 1096 }, 1097 { 1098 .vtype = vtype_NvHandle, 1099 .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hObject), 1100 .name = "hObject" 1101 }, 1102 { 1103 .vtype = vtype_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03, 1104 .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, params), 1105 .name = "params" 1106 }, 1107 { 1108 .vtype = vt_end 1109 } 1110 }; 1111 1112 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 = { 1113 .name = "rpc_ctrl_bus_unset_p2p_mapping", 1114 .header_length = NV_SIZEOF32(rpc_ctrl_bus_unset_p2p_mapping_v21_03), 1115 .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 1116 }; 1117 #endif 1118 1119 #ifndef SKIP_PRINT_rpc_rmfs_init_v15_00 1120 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_init_v15_00[] = { 1121 { 1122 .vtype = vtype_NvU64, 1123 .offset = NV_OFFSETOF(rpc_rmfs_init_v15_00, statusQueuePhysAddr), 1124 .name = "statusQueuePhysAddr" 1125 }, 1126 { 1127 .vtype = vt_end 1128 } 1129 }; 1130 1131 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_init_v15_00 = { 1132 .name = "rpc_rmfs_init", 1133 .header_length = NV_SIZEOF32(rpc_rmfs_init_v15_00), 1134 .fdesc = vmiopd_fdesc_t_rpc_rmfs_init_v15_00 1135 }; 1136 #endif 1137 1138 #ifndef SKIP_PRINT_rpc_rmfs_close_queue_v15_00 1139 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_close_queue_v15_00[] = { 1140 { 1141 .vtype = vt_end 1142 } 1143 }; 1144 1145 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_close_queue_v15_00 = { 1146 .name = "rpc_rmfs_close_queue", 1147 .fdesc = vmiopd_fdesc_t_rpc_rmfs_close_queue_v15_00 1148 }; 1149 #endif 1150 1151 #ifndef SKIP_PRINT_rpc_rmfs_cleanup_v15_00 1152 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_cleanup_v15_00[] = { 1153 { 1154 .vtype = vt_end 1155 } 1156 }; 1157 1158 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_cleanup_v15_00 = { 1159 .name = "rpc_rmfs_cleanup", 1160 .fdesc = vmiopd_fdesc_t_rpc_rmfs_cleanup_v15_00 1161 }; 1162 #endif 1163 1164 #ifndef SKIP_PRINT_rpc_rmfs_test_v15_00 1165 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_test_v15_00[] = { 1166 { 1167 .vtype = vtype_NvU32, 1168 .offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, numReps), 1169 .name = "numReps" 1170 }, 1171 { 1172 .vtype = vtype_NvU32, 1173 .offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, flags), 1174 .name = "flags" 1175 }, 1176 { 1177 .vtype = vtype_NvU32, 1178 .offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, testData1), 1179 .name = "testData1" 1180 }, 1181 { 1182 .vtype = vtype_NvU32, 1183 .offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, testData2), 1184 .name = "testData2" 1185 }, 1186 { 1187 .vtype = vt_end 1188 } 1189 }; 1190 1191 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_test_v15_00 = { 1192 .name = "rpc_rmfs_test", 1193 .header_length = NV_SIZEOF32(rpc_rmfs_test_v15_00), 1194 .fdesc = vmiopd_fdesc_t_rpc_rmfs_test_v15_00 1195 }; 1196 #endif 1197 1198 #ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00 1199 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00[] = { 1200 { 1201 .vtype = vtype_NvU32, 1202 .offset = NV_OFFSETOF(rpc_gsp_set_system_info_v17_00, data), 1203 .name = "data" 1204 }, 1205 { 1206 .vtype = vt_end 1207 } 1208 }; 1209 1210 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00 = { 1211 .name = "rpc_gsp_set_system_info", 1212 .header_length = NV_SIZEOF32(rpc_gsp_set_system_info_v17_00), 1213 .fdesc = vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00 1214 }; 1215 #endif 1216 1217 #ifndef SKIP_PRINT_rpc_set_registry_v17_00 1218 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_registry_v17_00[] = { 1219 { 1220 .vtype = vt_end 1221 } 1222 }; 1223 1224 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_registry_v17_00 = { 1225 .name = "rpc_set_registry", 1226 .fdesc = vmiopd_fdesc_t_rpc_set_registry_v17_00 1227 }; 1228 #endif 1229 1230 #ifndef SKIP_PRINT_rpc_gsp_rm_alloc_v03_00 1231 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00[] = { 1232 { 1233 .vtype = vtype_NvHandle, 1234 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClient), 1235 .name = "hClient" 1236 }, 1237 { 1238 .vtype = vtype_NvHandle, 1239 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hParent), 1240 .name = "hParent" 1241 }, 1242 { 1243 .vtype = vtype_NvHandle, 1244 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hObject), 1245 .name = "hObject" 1246 }, 1247 { 1248 .vtype = vtype_NvU32, 1249 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClass), 1250 .name = "hClass" 1251 }, 1252 { 1253 .vtype = vtype_NvU32, 1254 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, status), 1255 .name = "status" 1256 }, 1257 { 1258 .vtype = vtype_NvU32, 1259 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, paramsSize), 1260 .name = "paramsSize" 1261 }, 1262 { 1263 .vtype = vtype_NvU8_array, 1264 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, params), 1265 .array_length = 0, 1266 .name = "params" 1267 }, 1268 { 1269 .vtype = vt_end 1270 } 1271 }; 1272 1273 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00 = { 1274 .name = "rpc_gsp_rm_alloc", 1275 .header_length = NV_SIZEOF32(rpc_gsp_rm_alloc_v03_00), 1276 .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00 1277 }; 1278 #endif 1279 1280 #ifndef SKIP_PRINT_rpc_gsp_rm_control_v03_00 1281 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = { 1282 { 1283 .vtype = vtype_NvHandle, 1284 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hClient), 1285 .name = "hClient" 1286 }, 1287 { 1288 .vtype = vtype_NvHandle, 1289 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hObject), 1290 .name = "hObject" 1291 }, 1292 { 1293 .vtype = vtype_NvU32, 1294 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, cmd), 1295 .name = "cmd" 1296 }, 1297 { 1298 .vtype = vtype_NvU32, 1299 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, status), 1300 .name = "status" 1301 }, 1302 { 1303 .vtype = vtype_NvU32, 1304 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, paramsSize), 1305 .name = "paramsSize" 1306 }, 1307 { 1308 .vtype = vtype_NvBool, 1309 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, serialized), 1310 .name = "serialized" 1311 }, 1312 { 1313 .vtype = vtype_NvBool, 1314 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, copyOutOnError), 1315 .name = "copyOutOnError" 1316 }, 1317 { 1318 .vtype = vtype_NvU8_array, 1319 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, reserved), 1320 .array_length = 2, 1321 .name = "reserved" 1322 }, 1323 { 1324 .vtype = vtype_NvU8_array, 1325 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, params), 1326 .array_length = 0, 1327 .name = "params" 1328 }, 1329 { 1330 .vtype = vt_end 1331 } 1332 }; 1333 1334 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00 = { 1335 .name = "rpc_gsp_rm_control", 1336 .header_length = NV_SIZEOF32(rpc_gsp_rm_control_v03_00), 1337 .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00 1338 }; 1339 #endif 1340 1341 #ifndef SKIP_PRINT_rpc_dump_protobuf_component_v18_12 1342 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12[] = { 1343 { 1344 .vtype = vtype_NvU16, 1345 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, component), 1346 .name = "component" 1347 }, 1348 { 1349 .vtype = vtype_NvU8, 1350 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, nvDumpType), 1351 .name = "nvDumpType" 1352 }, 1353 { 1354 .vtype = vtype_NvBool, 1355 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, countOnly), 1356 .name = "countOnly" 1357 }, 1358 { 1359 .vtype = vtype_NvU32, 1360 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bugCheckCode), 1361 .name = "bugCheckCode" 1362 }, 1363 { 1364 .vtype = vtype_NvU32, 1365 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, internalCode), 1366 .name = "internalCode" 1367 }, 1368 { 1369 .vtype = vtype_NvU32, 1370 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bufferSize), 1371 .name = "bufferSize" 1372 }, 1373 { 1374 .vtype = vtype_NvU8_array, 1375 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, blob), 1376 .array_length = 0, 1377 .name = "blob" 1378 }, 1379 { 1380 .vtype = vt_end 1381 } 1382 }; 1383 1384 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12 = { 1385 .name = "rpc_dump_protobuf_component", 1386 .header_length = NV_SIZEOF32(rpc_dump_protobuf_component_v18_12), 1387 .fdesc = vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12 1388 }; 1389 #endif 1390 1391 #ifndef SKIP_PRINT_rpc_run_cpu_sequencer_v17_00 1392 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00[] = { 1393 { 1394 .vtype = vtype_NvU32, 1395 .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, bufferSizeDWord), 1396 .name = "bufferSizeDWord" 1397 }, 1398 { 1399 .vtype = vtype_NvU32, 1400 .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, cmdIndex), 1401 .name = "cmdIndex" 1402 }, 1403 { 1404 .vtype = vtype_NvU32_array, 1405 .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, regSaveArea), 1406 .array_length = 8, 1407 .name = "regSaveArea" 1408 }, 1409 { 1410 .vtype = vtype_NvU32_array, 1411 .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, commandBuffer), 1412 .array_length = 0, 1413 .name = "commandBuffer" 1414 }, 1415 { 1416 .vtype = vt_end 1417 } 1418 }; 1419 1420 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00 = { 1421 .name = "rpc_run_cpu_sequencer", 1422 .header_length = NV_SIZEOF32(rpc_run_cpu_sequencer_v17_00), 1423 .fdesc = vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00 1424 }; 1425 #endif 1426 1427 #ifndef SKIP_PRINT_rpc_post_event_v17_00 1428 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_post_event_v17_00[] = { 1429 { 1430 .vtype = vtype_NvHandle, 1431 .offset = NV_OFFSETOF(rpc_post_event_v17_00, hClient), 1432 .name = "hClient" 1433 }, 1434 { 1435 .vtype = vtype_NvHandle, 1436 .offset = NV_OFFSETOF(rpc_post_event_v17_00, hEvent), 1437 .name = "hEvent" 1438 }, 1439 { 1440 .vtype = vtype_NvU32, 1441 .offset = NV_OFFSETOF(rpc_post_event_v17_00, notifyIndex), 1442 .name = "notifyIndex" 1443 }, 1444 { 1445 .vtype = vtype_NvU32, 1446 .offset = NV_OFFSETOF(rpc_post_event_v17_00, data), 1447 .name = "data" 1448 }, 1449 { 1450 .vtype = vtype_NvU32, 1451 .offset = NV_OFFSETOF(rpc_post_event_v17_00, status), 1452 .name = "status" 1453 }, 1454 { 1455 .vtype = vtype_NvU32, 1456 .offset = NV_OFFSETOF(rpc_post_event_v17_00, eventDataSize), 1457 .name = "eventDataSize" 1458 }, 1459 { 1460 .vtype = vtype_NvBool, 1461 .offset = NV_OFFSETOF(rpc_post_event_v17_00, bNotifyList), 1462 .name = "bNotifyList" 1463 }, 1464 { 1465 .vtype = vtype_NvU8_array, 1466 .offset = NV_OFFSETOF(rpc_post_event_v17_00, eventData), 1467 .array_length = 0, 1468 .name = "eventData" 1469 }, 1470 { 1471 .vtype = vt_end 1472 } 1473 }; 1474 1475 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_post_event_v17_00 = { 1476 .name = "rpc_post_event", 1477 .header_length = NV_SIZEOF32(rpc_post_event_v17_00), 1478 .fdesc = vmiopd_fdesc_t_rpc_post_event_v17_00 1479 }; 1480 #endif 1481 1482 #ifndef SKIP_PRINT_rpc_rc_triggered_v17_02 1483 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rc_triggered_v17_02[] = { 1484 { 1485 .vtype = vtype_NvU32, 1486 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, nv2080EngineType), 1487 .name = "nv2080EngineType" 1488 }, 1489 { 1490 .vtype = vtype_NvU32, 1491 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, chid), 1492 .name = "chid" 1493 }, 1494 { 1495 .vtype = vtype_NvU32, 1496 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, exceptType), 1497 .name = "exceptType" 1498 }, 1499 { 1500 .vtype = vtype_NvU32, 1501 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, scope), 1502 .name = "scope" 1503 }, 1504 { 1505 .vtype = vtype_NvU16, 1506 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, partitionAttributionId), 1507 .name = "partitionAttributionId" 1508 }, 1509 { 1510 .vtype = vt_end 1511 } 1512 }; 1513 1514 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rc_triggered_v17_02 = { 1515 .name = "rpc_rc_triggered", 1516 .header_length = NV_SIZEOF32(rpc_rc_triggered_v17_02), 1517 .fdesc = vmiopd_fdesc_t_rpc_rc_triggered_v17_02 1518 }; 1519 #endif 1520 1521 #ifndef SKIP_PRINT_rpc_os_error_log_v17_00 1522 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_os_error_log_v17_00[] = { 1523 { 1524 .vtype = vtype_NvU32, 1525 .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, exceptType), 1526 .name = "exceptType" 1527 }, 1528 { 1529 .vtype = vtype_NvU32, 1530 .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, runlistId), 1531 .name = "runlistId" 1532 }, 1533 { 1534 .vtype = vtype_NvU32, 1535 .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, chid), 1536 .name = "chid" 1537 }, 1538 { 1539 .vtype = vtype_char_array, 1540 .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, errString), 1541 .array_length = 0x100, 1542 .name = "errString" 1543 }, 1544 { 1545 .vtype = vt_end 1546 } 1547 }; 1548 1549 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_os_error_log_v17_00 = { 1550 .name = "rpc_os_error_log", 1551 .header_length = NV_SIZEOF32(rpc_os_error_log_v17_00), 1552 .fdesc = vmiopd_fdesc_t_rpc_os_error_log_v17_00 1553 }; 1554 #endif 1555 1556 #ifndef SKIP_PRINT_rpc_rg_line_intr_v17_00 1557 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rg_line_intr_v17_00[] = { 1558 { 1559 .vtype = vtype_NvU32, 1560 .offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, head), 1561 .name = "head" 1562 }, 1563 { 1564 .vtype = vtype_NvU32, 1565 .offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, rgIntr), 1566 .name = "rgIntr" 1567 }, 1568 { 1569 .vtype = vt_end 1570 } 1571 }; 1572 1573 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rg_line_intr_v17_00 = { 1574 .name = "rpc_rg_line_intr", 1575 .header_length = NV_SIZEOF32(rpc_rg_line_intr_v17_00), 1576 .fdesc = vmiopd_fdesc_t_rpc_rg_line_intr_v17_00 1577 }; 1578 #endif 1579 1580 #ifndef SKIP_PRINT_rpc_display_modeset_v01_00 1581 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_display_modeset_v01_00[] = { 1582 { 1583 .vtype = vtype_NvBool, 1584 .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, bModesetStart), 1585 .name = "bModesetStart" 1586 }, 1587 { 1588 .vtype = vtype_NvU32, 1589 .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredIsoBandwidthKBPS), 1590 .name = "minRequiredIsoBandwidthKBPS" 1591 }, 1592 { 1593 .vtype = vtype_NvU32, 1594 .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredFloorBandwidthKBPS), 1595 .name = "minRequiredFloorBandwidthKBPS" 1596 }, 1597 { 1598 .vtype = vt_end 1599 } 1600 }; 1601 1602 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_display_modeset_v01_00 = { 1603 .name = "rpc_display_modeset", 1604 .header_length = NV_SIZEOF32(rpc_display_modeset_v01_00), 1605 .fdesc = vmiopd_fdesc_t_rpc_display_modeset_v01_00 1606 }; 1607 #endif 1608 1609 #ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v17_00 1610 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00[] = { 1611 { 1612 .vtype = vtype_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00, 1613 .offset = NV_OFFSETOF(rpc_gpuacct_perfmon_util_samples_v17_00, params), 1614 .name = "params" 1615 }, 1616 { 1617 .vtype = vt_end 1618 } 1619 }; 1620 1621 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00 = { 1622 .name = "rpc_gpuacct_perfmon_util_samples", 1623 .header_length = NV_SIZEOF32(rpc_gpuacct_perfmon_util_samples_v17_00), 1624 .fdesc = vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00 1625 }; 1626 #endif 1627 1628 #ifndef SKIP_PRINT_rpc_vgpu_gsp_plugin_triggered_v17_00 1629 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00[] = { 1630 { 1631 .vtype = vtype_NvU32, 1632 .offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, gfid), 1633 .name = "gfid" 1634 }, 1635 { 1636 .vtype = vtype_NvU32, 1637 .offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, notifyIndex), 1638 .name = "notifyIndex" 1639 }, 1640 { 1641 .vtype = vt_end 1642 } 1643 }; 1644 1645 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 = { 1646 .name = "rpc_vgpu_gsp_plugin_triggered", 1647 .header_length = NV_SIZEOF32(rpc_vgpu_gsp_plugin_triggered_v17_00), 1648 .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 1649 }; 1650 #endif 1651 1652 #ifndef SKIP_PRINT_rpc_vgpu_config_event_v17_00 1653 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00[] = { 1654 { 1655 .vtype = vtype_NvU32, 1656 .offset = NV_OFFSETOF(rpc_vgpu_config_event_v17_00, notifyIndex), 1657 .name = "notifyIndex" 1658 }, 1659 { 1660 .vtype = vt_end 1661 } 1662 }; 1663 1664 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00 = { 1665 .name = "rpc_vgpu_config_event", 1666 .header_length = NV_SIZEOF32(rpc_vgpu_config_event_v17_00), 1667 .fdesc = vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00 1668 }; 1669 #endif 1670 1671 #ifndef SKIP_PRINT_rpc_dce_rm_init_v01_00 1672 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dce_rm_init_v01_00[] = { 1673 { 1674 .vtype = vtype_NvBool, 1675 .offset = NV_OFFSETOF(rpc_dce_rm_init_v01_00, bInit), 1676 .name = "bInit" 1677 }, 1678 { 1679 .vtype = vt_end 1680 } 1681 }; 1682 1683 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dce_rm_init_v01_00 = { 1684 .name = "rpc_dce_rm_init", 1685 .header_length = NV_SIZEOF32(rpc_dce_rm_init_v01_00), 1686 .fdesc = vmiopd_fdesc_t_rpc_dce_rm_init_v01_00 1687 }; 1688 #endif 1689 1690 #ifndef SKIP_PRINT_rpc_sim_read_v1E_01 1691 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_read_v1E_01[] = { 1692 { 1693 .vtype = vtype_char_array, 1694 .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, path), 1695 .array_length = 0x100, 1696 .name = "path" 1697 }, 1698 { 1699 .vtype = vtype_NvU32, 1700 .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, index), 1701 .name = "index" 1702 }, 1703 { 1704 .vtype = vtype_NvU32, 1705 .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, count), 1706 .name = "count" 1707 }, 1708 { 1709 .vtype = vt_end 1710 } 1711 }; 1712 1713 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_read_v1E_01 = { 1714 .name = "rpc_sim_read", 1715 .header_length = NV_SIZEOF32(rpc_sim_read_v1E_01), 1716 .fdesc = vmiopd_fdesc_t_rpc_sim_read_v1E_01 1717 }; 1718 #endif 1719 1720 #ifndef SKIP_PRINT_rpc_sim_write_v1E_01 1721 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_write_v1E_01[] = { 1722 { 1723 .vtype = vtype_char_array, 1724 .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, path), 1725 .array_length = 0x100, 1726 .name = "path" 1727 }, 1728 { 1729 .vtype = vtype_NvU32, 1730 .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, index), 1731 .name = "index" 1732 }, 1733 { 1734 .vtype = vtype_NvU32, 1735 .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, count), 1736 .name = "count" 1737 }, 1738 { 1739 .vtype = vtype_NvU32, 1740 .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, data), 1741 .name = "data" 1742 }, 1743 { 1744 .vtype = vt_end 1745 } 1746 }; 1747 1748 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_write_v1E_01 = { 1749 .name = "rpc_sim_write", 1750 .header_length = NV_SIZEOF32(rpc_sim_write_v1E_01), 1751 .fdesc = vmiopd_fdesc_t_rpc_sim_write_v1E_01 1752 }; 1753 #endif 1754 1755 #ifndef SKIP_PRINT_rpc_ucode_libos_print_v1E_08 1756 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08[] = { 1757 { 1758 .vtype = vtype_NvU32, 1759 .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, ucodeEngDesc), 1760 .name = "ucodeEngDesc" 1761 }, 1762 { 1763 .vtype = vtype_NvU32, 1764 .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBufSize), 1765 .name = "libosPrintBufSize" 1766 }, 1767 { 1768 .vtype = vtype_NvU8_array, 1769 .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBuf), 1770 .array_length = 0, 1771 .name = "libosPrintBuf" 1772 }, 1773 { 1774 .vtype = vt_end 1775 } 1776 }; 1777 1778 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08 = { 1779 .name = "rpc_ucode_libos_print", 1780 .header_length = NV_SIZEOF32(rpc_ucode_libos_print_v1E_08), 1781 .fdesc = vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08 1782 }; 1783 #endif 1784 1785 #ifndef SKIP_PRINT_rpc_init_done_v17_00 1786 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_init_done_v17_00[] = { 1787 { 1788 .vtype = vtype_NvU32, 1789 .offset = NV_OFFSETOF(rpc_init_done_v17_00, not_used), 1790 .name = "not_used" 1791 }, 1792 { 1793 .vtype = vt_end 1794 } 1795 }; 1796 1797 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_init_done_v17_00 = { 1798 .name = "rpc_init_done", 1799 .header_length = NV_SIZEOF32(rpc_init_done_v17_00), 1800 .fdesc = vmiopd_fdesc_t_rpc_init_done_v17_00 1801 }; 1802 #endif 1803 1804 #ifndef SKIP_PRINT_rpc_semaphore_schedule_callback_v17_00 1805 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00[] = { 1806 { 1807 .vtype = vtype_NvU64, 1808 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, GPUVA), 1809 .name = "GPUVA" 1810 }, 1811 { 1812 .vtype = vtype_NvU32, 1813 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hVASpace), 1814 .name = "hVASpace" 1815 }, 1816 { 1817 .vtype = vtype_NvU32, 1818 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, ReleaseValue), 1819 .name = "ReleaseValue" 1820 }, 1821 { 1822 .vtype = vtype_NvU32, 1823 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, Flags), 1824 .name = "Flags" 1825 }, 1826 { 1827 .vtype = vtype_NvU32, 1828 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, completionStatus), 1829 .name = "completionStatus" 1830 }, 1831 { 1832 .vtype = vtype_NvHandle, 1833 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hClient), 1834 .name = "hClient" 1835 }, 1836 { 1837 .vtype = vtype_NvHandle, 1838 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hEvent), 1839 .name = "hEvent" 1840 }, 1841 { 1842 .vtype = vt_end 1843 } 1844 }; 1845 1846 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00 = { 1847 .name = "rpc_semaphore_schedule_callback", 1848 .header_length = NV_SIZEOF32(rpc_semaphore_schedule_callback_v17_00), 1849 .fdesc = vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00 1850 }; 1851 #endif 1852 1853 #ifndef SKIP_PRINT_rpc_timed_semaphore_release_v01_00 1854 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00[] = { 1855 { 1856 .vtype = vtype_NvU64, 1857 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, semaphoreVA), 1858 .name = "semaphoreVA" 1859 }, 1860 { 1861 .vtype = vtype_NvU64, 1862 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, notifierVA), 1863 .name = "notifierVA" 1864 }, 1865 { 1866 .vtype = vtype_NvU32, 1867 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hVASpace), 1868 .name = "hVASpace" 1869 }, 1870 { 1871 .vtype = vtype_NvU32, 1872 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, releaseValue), 1873 .name = "releaseValue" 1874 }, 1875 { 1876 .vtype = vtype_NvU32, 1877 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, completionStatus), 1878 .name = "completionStatus" 1879 }, 1880 { 1881 .vtype = vtype_NvHandle, 1882 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hClient), 1883 .name = "hClient" 1884 }, 1885 { 1886 .vtype = vt_end 1887 } 1888 }; 1889 1890 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00 = { 1891 .name = "rpc_timed_semaphore_release", 1892 .header_length = NV_SIZEOF32(rpc_timed_semaphore_release_v01_00), 1893 .fdesc = vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00 1894 }; 1895 #endif 1896 1897 #ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00 1898 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00[] = { 1899 { 1900 .vtype = vtype_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00, 1901 .offset = NV_OFFSETOF(rpc_perf_gpu_boost_sync_limits_callback_v17_00, params), 1902 .name = "params" 1903 }, 1904 { 1905 .vtype = vt_end 1906 } 1907 }; 1908 1909 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 = { 1910 .name = "rpc_perf_gpu_boost_sync_limits_callback", 1911 .header_length = NV_SIZEOF32(rpc_perf_gpu_boost_sync_limits_callback_v17_00), 1912 .fdesc = vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 1913 }; 1914 #endif 1915 1916 #ifndef SKIP_PRINT_rpc_perf_bridgeless_info_update_v17_00 1917 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00[] = { 1918 { 1919 .vtype = vtype_NvU64, 1920 .offset = NV_OFFSETOF(rpc_perf_bridgeless_info_update_v17_00, bBridgeless), 1921 .name = "bBridgeless" 1922 }, 1923 { 1924 .vtype = vt_end 1925 } 1926 }; 1927 1928 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = { 1929 .name = "rpc_perf_bridgeless_info_update", 1930 .header_length = NV_SIZEOF32(rpc_perf_bridgeless_info_update_v17_00), 1931 .fdesc = vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00 1932 }; 1933 #endif 1934 1935 #ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00 1936 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00[] = { 1937 { 1938 .vtype = vtype_NvU32, 1939 .offset = NV_OFFSETOF(rpc_nvlink_fault_up_v17_00, linkId), 1940 .name = "linkId" 1941 }, 1942 { 1943 .vtype = vt_end 1944 } 1945 }; 1946 1947 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00 = { 1948 .name = "rpc_nvlink_fault_up", 1949 .header_length = NV_SIZEOF32(rpc_nvlink_fault_up_v17_00), 1950 .fdesc = vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00 1951 }; 1952 #endif 1953 1954 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00 1955 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00[] = { 1956 { 1957 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00, 1958 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_256_v17_00, params), 1959 .name = "params" 1960 }, 1961 { 1962 .vtype = vt_end 1963 } 1964 }; 1965 1966 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00 = { 1967 .name = "rpc_nvlink_inband_received_data_256", 1968 .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_256_v17_00), 1969 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00 1970 }; 1971 #endif 1972 1973 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_512_v17_00 1974 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00[] = { 1975 { 1976 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00, 1977 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_512_v17_00, params), 1978 .name = "params" 1979 }, 1980 { 1981 .vtype = vt_end 1982 } 1983 }; 1984 1985 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00 = { 1986 .name = "rpc_nvlink_inband_received_data_512", 1987 .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_512_v17_00), 1988 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00 1989 }; 1990 #endif 1991 1992 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_1024_v17_00 1993 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00[] = { 1994 { 1995 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00, 1996 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_1024_v17_00, params), 1997 .name = "params" 1998 }, 1999 { 2000 .vtype = vt_end 2001 } 2002 }; 2003 2004 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 = { 2005 .name = "rpc_nvlink_inband_received_data_1024", 2006 .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_1024_v17_00), 2007 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 2008 }; 2009 #endif 2010 2011 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_2048_v17_00 2012 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00[] = { 2013 { 2014 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00, 2015 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_2048_v17_00, params), 2016 .name = "params" 2017 }, 2018 { 2019 .vtype = vt_end 2020 } 2021 }; 2022 2023 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 = { 2024 .name = "rpc_nvlink_inband_received_data_2048", 2025 .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_2048_v17_00), 2026 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 2027 }; 2028 #endif 2029 2030 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_4096_v17_00 2031 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00[] = { 2032 { 2033 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00, 2034 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_4096_v17_00, params), 2035 .name = "params" 2036 }, 2037 { 2038 .vtype = vt_end 2039 } 2040 }; 2041 2042 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 = { 2043 .name = "rpc_nvlink_inband_received_data_4096", 2044 .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_4096_v17_00), 2045 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 2046 }; 2047 #endif 2048 2049 #ifndef SKIP_PRINT_rpc_nvlink_is_gpu_degraded_v17_00 2050 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00[] = { 2051 { 2052 .vtype = vtype_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00, 2053 .offset = NV_OFFSETOF(rpc_nvlink_is_gpu_degraded_v17_00, params), 2054 .name = "params" 2055 }, 2056 { 2057 .vtype = vt_end 2058 } 2059 }; 2060 2061 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 = { 2062 .name = "rpc_nvlink_is_gpu_degraded", 2063 .header_length = NV_SIZEOF32(rpc_nvlink_is_gpu_degraded_v17_00), 2064 .fdesc = vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 2065 }; 2066 #endif 2067 2068 #ifndef SKIP_PRINT_rpc_gsp_send_user_shared_data_v17_00 2069 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00[] = { 2070 { 2071 .vtype = vtype_NvU32, 2072 .offset = NV_OFFSETOF(rpc_gsp_send_user_shared_data_v17_00, data), 2073 .name = "data" 2074 }, 2075 { 2076 .vtype = vt_end 2077 } 2078 }; 2079 2080 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00 = { 2081 .name = "rpc_gsp_send_user_shared_data", 2082 .header_length = NV_SIZEOF32(rpc_gsp_send_user_shared_data_v17_00), 2083 .fdesc = vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00 2084 }; 2085 #endif 2086 2087 #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 2088 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00[] = { 2089 { 2090 .vtype = vtype_NvU32, 2091 .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmapRing), 2092 .name = "sysmemPfnBitmapRing" 2093 }, 2094 { 2095 .vtype = vtype_NvU32, 2096 .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmapRingHi), 2097 .name = "sysmemPfnBitmapRingHi" 2098 }, 2099 { 2100 .vtype = vtype_NvU32, 2101 .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmap), 2102 .name = "sysmemPfnBitmap" 2103 }, 2104 { 2105 .vtype = vt_end 2106 } 2107 }; 2108 2109 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 = { 2110 .name = "rpc_set_sysmem_dirty_page_tracking_buffer", 2111 .header_length = NV_SIZEOF32(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00), 2112 .fdesc = vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 2113 }; 2114 #endif 2115 2116 #ifndef SKIP_PRINT_rpc_extdev_intr_service_v17_00 2117 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00[] = { 2118 { 2119 .vtype = vtype_NvU8, 2120 .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, lossRegStatus), 2121 .name = "lossRegStatus" 2122 }, 2123 { 2124 .vtype = vtype_NvU8, 2125 .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, gainRegStatus), 2126 .name = "gainRegStatus" 2127 }, 2128 { 2129 .vtype = vtype_NvU8, 2130 .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, miscRegStatus), 2131 .name = "miscRegStatus" 2132 }, 2133 { 2134 .vtype = vtype_NvBool, 2135 .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, rmStatus), 2136 .name = "rmStatus" 2137 }, 2138 { 2139 .vtype = vt_end 2140 } 2141 }; 2142 2143 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00 = { 2144 .name = "rpc_extdev_intr_service", 2145 .header_length = NV_SIZEOF32(rpc_extdev_intr_service_v17_00), 2146 .fdesc = vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00 2147 }; 2148 #endif 2149 2150 #ifndef SKIP_PRINT_rpc_pfm_req_hndlr_state_sync_callback_v21_04 2151 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04[] = { 2152 { 2153 .vtype = vtype_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04, 2154 .offset = NV_OFFSETOF(rpc_pfm_req_hndlr_state_sync_callback_v21_04, params), 2155 .name = "params" 2156 }, 2157 { 2158 .vtype = vt_end 2159 } 2160 }; 2161 2162 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 = { 2163 .name = "rpc_pfm_req_hndlr_state_sync_callback", 2164 .header_length = NV_SIZEOF32(rpc_pfm_req_hndlr_state_sync_callback_v21_04), 2165 .fdesc = vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 2166 }; 2167 #endif 2168 2169 #ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00 2170 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00[] = { 2171 { 2172 .vtype = vtype_NvBool, 2173 .offset = NV_OFFSETOF(rpc_gsp_lockdown_notice_v17_00, bLockdownEngaging), 2174 .name = "bLockdownEngaging" 2175 }, 2176 { 2177 .vtype = vt_end 2178 } 2179 }; 2180 2181 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_lockdown_notice_v17_00 = { 2182 .name = "rpc_gsp_lockdown_notice", 2183 .header_length = NV_SIZEOF32(rpc_gsp_lockdown_notice_v17_00), 2184 .fdesc = vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00 2185 }; 2186 #endif 2187 2188 #endif 2189 2190 #ifdef RPC_DEBUG_PRINT_FUNCTIONS 2191 // These are definitions for versioned functions. These will be used for RPC logging in the vmioplugin. 2192 #define SDK_DEBUG_PRINT_FUNCTIONS 2193 #include "g_sdk-structures.h" 2194 #undef SDK_DEBUG_PRINT_FUNCTIONS 2195 #ifndef SKIP_PRINT_rpc_nop_v03_00 2196 vmiopd_mdesc_t *rpcdebugNop_v03_00(void) 2197 { 2198 return &vmiopd_mdesc_t_rpc_nop_v03_00; 2199 } 2200 #endif 2201 2202 #ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00 2203 vmiopd_mdesc_t *rpcdebugSetGuestSystemInfo_v03_00(void) 2204 { 2205 return &vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00; 2206 } 2207 #endif 2208 2209 #ifndef SKIP_PRINT_rpc_alloc_memory_v13_01 2210 vmiopd_mdesc_t *rpcdebugAllocMemory_v13_01(void) 2211 { 2212 return &vmiopd_mdesc_t_rpc_alloc_memory_v13_01; 2213 } 2214 #endif 2215 2216 #ifndef SKIP_PRINT_rpc_free_v03_00 2217 vmiopd_mdesc_t *rpcdebugFree_v03_00(void) 2218 { 2219 return &vmiopd_mdesc_t_rpc_free_v03_00; 2220 } 2221 #endif 2222 2223 #ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00 2224 vmiopd_mdesc_t *rpcdebugMapMemoryDma_v03_00(void) 2225 { 2226 return &vmiopd_mdesc_t_rpc_map_memory_dma_v03_00; 2227 } 2228 #endif 2229 2230 #ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00 2231 vmiopd_mdesc_t *rpcdebugUnmapMemoryDma_v03_00(void) 2232 { 2233 return &vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00; 2234 } 2235 #endif 2236 2237 #ifndef SKIP_PRINT_rpc_dup_object_v03_00 2238 vmiopd_mdesc_t *rpcdebugDupObject_v03_00(void) 2239 { 2240 return &vmiopd_mdesc_t_rpc_dup_object_v03_00; 2241 } 2242 #endif 2243 2244 #ifndef SKIP_PRINT_rpc_idle_channels_v03_00 2245 vmiopd_mdesc_t *rpcdebugIdleChannels_v03_00(void) 2246 { 2247 return &vmiopd_mdesc_t_rpc_idle_channels_v03_00; 2248 } 2249 #endif 2250 2251 #ifndef SKIP_PRINT_rpc_unloading_guest_driver_v03_00 2252 vmiopd_mdesc_t *rpcdebugUnloadingGuestDriver_v03_00(void) 2253 { 2254 return &vmiopd_mdesc_t_rpc_unloading_guest_driver_v03_00; 2255 } 2256 #endif 2257 2258 #ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07 2259 vmiopd_mdesc_t *rpcdebugUnloadingGuestDriver_v1F_07(void) 2260 { 2261 return &vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07; 2262 } 2263 #endif 2264 2265 #ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01 2266 vmiopd_mdesc_t *rpcdebugGpuExecRegOps_v12_01(void) 2267 { 2268 return &vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01; 2269 } 2270 #endif 2271 2272 #ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05 2273 vmiopd_mdesc_t *rpcdebugSetPageDirectory_v1E_05(void) 2274 { 2275 return &vmiopd_mdesc_t_rpc_set_page_directory_v1E_05; 2276 } 2277 #endif 2278 2279 #ifndef SKIP_PRINT_rpc_set_page_directory_v03_00 2280 vmiopd_mdesc_t *rpcdebugSetPageDirectory_v03_00(void) 2281 { 2282 return &vmiopd_mdesc_t_rpc_set_page_directory_v03_00; 2283 } 2284 #endif 2285 2286 #ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05 2287 vmiopd_mdesc_t *rpcdebugUnsetPageDirectory_v1E_05(void) 2288 { 2289 return &vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05; 2290 } 2291 #endif 2292 2293 #ifndef SKIP_PRINT_rpc_unset_page_directory_v03_00 2294 vmiopd_mdesc_t *rpcdebugUnsetPageDirectory_v03_00(void) 2295 { 2296 return &vmiopd_mdesc_t_rpc_unset_page_directory_v03_00; 2297 } 2298 #endif 2299 2300 #ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00 2301 vmiopd_mdesc_t *rpcdebugGetGspStaticInfo_v14_00(void) 2302 { 2303 return &vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00; 2304 } 2305 #endif 2306 2307 #ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00 2308 vmiopd_mdesc_t *rpcdebugUpdateBarPde_v15_00(void) 2309 { 2310 return &vmiopd_mdesc_t_rpc_update_bar_pde_v15_00; 2311 } 2312 #endif 2313 2314 #ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00 2315 vmiopd_mdesc_t *rpcdebugVgpuPfRegRead32_v15_00(void) 2316 { 2317 return &vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00; 2318 } 2319 #endif 2320 2321 #ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02 2322 vmiopd_mdesc_t *rpcdebugCtrlSubdeviceGetP2pCaps_v21_02(void) 2323 { 2324 return &vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02; 2325 } 2326 #endif 2327 2328 #ifndef SKIP_PRINT_rpc_ctrl_bus_set_p2p_mapping_v21_03 2329 vmiopd_mdesc_t *rpcdebugCtrlBusSetP2pMapping_v21_03(void) 2330 { 2331 return &vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03; 2332 } 2333 #endif 2334 2335 #ifndef SKIP_PRINT_rpc_ctrl_bus_unset_p2p_mapping_v21_03 2336 vmiopd_mdesc_t *rpcdebugCtrlBusUnsetP2pMapping_v21_03(void) 2337 { 2338 return &vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03; 2339 } 2340 #endif 2341 2342 #ifndef SKIP_PRINT_rpc_rmfs_init_v15_00 2343 vmiopd_mdesc_t *rpcdebugRmfsInit_v15_00(void) 2344 { 2345 return &vmiopd_mdesc_t_rpc_rmfs_init_v15_00; 2346 } 2347 #endif 2348 2349 #ifndef SKIP_PRINT_rpc_rmfs_close_queue_v15_00 2350 vmiopd_mdesc_t *rpcdebugRmfsCloseQueue_v15_00(void) 2351 { 2352 return &vmiopd_mdesc_t_rpc_rmfs_close_queue_v15_00; 2353 } 2354 #endif 2355 2356 #ifndef SKIP_PRINT_rpc_rmfs_cleanup_v15_00 2357 vmiopd_mdesc_t *rpcdebugRmfsCleanup_v15_00(void) 2358 { 2359 return &vmiopd_mdesc_t_rpc_rmfs_cleanup_v15_00; 2360 } 2361 #endif 2362 2363 #ifndef SKIP_PRINT_rpc_rmfs_test_v15_00 2364 vmiopd_mdesc_t *rpcdebugRmfsTest_v15_00(void) 2365 { 2366 return &vmiopd_mdesc_t_rpc_rmfs_test_v15_00; 2367 } 2368 #endif 2369 2370 #ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00 2371 vmiopd_mdesc_t *rpcdebugGspSetSystemInfo_v17_00(void) 2372 { 2373 return &vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00; 2374 } 2375 #endif 2376 2377 #ifndef SKIP_PRINT_rpc_set_registry_v17_00 2378 vmiopd_mdesc_t *rpcdebugSetRegistry_v17_00(void) 2379 { 2380 return &vmiopd_mdesc_t_rpc_set_registry_v17_00; 2381 } 2382 #endif 2383 2384 #ifndef SKIP_PRINT_rpc_gsp_rm_alloc_v03_00 2385 vmiopd_mdesc_t *rpcdebugGspRmAlloc_v03_00(void) 2386 { 2387 return &vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00; 2388 } 2389 #endif 2390 2391 #ifndef SKIP_PRINT_rpc_gsp_rm_control_v03_00 2392 vmiopd_mdesc_t *rpcdebugGspRmControl_v03_00(void) 2393 { 2394 return &vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00; 2395 } 2396 #endif 2397 2398 #ifndef SKIP_PRINT_rpc_dump_protobuf_component_v18_12 2399 vmiopd_mdesc_t *rpcdebugDumpProtobufComponent_v18_12(void) 2400 { 2401 return &vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12; 2402 } 2403 #endif 2404 2405 #ifndef SKIP_PRINT_rpc_run_cpu_sequencer_v17_00 2406 vmiopd_mdesc_t *rpcdebugRunCpuSequencer_v17_00(void) 2407 { 2408 return &vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00; 2409 } 2410 #endif 2411 2412 #ifndef SKIP_PRINT_rpc_post_event_v17_00 2413 vmiopd_mdesc_t *rpcdebugPostEvent_v17_00(void) 2414 { 2415 return &vmiopd_mdesc_t_rpc_post_event_v17_00; 2416 } 2417 #endif 2418 2419 #ifndef SKIP_PRINT_rpc_rc_triggered_v17_02 2420 vmiopd_mdesc_t *rpcdebugRcTriggered_v17_02(void) 2421 { 2422 return &vmiopd_mdesc_t_rpc_rc_triggered_v17_02; 2423 } 2424 #endif 2425 2426 #ifndef SKIP_PRINT_rpc_os_error_log_v17_00 2427 vmiopd_mdesc_t *rpcdebugOsErrorLog_v17_00(void) 2428 { 2429 return &vmiopd_mdesc_t_rpc_os_error_log_v17_00; 2430 } 2431 #endif 2432 2433 #ifndef SKIP_PRINT_rpc_rg_line_intr_v17_00 2434 vmiopd_mdesc_t *rpcdebugRgLineIntr_v17_00(void) 2435 { 2436 return &vmiopd_mdesc_t_rpc_rg_line_intr_v17_00; 2437 } 2438 #endif 2439 2440 #ifndef SKIP_PRINT_rpc_display_modeset_v01_00 2441 vmiopd_mdesc_t *rpcdebugDisplayModeset_v01_00(void) 2442 { 2443 return &vmiopd_mdesc_t_rpc_display_modeset_v01_00; 2444 } 2445 #endif 2446 2447 #ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v17_00 2448 vmiopd_mdesc_t *rpcdebugGpuacctPerfmonUtilSamples_v17_00(void) 2449 { 2450 return &vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00; 2451 } 2452 #endif 2453 2454 #ifndef SKIP_PRINT_rpc_vgpu_gsp_plugin_triggered_v17_00 2455 vmiopd_mdesc_t *rpcdebugVgpuGspPluginTriggered_v17_00(void) 2456 { 2457 return &vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00; 2458 } 2459 #endif 2460 2461 #ifndef SKIP_PRINT_rpc_vgpu_config_event_v17_00 2462 vmiopd_mdesc_t *rpcdebugVgpuConfigEvent_v17_00(void) 2463 { 2464 return &vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00; 2465 } 2466 #endif 2467 2468 #ifndef SKIP_PRINT_rpc_dce_rm_init_v01_00 2469 vmiopd_mdesc_t *rpcdebugDceRmInit_v01_00(void) 2470 { 2471 return &vmiopd_mdesc_t_rpc_dce_rm_init_v01_00; 2472 } 2473 #endif 2474 2475 #ifndef SKIP_PRINT_rpc_sim_read_v1E_01 2476 vmiopd_mdesc_t *rpcdebugSimRead_v1E_01(void) 2477 { 2478 return &vmiopd_mdesc_t_rpc_sim_read_v1E_01; 2479 } 2480 #endif 2481 2482 #ifndef SKIP_PRINT_rpc_sim_write_v1E_01 2483 vmiopd_mdesc_t *rpcdebugSimWrite_v1E_01(void) 2484 { 2485 return &vmiopd_mdesc_t_rpc_sim_write_v1E_01; 2486 } 2487 #endif 2488 2489 #ifndef SKIP_PRINT_rpc_ucode_libos_print_v1E_08 2490 vmiopd_mdesc_t *rpcdebugUcodeLibosPrint_v1E_08(void) 2491 { 2492 return &vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08; 2493 } 2494 #endif 2495 2496 #ifndef SKIP_PRINT_rpc_init_done_v17_00 2497 vmiopd_mdesc_t *rpcdebugInitDone_v17_00(void) 2498 { 2499 return &vmiopd_mdesc_t_rpc_init_done_v17_00; 2500 } 2501 #endif 2502 2503 #ifndef SKIP_PRINT_rpc_semaphore_schedule_callback_v17_00 2504 vmiopd_mdesc_t *rpcdebugSemaphoreScheduleCallback_v17_00(void) 2505 { 2506 return &vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00; 2507 } 2508 #endif 2509 2510 #ifndef SKIP_PRINT_rpc_timed_semaphore_release_v01_00 2511 vmiopd_mdesc_t *rpcdebugTimedSemaphoreRelease_v01_00(void) 2512 { 2513 return &vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00; 2514 } 2515 #endif 2516 2517 #ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00 2518 vmiopd_mdesc_t *rpcdebugPerfGpuBoostSyncLimitsCallback_v17_00(void) 2519 { 2520 return &vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00; 2521 } 2522 #endif 2523 2524 #ifndef SKIP_PRINT_rpc_perf_bridgeless_info_update_v17_00 2525 vmiopd_mdesc_t *rpcdebugPerfBridgelessInfoUpdate_v17_00(void) 2526 { 2527 return &vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00; 2528 } 2529 #endif 2530 2531 #ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00 2532 vmiopd_mdesc_t *rpcdebugNvlinkFaultUp_v17_00(void) 2533 { 2534 return &vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00; 2535 } 2536 #endif 2537 2538 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00 2539 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData256_v17_00(void) 2540 { 2541 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00; 2542 } 2543 #endif 2544 2545 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_512_v17_00 2546 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData512_v17_00(void) 2547 { 2548 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00; 2549 } 2550 #endif 2551 2552 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_1024_v17_00 2553 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData1024_v17_00(void) 2554 { 2555 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00; 2556 } 2557 #endif 2558 2559 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_2048_v17_00 2560 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData2048_v17_00(void) 2561 { 2562 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00; 2563 } 2564 #endif 2565 2566 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_4096_v17_00 2567 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData4096_v17_00(void) 2568 { 2569 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00; 2570 } 2571 #endif 2572 2573 #ifndef SKIP_PRINT_rpc_nvlink_is_gpu_degraded_v17_00 2574 vmiopd_mdesc_t *rpcdebugNvlinkIsGpuDegraded_v17_00(void) 2575 { 2576 return &vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00; 2577 } 2578 #endif 2579 2580 #ifndef SKIP_PRINT_rpc_gsp_send_user_shared_data_v17_00 2581 vmiopd_mdesc_t *rpcdebugGspSendUserSharedData_v17_00(void) 2582 { 2583 return &vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00; 2584 } 2585 #endif 2586 2587 #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 2588 vmiopd_mdesc_t *rpcdebugSetSysmemDirtyPageTrackingBuffer_v20_00(void) 2589 { 2590 return &vmiopd_mdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00; 2591 } 2592 #endif 2593 2594 #ifndef SKIP_PRINT_rpc_extdev_intr_service_v17_00 2595 vmiopd_mdesc_t *rpcdebugExtdevIntrService_v17_00(void) 2596 { 2597 return &vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00; 2598 } 2599 #endif 2600 2601 #ifndef SKIP_PRINT_rpc_pfm_req_hndlr_state_sync_callback_v21_04 2602 vmiopd_mdesc_t *rpcdebugPfmReqHndlrStateSyncCallback_v21_04(void) 2603 { 2604 return &vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04; 2605 } 2606 #endif 2607 2608 #ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00 2609 vmiopd_mdesc_t *rpcdebugGspLockdownNotice_v17_00(void) 2610 { 2611 return &vmiopd_mdesc_t_rpc_gsp_lockdown_notice_v17_00; 2612 } 2613 #endif 2614 2615 2616 #endif 2617 2618 #ifdef RPC_GENERIC_UNION 2619 // This is a generic union, that will be used for the communication between the vmioplugin & guest RM. 2620 typedef union rpc_generic_union { 2621 rpc_set_guest_system_info_v03_00 set_guest_system_info_v03_00; 2622 rpc_set_guest_system_info_v set_guest_system_info_v; 2623 rpc_alloc_memory_v13_01 alloc_memory_v13_01; 2624 rpc_alloc_memory_v alloc_memory_v; 2625 rpc_free_v03_00 free_v03_00; 2626 rpc_free_v free_v; 2627 rpc_map_memory_dma_v03_00 map_memory_dma_v03_00; 2628 rpc_map_memory_dma_v map_memory_dma_v; 2629 rpc_unmap_memory_dma_v03_00 unmap_memory_dma_v03_00; 2630 rpc_unmap_memory_dma_v unmap_memory_dma_v; 2631 rpc_dup_object_v03_00 dup_object_v03_00; 2632 rpc_dup_object_v dup_object_v; 2633 rpc_idle_channels_v03_00 idle_channels_v03_00; 2634 rpc_idle_channels_v idle_channels_v; 2635 rpc_unloading_guest_driver_v1F_07 unloading_guest_driver_v1F_07; 2636 rpc_unloading_guest_driver_v unloading_guest_driver_v; 2637 rpc_gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v12_01; 2638 rpc_gpu_exec_reg_ops_v gpu_exec_reg_ops_v; 2639 rpc_set_page_directory_v1E_05 set_page_directory_v1E_05; 2640 rpc_set_page_directory_v03_00 set_page_directory_v03_00; 2641 rpc_set_page_directory_v set_page_directory_v; 2642 rpc_unset_page_directory_v1E_05 unset_page_directory_v1E_05; 2643 rpc_unset_page_directory_v03_00 unset_page_directory_v03_00; 2644 rpc_unset_page_directory_v unset_page_directory_v; 2645 rpc_get_gsp_static_info_v14_00 get_gsp_static_info_v14_00; 2646 rpc_get_gsp_static_info_v get_gsp_static_info_v; 2647 rpc_update_bar_pde_v15_00 update_bar_pde_v15_00; 2648 rpc_update_bar_pde_v update_bar_pde_v; 2649 rpc_vgpu_pf_reg_read32_v15_00 vgpu_pf_reg_read32_v15_00; 2650 rpc_vgpu_pf_reg_read32_v vgpu_pf_reg_read32_v; 2651 rpc_ctrl_subdevice_get_p2p_caps_v21_02 ctrl_subdevice_get_p2p_caps_v21_02; 2652 rpc_ctrl_subdevice_get_p2p_caps_v ctrl_subdevice_get_p2p_caps_v; 2653 rpc_ctrl_bus_set_p2p_mapping_v21_03 ctrl_bus_set_p2p_mapping_v21_03; 2654 rpc_ctrl_bus_set_p2p_mapping_v ctrl_bus_set_p2p_mapping_v; 2655 rpc_ctrl_bus_unset_p2p_mapping_v21_03 ctrl_bus_unset_p2p_mapping_v21_03; 2656 rpc_ctrl_bus_unset_p2p_mapping_v ctrl_bus_unset_p2p_mapping_v; 2657 rpc_rmfs_init_v15_00 rmfs_init_v15_00; 2658 rpc_rmfs_init_v rmfs_init_v; 2659 rpc_rmfs_test_v15_00 rmfs_test_v15_00; 2660 rpc_rmfs_test_v rmfs_test_v; 2661 rpc_gsp_set_system_info_v17_00 gsp_set_system_info_v17_00; 2662 rpc_gsp_set_system_info_v gsp_set_system_info_v; 2663 rpc_gsp_rm_alloc_v03_00 gsp_rm_alloc_v03_00; 2664 rpc_gsp_rm_alloc_v gsp_rm_alloc_v; 2665 rpc_gsp_rm_control_v03_00 gsp_rm_control_v03_00; 2666 rpc_gsp_rm_control_v gsp_rm_control_v; 2667 rpc_dump_protobuf_component_v18_12 dump_protobuf_component_v18_12; 2668 rpc_dump_protobuf_component_v dump_protobuf_component_v; 2669 rpc_run_cpu_sequencer_v17_00 run_cpu_sequencer_v17_00; 2670 rpc_run_cpu_sequencer_v run_cpu_sequencer_v; 2671 rpc_post_event_v17_00 post_event_v17_00; 2672 rpc_post_event_v post_event_v; 2673 rpc_rc_triggered_v17_02 rc_triggered_v17_02; 2674 rpc_rc_triggered_v rc_triggered_v; 2675 rpc_os_error_log_v17_00 os_error_log_v17_00; 2676 rpc_os_error_log_v os_error_log_v; 2677 rpc_rg_line_intr_v17_00 rg_line_intr_v17_00; 2678 rpc_rg_line_intr_v rg_line_intr_v; 2679 rpc_display_modeset_v01_00 display_modeset_v01_00; 2680 rpc_display_modeset_v display_modeset_v; 2681 rpc_gpuacct_perfmon_util_samples_v17_00 gpuacct_perfmon_util_samples_v17_00; 2682 rpc_gpuacct_perfmon_util_samples_v gpuacct_perfmon_util_samples_v; 2683 rpc_vgpu_gsp_plugin_triggered_v17_00 vgpu_gsp_plugin_triggered_v17_00; 2684 rpc_vgpu_gsp_plugin_triggered_v vgpu_gsp_plugin_triggered_v; 2685 rpc_vgpu_config_event_v17_00 vgpu_config_event_v17_00; 2686 rpc_vgpu_config_event_v vgpu_config_event_v; 2687 rpc_dce_rm_init_v01_00 dce_rm_init_v01_00; 2688 rpc_dce_rm_init_v dce_rm_init_v; 2689 rpc_sim_read_v1E_01 sim_read_v1E_01; 2690 rpc_sim_read_v sim_read_v; 2691 rpc_sim_write_v1E_01 sim_write_v1E_01; 2692 rpc_sim_write_v sim_write_v; 2693 rpc_ucode_libos_print_v1E_08 ucode_libos_print_v1E_08; 2694 rpc_ucode_libos_print_v ucode_libos_print_v; 2695 rpc_init_done_v17_00 init_done_v17_00; 2696 rpc_init_done_v init_done_v; 2697 rpc_semaphore_schedule_callback_v17_00 semaphore_schedule_callback_v17_00; 2698 rpc_semaphore_schedule_callback_v semaphore_schedule_callback_v; 2699 rpc_timed_semaphore_release_v01_00 timed_semaphore_release_v01_00; 2700 rpc_timed_semaphore_release_v timed_semaphore_release_v; 2701 rpc_perf_gpu_boost_sync_limits_callback_v17_00 perf_gpu_boost_sync_limits_callback_v17_00; 2702 rpc_perf_gpu_boost_sync_limits_callback_v perf_gpu_boost_sync_limits_callback_v; 2703 rpc_perf_bridgeless_info_update_v17_00 perf_bridgeless_info_update_v17_00; 2704 rpc_perf_bridgeless_info_update_v perf_bridgeless_info_update_v; 2705 rpc_nvlink_fault_up_v17_00 nvlink_fault_up_v17_00; 2706 rpc_nvlink_fault_up_v nvlink_fault_up_v; 2707 rpc_nvlink_inband_received_data_256_v17_00 nvlink_inband_received_data_256_v17_00; 2708 rpc_nvlink_inband_received_data_256_v nvlink_inband_received_data_256_v; 2709 rpc_nvlink_inband_received_data_512_v17_00 nvlink_inband_received_data_512_v17_00; 2710 rpc_nvlink_inband_received_data_512_v nvlink_inband_received_data_512_v; 2711 rpc_nvlink_inband_received_data_1024_v17_00 nvlink_inband_received_data_1024_v17_00; 2712 rpc_nvlink_inband_received_data_1024_v nvlink_inband_received_data_1024_v; 2713 rpc_nvlink_inband_received_data_2048_v17_00 nvlink_inband_received_data_2048_v17_00; 2714 rpc_nvlink_inband_received_data_2048_v nvlink_inband_received_data_2048_v; 2715 rpc_nvlink_inband_received_data_4096_v17_00 nvlink_inband_received_data_4096_v17_00; 2716 rpc_nvlink_inband_received_data_4096_v nvlink_inband_received_data_4096_v; 2717 rpc_nvlink_is_gpu_degraded_v17_00 nvlink_is_gpu_degraded_v17_00; 2718 rpc_nvlink_is_gpu_degraded_v nvlink_is_gpu_degraded_v; 2719 rpc_gsp_send_user_shared_data_v17_00 gsp_send_user_shared_data_v17_00; 2720 rpc_gsp_send_user_shared_data_v gsp_send_user_shared_data_v; 2721 rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 set_sysmem_dirty_page_tracking_buffer_v20_00; 2722 rpc_set_sysmem_dirty_page_tracking_buffer_v set_sysmem_dirty_page_tracking_buffer_v; 2723 rpc_extdev_intr_service_v17_00 extdev_intr_service_v17_00; 2724 rpc_extdev_intr_service_v extdev_intr_service_v; 2725 rpc_pfm_req_hndlr_state_sync_callback_v21_04 pfm_req_hndlr_state_sync_callback_v21_04; 2726 rpc_pfm_req_hndlr_state_sync_callback_v pfm_req_hndlr_state_sync_callback_v; 2727 rpc_gsp_lockdown_notice_v17_00 gsp_lockdown_notice_v17_00; 2728 rpc_gsp_lockdown_notice_v gsp_lockdown_notice_v; 2729 } rpc_generic_union; 2730 2731 #endif 2732 2733 #ifdef RPC_UNION_MEMBER_NAME_FUNCTIONS_CMD 2734 #define SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD 2735 #include "g_sdk-structures.h" 2736 #undef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD 2737 2738 #endif 2739 2740 2741 #ifdef RPC_ARRAY_LENGTH_FUNCTIONS 2742 #define SDK_ARRAY_LENGTH_FUNCTIONS 2743 #include "g_sdk-structures.h" 2744 #undef SDK_ARRAY_LENGTH_FUNCTIONS 2745 2746 // Array length functions for IDLE_CHANNELS: 2747 static NV_STATUS get_array_length_rpc_idle_channels_v03_00_channel_list(void *msg, NvS32 bytes_remaining, uint32_t* length) 2748 { 2749 rpc_idle_channels_v03_00 *param = msg; 2750 2751 if ((NvS32)(NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels) + sizeof(param->nchannels)) > bytes_remaining) 2752 return NV_ERR_BUFFER_TOO_SMALL; 2753 2754 *length = param->nchannels; 2755 return NV_OK; 2756 } 2757 2758 #endif 2759 2760 #ifdef AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION 2761 #define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR 0x18 2762 #define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR 0x00 2763 #endif 2764