1 // This file is automatically generated by rmconfig - DO NOT EDIT! 2 // 3 // Provides access to RPC Hal interfaces. 4 // 5 // Profile: shipping-gpus-openrm 6 // Haldef: rpc.def 7 // Template: templates/gt_eng_hal.h 8 // 9 10 #ifndef _G_RPCHAL_H_ 11 #define _G_RPCHAL_H_ 12 13 // 14 // Typedefs for RPC public object interfaces. 15 // 16 17 typedef NV_STATUS RpcConstruct(POBJGPU, POBJRPC); 18 typedef void RpcDestroy(POBJGPU, POBJRPC); 19 typedef NV_STATUS RpcSendMessage(POBJGPU, POBJRPC); 20 typedef NV_STATUS RpcRecvPoll(POBJGPU, POBJRPC, NvU32); 21 22 23 // 24 // "struct" to list RPC's public interfaces, eg: pRpc->rpcInit(pGpu, pRpc) 25 // 26 27 typedef struct RPC_OBJ_IFACES { 28 RpcConstruct *__rpcConstruct__ ; /* Construct the RPC object */ 29 RpcDestroy *__rpcDestroy__ ; /* Destroy the RPC object */ 30 RpcSendMessage *__rpcSendMessage__ ; /* Send an RPC message */ 31 RpcRecvPoll *__rpcRecvPoll__ ; /* Receive an RPC message */ 32 } RPC_OBJ_IFACES; 33 34 35 36 // 37 // macro defines to directly access RPC's OBJ interfaces, 38 // eg: #define rpcReadFoo(_pGpu, _pRpc) _pRpc->obj._rpcReadFoo(_pGpu, _pRpc) 39 // 40 41 #define rpcConstruct(_pGpu, _pRpc) \ 42 (_pRpc)->obj.__rpcConstruct__(_pGpu, _pRpc) 43 #define rpcDestroy(_pGpu, _pRpc) \ 44 (_pRpc)->obj.__rpcDestroy__(_pGpu, _pRpc) 45 #define rpcSendMessage(_pGpu, _pRpc) \ 46 (_pRpc)->obj.__rpcSendMessage__(_pGpu, _pRpc) 47 #define rpcRecvPoll(_pGpu, _pRpc, _arg0) \ 48 (_pRpc)->obj.__rpcRecvPoll__(_pGpu, _pRpc, _arg0) 49 50 51 // 52 // macro defines to access RPC's function pointers, 53 // eg: #define rpcReadFoo_FNPTR(_pRpc) _pRpc->obj.__rpcReadFoo__ 54 // or #define rpcReadFoo_FNPTR(_pRpc) _pRpc->__rpcReadFoo__ 55 // 56 57 #define rpcSendMessage_FNPTR(_pRpc) \ 58 (_pRpc)->obj.__rpcSendMessage__ 59 #define rpcRecvPoll_FNPTR(_pRpc) \ 60 (_pRpc)->obj.__rpcRecvPoll__ 61 62 63 // 64 // Typedefs for RPC HAL interfaces. 65 // 66 67 typedef NV_STATUS RpcCtrlFifoSetupVfZombieSubctxPdb(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 68 typedef NV_STATUS RpcVgpuPfRegRead32(POBJGPU, POBJRPC, NvU64, NvU32*, NvU32); 69 typedef NV_STATUS RpcCtrlBusUnsetP2pMapping(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 70 typedef NV_STATUS RpcDumpProtobufComponent(POBJGPU, POBJRPC, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, NVDUMP_COMPONENT component); 71 typedef NV_STATUS RpcEccNotifierWriteAck(POBJGPU, POBJRPC); 72 typedef NV_STATUS RpcAllocMemory(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, 73 NvU32, NvU32, MEMORY_DESCRIPTOR*); 74 typedef NV_STATUS RpcCtrlDbgReadSingleSmErrorState(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 75 typedef NV_STATUS RpcDisableChannels(POBJGPU, POBJRPC, NvU32); 76 typedef NV_STATUS RpcGpuExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, 77 NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS*, NV2080_CTRL_GPU_REG_OP*); 78 typedef NV_STATUS RpcCtrlGpuPromoteCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 79 typedef NV_STATUS RpcCtrlDbgSetNextStopTriggerType(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 80 typedef NV_STATUS RpcAllocShareDevice(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, 81 NvHandle, NvHandle, NvU32, NvU32, NvU64, NvU32); 82 typedef NV_STATUS RpcCtrlPreempt(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 83 typedef NV_STATUS RpcCtrlGpuInitializeCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 84 typedef NV_STATUS RpcCtrlReservePmAreaSmpc(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 85 typedef NV_STATUS RpcCtrlGpuMigratableOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 86 typedef NV_STATUS RpcCtrlDbgSetModeErrbarDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 87 typedef NV_STATUS RpcCtrlPmaStreamUpdateGetPut(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 88 typedef NV_STATUS RpcCtrlFabricMemoryDescribe(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 89 typedef NV_STATUS RpcAllocChannelDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, 90 NvU32, NV_CHANNEL_ALLOC_PARAMS*, NvU32*); 91 typedef NV_STATUS RpcCtrlSetZbcDepthClear(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 92 typedef NV_STATUS RpcCtrlResetIsolatedChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 93 typedef NV_STATUS RpcCtrlDmaSetDefaultVaspace(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 94 typedef NV_STATUS RpcAllocSubdevice(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvU32, NvU32); 95 typedef NV_STATUS RpcFree(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle); 96 typedef NV_STATUS RpcDmaControl(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32); 97 typedef NV_STATUS RpcCtrlDbgClearSingleSmErrorState(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 98 typedef NV_STATUS RpcUnsetPageDirectory(POBJGPU, POBJRPC, NvHandle, NvHandle, 99 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS*); 100 typedef NV_STATUS RpcGetGspStaticInfo(POBJGPU, POBJRPC); 101 typedef NV_STATUS RpcSaveHibernationData(POBJGPU, POBJRPC); 102 typedef NV_STATUS RpcDupObject(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, 103 NvHandle, NvHandle, NvU32); 104 typedef NV_STATUS RpcGspSetSystemInfo(POBJGPU, POBJRPC); 105 typedef NV_STATUS RpcCtrlPmAreaPcSampler(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*); 106 typedef NV_STATUS RpcCtrlDbgSetExceptionMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 107 typedef NV_STATUS RpcCtrlVaspaceCopyServerReservedPdes(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 108 typedef NV_STATUS RpcCtrlGrCtxswPreemptionBind(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 109 typedef NV_STATUS RpcCtrlAllocPmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 110 typedef NV_STATUS RpcCtrlReserveHwpmLegacy(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 111 typedef NV_STATUS RpcCtrlInternalQuiescePmaChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 112 typedef NV_STATUS RpcCtrlPerfRatedTdpGetStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 113 typedef NV_STATUS RpcCtrlBusSetP2pMapping(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 114 typedef NV_STATUS RpcCtrlGpuGetInfoV2(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 115 typedef NV_STATUS RpcCtrlGetHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 116 typedef NV_STATUS RpcCtrlGrSetCtxswPreemptionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 117 typedef NV_STATUS RpcCtrlB0ccExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 118 typedef NV_STATUS RpcCtrlGrmgrGetGrFsInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 119 typedef NV_STATUS RpcCtrlGetZbcClearTable(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 120 typedef NV_STATUS RpcCleanupSurface(POBJGPU, POBJRPC, 121 NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS*); 122 typedef NV_STATUS RpcCtrlSetTimeslice(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 123 typedef NV_STATUS RpcCtrlGpuQueryEccStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 124 typedef NV_STATUS RpcCtrlDbgGetModeMmuDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 125 typedef NV_STATUS RpcCtrlDbgClearAllSmErrorStates(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 126 typedef NV_STATUS RpcVgpuGspRingDoorbell(POBJGPU, NvU32); 127 typedef NV_STATUS RpcCtrlGrSetTpcPartitionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 128 typedef NV_STATUS RpcCtrlGetTotalHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 129 typedef NV_STATUS RpcCtrlInternalPromoteFaultMethodBuffers(OBJGPU *, OBJRPC *, NvHandle, NvHandle, void *); 130 typedef NV_STATUS RpcCtrlFbGetInfoV2(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 131 typedef NV_STATUS RpcVgpuGspWriteScratchRegister(POBJGPU, NvU64); 132 typedef NV_STATUS RpcSetPageDirectory(POBJGPU, POBJRPC, NvHandle, NvHandle, 133 NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS*); 134 typedef NV_STATUS RpcCtrlGetP2pCapsV2(POBJGPU, POBJRPC, void*); 135 typedef NV_STATUS RpcCtrlNvlinkGetInbandReceivedData(POBJGPU, POBJRPC, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS*, NvU16, NvBool*); 136 typedef NV_STATUS RpcCtrlGetCePceMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 137 typedef NV_STATUS RpcCtrlGetNvlinkPeerIdMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 138 typedef NV_STATUS RpcCtrlGpuEvictCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 139 typedef NV_STATUS RpcCtrlGetMmuDebugMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 140 typedef NV_STATUS RpcInvalidateTlb(POBJGPU, POBJRPC, NvU64, NvU32); 141 typedef NV_STATUS RpcCtrlDbgSetSingleSmSingleStep(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 142 typedef NV_STATUS RpcUnloadingGuestDriver(POBJGPU, POBJRPC, NvBool, NvBool, NvU32); 143 typedef NV_STATUS RpcGetEngineUtilizationWrapper(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32); 144 typedef NV_STATUS RpcGetConsolidatedGrStaticInfo(POBJGPU, POBJRPC); 145 typedef NV_STATUS RpcSwitchToVga(POBJGPU, POBJRPC); 146 typedef NV_STATUS RpcCtrlResetChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 147 typedef NV_STATUS RpcCtrlGpfifoSchedule(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*); 148 typedef NV_STATUS RpcSetRegistry(POBJGPU, POBJRPC); 149 typedef NV_STATUS RpcCtrlGetNvlinkStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 150 typedef NV_STATUS RpcGetStaticData(POBJGPU, POBJRPC); 151 typedef NV_STATUS RpcCtrlGrGetTpcPartitionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 152 typedef NV_STATUS RpcCtrlStopChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 153 typedef NV_STATUS RpcSetSurfaceProperties(POBJGPU, POBJRPC, NvHandle, 154 NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES*, 155 NvBool); 156 typedef NV_STATUS RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 157 typedef NV_STATUS RpcCtrlTimerSetGrTickFreq(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 158 typedef NV_STATUS RpcAllocEvent(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, 159 NvHandle, NvHandle, NvU32, NvU32); 160 typedef NV_STATUS RpcCtrlGrPcSamplingMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 161 typedef NV_STATUS RpcCtrlMcServiceInterrupts(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 162 typedef NV_STATUS RpcCtrlDbgReadAllSmErrorStates(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 163 typedef NV_STATUS RpcCtrlSetZbcColorClear(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 164 typedef NV_STATUS RpcGetEncoderCapacity(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32*); 165 typedef NV_STATUS RpcCtrlGetP2pCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 166 typedef NV_STATUS RpcPerfGetLevelInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, 167 NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS*, 168 NV2080_CTRL_PERF_GET_CLK_INFO*); 169 typedef NV_STATUS RpcAllocObject(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvU32, void*); 170 typedef NV_STATUS RpcCtrlGpuHandleVfPriFault(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 171 typedef NV_STATUS RpcRmApiControl(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32); 172 typedef NV_STATUS RpcCtrlFabricMemStats(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 173 typedef NV_STATUS RpcCtrlGrCtxswZcullBind(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 174 typedef NV_STATUS RpcCtrlInternalMemsysSetZbcReferenced(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 175 typedef NV_STATUS RpcCtrlPerfRatedTdpSetControl(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 176 typedef NV_STATUS RpcCtrlExecPartitionsCreate(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 177 typedef NV_STATUS RpcCtrlGpfifoGetWorkSubmitToken(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 178 typedef NV_STATUS RpcIdleChannels(OBJGPU *, OBJRPC *, NvHandle *phclients, 179 NvHandle *phdevices, NvHandle *phchannels, 180 NvU32 nentries, NvU32 flags, NvU32 timeout); 181 typedef NV_STATUS RpcCtrlCmdInternalGpuStartFabricProbe(POBJGPU, POBJRPC, NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS*); 182 typedef NV_STATUS RpcGetBrandCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32); 183 typedef NV_STATUS RpcRestoreHibernationData(POBJGPU, POBJRPC); 184 typedef NV_STATUS RpcCtrlFlaSetupInstanceMemBlock(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 185 typedef NV_STATUS RpcCtrlInternalSriovPromotePmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 186 typedef NV_STATUS RpcCtrlFbGetFsInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 187 typedef NV_STATUS RpcCtrlSetChannelInterleaveLevel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 188 typedef NV_STATUS RpcCtrlDbgResumeContext(POBJGPU, POBJRPC, NvHandle, NvHandle); 189 typedef NV_STATUS RpcAllocRoot(POBJGPU, POBJRPC, NvHandle); 190 typedef NV_STATUS RpcCtrlFifoDisableChannels(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 191 typedef NV_STATUS RpcCtrlSetHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 192 typedef NV_STATUS RpcGetEngineUtilization(POBJGPU, POBJRPC, NvHandle, 193 NvHandle, NvU32, void*, NvU32); 194 typedef NV_STATUS RpcCtrlGetZbcClearTableEntry(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 195 typedef NV_STATUS RpcCtrlNvencSwSessionUpdateInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 196 typedef NV_STATUS RpcCtrlDbgSuspendContext(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 197 typedef NV_STATUS RpcCtrlGetP2pCapsMatrix(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 198 typedef NV_STATUS RpcCtrlDbgExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 199 typedef NV_STATUS RpcCtrlFreePmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 200 typedef NV_STATUS RpcCtrlSetTsgInterleaveLevel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 201 typedef NV_STATUS RpcCtrlMasterGetVirtualFunctionErrorContIntrMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 202 typedef NV_STATUS RpcLog(POBJGPU, POBJRPC, const char*, NvU32); 203 typedef NV_STATUS RpcCtrlExecPartitionsDelete(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 204 typedef NV_STATUS RpcCtrlPerfBoost(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 205 typedef NV_STATUS RpcCtrlDbgSetModeMmuDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 206 typedef NV_STATUS RpcCtrlFifoSetChannelProperties(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 207 typedef NV_STATUS RpcCtrlSubdeviceGetP2pCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); 208 typedef NV_STATUS RpcUpdateBarPde(POBJGPU, POBJRPC, NV_RPC_UPDATE_PDE_BAR_TYPE, NvU64, NvU64); 209 typedef NV_STATUS RpcCtrlBindPmResources(POBJGPU, POBJRPC, NvHandle, NvHandle); 210 typedef NV_STATUS RpcMapMemoryDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, 211 NvHandle, NvU64, NvU64, NvU32, NvU64*); 212 typedef NV_STATUS RpcUnmapMemoryDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU64); 213 typedef NV_STATUS RpcSetGuestSystemInfoExt(POBJGPU, POBJRPC); 214 typedef NV_STATUS Rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *); 215 216 217 // 218 // struct to access RPC's hal interfaces, eg: pRpc->hal.rpcReadFoo(pGpu, pRpc) 219 // 220 221 typedef struct RPC_HAL_IFACES { 222 RpcCtrlFifoSetupVfZombieSubctxPdb *rpcCtrlFifoSetupVfZombieSubctxPdb; /* CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB */ 223 RpcVgpuPfRegRead32 *rpcVgpuPfRegRead32; /* Read reg value from plugin */ 224 RpcCtrlBusUnsetP2pMapping *rpcCtrlBusUnsetP2pMapping; /* CTRL_BUS_UNSET_P2P_MAPPING */ 225 RpcDumpProtobufComponent *rpcDumpProtobufComponent; /* Dump a GSP component into the protobuf. */ 226 RpcEccNotifierWriteAck *rpcEccNotifierWriteAck; /* ECC_NOTIFIER_WRITE_ACK */ 227 RpcAllocMemory *rpcAllocMemory; /* ALLOC_MEMORY */ 228 RpcCtrlDbgReadSingleSmErrorState *rpcCtrlDbgReadSingleSmErrorState; /* CTRL_DBG_READ_SINGLE_SM_ERROR_STATE */ 229 RpcDisableChannels *rpcDisableChannels; /* Disable channels */ 230 RpcGpuExecRegOps *rpcGpuExecRegOps; /* GPU_EXEC_REG_OPS */ 231 RpcCtrlGpuPromoteCtx *rpcCtrlGpuPromoteCtx; /* GPU_PROMOTE_CTX */ 232 RpcCtrlDbgSetNextStopTriggerType *rpcCtrlDbgSetNextStopTriggerType; /* CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE */ 233 RpcAllocShareDevice *rpcAllocShareDevice; /* ALLOC_SHARE_DEVICE */ 234 RpcCtrlPreempt *rpcCtrlPreempt; /* CTRL_PREEMPT */ 235 RpcCtrlGpuInitializeCtx *rpcCtrlGpuInitializeCtx; /* CTRL_GPU_INITIALIZE_CTX */ 236 RpcCtrlReservePmAreaSmpc *rpcCtrlReservePmAreaSmpc; /* CTRL_RESERVE_PM_AREA_SMPC */ 237 RpcCtrlGpuMigratableOps *rpcCtrlGpuMigratableOps; /* NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS */ 238 RpcCtrlDbgSetModeErrbarDebug *rpcCtrlDbgSetModeErrbarDebug; /* CTRL_DBG_SET_MODE_ERRBAR_DEBUG */ 239 RpcCtrlPmaStreamUpdateGetPut *rpcCtrlPmaStreamUpdateGetPut; /* CTRL_HWPM_STREAMOUT_UPDATE_GET_PUT */ 240 RpcCtrlFabricMemoryDescribe *rpcCtrlFabricMemoryDescribe; /* CTRL_FABRIC_MEMORY_DESCRIBE */ 241 RpcAllocChannelDma *rpcAllocChannelDma; /* ALLOC_CHANNEL_DMA */ 242 RpcCtrlSetZbcDepthClear *rpcCtrlSetZbcDepthClear; /* CTRL_SET_ZBC_DEPTH_CLEAR */ 243 RpcCtrlResetIsolatedChannel *rpcCtrlResetIsolatedChannel; /* CTRL_RESET_ISOLATED_CHANNEL */ 244 RpcCtrlDmaSetDefaultVaspace *rpcCtrlDmaSetDefaultVaspace; /* CTRL_DMA_SET_DEFAULT_VASPACE */ 245 RpcAllocSubdevice *rpcAllocSubdevice; /* ALLOC_SUBDEVICE */ 246 RpcFree *rpcFree; /* FREE */ 247 RpcDmaControl *rpcDmaControl; /* DMA_CONTROL */ 248 RpcCtrlDbgClearSingleSmErrorState *rpcCtrlDbgClearSingleSmErrorState; /* CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE */ 249 RpcUnsetPageDirectory *rpcUnsetPageDirectory; /* UNSET_PAGE_DIRECTORY */ 250 RpcGetGspStaticInfo *rpcGetGspStaticInfo; /* Get static info from GSP RM. */ 251 RpcSaveHibernationData *rpcSaveHibernationData; /* SAVE_HIBERNATION_DATA */ 252 RpcDupObject *rpcDupObject; /* DUP_OBJECT */ 253 RpcGspSetSystemInfo *rpcGspSetSystemInfo; /* Tells GSP-RM about the overall system environment */ 254 RpcCtrlPmAreaPcSampler *rpcCtrlPmAreaPcSampler; /* CTRL_PM_AREA_PC_SAMPLER */ 255 RpcCtrlDbgSetExceptionMask *rpcCtrlDbgSetExceptionMask; /* CTRL_DBG_SET_EXCEPTION_MASK */ 256 RpcCtrlVaspaceCopyServerReservedPdes *rpcCtrlVaspaceCopyServerReservedPdes; /* CTRL_VASPACE_COPY_SERVER_RESERVED_PDES */ 257 RpcCtrlGrCtxswPreemptionBind *rpcCtrlGrCtxswPreemptionBind; /* CTRL_GR_CTXSW_PREEMPTION_BIND */ 258 RpcCtrlAllocPmaStream *rpcCtrlAllocPmaStream; /* CTRL_ALLOC_PMA_STREAM */ 259 RpcCtrlReserveHwpmLegacy *rpcCtrlReserveHwpmLegacy; /* CTRL_RESERVE_HWPM_LEGACY */ 260 RpcCtrlInternalQuiescePmaChannel *rpcCtrlInternalQuiescePmaChannel; /* CTRL_INTERNAL_QUIESCE_PMA_CHANNEL */ 261 RpcCtrlPerfRatedTdpGetStatus *rpcCtrlPerfRatedTdpGetStatus; /* CTRL_PERF_RATED_TDP_GET_STATUS */ 262 RpcCtrlBusSetP2pMapping *rpcCtrlBusSetP2pMapping; /* CTRL_BUS_SET_P2P_MAPPING */ 263 RpcCtrlGpuGetInfoV2 *rpcCtrlGpuGetInfoV2; /* CTRL_GPU_GET_INFO_V2 */ 264 RpcCtrlGetHsCredits *rpcCtrlGetHsCredits; /* CTRL_GET_HS_CREDITS */ 265 RpcCtrlGrSetCtxswPreemptionMode *rpcCtrlGrSetCtxswPreemptionMode; /* CTRL_GR_SET_CTXSW_PREEMPTION_MODE */ 266 RpcCtrlB0ccExecRegOps *rpcCtrlB0ccExecRegOps; /* CTRL_B0CC_EXEC_REG_OPS */ 267 RpcCtrlGrmgrGetGrFsInfo *rpcCtrlGrmgrGetGrFsInfo; /* CTRL_GRMGR_GET_GR_FS_INFO */ 268 RpcCtrlGetZbcClearTable *rpcCtrlGetZbcClearTable; /* CTRL_GET_ZBC_CLEAR_TABLE */ 269 RpcCleanupSurface *rpcCleanupSurface; /* CLEANUP_SURFACE */ 270 RpcCtrlSetTimeslice *rpcCtrlSetTimeslice; /* CTRL_SET_TIMESLICE */ 271 RpcCtrlGpuQueryEccStatus *rpcCtrlGpuQueryEccStatus; /* CTRL_GPU_QUERY_ECC_STATUS */ 272 RpcCtrlDbgGetModeMmuDebug *rpcCtrlDbgGetModeMmuDebug; /* CTRL_DBG_GET_MODE_MMU_DEBUG */ 273 RpcCtrlDbgClearAllSmErrorStates *rpcCtrlDbgClearAllSmErrorStates; /* CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES */ 274 RpcVgpuGspRingDoorbell *rpcVgpuGspRingDoorbell; /* Ring the doorbell register */ 275 RpcCtrlGrSetTpcPartitionMode *rpcCtrlGrSetTpcPartitionMode; /* CTRL_GR_SET_TPC_PARTITION_MODE */ 276 RpcCtrlGetTotalHsCredits *rpcCtrlGetTotalHsCredits; /* CTRL_GET_TOTAL_HS_CREDITS */ 277 RpcCtrlInternalPromoteFaultMethodBuffers *rpcCtrlInternalPromoteFaultMethodBuffers; /* CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS */ 278 RpcCtrlFbGetInfoV2 *rpcCtrlFbGetInfoV2; /* CTRL_FB_GET_INFO_V2 */ 279 RpcVgpuGspWriteScratchRegister *rpcVgpuGspWriteScratchRegister; /* Write the vGPU GSP scratch register */ 280 RpcSetPageDirectory *rpcSetPageDirectory; /* SET_PAGE_DIRECTORY */ 281 RpcCtrlGetP2pCapsV2 *rpcCtrlGetP2pCapsV2; /* CTRL_GET_P2P_CAPS_V2 */ 282 RpcCtrlNvlinkGetInbandReceivedData *rpcCtrlNvlinkGetInbandReceivedData; /* CTRL_NVLINK_GET_INBAND_RECEIVED_DATA */ 283 RpcCtrlGetCePceMask *rpcCtrlGetCePceMask; /* CTRL_GET_CE_PCE_MASK */ 284 RpcCtrlGetNvlinkPeerIdMask *rpcCtrlGetNvlinkPeerIdMask; /* CTRL_GET_NVLINK_PEER_ID_MASK */ 285 RpcCtrlGpuEvictCtx *rpcCtrlGpuEvictCtx; /* CTRL_GPU_EVICT_CTX */ 286 RpcCtrlGetMmuDebugMode *rpcCtrlGetMmuDebugMode; /* CTRL_GET_MMU_DEBUG_MODE */ 287 RpcInvalidateTlb *rpcInvalidateTlb; /* INVALIDATE_TLB */ 288 RpcCtrlDbgSetSingleSmSingleStep *rpcCtrlDbgSetSingleSmSingleStep; /* CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP */ 289 RpcUnloadingGuestDriver *rpcUnloadingGuestDriver; /* UNLOADING_GUEST_DRIVER */ 290 RpcGetEngineUtilizationWrapper *rpcGetEngineUtilizationWrapper; /* Get engine utilization wrapper */ 291 RpcGetConsolidatedGrStaticInfo *rpcGetConsolidatedGrStaticInfo; /* GET_CONSOLIDATED_GR_STATIC_INFO */ 292 RpcSwitchToVga *rpcSwitchToVga; /* SWITCH_TO_VGA */ 293 RpcCtrlResetChannel *rpcCtrlResetChannel; /* CTRL_RESET_CHANNEL */ 294 RpcCtrlGpfifoSchedule *rpcCtrlGpfifoSchedule; /* CTRL_GPFIFO_SCHEDULE */ 295 RpcSetRegistry *rpcSetRegistry; /* GSP Init Set registry values */ 296 RpcCtrlGetNvlinkStatus *rpcCtrlGetNvlinkStatus; /* CTRL_NVLINK_GET_NVLINK_STATUS */ 297 RpcGetStaticData *rpcGetStaticData; /* GET_STATIC_DATA published for OpenRM */ 298 RpcCtrlGrGetTpcPartitionMode *rpcCtrlGrGetTpcPartitionMode; /* CTRL_GR_GET_TPC_PARTITION_MODE */ 299 RpcCtrlStopChannel *rpcCtrlStopChannel; /* CTRL_STOP_CHANNEL */ 300 RpcSetSurfaceProperties *rpcSetSurfaceProperties; /* SET_SURFACE_PROPERTIES */ 301 RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex *rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex; /* CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX */ 302 RpcCtrlTimerSetGrTickFreq *rpcCtrlTimerSetGrTickFreq; /* CTRL_TIMER_SET_GR_TICK_FREQ */ 303 RpcAllocEvent *rpcAllocEvent; /* ALLOC_EVENT */ 304 RpcCtrlGrPcSamplingMode *rpcCtrlGrPcSamplingMode; /* CTRL_GR_PC_SAMPLING_MODE */ 305 RpcCtrlMcServiceInterrupts *rpcCtrlMcServiceInterrupts; /* CTRL_MC_SERVICE_INTERRUPTS */ 306 RpcCtrlDbgReadAllSmErrorStates *rpcCtrlDbgReadAllSmErrorStates; /* CTRL_DBG_READ_ALL_SM_ERROR_STATES */ 307 RpcCtrlSetZbcColorClear *rpcCtrlSetZbcColorClear; /* CTRL_SET_ZBC_COLOR_CLEAR */ 308 RpcGetEncoderCapacity *rpcGetEncoderCapacity; /* Get encoder capacity */ 309 RpcCtrlGetP2pCaps *rpcCtrlGetP2pCaps; /* CTRL_GET_P2P_CAPS */ 310 RpcPerfGetLevelInfo *rpcPerfGetLevelInfo; /* PERF_GET_LEVEL_INFO */ 311 RpcAllocObject *rpcAllocObject; /* ALLOC_OBJECT */ 312 RpcCtrlGpuHandleVfPriFault *rpcCtrlGpuHandleVfPriFault; /* CTRL_GPU_HANDLE_VF_PRI_FAULT */ 313 RpcRmApiControl *rpcRmApiControl; /* RM_API_CONTROL */ 314 RpcCtrlFabricMemStats *rpcCtrlFabricMemStats; /* CTRL_FABRIC_MEM_STATS */ 315 RpcCtrlGrCtxswZcullBind *rpcCtrlGrCtxswZcullBind; /* CTRL_GR_CTXSW_ZCULL_BIND */ 316 RpcCtrlInternalMemsysSetZbcReferenced *rpcCtrlInternalMemsysSetZbcReferenced; /* CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED */ 317 RpcCtrlPerfRatedTdpSetControl *rpcCtrlPerfRatedTdpSetControl; /* CTRL_PERF_RATED_TDP_SET_CONTROL */ 318 RpcCtrlExecPartitionsCreate *rpcCtrlExecPartitionsCreate; /* CTRL_EXEC_PARTITIONS_CREATE */ 319 RpcCtrlGpfifoGetWorkSubmitToken *rpcCtrlGpfifoGetWorkSubmitToken; /* CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN */ 320 RpcIdleChannels *rpcIdleChannels; /* IDLE_CHANNELS */ 321 RpcCtrlCmdInternalGpuStartFabricProbe *rpcCtrlCmdInternalGpuStartFabricProbe; /* CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS */ 322 RpcGetBrandCaps *rpcGetBrandCaps; /* GET_BRAND_CAPS */ 323 RpcRestoreHibernationData *rpcRestoreHibernationData; /* RESTORE_HIBERNATION_DATA */ 324 RpcCtrlFlaSetupInstanceMemBlock *rpcCtrlFlaSetupInstanceMemBlock; /* NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK */ 325 RpcCtrlInternalSriovPromotePmaStream *rpcCtrlInternalSriovPromotePmaStream; /* CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM */ 326 RpcCtrlFbGetFsInfo *rpcCtrlFbGetFsInfo; /* CTRL_FB_GET_FS_INFO */ 327 RpcCtrlSetChannelInterleaveLevel *rpcCtrlSetChannelInterleaveLevel; /* CTRL_SET_CHANNEL_INTERLEAVE_LEVEL */ 328 RpcCtrlDbgResumeContext *rpcCtrlDbgResumeContext; /* CTRL_DBG_RESUME_CONTEXT */ 329 RpcAllocRoot *rpcAllocRoot; /* ALLOC_ROOT */ 330 RpcCtrlFifoDisableChannels *rpcCtrlFifoDisableChannels; /* CTRL_FIFO_DISABLE_CHANNELS */ 331 RpcCtrlSetHsCredits *rpcCtrlSetHsCredits; /* CTRL_SET_HS_CREDITS */ 332 RpcGetEngineUtilization *rpcGetEngineUtilization; /* GET_ENGINE_UTILIZATION */ 333 RpcCtrlGetZbcClearTableEntry *rpcCtrlGetZbcClearTableEntry; /* CTRL_GET_ZBC_CLEAR_TABLE_ENTRY */ 334 RpcCtrlNvencSwSessionUpdateInfo *rpcCtrlNvencSwSessionUpdateInfo; /* CTRL_NVENC_SW_SESSION_UPDATE_INFO */ 335 RpcCtrlDbgSuspendContext *rpcCtrlDbgSuspendContext; /* CTRL_DBG_SUSPEND_CONTEXT */ 336 RpcCtrlGetP2pCapsMatrix *rpcCtrlGetP2pCapsMatrix; /* CTRL_GET_P2P_CAPS_MATRIX */ 337 RpcCtrlDbgExecRegOps *rpcCtrlDbgExecRegOps; /* CTRL_DBG_EXEC_REG_OPS */ 338 RpcCtrlFreePmaStream *rpcCtrlFreePmaStream; /* CTRL_FREE_PMA_STREAM */ 339 RpcCtrlSetTsgInterleaveLevel *rpcCtrlSetTsgInterleaveLevel; /* CTRL_SET_TSG_INTERLEAVE_LEVEL */ 340 RpcCtrlMasterGetVirtualFunctionErrorContIntrMask *rpcCtrlMasterGetVirtualFunctionErrorContIntrMask; /* CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK */ 341 RpcLog *rpcLog; /* LOG */ 342 RpcCtrlExecPartitionsDelete *rpcCtrlExecPartitionsDelete; /* CTRL_EXEC_PARTITIONS_DELETE */ 343 RpcCtrlPerfBoost *rpcCtrlPerfBoost; /* CTRL_PERF_BOOST */ 344 RpcCtrlDbgSetModeMmuDebug *rpcCtrlDbgSetModeMmuDebug; /* CTRL_DBG_SET_MODE_MMU_DEBUG */ 345 RpcCtrlFifoSetChannelProperties *rpcCtrlFifoSetChannelProperties; /* CTRL_FIFO_SET_CHANNEL_PROPERTIES */ 346 RpcCtrlSubdeviceGetP2pCaps *rpcCtrlSubdeviceGetP2pCaps; /* CTRL_SUBDEVICE_GET_P2P_CAPS */ 347 RpcUpdateBarPde *rpcUpdateBarPde; /* Update the value of BAR1/BAR2 PDE */ 348 RpcCtrlBindPmResources *rpcCtrlBindPmResources; /* CTRL_BIND_PM_RESOURCES */ 349 RpcMapMemoryDma *rpcMapMemoryDma; /* MAP_MEMORY_DMA */ 350 RpcUnmapMemoryDma *rpcUnmapMemoryDma; /* UNMAP_MEMORY_DMA */ 351 RpcSetGuestSystemInfoExt *rpcSetGuestSystemInfoExt; /* SET_GUEST_SYSTEM_INFO_EXT */ 352 Rpc_iGrp_ipVersions_getInfo *rpc_iGrp_ipVersions_getInfo; /* Return lookup table of hal interface ptrs based on IP_VERSION */ 353 } RPC_HAL_IFACES; 354 355 356 // 357 // macro defines to directly access RPC's hal interfaces, 358 // eg: #define rpcReadFoo_HAL(_pGpu, _pRpc) _pRpc->hal.rpcReadFoo(_pGpu, _pRpc) 359 // 360 361 #define rpcCtrlFifoSetupVfZombieSubctxPdb_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 362 (_pRpc)->_hal.rpcCtrlFifoSetupVfZombieSubctxPdb(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 363 #define rpcVgpuPfRegRead32_HAL(_pGpu, _pRpc, _arg0, _pArg1, _arg2) \ 364 (_pRpc)->_hal.rpcVgpuPfRegRead32(_pGpu, _pRpc, _arg0, _pArg1, _arg2) 365 #define rpcCtrlBusUnsetP2pMapping_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 366 (_pRpc)->_hal.rpcCtrlBusUnsetP2pMapping(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 367 #define rpcDumpProtobufComponent_HAL(_pGpu, _pRpc, _pPrbEnc, _pNvDumpState, _component) \ 368 (_pRpc)->_hal.rpcDumpProtobufComponent(_pGpu, _pRpc, _pPrbEnc, _pNvDumpState, _component) 369 #define rpcEccNotifierWriteAck_HAL(_pGpu, _pRpc) \ 370 (_pRpc)->_hal.rpcEccNotifierWriteAck(_pGpu, _pRpc) 371 #define rpcAllocMemory_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _pArg5) \ 372 (_pRpc)->_hal.rpcAllocMemory(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _pArg5) 373 #define rpcCtrlDbgReadSingleSmErrorState_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 374 (_pRpc)->_hal.rpcCtrlDbgReadSingleSmErrorState(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 375 #define rpcDisableChannels_HAL(_pGpu, _pRpc, _arg0) \ 376 (_pRpc)->_hal.rpcDisableChannels(_pGpu, _pRpc, _arg0) 377 #define rpcGpuExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) \ 378 (_pRpc)->_hal.rpcGpuExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) 379 #define rpcCtrlGpuPromoteCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 380 (_pRpc)->_hal.rpcCtrlGpuPromoteCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 381 #define rpcCtrlDbgSetNextStopTriggerType_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 382 (_pRpc)->_hal.rpcCtrlDbgSetNextStopTriggerType(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 383 #define rpcAllocShareDevice_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _arg7, _arg8) \ 384 (_pRpc)->_hal.rpcAllocShareDevice(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _arg7, _arg8) 385 #define rpcCtrlPreempt_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 386 (_pRpc)->_hal.rpcCtrlPreempt(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 387 #define rpcCtrlGpuInitializeCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 388 (_pRpc)->_hal.rpcCtrlGpuInitializeCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 389 #define rpcCtrlReservePmAreaSmpc_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 390 (_pRpc)->_hal.rpcCtrlReservePmAreaSmpc(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 391 #define rpcCtrlGpuMigratableOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 392 (_pRpc)->_hal.rpcCtrlGpuMigratableOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 393 #define rpcCtrlDbgSetModeErrbarDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 394 (_pRpc)->_hal.rpcCtrlDbgSetModeErrbarDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 395 #define rpcCtrlPmaStreamUpdateGetPut_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 396 (_pRpc)->_hal.rpcCtrlPmaStreamUpdateGetPut(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 397 #define rpcCtrlFabricMemoryDescribe_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 398 (_pRpc)->_hal.rpcCtrlFabricMemoryDescribe(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 399 #define rpcAllocChannelDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4, _pArg5) \ 400 (_pRpc)->_hal.rpcAllocChannelDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4, _pArg5) 401 #define rpcCtrlSetZbcDepthClear_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 402 (_pRpc)->_hal.rpcCtrlSetZbcDepthClear(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 403 #define rpcCtrlResetIsolatedChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 404 (_pRpc)->_hal.rpcCtrlResetIsolatedChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 405 #define rpcCtrlDmaSetDefaultVaspace_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 406 (_pRpc)->_hal.rpcCtrlDmaSetDefaultVaspace(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 407 #define rpcAllocSubdevice_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4) \ 408 (_pRpc)->_hal.rpcAllocSubdevice(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4) 409 #define rpcFree_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \ 410 (_pRpc)->_hal.rpcFree(_pGpu, _pRpc, _arg0, _arg1, _arg2) 411 #define rpcDmaControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ 412 (_pRpc)->_hal.rpcDmaControl(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) 413 #define rpcCtrlDbgClearSingleSmErrorState_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 414 (_pRpc)->_hal.rpcCtrlDbgClearSingleSmErrorState(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 415 #define rpcUnsetPageDirectory_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 416 (_pRpc)->_hal.rpcUnsetPageDirectory(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 417 #define rpcGetGspStaticInfo_HAL(_pGpu, _pRpc) \ 418 (_pRpc)->_hal.rpcGetGspStaticInfo(_pGpu, _pRpc) 419 #define rpcSaveHibernationData_HAL(_pGpu, _pRpc) \ 420 (_pRpc)->_hal.rpcSaveHibernationData(_pGpu, _pRpc) 421 #define rpcDupObject_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) \ 422 (_pRpc)->_hal.rpcDupObject(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) 423 #define rpcGspSetSystemInfo_HAL(_pGpu, _pRpc) \ 424 (_pRpc)->_hal.rpcGspSetSystemInfo(_pGpu, _pRpc) 425 #define rpcCtrlPmAreaPcSampler_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) \ 426 (_pRpc)->_hal.rpcCtrlPmAreaPcSampler(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) 427 #define rpcCtrlDbgSetExceptionMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 428 (_pRpc)->_hal.rpcCtrlDbgSetExceptionMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 429 #define rpcCtrlVaspaceCopyServerReservedPdes_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 430 (_pRpc)->_hal.rpcCtrlVaspaceCopyServerReservedPdes(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 431 #define rpcCtrlGrCtxswPreemptionBind_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 432 (_pRpc)->_hal.rpcCtrlGrCtxswPreemptionBind(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 433 #define rpcCtrlAllocPmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 434 (_pRpc)->_hal.rpcCtrlAllocPmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 435 #define rpcCtrlReserveHwpmLegacy_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 436 (_pRpc)->_hal.rpcCtrlReserveHwpmLegacy(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 437 #define rpcCtrlInternalQuiescePmaChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 438 (_pRpc)->_hal.rpcCtrlInternalQuiescePmaChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 439 #define rpcCtrlPerfRatedTdpGetStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 440 (_pRpc)->_hal.rpcCtrlPerfRatedTdpGetStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 441 #define rpcCtrlBusSetP2pMapping_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 442 (_pRpc)->_hal.rpcCtrlBusSetP2pMapping(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 443 #define rpcCtrlGpuGetInfoV2_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 444 (_pRpc)->_hal.rpcCtrlGpuGetInfoV2(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 445 #define rpcCtrlGetHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 446 (_pRpc)->_hal.rpcCtrlGetHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 447 #define rpcCtrlGrSetCtxswPreemptionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 448 (_pRpc)->_hal.rpcCtrlGrSetCtxswPreemptionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 449 #define rpcCtrlB0ccExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 450 (_pRpc)->_hal.rpcCtrlB0ccExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 451 #define rpcCtrlGrmgrGetGrFsInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 452 (_pRpc)->_hal.rpcCtrlGrmgrGetGrFsInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 453 #define rpcCtrlGetZbcClearTable_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 454 (_pRpc)->_hal.rpcCtrlGetZbcClearTable(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 455 #define rpcCleanupSurface_HAL(_pGpu, _pRpc, _pArg0) \ 456 (_pRpc)->_hal.rpcCleanupSurface(_pGpu, _pRpc, _pArg0) 457 #define rpcCtrlSetTimeslice_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 458 (_pRpc)->_hal.rpcCtrlSetTimeslice(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 459 #define rpcCtrlGpuQueryEccStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 460 (_pRpc)->_hal.rpcCtrlGpuQueryEccStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 461 #define rpcCtrlDbgGetModeMmuDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 462 (_pRpc)->_hal.rpcCtrlDbgGetModeMmuDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 463 #define rpcCtrlDbgClearAllSmErrorStates_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 464 (_pRpc)->_hal.rpcCtrlDbgClearAllSmErrorStates(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 465 #define rpcVgpuGspRingDoorbell_HAL(_pRpc, _pGpu, _arg0) \ 466 (_pRpc)->_hal.rpcVgpuGspRingDoorbell(_pGpu, _arg0) 467 #define rpcCtrlGrSetTpcPartitionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 468 (_pRpc)->_hal.rpcCtrlGrSetTpcPartitionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 469 #define rpcCtrlGetTotalHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 470 (_pRpc)->_hal.rpcCtrlGetTotalHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 471 #define rpcCtrlInternalPromoteFaultMethodBuffers_HAL(_pArg0, _pRpc, _arg1, _arg2, _pArg3) \ 472 (_pRpc)->_hal.rpcCtrlInternalPromoteFaultMethodBuffers(_pArg0, _pRpc, _arg1, _arg2, _pArg3) 473 #define rpcCtrlFbGetInfoV2_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 474 (_pRpc)->_hal.rpcCtrlFbGetInfoV2(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 475 #define rpcVgpuGspWriteScratchRegister_HAL(_pRpc, _pGpu, _arg0) \ 476 (_pRpc)->_hal.rpcVgpuGspWriteScratchRegister(_pGpu, _arg0) 477 #define rpcSetPageDirectory_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 478 (_pRpc)->_hal.rpcSetPageDirectory(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 479 #define rpcCtrlGetP2pCapsV2_HAL(_pGpu, _pRpc, _pArg0) \ 480 (_pRpc)->_hal.rpcCtrlGetP2pCapsV2(_pGpu, _pRpc, _pArg0) 481 #define rpcCtrlNvlinkGetInbandReceivedData_HAL(_pGpu, _pRpc, _pArg0, _arg1, _pArg2) \ 482 (_pRpc)->_hal.rpcCtrlNvlinkGetInbandReceivedData(_pGpu, _pRpc, _pArg0, _arg1, _pArg2) 483 #define rpcCtrlGetCePceMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 484 (_pRpc)->_hal.rpcCtrlGetCePceMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 485 #define rpcCtrlGetNvlinkPeerIdMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 486 (_pRpc)->_hal.rpcCtrlGetNvlinkPeerIdMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 487 #define rpcCtrlGpuEvictCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 488 (_pRpc)->_hal.rpcCtrlGpuEvictCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 489 #define rpcCtrlGetMmuDebugMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 490 (_pRpc)->_hal.rpcCtrlGetMmuDebugMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 491 #define rpcInvalidateTlb_HAL(_pGpu, _pRpc, _arg0, _arg1) \ 492 (_pRpc)->_hal.rpcInvalidateTlb(_pGpu, _pRpc, _arg0, _arg1) 493 #define rpcCtrlDbgSetSingleSmSingleStep_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 494 (_pRpc)->_hal.rpcCtrlDbgSetSingleSmSingleStep(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 495 #define rpcUnloadingGuestDriver_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \ 496 (_pRpc)->_hal.rpcUnloadingGuestDriver(_pGpu, _pRpc, _arg0, _arg1, _arg2) 497 #define rpcGetEngineUtilizationWrapper_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ 498 (_pRpc)->_hal.rpcGetEngineUtilizationWrapper(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) 499 #define rpcGetConsolidatedGrStaticInfo_HAL(_pGpu, _pRpc) \ 500 (_pRpc)->_hal.rpcGetConsolidatedGrStaticInfo(_pGpu, _pRpc) 501 #define rpcSwitchToVga_HAL(_pGpu, _pRpc) \ 502 (_pRpc)->_hal.rpcSwitchToVga(_pGpu, _pRpc) 503 #define rpcCtrlResetChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 504 (_pRpc)->_hal.rpcCtrlResetChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 505 #define rpcCtrlGpfifoSchedule_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) \ 506 (_pRpc)->_hal.rpcCtrlGpfifoSchedule(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) 507 #define rpcSetRegistry_HAL(_pGpu, _pRpc) \ 508 (_pRpc)->_hal.rpcSetRegistry(_pGpu, _pRpc) 509 #define rpcCtrlGetNvlinkStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 510 (_pRpc)->_hal.rpcCtrlGetNvlinkStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 511 #define rpcGetStaticData_HAL(_pGpu, _pRpc) \ 512 (_pRpc)->_hal.rpcGetStaticData(_pGpu, _pRpc) 513 #define rpcCtrlGrGetTpcPartitionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 514 (_pRpc)->_hal.rpcCtrlGrGetTpcPartitionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 515 #define rpcCtrlStopChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 516 (_pRpc)->_hal.rpcCtrlStopChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 517 #define rpcSetSurfaceProperties_HAL(_pGpu, _pRpc, _arg0, _pArg1, _arg2) \ 518 (_pRpc)->_hal.rpcSetSurfaceProperties(_pGpu, _pRpc, _arg0, _pArg1, _arg2) 519 #define rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 520 (_pRpc)->_hal.rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 521 #define rpcCtrlTimerSetGrTickFreq_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 522 (_pRpc)->_hal.rpcCtrlTimerSetGrTickFreq(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 523 #define rpcAllocEvent_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6) \ 524 (_pRpc)->_hal.rpcAllocEvent(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6) 525 #define rpcCtrlGrPcSamplingMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 526 (_pRpc)->_hal.rpcCtrlGrPcSamplingMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 527 #define rpcCtrlMcServiceInterrupts_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 528 (_pRpc)->_hal.rpcCtrlMcServiceInterrupts(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 529 #define rpcCtrlDbgReadAllSmErrorStates_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 530 (_pRpc)->_hal.rpcCtrlDbgReadAllSmErrorStates(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 531 #define rpcCtrlSetZbcColorClear_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 532 (_pRpc)->_hal.rpcCtrlSetZbcColorClear(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 533 #define rpcGetEncoderCapacity_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 534 (_pRpc)->_hal.rpcGetEncoderCapacity(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 535 #define rpcCtrlGetP2pCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 536 (_pRpc)->_hal.rpcCtrlGetP2pCaps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 537 #define rpcPerfGetLevelInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) \ 538 (_pRpc)->_hal.rpcPerfGetLevelInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) 539 #define rpcAllocObject_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4) \ 540 (_pRpc)->_hal.rpcAllocObject(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4) 541 #define rpcCtrlGpuHandleVfPriFault_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 542 (_pRpc)->_hal.rpcCtrlGpuHandleVfPriFault(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 543 #define rpcRmApiControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ 544 (_pRpc)->_hal.rpcRmApiControl(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) 545 #define rpcCtrlFabricMemStats_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 546 (_pRpc)->_hal.rpcCtrlFabricMemStats(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 547 #define rpcCtrlGrCtxswZcullBind_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 548 (_pRpc)->_hal.rpcCtrlGrCtxswZcullBind(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 549 #define rpcCtrlInternalMemsysSetZbcReferenced_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 550 (_pRpc)->_hal.rpcCtrlInternalMemsysSetZbcReferenced(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 551 #define rpcCtrlPerfRatedTdpSetControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 552 (_pRpc)->_hal.rpcCtrlPerfRatedTdpSetControl(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 553 #define rpcCtrlExecPartitionsCreate_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 554 (_pRpc)->_hal.rpcCtrlExecPartitionsCreate(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 555 #define rpcCtrlGpfifoGetWorkSubmitToken_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 556 (_pRpc)->_hal.rpcCtrlGpfifoGetWorkSubmitToken(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 557 #define rpcIdleChannels_HAL(_pArg0, _pRpc, _pPhclients, _pPhdevices, _pPhchannels, _nentries, _flags, _timeout) \ 558 (_pRpc)->_hal.rpcIdleChannels(_pArg0, _pRpc, _pPhclients, _pPhdevices, _pPhchannels, _nentries, _flags, _timeout) 559 #define rpcCtrlCmdInternalGpuStartFabricProbe_HAL(_pGpu, _pRpc, _pArg0) \ 560 (_pRpc)->_hal.rpcCtrlCmdInternalGpuStartFabricProbe(_pGpu, _pRpc, _pArg0) 561 #define rpcGetBrandCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ 562 (_pRpc)->_hal.rpcGetBrandCaps(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) 563 #define rpcRestoreHibernationData_HAL(_pGpu, _pRpc) \ 564 (_pRpc)->_hal.rpcRestoreHibernationData(_pGpu, _pRpc) 565 #define rpcCtrlFlaSetupInstanceMemBlock_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 566 (_pRpc)->_hal.rpcCtrlFlaSetupInstanceMemBlock(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 567 #define rpcCtrlInternalSriovPromotePmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 568 (_pRpc)->_hal.rpcCtrlInternalSriovPromotePmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 569 #define rpcCtrlFbGetFsInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 570 (_pRpc)->_hal.rpcCtrlFbGetFsInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 571 #define rpcCtrlSetChannelInterleaveLevel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 572 (_pRpc)->_hal.rpcCtrlSetChannelInterleaveLevel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 573 #define rpcCtrlDbgResumeContext_HAL(_pGpu, _pRpc, _arg0, _arg1) \ 574 (_pRpc)->_hal.rpcCtrlDbgResumeContext(_pGpu, _pRpc, _arg0, _arg1) 575 #define rpcAllocRoot_HAL(_pGpu, _pRpc, _arg0) \ 576 (_pRpc)->_hal.rpcAllocRoot(_pGpu, _pRpc, _arg0) 577 #define rpcCtrlFifoDisableChannels_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 578 (_pRpc)->_hal.rpcCtrlFifoDisableChannels(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 579 #define rpcCtrlSetHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 580 (_pRpc)->_hal.rpcCtrlSetHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 581 #define rpcGetEngineUtilization_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ 582 (_pRpc)->_hal.rpcGetEngineUtilization(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) 583 #define rpcCtrlGetZbcClearTableEntry_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 584 (_pRpc)->_hal.rpcCtrlGetZbcClearTableEntry(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 585 #define rpcCtrlNvencSwSessionUpdateInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 586 (_pRpc)->_hal.rpcCtrlNvencSwSessionUpdateInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 587 #define rpcCtrlDbgSuspendContext_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 588 (_pRpc)->_hal.rpcCtrlDbgSuspendContext(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 589 #define rpcCtrlGetP2pCapsMatrix_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 590 (_pRpc)->_hal.rpcCtrlGetP2pCapsMatrix(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 591 #define rpcCtrlDbgExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 592 (_pRpc)->_hal.rpcCtrlDbgExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 593 #define rpcCtrlFreePmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 594 (_pRpc)->_hal.rpcCtrlFreePmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 595 #define rpcCtrlSetTsgInterleaveLevel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 596 (_pRpc)->_hal.rpcCtrlSetTsgInterleaveLevel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 597 #define rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 598 (_pRpc)->_hal.rpcCtrlMasterGetVirtualFunctionErrorContIntrMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 599 #define rpcLog_HAL(_pGpu, _pRpc, _pChar, _arg0) \ 600 (_pRpc)->_hal.rpcLog(_pGpu, _pRpc, _pChar, _arg0) 601 #define rpcCtrlExecPartitionsDelete_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 602 (_pRpc)->_hal.rpcCtrlExecPartitionsDelete(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 603 #define rpcCtrlPerfBoost_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 604 (_pRpc)->_hal.rpcCtrlPerfBoost(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 605 #define rpcCtrlDbgSetModeMmuDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 606 (_pRpc)->_hal.rpcCtrlDbgSetModeMmuDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 607 #define rpcCtrlFifoSetChannelProperties_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 608 (_pRpc)->_hal.rpcCtrlFifoSetChannelProperties(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 609 #define rpcCtrlSubdeviceGetP2pCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ 610 (_pRpc)->_hal.rpcCtrlSubdeviceGetP2pCaps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) 611 #define rpcUpdateBarPde_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \ 612 (_pRpc)->_hal.rpcUpdateBarPde(_pGpu, _pRpc, _arg0, _arg1, _arg2) 613 #define rpcCtrlBindPmResources_HAL(_pGpu, _pRpc, _arg0, _arg1) \ 614 (_pRpc)->_hal.rpcCtrlBindPmResources(_pGpu, _pRpc, _arg0, _arg1) 615 #define rpcMapMemoryDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _pArg7) \ 616 (_pRpc)->_hal.rpcMapMemoryDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _pArg7) 617 #define rpcUnmapMemoryDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) \ 618 (_pRpc)->_hal.rpcUnmapMemoryDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) 619 #define rpcSetGuestSystemInfoExt_HAL(_pGpu, _pRpc) \ 620 (_pRpc)->_hal.rpcSetGuestSystemInfoExt(_pGpu, _pRpc) 621 #define rpc_iGrp_ipVersions_getInfo_HAL(_pRpc, _pArg0) \ 622 (_pRpc)->_hal.rpc_iGrp_ipVersions_getInfo(_pArg0) 623 624 // 625 // hal function pointer defines requested by the :GEN_FNPTR_DEFINE flag 626 // 627 628 #define rpc_iGrp_ipVersions_getInfo_HAL_FNPTR(_pObj) (_pObj)->_hal.rpc_iGrp_ipVersions_getInfo 629 630 // Are there any optimized hal interfaces? 631 #define RPC_DIRECT_HAL_CALLS 0 632 633 // Are there any non-optimized hal interfaces? 634 #define RPC_INDIRECT_HAL_CALLS 1 635 636 637 // 638 // Inline stub function definitions. 639 // 640 641 642 643 // 644 // RPC PDB properties 645 // 646 647 648 649 #endif // _G_RPCHAL_H_ 650