1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 /* 24 * WARNING: This is an autogenerated file. DO NOT EDIT. 25 * This file is generated using below files: 26 * template file: kernel/inc/vgpu/gt_sdk-structures.h 27 * definition file: kernel/inc/vgpu/sdk-structures.def 28 */ 29 30 31 #ifdef SDK_STRUCTURES 32 // These are copy of sdk structures, that will be used for the communication between the vmioplugin & guest RM. 33 // #if condition can be removed when this file is included in OpenRM-Orin build. 34 #include "vgpu/sdk-structures.h" 35 typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00 36 { 37 NvU64 physAddress NV_ALIGN_BYTES(8); 38 NvU32 numEntries; 39 NvU32 flags; 40 NvHandle hVASpace; 41 NvU32 chId; 42 NvU32 subDeviceId; 43 } NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00; 44 45 typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 46 { 47 NvU64 physAddress NV_ALIGN_BYTES(8); 48 NvU32 numEntries; 49 NvU32 flags; 50 NvHandle hVASpace; 51 NvU32 chId; 52 NvU32 subDeviceId; 53 NvU32 pasid; 54 } NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05; 55 56 typedef NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v; 57 58 typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00 59 { 60 NvU64 physAddr NV_ALIGN_BYTES(8); 61 NvU32 numEntries; 62 NvU32 aperture; 63 } NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00; 64 65 typedef NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00 NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v; 66 67 typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00 68 { 69 NvU32 pdeIndex; 70 NvU32 flags; 71 NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00 ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE]; 72 NvHandle hVASpace; 73 NvP64 pPdeBuffer NV_ALIGN_BYTES(8); 74 NvU32 subDeviceId; 75 } NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00; 76 77 typedef NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00 NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v; 78 79 typedef struct NVOS00_PARAMETERS_v03_00 80 { 81 NvHandle hRoot; 82 NvHandle hObjectParent; 83 NvHandle hObjectOld; 84 NvV32 status; 85 } NVOS00_PARAMETERS_v03_00; 86 87 typedef NVOS00_PARAMETERS_v03_00 NVOS00_PARAMETERS_v; 88 89 typedef struct NVOS46_PARAMETERS_v03_00 90 { 91 NvHandle hClient; 92 NvHandle hDevice; 93 NvHandle hDma; 94 NvHandle hMemory; 95 NvU64 offset NV_ALIGN_BYTES(8); 96 NvU64 length NV_ALIGN_BYTES(8); 97 NvV32 flags; 98 NvU64 dmaOffset NV_ALIGN_BYTES(8); 99 NvV32 status; 100 } NVOS46_PARAMETERS_v03_00; 101 102 typedef NVOS46_PARAMETERS_v03_00 NVOS46_PARAMETERS_v; 103 104 typedef struct NVOS47_PARAMETERS_v03_00 105 { 106 NvHandle hClient; 107 NvHandle hDevice; 108 NvHandle hDma; 109 NvHandle hMemory; 110 NvV32 flags; 111 NvU64 dmaOffset NV_ALIGN_BYTES(8); 112 NvV32 status; 113 } NVOS47_PARAMETERS_v03_00; 114 115 typedef NVOS47_PARAMETERS_v03_00 NVOS47_PARAMETERS_v; 116 117 typedef struct NVOS55_PARAMETERS_v03_00 118 { 119 NvHandle hClient; 120 NvHandle hParent; 121 NvHandle hObject; 122 NvHandle hClientSrc; 123 NvHandle hObjectSrc; 124 NvU32 flags; 125 NvU32 status; 126 } NVOS55_PARAMETERS_v03_00; 127 128 typedef NVOS55_PARAMETERS_v03_00 NVOS55_PARAMETERS_v; 129 130 typedef struct NV2080_CTRL_GR_ROUTE_INFO_v12_01 131 { 132 NvU32 flags; 133 NvU64 route NV_ALIGN_BYTES(8); 134 } NV2080_CTRL_GR_ROUTE_INFO_v12_01; 135 136 typedef NV2080_CTRL_GR_ROUTE_INFO_v12_01 NV2080_CTRL_GR_ROUTE_INFO_v; 137 138 typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00 139 { 140 NvHandle hClientTarget; 141 NvHandle hChannelTarget; 142 NvU32 reserved00[3]; 143 NvU32 regOpCount; 144 NvP64 regOps NV_ALIGN_BYTES(8); 145 } NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00; 146 147 typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 148 { 149 NvHandle hClientTarget; 150 NvHandle hChannelTarget; 151 NvU32 reserved00[3]; 152 NvU32 regOpCount; 153 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; 154 NvP64 regOps NV_ALIGN_BYTES(8); 155 } NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01; 156 157 typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v; 158 159 typedef struct NV2080_CTRL_GPU_REG_OP_v03_00 160 { 161 NvU8 regOp; 162 NvU8 regType; 163 NvU8 regStatus; 164 NvU8 regQuad; 165 NvU32 regGroupMask; 166 NvU32 regSubGroupMask; 167 NvU32 regOffset; 168 NvU32 regValueHi; 169 NvU32 regValueLo; 170 NvU32 regAndNMaskHi; 171 NvU32 regAndNMaskLo; 172 } NV2080_CTRL_GPU_REG_OP_v03_00; 173 174 typedef NV2080_CTRL_GPU_REG_OP_v03_00 NV2080_CTRL_GPU_REG_OP_v; 175 176 typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 177 { 178 NvU32 util; 179 NvU32 procId; 180 } NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01; 181 182 typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 183 { 184 NvU32 util; 185 NvU32 procId; 186 NvU32 subProcessID; 187 } NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00; 188 189 typedef NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v; 190 191 typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v06_01 192 { 193 NvU64 timeStamp NV_ALIGN_BYTES(8); 194 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 fb; 195 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 gr; 196 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 nvenc; 197 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 nvdec; 198 } NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v06_01; 199 200 typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00 201 { 202 NvU64 timeStamp NV_ALIGN_BYTES(8); 203 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 fb; 204 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 gr; 205 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvenc; 206 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvdec; 207 } NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00; 208 209 typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E 210 { 211 NvU64 timeStamp NV_ALIGN_BYTES(8); 212 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 fb; 213 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 gr; 214 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvenc; 215 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvdec; 216 } NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E; 217 218 typedef NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v; 219 220 typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00 221 { 222 NvU8 type; 223 NvU32 bufSize; 224 NvU32 count; 225 NvU32 tracker; 226 NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00 samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL]; 227 } NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00; 228 229 typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E 230 { 231 NvU8 type; 232 NvU32 bufSize; 233 NvU32 count; 234 NvU32 tracker; 235 NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E]; 236 } NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E; 237 238 typedef NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v; 239 240 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 241 { 242 NvU32 flags; 243 NvBool bBridgeless; 244 NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM]; 245 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00; 246 247 typedef NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v; 248 249 typedef struct UpdateBarPde_v15_00 250 { 251 NV_RPC_UPDATE_PDE_BAR_TYPE barType; 252 NvU64 entryValue NV_ALIGN_BYTES(8); 253 NvU64 entryLevelShift NV_ALIGN_BYTES(8); 254 } UpdateBarPde_v15_00; 255 256 typedef UpdateBarPde_v15_00 UpdateBarPde_v; 257 258 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 259 { 260 NvU32 dataSize; 261 NvU8 data[256]; 262 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00; 263 264 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v; 265 266 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 267 { 268 NvU32 dataSize; 269 NvU8 data[512]; 270 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00; 271 272 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v; 273 274 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 275 { 276 NvU32 dataSize; 277 NvU8 data[1024]; 278 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00; 279 280 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v; 281 282 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 283 { 284 NvU32 dataSize; 285 NvU8 data[2048]; 286 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00; 287 288 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v; 289 290 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 291 { 292 NvU32 dataSize; 293 NvU8 data[4096]; 294 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00; 295 296 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v; 297 298 typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 299 { 300 NvU32 linkId; 301 NvBool bIsGpuDegraded; 302 } NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00; 303 304 typedef NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v; 305 306 typedef struct gpu_exec_reg_ops_v03_00 307 { 308 NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00 reg_op_params; 309 NV2080_CTRL_GPU_REG_OP_v03_00 operations[]; 310 } gpu_exec_reg_ops_v03_00; 311 312 typedef struct gpu_exec_reg_ops_v12_01 313 { 314 NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 reg_op_params; 315 NV2080_CTRL_GPU_REG_OP_v03_00 operations[]; 316 } gpu_exec_reg_ops_v12_01; 317 318 typedef gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v; 319 320 typedef struct idle_channel_list_v03_00 321 { 322 NvU32 phClient; 323 NvU32 phDevice; 324 NvU32 phChannel; 325 } idle_channel_list_v03_00; 326 327 typedef idle_channel_list_v03_00 idle_channel_list_v; 328 329 typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00 330 { 331 NvHandle hVASpace; 332 NvU32 subDeviceId; 333 } NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00; 334 335 typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 336 { 337 NvHandle hVASpace; 338 NvU32 subDeviceId; 339 } NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05; 340 341 typedef NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v; 342 343 typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F 344 { 345 NvU32 regOpCount; 346 NVB0CC_REGOPS_MODE mode; 347 NvBool bPassed; 348 NvBool bDirect; 349 NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NVB0CC_REGOPS_MAX_COUNT]; 350 } NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F; 351 352 typedef NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v; 353 354 typedef struct ATOMIC_OP_v1F_08 355 { 356 NvBool bSupported; 357 NvU32 attributes; 358 } ATOMIC_OP_v1F_08; 359 360 typedef ATOMIC_OP_v1F_08 ATOMIC_OP_v; 361 362 typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 363 { 364 NvU32 gpuId; 365 NvU8 gpuUuid[VM_UUID_SIZE_v21_02]; 366 NvU32 p2pCaps; 367 NvU32 p2pOptimalReadCEs; 368 NvU32 p2pOptimalWriteCEs; 369 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D]; 370 NvU32 busPeerId; 371 } NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02; 372 373 typedef NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v; 374 375 typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 376 { 377 NvBool bAllCaps; 378 NvBool bUseUuid; 379 NvU32 peerGpuCount; 380 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02]; 381 } NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02; 382 383 typedef NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v; 384 385 typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 386 { 387 NvU32 connectionType; 388 NvU32 peerId; 389 NvU32 bSpaAccessOnly; 390 NvBool bUseUuid; 391 NvU32 remoteGpuId; 392 NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02]; 393 } NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03; 394 395 typedef NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v; 396 397 typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 398 { 399 NvU32 connectionType; 400 NvU32 peerId; 401 NvBool bUseUuid; 402 NvU32 remoteGpuId; 403 NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02]; 404 } NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03; 405 406 typedef NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v; 407 408 typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 409 { 410 NvU8 chipletType; 411 NvU8 chipletIndex; 412 NvU16 numCredits; 413 } NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08; 414 415 typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v; 416 417 typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 418 { 419 NvU8 status; 420 NvU8 entryIndex; 421 } NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08; 422 423 typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v; 424 425 typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 426 { 427 NvU32 numCredits; 428 } NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08; 429 430 typedef NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v; 431 432 typedef struct NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 433 { 434 NvU8 pmaChannelIdx; 435 NvU8 numEntries; 436 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 statusInfo; 437 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08]; 438 } NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08; 439 440 typedef NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v; 441 442 typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 443 { 444 NvU8 pmaChannelIdx; 445 NvU8 numEntries; 446 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 statusInfo; 447 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08]; 448 } NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08; 449 450 typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v; 451 452 typedef struct NV2080_CTRL_CE_CAPS_v21_0A 453 { 454 NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A]; 455 } NV2080_CTRL_CE_CAPS_v21_0A; 456 457 typedef NV2080_CTRL_CE_CAPS_v21_0A NV2080_CTRL_CE_CAPS_v; 458 459 typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A 460 { 461 NV2080_CTRL_CE_CAPS_v21_0A ceCaps[NV2080_CTRL_MAX_PCES_v21_0A]; 462 NvU32 present; 463 } NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A; 464 465 typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v; 466 467 typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 468 { 469 NvBool bIsLinkUp; 470 NvU32 nrLinks; 471 NvU32 linkMask; 472 NvU32 perLinkBwMBps; 473 NvU32 remoteType; 474 } NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01; 475 476 typedef NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v; 477 478 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 479 { 480 NvU32 sensorId; 481 NvU32 limit; 482 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04; 483 484 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v; 485 486 typedef union NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 487 { 488 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 smbpbi; 489 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04; 490 491 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v; 492 493 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 494 { 495 NvU8 type ; 496 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 data; 497 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04; 498 499 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v; 500 501 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 502 { 503 NvU8 flags; 504 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 syncData; 505 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04; 506 507 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v; 508 509 510 #endif 511 512 #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS 513 // Union member index functions for NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type 514 uint32_t _get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(NvU32 cmd) 515 { 516 switch (cmd) 517 { 518 case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI: 519 return 0; // "smbpbi" 520 521 default: 522 return UNION_UNKNOWN_FIELD_PRINT; 523 } 524 } 525 526 527 528 529 530 #endif 531 532 #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD 533 static NV_STATUS get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04_data(void *msg, NvS32 bytes_remaining, uint32_t* index) 534 { 535 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 *param = msg; 536 537 if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04, type) + sizeof(param->type)) > bytes_remaining) 538 return NV_ERR_BUFFER_TOO_SMALL; 539 *index = _get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(param->type); 540 return NV_OK; 541 } 542 543 #endif 544 545 #ifdef SDK_ARRAY_LENGTH_FUNCTIONS 546 547 // Array length functions for gpu_exec_reg_ops: 548 static NV_STATUS get_array_length_gpu_exec_reg_ops_v03_00_operations(void *msg, NvS32 bytes_remaining, uint32_t* length) 549 { 550 gpu_exec_reg_ops_v03_00 *param = msg; 551 552 if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v03_00, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining) 553 return NV_ERR_BUFFER_TOO_SMALL; 554 *length = param->reg_op_params.regOpCount; 555 return NV_OK; 556 } 557 static NV_STATUS get_array_length_gpu_exec_reg_ops_v12_01_operations(void *msg, NvS32 bytes_remaining, uint32_t* length) 558 { 559 gpu_exec_reg_ops_v12_01 *param = msg; 560 561 if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v12_01, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining) 562 return NV_ERR_BUFFER_TOO_SMALL; 563 *length = param->reg_op_params.regOpCount; 564 return NV_OK; 565 } 566 567 #endif 568 569