1 #ifndef _G_UVM_NVOC_H_ 2 #define _G_UVM_NVOC_H_ 3 #include "nvoc/runtime.h" 4 5 #ifdef __cplusplus 6 extern "C" { 7 #endif 8 9 /* 10 * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 11 * SPDX-License-Identifier: MIT 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 28 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 29 * DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include "g_uvm_nvoc.h" 33 34 #ifndef UVM_H 35 #define UVM_H 36 37 /*! 38 * @file 39 * @brief Provides definitions for all OBJUVM data structures and interfaces. 40 */ 41 42 #include "core/core.h" 43 #include "rmapi/control.h" 44 #include "rmapi/rmapi_utils.h" 45 #include "gpu/mem_mgr/mem_desc.h" 46 #include "gpu/gpu.h" 47 #include "nvoc/utility.h" 48 #include "kernel/gpu/intr/intr_service.h" 49 50 #include "gpu/eng_state.h" 51 52 typedef enum 53 { 54 MIMC, 55 MOMC 56 } ACCESS_CNTR_TYPE; 57 58 /*! 59 * Defines the structure used to contain all generic information related to 60 * the OBJUVM. 61 * Contains the Unified Virtual Memory (UVM) feature related data. 62 */ 63 64 struct AccessCounterBuffer; 65 66 #ifndef __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ 67 #define __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ 68 typedef struct AccessCounterBuffer AccessCounterBuffer; 69 #endif /* __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ */ 70 71 #ifndef __nvoc_class_id_AccessCounterBuffer 72 #define __nvoc_class_id_AccessCounterBuffer 0x1f0074 73 #endif /* __nvoc_class_id_AccessCounterBuffer */ 74 75 76 77 /* 78 * This structure is used to store all the necessary information concerning the access counter buffer. 79 * It is contained within the UVM object. 80 */ 81 typedef struct 82 { 83 // kernel fields 84 struct AccessCounterBuffer *pAccessCounterBuffer; // AccessCounterBuffer object 85 86 // physical fields 87 NvU64 bar2UvmAccessCntrBufferAddr; //This is the bar2 VA that is used by the gpu in 88 // order to access the buffer 89 MEMORY_DESCRIPTOR *pUvmAccessCntrMemDesc; // Memory descriptor of the reconstructed access counter buffer 90 } ACCESS_CNTR_BUFFER; 91 92 typedef enum 93 { 94 intr_notify, 95 intr_error, 96 intr_all 97 } ACCESS_CNTR_INTR_TYPE; 98 99 typedef struct OBJUVM *POBJUVM; 100 101 #ifdef NVOC_UVM_H_PRIVATE_ACCESS_ALLOWED 102 #define PRIVATE_FIELD(x) x 103 #else 104 #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) 105 #endif 106 struct OBJUVM { 107 const struct NVOC_RTTI *__nvoc_rtti; 108 struct OBJENGSTATE __nvoc_base_OBJENGSTATE; 109 struct IntrService __nvoc_base_IntrService; 110 struct Object *__nvoc_pbase_Object; 111 struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; 112 struct IntrService *__nvoc_pbase_IntrService; 113 struct OBJUVM *__nvoc_pbase_OBJUVM; 114 void (*__uvmStateDestroy__)(OBJGPU *, struct OBJUVM *); 115 NV_STATUS (*__uvmStateInitUnlocked__)(OBJGPU *, struct OBJUVM *); 116 void (*__uvmRegisterIntrService__)(OBJGPU *, struct OBJUVM *, IntrServiceRecord *); 117 NvU32 (*__uvmServiceInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceInterruptArguments *); 118 NV_STATUS (*__uvmStateLoad__)(POBJGPU, struct OBJUVM *, NvU32); 119 NV_STATUS (*__uvmStateUnload__)(POBJGPU, struct OBJUVM *, NvU32); 120 NV_STATUS (*__uvmServiceNotificationInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceNotificationInterruptArguments *); 121 NV_STATUS (*__uvmStateInitLocked__)(POBJGPU, struct OBJUVM *); 122 NV_STATUS (*__uvmStatePreLoad__)(POBJGPU, struct OBJUVM *, NvU32); 123 NV_STATUS (*__uvmStatePostUnload__)(POBJGPU, struct OBJUVM *, NvU32); 124 NV_STATUS (*__uvmStatePreUnload__)(POBJGPU, struct OBJUVM *, NvU32); 125 void (*__uvmInitMissing__)(POBJGPU, struct OBJUVM *); 126 NV_STATUS (*__uvmStatePreInitLocked__)(POBJGPU, struct OBJUVM *); 127 NV_STATUS (*__uvmStatePreInitUnlocked__)(POBJGPU, struct OBJUVM *); 128 NvBool (*__uvmClearInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceClearInterruptArguments *); 129 NV_STATUS (*__uvmStatePostLoad__)(POBJGPU, struct OBJUVM *, NvU32); 130 NV_STATUS (*__uvmConstructEngine__)(POBJGPU, struct OBJUVM *, ENGDESCRIPTOR); 131 NvBool (*__uvmIsPresent__)(POBJGPU, struct OBJUVM *); 132 ACCESS_CNTR_BUFFER *pAccessCounterBuffers; 133 NvU32 accessCounterBufferCount; 134 NvHandle hClient; 135 NvHandle hSubdevice; 136 RM_API *pRmApi; 137 }; 138 139 #ifndef __NVOC_CLASS_OBJUVM_TYPEDEF__ 140 #define __NVOC_CLASS_OBJUVM_TYPEDEF__ 141 typedef struct OBJUVM OBJUVM; 142 #endif /* __NVOC_CLASS_OBJUVM_TYPEDEF__ */ 143 144 #ifndef __nvoc_class_id_OBJUVM 145 #define __nvoc_class_id_OBJUVM 0xf9a17d 146 #endif /* __nvoc_class_id_OBJUVM */ 147 148 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJUVM; 149 150 #define __staticCast_OBJUVM(pThis) \ 151 ((pThis)->__nvoc_pbase_OBJUVM) 152 153 #ifdef __nvoc_uvm_h_disabled 154 #define __dynamicCast_OBJUVM(pThis) ((OBJUVM*)NULL) 155 #else //__nvoc_uvm_h_disabled 156 #define __dynamicCast_OBJUVM(pThis) \ 157 ((OBJUVM*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJUVM))) 158 #endif //__nvoc_uvm_h_disabled 159 160 #define PDB_PROP_UVM_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. 161 #define PDB_PROP_UVM_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING 162 163 NV_STATUS __nvoc_objCreateDynamic_OBJUVM(OBJUVM**, Dynamic*, NvU32, va_list); 164 165 NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM**, Dynamic*, NvU32); 166 #define __objCreate_OBJUVM(ppNewObj, pParent, createFlags) \ 167 __nvoc_objCreate_OBJUVM((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) 168 169 #define uvmStateDestroy(pGpu, pUvm) uvmStateDestroy_DISPATCH(pGpu, pUvm) 170 #define uvmStateInitUnlocked(pGpu, pUvm) uvmStateInitUnlocked_DISPATCH(pGpu, pUvm) 171 #define uvmRegisterIntrService(arg0, pUvm, arg1) uvmRegisterIntrService_DISPATCH(arg0, pUvm, arg1) 172 #define uvmServiceInterrupt(arg0, pUvm, arg1) uvmServiceInterrupt_DISPATCH(arg0, pUvm, arg1) 173 #define uvmStateLoad(pGpu, pEngstate, arg0) uvmStateLoad_DISPATCH(pGpu, pEngstate, arg0) 174 #define uvmStateUnload(pGpu, pEngstate, arg0) uvmStateUnload_DISPATCH(pGpu, pEngstate, arg0) 175 #define uvmServiceNotificationInterrupt(pGpu, pIntrService, pParams) uvmServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) 176 #define uvmStateInitLocked(pGpu, pEngstate) uvmStateInitLocked_DISPATCH(pGpu, pEngstate) 177 #define uvmStatePreLoad(pGpu, pEngstate, arg0) uvmStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) 178 #define uvmStatePostUnload(pGpu, pEngstate, arg0) uvmStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) 179 #define uvmStatePreUnload(pGpu, pEngstate, arg0) uvmStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) 180 #define uvmInitMissing(pGpu, pEngstate) uvmInitMissing_DISPATCH(pGpu, pEngstate) 181 #define uvmStatePreInitLocked(pGpu, pEngstate) uvmStatePreInitLocked_DISPATCH(pGpu, pEngstate) 182 #define uvmStatePreInitUnlocked(pGpu, pEngstate) uvmStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) 183 #define uvmClearInterrupt(pGpu, pIntrService, pParams) uvmClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) 184 #define uvmStatePostLoad(pGpu, pEngstate, arg0) uvmStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) 185 #define uvmConstructEngine(pGpu, pEngstate, arg0) uvmConstructEngine_DISPATCH(pGpu, pEngstate, arg0) 186 #define uvmIsPresent(pGpu, pEngstate) uvmIsPresent_DISPATCH(pGpu, pEngstate) 187 NV_STATUS uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); 188 189 190 #ifdef __nvoc_uvm_h_disabled 191 static inline NV_STATUS uvmInitializeAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { 192 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 193 return NV_ERR_NOT_SUPPORTED; 194 } 195 #else //__nvoc_uvm_h_disabled 196 #define uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmInitializeAccessCntrBuffer_IMPL(pGpu, pUvm, pAccessCounterBuffer) 197 #endif //__nvoc_uvm_h_disabled 198 199 #define uvmInitializeAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) 200 201 NV_STATUS uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); 202 203 204 #ifdef __nvoc_uvm_h_disabled 205 static inline NV_STATUS uvmTerminateAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { 206 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 207 return NV_ERR_NOT_SUPPORTED; 208 } 209 #else //__nvoc_uvm_h_disabled 210 #define uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmTerminateAccessCntrBuffer_IMPL(pGpu, pUvm, pAccessCounterBuffer) 211 #endif //__nvoc_uvm_h_disabled 212 213 #define uvmTerminateAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) 214 215 NV_STATUS uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); 216 217 218 #ifdef __nvoc_uvm_h_disabled 219 static inline NV_STATUS uvmInitAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { 220 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 221 return NV_ERR_NOT_SUPPORTED; 222 } 223 #else //__nvoc_uvm_h_disabled 224 #define uvmInitAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmInitAccessCntrBuffer_GV100(pGpu, pUvm, pAccessCounterBuffer) 225 #endif //__nvoc_uvm_h_disabled 226 227 #define uvmInitAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmInitAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) 228 229 NV_STATUS uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer); 230 231 232 #ifdef __nvoc_uvm_h_disabled 233 static inline NV_STATUS uvmDestroyAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) { 234 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 235 return NV_ERR_NOT_SUPPORTED; 236 } 237 #else //__nvoc_uvm_h_disabled 238 #define uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer_GV100(pGpu, pUvm, pAccessCounterBuffer) 239 #endif //__nvoc_uvm_h_disabled 240 241 #define uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) 242 243 static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { 244 return NV_OK; 245 } 246 247 248 #ifdef __nvoc_uvm_h_disabled 249 static inline NV_STATUS uvmAccessCntrBufferUnregister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { 250 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 251 return NV_ERR_NOT_SUPPORTED; 252 } 253 #else //__nvoc_uvm_h_disabled 254 #define uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister_ac1694(arg0, arg1, accessCounterIndex) 255 #endif //__nvoc_uvm_h_disabled 256 257 #define uvmAccessCntrBufferUnregister_HAL(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) 258 259 static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { 260 return NV_OK; 261 } 262 263 264 #ifdef __nvoc_uvm_h_disabled 265 static inline NV_STATUS uvmAccessCntrBufferRegister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { 266 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 267 return NV_ERR_NOT_SUPPORTED; 268 } 269 #else //__nvoc_uvm_h_disabled 270 #define uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister_ac1694(arg0, arg1, accessCounterIndex, arg2, arg3) 271 #endif //__nvoc_uvm_h_disabled 272 273 #define uvmAccessCntrBufferRegister_HAL(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) 274 275 NV_STATUS uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); 276 277 278 #ifdef __nvoc_uvm_h_disabled 279 static inline NV_STATUS uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 280 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 281 return NV_ERR_NOT_SUPPORTED; 282 } 283 #else //__nvoc_uvm_h_disabled 284 #define uvmUnloadAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) uvmUnloadAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex) 285 #endif //__nvoc_uvm_h_disabled 286 287 #define uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex) uvmUnloadAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) 288 289 NV_STATUS uvmSetupAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); 290 291 292 #ifdef __nvoc_uvm_h_disabled 293 static inline NV_STATUS uvmSetupAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 294 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 295 return NV_ERR_NOT_SUPPORTED; 296 } 297 #else //__nvoc_uvm_h_disabled 298 #define uvmSetupAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) uvmSetupAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex) 299 #endif //__nvoc_uvm_h_disabled 300 301 #define uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex) uvmSetupAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) 302 303 NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0); 304 305 306 #ifdef __nvoc_uvm_h_disabled 307 static inline NV_STATUS uvmReadAccessCntrBufferPutPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0) { 308 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 309 return NV_ERR_NOT_SUPPORTED; 310 } 311 #else //__nvoc_uvm_h_disabled 312 #define uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferPutPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) 313 #endif //__nvoc_uvm_h_disabled 314 315 #define uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, accessCounterIndex, arg0) 316 317 NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0); 318 319 320 #ifdef __nvoc_uvm_h_disabled 321 static inline NV_STATUS uvmReadAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0) { 322 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 323 return NV_ERR_NOT_SUPPORTED; 324 } 325 #else //__nvoc_uvm_h_disabled 326 #define uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferGetPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) 327 #endif //__nvoc_uvm_h_disabled 328 329 #define uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) 330 331 NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool *arg0); 332 333 334 #ifdef __nvoc_uvm_h_disabled 335 static inline NV_STATUS uvmReadAccessCntrBufferFullPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool *arg0) { 336 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 337 return NV_ERR_NOT_SUPPORTED; 338 } 339 #else //__nvoc_uvm_h_disabled 340 #define uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferFullPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) 341 #endif //__nvoc_uvm_h_disabled 342 343 #define uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, accessCounterIndex, arg0) 344 345 NV_STATUS uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); 346 347 348 #ifdef __nvoc_uvm_h_disabled 349 static inline NV_STATUS uvmResetAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { 350 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 351 return NV_ERR_NOT_SUPPORTED; 352 } 353 #else //__nvoc_uvm_h_disabled 354 #define uvmResetAccessCntrBuffer(pGpu, pUvm, accessCounterIndex, arg0) uvmResetAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex, arg0) 355 #endif //__nvoc_uvm_h_disabled 356 357 #define uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmResetAccessCntrBuffer(pGpu, pUvm, accessCounterIndex, arg0) 358 359 NV_STATUS uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, ACCESS_CNTR_TYPE arg0, NvU32 arg1); 360 361 362 #ifdef __nvoc_uvm_h_disabled 363 static inline NV_STATUS uvmAccessCntrSetGranularity(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, ACCESS_CNTR_TYPE arg0, NvU32 arg1) { 364 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 365 return NV_ERR_NOT_SUPPORTED; 366 } 367 #else //__nvoc_uvm_h_disabled 368 #define uvmAccessCntrSetGranularity(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetGranularity_TU102(pGpu, pUvm, accessCounterIndex, arg0, arg1) 369 #endif //__nvoc_uvm_h_disabled 370 371 #define uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetGranularity(pGpu, pUvm, accessCounterIndex, arg0, arg1) 372 373 NV_STATUS uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); 374 375 376 #ifdef __nvoc_uvm_h_disabled 377 static inline NV_STATUS uvmAccessCntrSetThreshold(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { 378 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 379 return NV_ERR_NOT_SUPPORTED; 380 } 381 #else //__nvoc_uvm_h_disabled 382 #define uvmAccessCntrSetThreshold(pGpu, pUvm, accessCounterIndex, arg0) uvmAccessCntrSetThreshold_TU102(pGpu, pUvm, accessCounterIndex, arg0) 383 #endif //__nvoc_uvm_h_disabled 384 385 #define uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmAccessCntrSetThreshold(pGpu, pUvm, accessCounterIndex, arg0) 386 387 NV_STATUS uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0, NvU32 arg1); 388 389 390 #ifdef __nvoc_uvm_h_disabled 391 static inline NV_STATUS uvmAccessCntrSetCounterLimit(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0, NvU32 arg1) { 392 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 393 return NV_ERR_NOT_SUPPORTED; 394 } 395 #else //__nvoc_uvm_h_disabled 396 #define uvmAccessCntrSetCounterLimit(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetCounterLimit_GV100(pGpu, pUvm, accessCounterIndex, arg0, arg1) 397 #endif //__nvoc_uvm_h_disabled 398 399 #define uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetCounterLimit(pGpu, pUvm, accessCounterIndex, arg0, arg1) 400 401 NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0); 402 403 404 #ifdef __nvoc_uvm_h_disabled 405 static inline NV_STATUS uvmWriteAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) { 406 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 407 return NV_ERR_NOT_SUPPORTED; 408 } 409 #else //__nvoc_uvm_h_disabled 410 #define uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmWriteAccessCntrBufferGetPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0) 411 #endif //__nvoc_uvm_h_disabled 412 413 #define uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) 414 415 NV_STATUS uvmEnableAccessCntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0); 416 417 418 #ifdef __nvoc_uvm_h_disabled 419 static inline NV_STATUS uvmEnableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0) { 420 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 421 return NV_ERR_NOT_SUPPORTED; 422 } 423 #else //__nvoc_uvm_h_disabled 424 #define uvmEnableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) uvmEnableAccessCntr_TU102(pGpu, pUvm, accessCounterIndex, arg0) 425 #endif //__nvoc_uvm_h_disabled 426 427 #define uvmEnableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmEnableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) 428 429 NV_STATUS uvmDisableAccessCntr_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0); 430 431 432 #ifdef __nvoc_uvm_h_disabled 433 static inline NV_STATUS uvmDisableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0) { 434 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 435 return NV_ERR_NOT_SUPPORTED; 436 } 437 #else //__nvoc_uvm_h_disabled 438 #define uvmDisableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) uvmDisableAccessCntr_GV100(pGpu, pUvm, accessCounterIndex, arg0) 439 #endif //__nvoc_uvm_h_disabled 440 441 #define uvmDisableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmDisableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) 442 443 NV_STATUS uvmEnableAccessCntrIntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); 444 445 446 #ifdef __nvoc_uvm_h_disabled 447 static inline NV_STATUS uvmEnableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { 448 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 449 return NV_ERR_NOT_SUPPORTED; 450 } 451 #else //__nvoc_uvm_h_disabled 452 #define uvmEnableAccessCntrIntr(pGpu, pUvm, arg0) uvmEnableAccessCntrIntr_TU102(pGpu, pUvm, arg0) 453 #endif //__nvoc_uvm_h_disabled 454 455 #define uvmEnableAccessCntrIntr_HAL(pGpu, pUvm, arg0) uvmEnableAccessCntrIntr(pGpu, pUvm, arg0) 456 457 NV_STATUS uvmDisableAccessCntrIntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); 458 459 460 #ifdef __nvoc_uvm_h_disabled 461 static inline NV_STATUS uvmDisableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pUvm) { 462 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 463 return NV_ERR_NOT_SUPPORTED; 464 } 465 #else //__nvoc_uvm_h_disabled 466 #define uvmDisableAccessCntrIntr(pGpu, pUvm) uvmDisableAccessCntrIntr_TU102(pGpu, pUvm) 467 #endif //__nvoc_uvm_h_disabled 468 469 #define uvmDisableAccessCntrIntr_HAL(pGpu, pUvm) uvmDisableAccessCntrIntr(pGpu, pUvm) 470 471 NV_STATUS uvmGetAccessCntrRegisterMappings_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6); 472 473 474 #ifdef __nvoc_uvm_h_disabled 475 static inline NV_STATUS uvmGetAccessCntrRegisterMappings(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6) { 476 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 477 return NV_ERR_NOT_SUPPORTED; 478 } 479 #else //__nvoc_uvm_h_disabled 480 #define uvmGetAccessCntrRegisterMappings(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings_TU102(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) 481 #endif //__nvoc_uvm_h_disabled 482 483 #define uvmGetAccessCntrRegisterMappings_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) 484 485 NV_STATUS uvmAccessCntrService_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); 486 487 488 #ifdef __nvoc_uvm_h_disabled 489 static inline NV_STATUS uvmAccessCntrService(OBJGPU *pGpu, struct OBJUVM *pUvm) { 490 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 491 return NV_ERR_NOT_SUPPORTED; 492 } 493 #else //__nvoc_uvm_h_disabled 494 #define uvmAccessCntrService(pGpu, pUvm) uvmAccessCntrService_TU102(pGpu, pUvm) 495 #endif //__nvoc_uvm_h_disabled 496 497 #define uvmAccessCntrService_HAL(pGpu, pUvm) uvmAccessCntrService(pGpu, pUvm) 498 499 NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); 500 501 502 #ifdef __nvoc_uvm_h_disabled 503 static inline NvU32 uvmGetAccessCounterBufferSize(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 504 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 505 return 0; 506 } 507 #else //__nvoc_uvm_h_disabled 508 #define uvmGetAccessCounterBufferSize(pGpu, pUvm, accessCounterIndex) uvmGetAccessCounterBufferSize_TU102(pGpu, pUvm, accessCounterIndex) 509 #endif //__nvoc_uvm_h_disabled 510 511 #define uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm, accessCounterIndex) uvmGetAccessCounterBufferSize(pGpu, pUvm, accessCounterIndex) 512 513 void uvmProgramWriteAccessCntrBufferAddress_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU64 addr); 514 515 516 #ifdef __nvoc_uvm_h_disabled 517 static inline void uvmProgramWriteAccessCntrBufferAddress(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU64 addr) { 518 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 519 } 520 #else //__nvoc_uvm_h_disabled 521 #define uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, accessCounterIndex, addr) uvmProgramWriteAccessCntrBufferAddress_TU102(pGpu, pUvm, accessCounterIndex, addr) 522 #endif //__nvoc_uvm_h_disabled 523 524 #define uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, accessCounterIndex, addr) uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, accessCounterIndex, addr) 525 526 void uvmProgramAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool bEn); 527 528 529 #ifdef __nvoc_uvm_h_disabled 530 static inline void uvmProgramAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool bEn) { 531 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 532 } 533 #else //__nvoc_uvm_h_disabled 534 #define uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex, bEn) uvmProgramAccessCntrBufferEnabled_TU102(pGpu, pUvm, accessCounterIndex, bEn) 535 #endif //__nvoc_uvm_h_disabled 536 537 #define uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, bEn) uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex, bEn) 538 539 NvBool uvmIsAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); 540 541 542 #ifdef __nvoc_uvm_h_disabled 543 static inline NvBool uvmIsAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 544 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 545 return NV_FALSE; 546 } 547 #else //__nvoc_uvm_h_disabled 548 #define uvmIsAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferEnabled_TU102(pGpu, pUvm, accessCounterIndex) 549 #endif //__nvoc_uvm_h_disabled 550 551 #define uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex) 552 553 NvBool uvmIsAccessCntrBufferPushed_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); 554 555 556 #ifdef __nvoc_uvm_h_disabled 557 static inline NvBool uvmIsAccessCntrBufferPushed(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 558 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 559 return NV_FALSE; 560 } 561 #else //__nvoc_uvm_h_disabled 562 #define uvmIsAccessCntrBufferPushed(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferPushed_TU102(pGpu, pUvm, accessCounterIndex) 563 #endif //__nvoc_uvm_h_disabled 564 565 #define uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferPushed(pGpu, pUvm, accessCounterIndex) 566 567 NvU32 uvmGetRegOffsetAccessCntrBufferPut_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); 568 569 570 #ifdef __nvoc_uvm_h_disabled 571 static inline NvU32 uvmGetRegOffsetAccessCntrBufferPut(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 572 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 573 return 0; 574 } 575 #else //__nvoc_uvm_h_disabled 576 #define uvmGetRegOffsetAccessCntrBufferPut(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferPut_TU102(pUvm, accessCounterIndex) 577 #endif //__nvoc_uvm_h_disabled 578 579 #define uvmGetRegOffsetAccessCntrBufferPut_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferPut(pUvm, accessCounterIndex) 580 581 NvU32 uvmGetRegOffsetAccessCntrBufferGet_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); 582 583 584 #ifdef __nvoc_uvm_h_disabled 585 static inline NvU32 uvmGetRegOffsetAccessCntrBufferGet(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 586 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 587 return 0; 588 } 589 #else //__nvoc_uvm_h_disabled 590 #define uvmGetRegOffsetAccessCntrBufferGet(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferGet_TU102(pUvm, accessCounterIndex) 591 #endif //__nvoc_uvm_h_disabled 592 593 #define uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferGet(pUvm, accessCounterIndex) 594 595 NvU32 uvmGetRegOffsetAccessCntrBufferHi_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); 596 597 598 #ifdef __nvoc_uvm_h_disabled 599 static inline NvU32 uvmGetRegOffsetAccessCntrBufferHi(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 600 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 601 return 0; 602 } 603 #else //__nvoc_uvm_h_disabled 604 #define uvmGetRegOffsetAccessCntrBufferHi(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferHi_TU102(pUvm, accessCounterIndex) 605 #endif //__nvoc_uvm_h_disabled 606 607 #define uvmGetRegOffsetAccessCntrBufferHi_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferHi(pUvm, accessCounterIndex) 608 609 NvU32 uvmGetRegOffsetAccessCntrBufferLo_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); 610 611 612 #ifdef __nvoc_uvm_h_disabled 613 static inline NvU32 uvmGetRegOffsetAccessCntrBufferLo(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 614 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 615 return 0; 616 } 617 #else //__nvoc_uvm_h_disabled 618 #define uvmGetRegOffsetAccessCntrBufferLo(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferLo_TU102(pUvm, accessCounterIndex) 619 #endif //__nvoc_uvm_h_disabled 620 621 #define uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferLo(pUvm, accessCounterIndex) 622 623 NvU32 uvmGetRegOffsetAccessCntrBufferConfig_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); 624 625 626 #ifdef __nvoc_uvm_h_disabled 627 static inline NvU32 uvmGetRegOffsetAccessCntrBufferConfig(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 628 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 629 return 0; 630 } 631 #else //__nvoc_uvm_h_disabled 632 #define uvmGetRegOffsetAccessCntrBufferConfig(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferConfig_TU102(pUvm, accessCounterIndex) 633 #endif //__nvoc_uvm_h_disabled 634 635 #define uvmGetRegOffsetAccessCntrBufferConfig_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferConfig(pUvm, accessCounterIndex) 636 637 NvU32 uvmGetRegOffsetAccessCntrBufferInfo_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); 638 639 640 #ifdef __nvoc_uvm_h_disabled 641 static inline NvU32 uvmGetRegOffsetAccessCntrBufferInfo(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 642 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 643 return 0; 644 } 645 #else //__nvoc_uvm_h_disabled 646 #define uvmGetRegOffsetAccessCntrBufferInfo(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferInfo_TU102(pUvm, accessCounterIndex) 647 #endif //__nvoc_uvm_h_disabled 648 649 #define uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferInfo(pUvm, accessCounterIndex) 650 651 NvU32 uvmGetRegOffsetAccessCntrBufferSize_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex); 652 653 654 #ifdef __nvoc_uvm_h_disabled 655 static inline NvU32 uvmGetRegOffsetAccessCntrBufferSize(struct OBJUVM *pUvm, NvU32 accessCounterIndex) { 656 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); 657 return 0; 658 } 659 #else //__nvoc_uvm_h_disabled 660 #define uvmGetRegOffsetAccessCntrBufferSize(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferSize_TU102(pUvm, accessCounterIndex) 661 #endif //__nvoc_uvm_h_disabled 662 663 #define uvmGetRegOffsetAccessCntrBufferSize_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferSize(pUvm, accessCounterIndex) 664 665 void uvmStateDestroy_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); 666 667 static inline void uvmStateDestroy_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pUvm) { 668 pUvm->__uvmStateDestroy__(pGpu, pUvm); 669 } 670 671 NV_STATUS uvmStateInitUnlocked_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); 672 673 static inline NV_STATUS uvmStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pUvm) { 674 return pUvm->__uvmStateInitUnlocked__(pGpu, pUvm); 675 } 676 677 void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[167]); 678 679 static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[167]) { 680 pUvm->__uvmRegisterIntrService__(arg0, pUvm, arg1); 681 } 682 683 NvU32 uvmServiceInterrupt_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceServiceInterruptArguments *arg1); 684 685 static inline NvU32 uvmServiceInterrupt_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceServiceInterruptArguments *arg1) { 686 return pUvm->__uvmServiceInterrupt__(arg0, pUvm, arg1); 687 } 688 689 static inline NV_STATUS uvmStateLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { 690 return pEngstate->__uvmStateLoad__(pGpu, pEngstate, arg0); 691 } 692 693 static inline NV_STATUS uvmStateUnload_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { 694 return pEngstate->__uvmStateUnload__(pGpu, pEngstate, arg0); 695 } 696 697 static inline NV_STATUS uvmServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { 698 return pIntrService->__uvmServiceNotificationInterrupt__(pGpu, pIntrService, pParams); 699 } 700 701 static inline NV_STATUS uvmStateInitLocked_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) { 702 return pEngstate->__uvmStateInitLocked__(pGpu, pEngstate); 703 } 704 705 static inline NV_STATUS uvmStatePreLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { 706 return pEngstate->__uvmStatePreLoad__(pGpu, pEngstate, arg0); 707 } 708 709 static inline NV_STATUS uvmStatePostUnload_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { 710 return pEngstate->__uvmStatePostUnload__(pGpu, pEngstate, arg0); 711 } 712 713 static inline NV_STATUS uvmStatePreUnload_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { 714 return pEngstate->__uvmStatePreUnload__(pGpu, pEngstate, arg0); 715 } 716 717 static inline void uvmInitMissing_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) { 718 pEngstate->__uvmInitMissing__(pGpu, pEngstate); 719 } 720 721 static inline NV_STATUS uvmStatePreInitLocked_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) { 722 return pEngstate->__uvmStatePreInitLocked__(pGpu, pEngstate); 723 } 724 725 static inline NV_STATUS uvmStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) { 726 return pEngstate->__uvmStatePreInitUnlocked__(pGpu, pEngstate); 727 } 728 729 static inline NvBool uvmClearInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pIntrService, IntrServiceClearInterruptArguments *pParams) { 730 return pIntrService->__uvmClearInterrupt__(pGpu, pIntrService, pParams); 731 } 732 733 static inline NV_STATUS uvmStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { 734 return pEngstate->__uvmStatePostLoad__(pGpu, pEngstate, arg0); 735 } 736 737 static inline NV_STATUS uvmConstructEngine_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, ENGDESCRIPTOR arg0) { 738 return pEngstate->__uvmConstructEngine__(pGpu, pEngstate, arg0); 739 } 740 741 static inline NvBool uvmIsPresent_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) { 742 return pEngstate->__uvmIsPresent__(pGpu, pEngstate); 743 } 744 745 #undef PRIVATE_FIELD 746 747 748 #endif // UVM_H 749 750 #ifdef __cplusplus 751 } // extern "C" 752 #endif 753 #endif // _G_UVM_NVOC_H_ 754