1 // This file is automatically generated by rmconfig - DO NOT EDIT! 2 // 3 // defines to indicate enabled/disabled for all chips, features, classes, engines, and apis. 4 // 5 // Profile: shipping-gpus-openrm 6 // Template: templates/gt_rmconfig.h 7 // 8 // Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X 9 // 10 11 #ifndef _RMCFG_H_ 12 #define _RMCFG_H_ 13 14 15 // 16 // CHIP families - enabled or disabled 17 // 18 #define RMCFG_CHIP_GF10X 0 19 #define RMCFG_CHIP_GF11X 0 20 #define RMCFG_CHIP_GF10XF 0 21 #define RMCFG_CHIP_GK10X 0 22 #define RMCFG_CHIP_GK11X 0 23 #define RMCFG_CHIP_GK20X 0 24 #define RMCFG_CHIP_GM10X 0 25 #define RMCFG_CHIP_GM20X 0 26 #define RMCFG_CHIP_GP10X 0 27 #define RMCFG_CHIP_GV10X 0 28 #define RMCFG_CHIP_GV11X 0 29 #define RMCFG_CHIP_TU10X 1 30 #define RMCFG_CHIP_GA10X 1 31 #define RMCFG_CHIP_GA10XF 0 32 #define RMCFG_CHIP_AD10X 1 33 #define RMCFG_CHIP_GH10X 1 34 #define RMCFG_CHIP_GH20X 0 35 #define RMCFG_CHIP_T12X 0 36 #define RMCFG_CHIP_T13X 0 37 #define RMCFG_CHIP_T21X 0 38 #define RMCFG_CHIP_T18X 0 39 #define RMCFG_CHIP_T19X 0 40 #define RMCFG_CHIP_T23XG 0 41 #define RMCFG_CHIP_T23XD 0 42 #define RMCFG_CHIP_SIMS 0 43 44 45 // 46 // CHIPS - enabled or disabled 47 // 48 #define RMCFG_CHIP_GM107 0 49 #define RMCFG_CHIP_GM108 0 50 51 #define RMCFG_CHIP_GM200 0 52 #define RMCFG_CHIP_GM204 0 53 #define RMCFG_CHIP_GM206 0 54 55 #define RMCFG_CHIP_GP100 0 56 #define RMCFG_CHIP_GP102 0 57 #define RMCFG_CHIP_GP104 0 58 #define RMCFG_CHIP_GP106 0 59 #define RMCFG_CHIP_GP107 0 60 #define RMCFG_CHIP_GP108 0 61 62 #define RMCFG_CHIP_GV100 0 63 64 #define RMCFG_CHIP_GV11B 0 65 66 #define RMCFG_CHIP_TU102 1 67 #define RMCFG_CHIP_TU104 1 68 #define RMCFG_CHIP_TU106 1 69 #define RMCFG_CHIP_TU116 1 70 #define RMCFG_CHIP_TU117 1 71 72 #define RMCFG_CHIP_GA100 1 73 #define RMCFG_CHIP_GA102 1 74 #define RMCFG_CHIP_GA103 1 75 #define RMCFG_CHIP_GA104 1 76 #define RMCFG_CHIP_GA106 1 77 #define RMCFG_CHIP_GA107 1 78 #define RMCFG_CHIP_GA10B 0 79 80 #define RMCFG_CHIP_GA102F 0 81 82 #define RMCFG_CHIP_AD102 1 83 #define RMCFG_CHIP_AD103 1 84 #define RMCFG_CHIP_AD104 1 85 #define RMCFG_CHIP_AD106 1 86 #define RMCFG_CHIP_AD107 1 87 88 #define RMCFG_CHIP_GH100 1 89 90 #define RMCFG_CHIP_T194 0 91 92 #define RMCFG_CHIP_T234 0 93 94 #define RMCFG_CHIP_T234D 0 95 96 #define RMCFG_CHIP_AMODEL 0 97 98 // 99 // Obsolete CHIPS 100 // 101 #define RMCFG_CHIP_GF100 0 102 #define RMCFG_CHIP_GF100B 0 103 #define RMCFG_CHIP_GF104 0 104 #define RMCFG_CHIP_GF104B 0 105 #define RMCFG_CHIP_GF106 0 106 #define RMCFG_CHIP_GF106B 0 107 #define RMCFG_CHIP_GF108 0 108 #define RMCFG_CHIP_GF110D 0 109 #define RMCFG_CHIP_GF110 0 110 #define RMCFG_CHIP_GF117 0 111 #define RMCFG_CHIP_GF118 0 112 #define RMCFG_CHIP_GF119 0 113 #define RMCFG_CHIP_GF110F 0 114 #define RMCFG_CHIP_GF110F2 0 115 #define RMCFG_CHIP_GF110F3 0 116 #define RMCFG_CHIP_GK104 0 117 #define RMCFG_CHIP_GK106 0 118 #define RMCFG_CHIP_GK107 0 119 #define RMCFG_CHIP_GK20A 0 120 #define RMCFG_CHIP_GK110 0 121 #define RMCFG_CHIP_GK110B 0 122 #define RMCFG_CHIP_GK110C 0 123 #define RMCFG_CHIP_GK208 0 124 #define RMCFG_CHIP_GK208S 0 125 #define RMCFG_CHIP_GH202 0 126 #define RMCFG_CHIP_T001_FERMI_NOT_EXIST 0 127 #define RMCFG_CHIP_T124 0 128 #define RMCFG_CHIP_T132 0 129 #define RMCFG_CHIP_T210 0 130 #define RMCFG_CHIP_T186 0 131 #define RMCFG_CHIP_T002_TURING_NOT_EXIST 0 132 #define RMCFG_CHIP_T003_ADA_NOT_EXIST 0 133 #define RMCFG_CHIP_T004_HOPPER_NOT_EXIST 0 134 135 136 // 137 // CHIP aliases 138 // 139 #define RMCFG_CHIP_CLASSIC_GPUS 1 140 #define RMCFG_CHIP_dFERMI 0 141 #define RMCFG_CHIP_DFERMI 0 142 #define RMCFG_CHIP_FERMI 0 143 #define RMCFG_CHIP_FERMI_CLASSIC_GPUS 0 144 #define RMCFG_CHIP_ALL 1 145 #define RMCFG_CHIP_ALL_CLASSIC_GPUS 1 146 #define RMCFG_CHIP_ALL_CHIPS 1 147 #define RMCFG_CHIP_ALL_CHIPS_CLASSIC_GPUS 1 148 #define RMCFG_CHIP_DISPLAYLESS 1 149 #define RMCFG_CHIP_dKEPLER 0 150 #define RMCFG_CHIP_DKEPLER 0 151 #define RMCFG_CHIP_KEPLER 0 152 #define RMCFG_CHIP_KEPLER_CLASSIC_GPUS 0 153 #define RMCFG_CHIP_dMAXWELL 0 154 #define RMCFG_CHIP_DMAXWELL 0 155 #define RMCFG_CHIP_MAXWELL 0 156 #define RMCFG_CHIP_MAXWELL_CLASSIC_GPUS 0 157 #define RMCFG_CHIP_dPASCAL 0 158 #define RMCFG_CHIP_DPASCAL 0 159 #define RMCFG_CHIP_PASCAL 0 160 #define RMCFG_CHIP_PASCAL_CLASSIC_GPUS 0 161 #define RMCFG_CHIP_dVOLTA 0 162 #define RMCFG_CHIP_DVOLTA 0 163 #define RMCFG_CHIP_VOLTA 0 164 #define RMCFG_CHIP_VOLTA_CLASSIC_GPUS 0 165 #define RMCFG_CHIP_dTURING 1 166 #define RMCFG_CHIP_DTURING 1 167 #define RMCFG_CHIP_TURING 1 168 #define RMCFG_CHIP_TURING_CLASSIC_GPUS 1 169 #define RMCFG_CHIP_dAMPERE 1 170 #define RMCFG_CHIP_DAMPERE 1 171 #define RMCFG_CHIP_AMPERE 1 172 #define RMCFG_CHIP_AMPERE_CLASSIC_GPUS 1 173 #define RMCFG_CHIP_TEGRA_DGPU_AMPERE 0 174 #define RMCFG_CHIP_TEGRA_DGPU 0 175 #define RMCFG_CHIP_DFPGA 0 176 #define RMCFG_CHIP_dADA 1 177 #define RMCFG_CHIP_DADA 1 178 #define RMCFG_CHIP_ADA 1 179 #define RMCFG_CHIP_ADA_CLASSIC_GPUS 1 180 #define RMCFG_CHIP_dHOPPER 1 181 #define RMCFG_CHIP_DHOPPER 1 182 #define RMCFG_CHIP_HOPPER 1 183 #define RMCFG_CHIP_HOPPER_CLASSIC_GPUS 1 184 #define RMCFG_CHIP_TEGRA_DISP 0 185 #define RMCFG_CHIP_TEGRA_BIG_GPUS 0 186 #define RMCFG_CHIP_FERMI_TEGRA_BIG_GPUS 0 187 #define RMCFG_CHIP_TEGRA 0 188 #define RMCFG_CHIP_TEGRA_TEGRA_BIG_GPUS 0 189 #define RMCFG_CHIP_ALL_TEGRA_BIG_GPUS 0 190 #define RMCFG_CHIP_ALL_CHIPS_TEGRA_BIG_GPUS 0 191 #define RMCFG_CHIP_tKEPLER 0 192 #define RMCFG_CHIP_TKEPLER 0 193 #define RMCFG_CHIP_KEPLER_TEGRA_BIG_GPUS 0 194 #define RMCFG_CHIP_tMAXWELL 0 195 #define RMCFG_CHIP_TMAXWELL 0 196 #define RMCFG_CHIP_MAXWELL_TEGRA_BIG_GPUS 0 197 #define RMCFG_CHIP_tPASCAL 0 198 #define RMCFG_CHIP_TPASCAL 0 199 #define RMCFG_CHIP_PASCAL_TEGRA_BIG_GPUS 0 200 #define RMCFG_CHIP_tVOLTA 0 201 #define RMCFG_CHIP_TVOLTA 0 202 #define RMCFG_CHIP_VOLTA_TEGRA_BIG_GPUS 0 203 #define RMCFG_CHIP_TEGRA_DISP_TEGRA_BIG_GPUS 0 204 #define RMCFG_CHIP_TURING_TEGRA_BIG_GPUS 0 205 #define RMCFG_CHIP_T23X 0 206 #define RMCFG_CHIP_T23X_TEGRA_BIG_GPUS 0 207 #define RMCFG_CHIP_tAMPERE 0 208 #define RMCFG_CHIP_TAMPERE 0 209 #define RMCFG_CHIP_AMPERE_TEGRA_BIG_GPUS 0 210 #define RMCFG_CHIP_ADA_TEGRA_BIG_GPUS 0 211 #define RMCFG_CHIP_HOPPER_TEGRA_BIG_GPUS 0 212 #define RMCFG_CHIP_TEGRA_NVDISP_GPUS 0 213 #define RMCFG_CHIP_T23X_TEGRA_NVDISP_GPUS 0 214 #define RMCFG_CHIP_TEGRA_TEGRA_NVDISP_GPUS 0 215 #define RMCFG_CHIP_TEGRA_DISP_TEGRA_NVDISP_GPUS 0 216 #define RMCFG_CHIP_ALL_TEGRA_NVDISP_GPUS 0 217 #define RMCFG_CHIP_ALL_CHIPS_TEGRA_NVDISP_GPUS 0 218 #define RMCFG_CHIP_SIMULATION_GPUS 0 219 #define RMCFG_CHIP_ALL_SIMULATION_GPUS 0 220 #define RMCFG_CHIP_ALL_CHIPS_SIMULATION_GPUS 0 221 222 223 // 224 // Features - enabled or disabled 225 // 226 #define RMCFG_FEATURE_PLATFORM_UNKNOWN 0 // Running on an unknown platform 227 #define RMCFG_FEATURE_PLATFORM_WINDOWS 0 // Running on Windows 228 #define RMCFG_FEATURE_PLATFORM_UNIX 1 // Running on Unix 229 #define RMCFG_FEATURE_PLATFORM_DCE 0 // Running on Display Control Engine (DCE, an ARM Cortex R5 on Tegra) 230 #define RMCFG_FEATURE_PLATFORM_SIM 0 // Running on Simulator 231 #define RMCFG_FEATURE_PLATFORM_MODS 0 // Running as part of MODS 232 #define RMCFG_FEATURE_PLATFORM_GSP 0 // Running as part of GSP Firmware 233 #define RMCFG_FEATURE_PLATFORM_MODS_WINDOWS 0 // Running as part of MODS on Windows 234 #define RMCFG_FEATURE_PLATFORM_MODS_UNIX 0 // Running as part of MODS on UNIX 235 #define RMCFG_FEATURE_PLATFORM_UNIX_VMWARE 0 // Running on VMware 236 #define RMCFG_FEATURE_ARCH_UNKNOWN 0 // unknown arch 237 #define RMCFG_FEATURE_ARCH_X86 0 // Intel x86, 32bit 238 #define RMCFG_FEATURE_ARCH_X64 0 // Intel 64bit 239 #define RMCFG_FEATURE_ARCH_RISCV64 0 // RISCV, 64bit 240 #define RMCFG_FEATURE_ARCH_AMD64 1 // AMD, 64bit 241 #define RMCFG_FEATURE_ARCH_PPC 0 // Power PC 242 #define RMCFG_FEATURE_ARCH_PPC64LE 0 // 64-bit PPC little-endian 243 #define RMCFG_FEATURE_ARCH_ARM 0 // ARM 244 #define RMCFG_FEATURE_ARCH_ARM_V7 0 // ARM v7 245 #define RMCFG_FEATURE_ARCH_AARCH64 0 // AArch64 246 #define RMCFG_FEATURE_RMCORE_BASE 1 // RMCORE Base 247 #define RMCFG_FEATURE_KERNEL_RM 1 // Kernel layer of RM 248 #define RMCFG_FEATURE_ORIN_PHYSICAL_RM 1 // Physical layer of RM, disabled only on Orin 249 #define RMCFG_FEATURE_VGPU_GSP_PLUGIN_OFFLOAD 1 // vGPU GSP plugin offload 250 #define RMCFG_FEATURE_SLINEXT 1 251 #define RMCFG_FEATURE_NOTEBOOK 1 // Notebook support 252 #define RMCFG_FEATURE_EXTDEV 1 // Daughter boards connected to Quadro GPUs 253 #define RMCFG_FEATURE_EXTDEV_GSYNC 1 // Quadro Sync (QSYNC) board for Quadro GPUs 254 #define RMCFG_FEATURE_EXTDEV_GSYNC_P2060 1 // Quadro Sync (QSYNC) board version 3 255 #define RMCFG_FEATURE_MXM 0 // MXM Module Support (all versions) 256 #define RMCFG_FEATURE_NBSI 1 // NoteBook System Information Structure 257 #define RMCFG_FEATURE_ONSEMI_NB7NQ621M 1 // ONSEMI_NB7NQ621M Redriver Support 258 #define RMCFG_FEATURE_DCB_0X 1 // Fallback DCB routines 259 #define RMCFG_FEATURE_DCB_4X 1 // DCB4x (used on G8x and later) 260 #define RMCFG_FEATURE_RMAPI_GRAVEYARD 1 // Use RMAPI Graveyard to translate deprecated APIs 261 #define RMCFG_FEATURE_HOTPLUG_POLLING 0 // HotPlug polling 262 #define RMCFG_FEATURE_MULTI_GPU 1 // Multiple GPUs managed by same RM instance 263 #define RMCFG_FEATURE_RM_BASIC_LOCK_MODEL 1 // Support for Basic Lock Model in RM 264 #define RMCFG_FEATURE_VIRTUALIZATION 0 // Detection and Guest RM Implementation within a Virtualization environment 265 #define RMCFG_FEATURE_VIRTUALIZATION_LEGACY 0 // aka VIRTUALIZATION 266 #define RMCFG_FEATURE_PRESILICON 0 // For builds that can run on simulated or emulated GPU 267 #define RMCFG_FEATURE_GSP_CLIENT_RM 1 // GSP client RM 268 #define RMCFG_FEATURE_DCE_CLIENT_RM 0 // DCE client RM 269 #define RMCFG_FEATURE_PROTOBUF 1 // Protobuf data encoding for OCA data dumps 270 #define RMCFG_FEATURE_RELEASE_BUILD 1 // Release Build 271 #define RMCFG_FEATURE_RM_NEW_TRACER_ETW 0 // New Event Tracing for Windows (ETW) in RM 272 #define RMCFG_FEATURE_VERIF_ONLY_CONTROLS 0 // Allow verify only control cmds to be used on verif builds (determined by this feature) 273 #define RMCFG_FEATURE_PAGE_RETIREMENT 1 // Offlining bad memory pages from the FB heap 274 #define RMCFG_FEATURE_PMA 1 // Physical memory allocator 275 #define RMCFG_FEATURE_DEVINIT_SCRIPT 0 // VBIOS scripting engine for sharing register sequences 276 #define RMCFG_FEATURE_UNIX_CONSOLE_STATE 1 // Unix console state management and display programming 277 #define RMCFG_FEATURE_OLD_DAC 1 // Legacy display support with dac code 278 #define RMCFG_FEATURE_CRC_POLLING 1 // GPU supports CRC Polling 279 #define RMCFG_FEATURE_DSI_INFO 0 // DSI information structures support 280 #define RMCFG_FEATURE_CLK2 1 // Tracks Clocks 2.0 project 281 #define RMCFG_FEATURE_GPU_LOW_POWER 1 // GPU low power Feature on Kepler and later 282 #define RMCFG_FEATURE_PC_VENDOR_SPECIFIC 1 // Vendor-specific code and features for PC 283 #define RMCFG_FEATURE_PEX_RESET_RECOVERY 1 // Enables the PEX Reset Recovery feature, which uses root/bridge port SBR to reset GPU when lost 284 #define RMCFG_FEATURE_HWBC 1 // Enables support bridge chip devices 285 #define RMCFG_FEATURE_SPARSE_TEXTURE 1 // Enables optimization and defaults for sparse texture 286 #define RMCFG_FEATURE_CFGEX_PERF_MODE 1 // legacy support for performance modes 287 #define RMCFG_FEATURE_TILED_RESOURCE_COMPR 1 288 #define RMCFG_FEATURE_SYNC_GPU_BOOST 1 // Synchronized GPU Boost 289 #define RMCFG_FEATURE_NVSR_ON_NVDISPLAY 1 // NVSR on Nvdisplay 290 #define RMCFG_FEATURE_MODS_FEATURES 0 // Flag for enabling MODS required features in RM 291 #define RMCFG_FEATURE_MULTINODE_FABRIC_IMEX 1 // Multinode fabric memory import/export support 292 #define RMCFG_FEATURE_MANUAL_TRIGGER_BA_DMA_MODE 0 // Support for manually actuated BA DMA mode data collection. 293 #define RMCFG_FEATURE_RM_DRIVEN_BA_DMA_MODE 0 // Support for RM-driven BA DMA mode data collection. 294 #define RMCFG_FEATURE_VBLANK_CALLBACK 1 // Vblank callback functionality within RM 295 #define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY 0 // Tegra SOC NvDisplay Driver 296 #define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY_MINIMAL 0 // Enable only those parts of display code which are needed for Tegra SOC NvDisplay Driver 297 #define RMCFG_FEATURE_HEAD_REGIONAL_CRC 0 // Display Head Regional CRC support 298 #define RMCFG_FEATURE_FEATURE_GH180 1 // RMconfig to encapsulate GH180 features 299 #define RMCFG_FEATURE_MULTICAST_FABRIC 1 // Support for MULTICAST_FABRIC 300 #define RMCFG_FEATURE_NVLINK_ERROR_THRESHOLD 1 // Support for NVLINK_ERROR_THRESHOLD 301 #define RMCFG_FEATURE_GSP_SEC2_ENC_CHNLMGMT_RC_WAR 1 // WAR required for RC handling. See comment #36 of bug 4406277 302 #define RMCFG_FEATURE_FABRIC_LINEAR_ADDRESSING 1 // Unicast fabric memory management 303 304 305 306 // 307 // Classes - enabled or disabled 308 // 309 #define RMCFG_CLASS_NV01_ROOT 1 310 #define RMCFG_CLASS_NV1_ROOT 1 // aka NV01_ROOT 311 #define RMCFG_CLASS_NV01_NULL_OBJECT 1 // aka NV01_ROOT 312 #define RMCFG_CLASS_NV1_NULL_OBJECT 1 // aka NV01_ROOT 313 #define RMCFG_CLASS_NV01_ROOT_NON_PRIV 1 314 #define RMCFG_CLASS_NV1_ROOT_NON_PRIV 1 // aka NV01_ROOT_NON_PRIV 315 #define RMCFG_CLASS_NV01_ROOT_CLIENT 1 316 #define RMCFG_CLASS_FABRIC_MANAGER_SESSION 1 317 #define RMCFG_CLASS_NV0020_GPU_MANAGEMENT 1 318 #define RMCFG_CLASS_NV01_DEVICE_0 1 319 #define RMCFG_CLASS_NV20_SUBDEVICE_0 1 320 #define RMCFG_CLASS_NV2081_BINAPI 1 321 #define RMCFG_CLASS_NV2082_BINAPI_PRIVILEGED 1 322 #define RMCFG_CLASS_NV20_SUBDEVICE_DIAG 1 323 #define RMCFG_CLASS_NV01_CONTEXT_DMA 1 324 #define RMCFG_CLASS_NV01_MEMORY_SYSTEM 1 325 #define RMCFG_CLASS_NV1_MEMORY_SYSTEM 1 // aka NV01_MEMORY_SYSTEM 326 #define RMCFG_CLASS_NV01_MEMORY_LOCAL_PRIVILEGED 1 327 #define RMCFG_CLASS_NV1_MEMORY_LOCAL_PRIVILEGED 1 // aka NV01_MEMORY_LOCAL_PRIVILEGED 328 #define RMCFG_CLASS_NV01_MEMORY_PRIVILEGED 1 // aka NV01_MEMORY_LOCAL_PRIVILEGED 329 #define RMCFG_CLASS_NV1_MEMORY_PRIVILEGED 1 // aka NV01_MEMORY_LOCAL_PRIVILEGED 330 #define RMCFG_CLASS_NV01_MEMORY_LOCAL_USER 1 331 #define RMCFG_CLASS_NV1_MEMORY_LOCAL_USER 1 // aka NV01_MEMORY_LOCAL_USER 332 #define RMCFG_CLASS_NV01_MEMORY_USER 1 // aka NV01_MEMORY_LOCAL_USER 333 #define RMCFG_CLASS_NV1_MEMORY_USER 1 // aka NV01_MEMORY_LOCAL_USER 334 #define RMCFG_CLASS_NV_MEMORY_EXTENDED_USER 1 // Extended GPU Memory 335 #define RMCFG_CLASS_NV01_MEMORY_VIRTUAL 1 336 #define RMCFG_CLASS_NV01_MEMORY_SYSTEM_DYNAMIC 1 // aka NV01_MEMORY_VIRTUAL 337 #define RMCFG_CLASS_NV1_MEMORY_SYSTEM_DYNAMIC 1 // aka NV01_MEMORY_VIRTUAL 338 #define RMCFG_CLASS_NV_MEMORY_MAPPER 1 339 #define RMCFG_CLASS_NV01_MEMORY_LOCAL_PHYSICAL 1 340 #define RMCFG_CLASS_NV01_MEMORY_SYNCPOINT 0 341 #define RMCFG_CLASS_NV01_MEMORY_SYSTEM_OS_DESCRIPTOR 1 342 #define RMCFG_CLASS_NV01_MEMORY_DEVICELESS 1 343 #define RMCFG_CLASS_NV01_MEMORY_FRAMEBUFFER_CONSOLE 1 344 #define RMCFG_CLASS_NV01_MEMORY_HW_RESOURCES 1 345 #define RMCFG_CLASS_NV01_MEMORY_LIST_SYSTEM 1 346 #define RMCFG_CLASS_NV01_MEMORY_LIST_FBMEM 1 347 #define RMCFG_CLASS_NV01_MEMORY_LIST_OBJECT 1 348 #define RMCFG_CLASS_NV_IMEX_SESSION 1 349 #define RMCFG_CLASS_NV01_MEMORY_FLA 1 350 #define RMCFG_CLASS_NV_MEMORY_EXPORT 1 351 #define RMCFG_CLASS_NV_CE_UTILS 1 352 #define RMCFG_CLASS_NV_MEMORY_FABRIC 1 353 #define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORT_V2 1 354 #define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORTED_REF 1 355 #define RMCFG_CLASS_FABRIC_VASPACE_A 1 356 #define RMCFG_CLASS_NV_MEMORY_MULTICAST_FABRIC 1 357 #define RMCFG_CLASS_NV_FB_SEGMENT 0 358 #define RMCFG_CLASS_IO_VASPACE_A 1 359 #define RMCFG_CLASS_NV01_NULL 1 360 #define RMCFG_CLASS_NV1_NULL 1 // aka NV01_NULL 361 #define RMCFG_CLASS_NV01_EVENT 1 362 #define RMCFG_CLASS_NV1_EVENT 1 // aka NV01_EVENT 363 #define RMCFG_CLASS_NV01_EVENT_KERNEL_CALLBACK 1 364 #define RMCFG_CLASS_NV1_EVENT_KERNEL_CALLBACK 1 // aka NV01_EVENT_KERNEL_CALLBACK 365 #define RMCFG_CLASS_NV01_EVENT_OS_EVENT 1 366 #define RMCFG_CLASS_NV1_EVENT_OS_EVENT 1 // aka NV01_EVENT_OS_EVENT 367 #define RMCFG_CLASS_NV01_EVENT_WIN32_EVENT 1 // aka NV01_EVENT_OS_EVENT 368 #define RMCFG_CLASS_NV1_EVENT_WIN32_EVENT 1 // aka NV01_EVENT_OS_EVENT 369 #define RMCFG_CLASS_NV01_EVENT_KERNEL_CALLBACK_EX 1 370 #define RMCFG_CLASS_NV1_EVENT_KERNEL_CALLBACK_EX 1 // aka NV01_EVENT_KERNEL_CALLBACK_EX 371 #define RMCFG_CLASS_NV01_TIMER 1 372 #define RMCFG_CLASS_NV1_TIMER 1 // aka NV01_TIMER 373 #define RMCFG_CLASS_KERNEL_GRAPHICS_CONTEXT 1 // Graphics Context in Kernel side 374 #define RMCFG_CLASS_NV50_CHANNEL_GPFIFO 1 375 #define RMCFG_CLASS_GF100_CHANNEL_GPFIFO 1 376 #define RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_A 1 377 #define RMCFG_CLASS_UVM_CHANNEL_RETAINER 1 378 #define RMCFG_CLASS_PHYSICAL_CHANNEL_GPFIFO 0 379 #define RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_B 1 380 #define RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_C 0 381 #define RMCFG_CLASS_MAXWELL_CHANNEL_GPFIFO_A 1 382 #define RMCFG_CLASS_PASCAL_CHANNEL_GPFIFO_A 1 383 #define RMCFG_CLASS_VOLTA_CHANNEL_GPFIFO_A 1 384 #define RMCFG_CLASS_TURING_CHANNEL_GPFIFO_A 1 385 #define RMCFG_CLASS_AMPERE_CHANNEL_GPFIFO_A 1 386 #define RMCFG_CLASS_HOPPER_CHANNEL_GPFIFO_A 1 387 #define RMCFG_CLASS_NV04_SOFTWARE_TEST 1 388 #define RMCFG_CLASS_NV4_SOFTWARE_TEST 1 // aka NV04_SOFTWARE_TEST 389 #define RMCFG_CLASS_NV30_GSYNC 1 390 #define RMCFG_CLASS_NV50_DISPLAY 0 391 #define RMCFG_CLASS_NV9470_DISPLAY 0 392 #define RMCFG_CLASS_NV9471_DISP_SF_USER 0 393 #define RMCFG_CLASS_NV9570_DISPLAY 0 394 #define RMCFG_CLASS_NV9571_DISP_SF_USER 0 395 #define RMCFG_CLASS_NV9770_DISPLAY 0 396 #define RMCFG_CLASS_NV9870_DISPLAY 0 397 #define RMCFG_CLASS_VOLTA_USERMODE_A 1 398 #define RMCFG_CLASS_TURING_USERMODE_A 1 399 #define RMCFG_CLASS_AMPERE_USERMODE_A 1 400 #define RMCFG_CLASS_HOPPER_USERMODE_A 1 401 #define RMCFG_CLASS_NVC370_DISPLAY 0 402 #define RMCFG_CLASS_NVC371_DISP_SF_USER 1 403 #define RMCFG_CLASS_NVC372_DISPLAY_SW 1 404 #define RMCFG_CLASS_NVC373_DISP_CAPABILITIES 0 405 #define RMCFG_CLASS_NVC573_DISP_CAPABILITIES 1 406 #define RMCFG_CLASS_NVC673_DISP_CAPABILITIES 1 407 #define RMCFG_CLASS_NVC773_DISP_CAPABILITIES 1 408 #define RMCFG_CLASS_NV04_DISPLAY_COMMON 1 409 #define RMCFG_CLASS_NV50_DEFERRED_API_CLASS 1 410 #define RMCFG_CLASS_MPS_COMPUTE 1 411 #define RMCFG_CLASS_NV917A_CURSOR_CHANNEL_PIO 0 412 #define RMCFG_CLASS_NV917B_OVERLAY_IMM_CHANNEL_PIO 0 413 #define RMCFG_CLASS_NV917E_OVERLAY_CHANNEL_DMA 0 414 #define RMCFG_CLASS_NV927C_BASE_CHANNEL_DMA 0 415 #define RMCFG_CLASS_NV947D_CORE_CHANNEL_DMA 0 416 #define RMCFG_CLASS_NV957D_CORE_CHANNEL_DMA 0 417 #define RMCFG_CLASS_NV977D_CORE_CHANNEL_DMA 0 418 #define RMCFG_CLASS_NV987D_CORE_CHANNEL_DMA 0 419 #define RMCFG_CLASS_NVC37A_CURSOR_IMM_CHANNEL_PIO 0 420 #define RMCFG_CLASS_NVC37B_WINDOW_IMM_CHANNEL_DMA 0 421 #define RMCFG_CLASS_NVC37D_CORE_CHANNEL_DMA 0 422 #define RMCFG_CLASS_NVC37E_WINDOW_CHANNEL_DMA 0 423 #define RMCFG_CLASS_NVC570_DISPLAY 1 424 #define RMCFG_CLASS_NVC57A_CURSOR_IMM_CHANNEL_PIO 1 425 #define RMCFG_CLASS_NVC57B_WINDOW_IMM_CHANNEL_DMA 1 426 #define RMCFG_CLASS_NVC57D_CORE_CHANNEL_DMA 1 427 #define RMCFG_CLASS_NVC57E_WINDOW_CHANNEL_DMA 1 428 #define RMCFG_CLASS_NVC670_DISPLAY 1 429 #define RMCFG_CLASS_NVC671_DISP_SF_USER 1 430 #define RMCFG_CLASS_NVC67A_CURSOR_IMM_CHANNEL_PIO 1 431 #define RMCFG_CLASS_NVC67B_WINDOW_IMM_CHANNEL_DMA 1 432 #define RMCFG_CLASS_NVC67D_CORE_CHANNEL_DMA 1 433 #define RMCFG_CLASS_NVC67E_WINDOW_CHANNEL_DMA 1 434 #define RMCFG_CLASS_NVC77F_ANY_CHANNEL_DMA 1 435 #define RMCFG_CLASS_NVC770_DISPLAY 1 436 #define RMCFG_CLASS_NVC771_DISP_SF_USER 1 437 #define RMCFG_CLASS_NVC77D_CORE_CHANNEL_DMA 1 438 #define RMCFG_CLASS_NV9010_VBLANK_CALLBACK 1 439 #define RMCFG_CLASS_GF100_PROFILER 1 // Profiler Client Support 440 #define RMCFG_CLASS_MAXWELL_PROFILER 1 // Base Profiler Class 441 #define RMCFG_CLASS_MAXWELL_PROFILER_DEVICE 1 // Device level Profiler Client Support 442 #define RMCFG_CLASS_GF100_SUBDEVICE_MASTER 1 443 #define RMCFG_CLASS_GF100_SUBDEVICE_INFOROM 1 // Inforom interface 444 #define RMCFG_CLASS_TURING_VMMU_A 0 445 #define RMCFG_CLASS_GF100_ZBC_CLEAR 1 446 #define RMCFG_CLASS_GF100_DISP_SW 1 447 #define RMCFG_CLASS_GF100_TIMED_SEMAPHORE_SW 1 448 #define RMCFG_CLASS_G84_PERFBUFFER 1 449 #define RMCFG_CLASS_NV50_MEMORY_VIRTUAL 1 450 #define RMCFG_CLASS_NV50_P2P 1 451 #define RMCFG_CLASS_NV50_THIRD_PARTY_P2P 1 452 #define RMCFG_CLASS_FERMI_TWOD_A 1 // FERMI Graphics 2D 453 #define RMCFG_CLASS_FERMI_VASPACE_A 1 // FERMI virtual address space 454 #define RMCFG_CLASS_HOPPER_SEC2_WORK_LAUNCH_A 1 // Confidential Computing Work Launch 455 #define RMCFG_CLASS_GF100_HDACODEC 1 456 #define RMCFG_CLASS_NVA0B0_VIDEO_DECODER 0 // Combined MSVLD, MSPPP, MSPDEC (Maxwell) 457 #define RMCFG_CLASS_NVB0B0_VIDEO_DECODER 0 // Decoder Class for GM20X 458 #define RMCFG_CLASS_NVB6B0_VIDEO_DECODER 0 // Decoder Class for GM206 459 #define RMCFG_CLASS_NVB8B0_VIDEO_DECODER 1 // Decoder Class for Hopper 460 #define RMCFG_CLASS_NVC1B0_VIDEO_DECODER 0 // Decoder Class for Pascal 461 #define RMCFG_CLASS_NVC2B0_VIDEO_DECODER 0 // Decoder Class for Pascal 462 #define RMCFG_CLASS_NVC3B0_VIDEO_DECODER 0 // Decoder Class for Volta 463 #define RMCFG_CLASS_NVC4B0_VIDEO_DECODER 1 // Decoder Class for Turing 464 #define RMCFG_CLASS_NVC6B0_VIDEO_DECODER 1 // Decoder Class for Ampere 465 #define RMCFG_CLASS_NVC7B0_VIDEO_DECODER 1 // Decoder Class for Ampere 466 #define RMCFG_CLASS_NVC9B0_VIDEO_DECODER 1 // Decoder Class for Ada 467 #define RMCFG_CLASS_NVC0B7_VIDEO_ENCODER 0 468 #define RMCFG_CLASS_NVD0B7_VIDEO_ENCODER 0 469 #define RMCFG_CLASS_NVC1B7_VIDEO_ENCODER 0 470 #define RMCFG_CLASS_NVC2B7_VIDEO_ENCODER 0 471 #define RMCFG_CLASS_NVC3B7_VIDEO_ENCODER 0 472 #define RMCFG_CLASS_NVC4B7_VIDEO_ENCODER 1 473 #define RMCFG_CLASS_NVB4B7_VIDEO_ENCODER 1 474 #define RMCFG_CLASS_NVC7B7_VIDEO_ENCODER 1 475 #define RMCFG_CLASS_NVC9B7_VIDEO_ENCODER 1 476 #define RMCFG_CLASS_NVB8D1_VIDEO_NVJPG 1 477 #define RMCFG_CLASS_NVC4D1_VIDEO_NVJPG 1 478 #define RMCFG_CLASS_NVC9D1_VIDEO_NVJPG 1 479 #define RMCFG_CLASS_NVB8FA_VIDEO_OFA 1 480 #define RMCFG_CLASS_NVC6FA_VIDEO_OFA 1 481 #define RMCFG_CLASS_NVC7FA_VIDEO_OFA 1 482 #define RMCFG_CLASS_NVC9FA_VIDEO_OFA 1 483 #define RMCFG_CLASS_KEPLER_INLINE_TO_MEMORY_B 1 // Kepler inline to memory 484 #define RMCFG_CLASS_FERMI_CONTEXT_SHARE_A 1 // Context Share class 485 #define RMCFG_CLASS_KEPLER_CHANNEL_GROUP_A 1 // Channel Group Class 486 #define RMCFG_CLASS_MAXWELL_A 0 // Maxwell Graphics 487 #define RMCFG_CLASS_MAXWELL_COMPUTE_A 0 // Maxwell Graphics Compute 488 #define RMCFG_CLASS_MAXWELL_B 0 // Maxwell Graphics second generation 489 #define RMCFG_CLASS_MAXWELL_COMPUTE_B 0 // Maxwell Graphics Compute 490 #define RMCFG_CLASS_PASCAL_A 0 // Pascal Graphics 491 #define RMCFG_CLASS_PASCAL_COMPUTE_A 0 // Pascal Graphics Compute 492 #define RMCFG_CLASS_PASCAL_DMA_COPY_A 1 493 #define RMCFG_CLASS_PASCAL_DMA_COPY_B 0 494 #define RMCFG_CLASS_VOLTA_DMA_COPY_A 0 495 #define RMCFG_CLASS_TURING_DMA_COPY_A 1 496 #define RMCFG_CLASS_AMPERE_DMA_COPY_A 1 497 #define RMCFG_CLASS_AMPERE_DMA_COPY_B 1 498 #define RMCFG_CLASS_HOPPER_DMA_COPY_A 1 499 #define RMCFG_CLASS_MAXWELL_DMA_COPY_A 1 500 #define RMCFG_CLASS_MAXWELL_FAULT_BUFFER_A 0 // Maxwell Fault Buffer for Gr 501 #define RMCFG_CLASS_ACCESS_COUNTER_NOTIFY_BUFFER 1 // Access Cntr Buffer for Gr 502 #define RMCFG_CLASS_MMU_FAULT_BUFFER 1 // Volta Fault Buffer for Gr 503 #define RMCFG_CLASS_MMU_VIDMEM_ACCESS_BIT_BUFFER 1 // Ampere Vidmem Access Bit Buffer 504 #define RMCFG_CLASS_PASCAL_B 0 // Pascal Graphics 2nd Gen 505 #define RMCFG_CLASS_PASCAL_COMPUTE_B 0 // Pascal Graphics Compute 2nd Gen 506 #define RMCFG_CLASS_VOLTA_A 0 // Volta Graphics 507 #define RMCFG_CLASS_VOLTA_COMPUTE_A 0 // Volta Graphics Compute 508 #define RMCFG_CLASS_TURING_A 1 // Turing Graphics 509 #define RMCFG_CLASS_TURING_COMPUTE_A 1 // Turing Graphics Compute 510 #define RMCFG_CLASS_AMPERE_A 1 // AmpereA (Graphics) 511 #define RMCFG_CLASS_AMPERE_COMPUTE_A 1 // AmpereComputeA (Graphics Compute) 512 #define RMCFG_CLASS_AMPERE_B 1 // AmpereB (Graphics) 513 #define RMCFG_CLASS_AMPERE_COMPUTE_B 1 // AmpereComputeB (Graphics Compute) 514 #define RMCFG_CLASS_ADA_A 1 // AdaA (Graphics) 515 #define RMCFG_CLASS_ADA_COMPUTE_A 1 // AdaComputeA (Graphics Compute) 516 #define RMCFG_CLASS_AMPERE_SMC_PARTITION_REF 1 // Ampere SMC Partition Subscription 517 #define RMCFG_CLASS_AMPERE_SMC_EXEC_PARTITION_REF 1 // Ampere SMC Execution Partition Subscription 518 #define RMCFG_CLASS_AMPERE_SMC_CONFIG_SESSION 1 // Ampere SMC config session subscription 519 #define RMCFG_CLASS_NV0092_RG_LINE_CALLBACK 1 // RG line callback functions 520 #define RMCFG_CLASS_AMPERE_SMC_MONITOR_SESSION 1 // Ampere SMC monitor session subscription 521 #define RMCFG_CLASS_HOPPER_A 1 // HopperA (Graphics) 522 #define RMCFG_CLASS_HOPPER_COMPUTE_A 1 // HopperComputeA (Graphics Compute) 523 #define RMCFG_CLASS_NV40_DEBUG_BUFFER 1 524 #define RMCFG_CLASS_RM_USER_SHARED_DATA 1 525 #define RMCFG_CLASS_GT200_DEBUGGER 1 // CUDA Debugger support 526 #define RMCFG_CLASS_NV40_I2C 1 // I2C operations 527 #define RMCFG_CLASS_NV_E3_THREED 0 // Tegra 3D class 528 #define RMCFG_CLASS_KEPLER_DEVICE_VGPU 1 // KEPLER virtual gpu 529 #define RMCFG_CLASS_NVA081_VGPU_CONFIG 1 // virtual gpu configuration 530 #define RMCFG_CLASS_NVA084_KERNEL_HOST_VGPU_DEVICE 1 // Kernel component of the host virtual gpu device 531 #define RMCFG_CLASS_NV0060_SYNC_GPU_BOOST 1 // Synchronized GPU Boost Class. Defines a set of GPUs for Synchronized Boost 532 #define RMCFG_CLASS_GP100_UVM_SW 1 // UVM SW class to support SW methods for fault cancel 533 #define RMCFG_CLASS_NVENC_SW_SESSION 1 // GPU NVENC Software Session 534 #define RMCFG_CLASS_NV_EVENT_BUFFER 1 // Event buffer class used to share event data with UMD 535 #define RMCFG_CLASS_NVFBC_SW_SESSION 1 // GPU NVFBC Software Session 536 #define RMCFG_CLASS_NV_CONFIDENTIAL_COMPUTE 1 // Confidential Computing Class 537 #define RMCFG_CLASS_NV_COUNTER_COLLECTION_UNIT 1 // Counter Collection Unit Class 538 #define RMCFG_CLASS_NV_SEMAPHORE_SURFACE 1 // GPU Semaphore encapsulation class 539 540 541 542 // 543 // MODULES - enabled or disabled 544 // 545 #define RMCFG_MODULE_Object 1 // Base class for NVOC objects 546 #define RMCFG_MODULE_OBJECT 1 // aka Object 547 #define RMCFG_MODULE_TRACEABLE 1 // Interface for CaptureState 548 #define RMCFG_MODULE_ENGSTATE 1 // Base class for engines with generic constructors, StateLoad, etc. 549 #define RMCFG_MODULE_HOSTENG 1 // Base class for host engines 550 #define RMCFG_MODULE_FLCNABLE 0 // Base class for engines requiring falcon 551 #define RMCFG_MODULE_PMUCLIENT 0 // Base class for implementations of behavior to interact with the PMU engine 552 #define RMCFG_MODULE_PMU_CLIENT_IMPLEMENTER 0 // Base class for engines that use PMU engine 553 #define RMCFG_MODULE_INTRABLE 0 // Base class to generate and service top-level interrupts 554 #define RMCFG_MODULE_MUTEXABLE 0 // Base class for engines that implements mutex 555 #define RMCFG_MODULE_GpuMutexMgr 0 // GPU Mutex Manager 556 #define RMCFG_MODULE_GPUMUTEXMGR 0 // aka GpuMutexMgr 557 #define RMCFG_MODULE_BIF 0 // Bus Interface 558 #define RMCFG_MODULE_KERNEL_BIF 1 // Bus Interface on Kernel(CPU) RM 559 #define RMCFG_MODULE_BUS 0 // Bus 560 #define RMCFG_MODULE_KERNEL_BUS 1 // Bus on Kernel(CPU) RM 561 #define RMCFG_MODULE_ClockManager 0 // Clock Manager 562 #define RMCFG_MODULE_CLOCKMANAGER 0 // aka ClockManager 563 #define RMCFG_MODULE_KERNEL_ClockManager 1 // Kernel controls for Clock Manager 564 #define RMCFG_MODULE_KERNEL_CLOCKMANAGER 1 // aka KERNEL_ClockManager 565 #define RMCFG_MODULE_DAC 0 // DAC Resource 566 #define RMCFG_MODULE_KERNEL_DISPLAY 1 // Display module on Kernel(CPU) RM 567 #define RMCFG_MODULE_DISP 0 // Display 568 #define RMCFG_MODULE_VIRT_MEM_ALLOCATOR 1 569 #define RMCFG_MODULE_DPAUX 0 570 #define RMCFG_MODULE_MEMORY_SYSTEM 0 // Memory System 571 #define RMCFG_MODULE_KERNEL_MEMORY_SYSTEM 1 // Kernel Memory System 572 #define RMCFG_MODULE_MEMORY_MANAGER 1 // Memory Manager 573 #define RMCFG_MODULE_FBFLCN 0 // FB falcon 574 #define RMCFG_MODULE_FBSR 1 // Frame Buffer Save/Restore 575 #define RMCFG_MODULE_KERNEL_FIFO 1 // Fifo Module on Kernel(CPU) RM 576 #define RMCFG_MODULE_FIFO 0 // aka. HOST 577 #define RMCFG_MODULE_SCHED 0 // Scheduler for runlist 578 #define RMCFG_MODULE_FLCN 0 // Falcon-derived engines 579 #define RMCFG_MODULE_KERNEL_FALCON 1 // Falcon on Kernel(CPU) RM. Used for booting Falcon cores. 580 #define RMCFG_MODULE_KERNEL_VIDEO_ENGINE 1 // Kernel Video Engine. Object to manage video engines (NVJPG, encoders, decoders, etc.) on Kernel RM 581 #define RMCFG_MODULE_GR 0 // Graphic 582 #define RMCFG_MODULE_GR0 0 // aka GR 583 #define RMCFG_MODULE_KERNEL_GRAPHICS 1 // Graphic on Kernel(CPU) RM 584 #define RMCFG_MODULE_GRMGR 0 // Graphics manager. Used for maintaining Gr partitioning policies 585 #define RMCFG_MODULE_MIG_MANAGER 0 // MIG manager on Physical (GSP) RM. Used for maintaining device partitioning policies 586 #define RMCFG_MODULE_KERNEL_MIG_MANAGER 1 // MIG manager on Kernel (CPU) RM. Used for maintaining device partitioning policies 587 #define RMCFG_MODULE_KERNEL_GRAPHICS_MANAGER 1 // Graphics manager on Kernel (CPU) RM. Used for maintaining Gr partitioning policies 588 #define RMCFG_MODULE_HAL 1 // Hardware Abstraction Layer 589 #define RMCFG_MODULE_HEAD 0 // Display component: Head 590 #define RMCFG_MODULE_SF 0 // Display component: Serial Formatter, output protocol formatting 591 #define RMCFG_MODULE_DISPLAY_INSTANCE_MEMORY 1 592 #define RMCFG_MODULE_KERNEL_HEAD 1 593 #define RMCFG_MODULE_INTR 1 594 #define RMCFG_MODULE_MC 0 595 #define RMCFG_MODULE_KERNEL_MC 1 // Master Control-related code needed in Kernel RM 596 #define RMCFG_MODULE_PRIV_RING 0 597 #define RMCFG_MODULE_KERNEL_PERF 1 // Performance module on Kernel(CPU) RM 598 #define RMCFG_MODULE_PERF 0 // Performance Monitor 599 #define RMCFG_MODULE_STEREO 0 // Stereo Viewing 600 #define RMCFG_MODULE_TMR 1 601 #define RMCFG_MODULE_SEQ 0 // Sequencer for backlight and LVDS control 602 #define RMCFG_MODULE_VGA 0 // Video Graphics Array 603 #define RMCFG_MODULE_VBIOS 0 604 #define RMCFG_MODULE_KERNEL_RC 1 // Robust Channels and Watchdog Kernel API 605 #define RMCFG_MODULE_RC 0 // Robust Channels 606 #define RMCFG_MODULE_NV_DEBUG_DUMP 1 // NV Debug 607 #define RMCFG_MODULE_SWENG 1 // Software Engine for all SW classes 608 #define RMCFG_MODULE_GPU 1 // GPU Control Object 609 #define RMCFG_MODULE_I2C 0 // i2c Serial Interface 610 #define RMCFG_MODULE_KERNEL_I2C 1 // Kernel controls for I2C 611 #define RMCFG_MODULE_SPI 0 // SPI Interface 612 #define RMCFG_MODULE_SMBPBI 0 // SMBus Post-Box Interface 613 #define RMCFG_MODULE_GPIO 0 // General Purpose I/O Pins 614 #define RMCFG_MODULE_KERNEL_GPIO 1 // Kernel controls for GPIO 615 #define RMCFG_MODULE_FAN 0 // General Purpose I/O Pins 616 #define RMCFG_MODULE_KERNEL_FAN 1 // Kernel controls for FAN 617 #define RMCFG_MODULE_FUSE 0 618 #define RMCFG_MODULE_VOLT 0 619 #define RMCFG_MODULE_KERNEL_VOLT 1 // Kernel controls for VOLT 620 #define RMCFG_MODULE_THERM 0 // Thermal Monitoring 621 #define RMCFG_MODULE_KERNEL_THERM 1 // Kernel controls Thermal Monitoring 622 #define RMCFG_MODULE_OR 0 // Display component: Output Resource 623 #define RMCFG_MODULE_PIOR 0 // Display component: Parallel Input Output Resource 624 #define RMCFG_MODULE_SOR 0 // Display component: Serial Output Resource 625 #define RMCFG_MODULE_DSI 0 // Display Serial Interface 626 #define RMCFG_MODULE_HDCP 0 // High-bandwidth Digital Content Protection 627 #define RMCFG_MODULE_HDMI 0 // High-Definition Multimedia Interface 628 #define RMCFG_MODULE_ISOHUB 0 // Display's memory read interface 629 #define RMCFG_MODULE_BSP 0 // Bit Stream Processor/NVDEC 630 #define RMCFG_MODULE_NVDEC 0 // aka BSP 631 #define RMCFG_MODULE_KERNEL_NVDEC 1 632 #define RMCFG_MODULE_CIPHER 0 633 #define RMCFG_MODULE_CE 0 // Copy Engine 634 #define RMCFG_MODULE_KERNEL_CE 1 // Kernel Copy Engine 635 #define RMCFG_MODULE_PMU 0 // PMU peregrine core 636 #define RMCFG_MODULE_KERNEL_PMU 1 // PMU peregrine core on Kernel(CPU) RM 637 #define RMCFG_MODULE_PLATFORM_REQUEST_HANDLER 1 // Platform Request Handler on Kernel(CPU) RM 638 #define RMCFG_MODULE_MSENC 0 // Video Encoder (MSENC) Engine 639 #define RMCFG_MODULE_KERNEL_NVENC 1 640 #define RMCFG_MODULE_HDA 0 // High Definition Audio (HDA) Engine 641 #define RMCFG_MODULE_HDACODEC 0 // High Definition Audio (HDA) Codec Engine 642 #define RMCFG_MODULE_INFOROM 0 // InfoROM Engine 643 #define RMCFG_MODULE_KERNEL_INFOROM 1 // Kernel controls for InfoROM Engine 644 #define RMCFG_MODULE_LPWR 0 // Low Power Object. This objects manages all power saving features. 645 #define RMCFG_MODULE_KERNEL_LPWR 1 // Low Power Object. This objects manages all power saving features. 646 #define RMCFG_MODULE_PGCTRL 1 // Power Gating Controller (PGCTRL) Engine 647 #define RMCFG_MODULE_LPWRFSM 0 // LPWR FSM Object Engine 648 649 #define RMCFG_MODULE_PGISLAND 1 // Power Gating Island (PGISLAND) 650 #define RMCFG_MODULE_AP 1 // Adaptive Power Object (AP) Engine 651 #define RMCFG_MODULE_PSI 1 // Phase State Indicator Engine. HW folks calls it as Power Saving Interface. 652 #define RMCFG_MODULE_CG 1 // Clock Gating Object Engine. 653 #define RMCFG_MODULE_RPPG 1 // RAM Periphery Power Gating Object Engine. 654 #define RMCFG_MODULE_EI 1 // Engine Idle Framework Object Engine. 655 #define RMCFG_MODULE_LPWR_SEQ 1 // LPWR Unified Sequencer Feature for Power Gating 656 #define RMCFG_MODULE_DPU 0 // Display Falcon 657 #define RMCFG_MODULE_PMGR 0 // PCB Manager engine 658 #define RMCFG_MODULE_KERNEL_PMGR 1 // Kernel controls for Pmgr 659 #define RMCFG_MODULE_SYS 1 // System 660 #define RMCFG_MODULE_OS 1 // OS Layer 661 #define RMCFG_MODULE_GPUMGR 1 // GPU Manager object 662 #define RMCFG_MODULE_HEAP 1 // Heap Engine Object 663 #define RMCFG_MODULE_BRIGHTC 1 // Backlight brightness control module 664 #define RMCFG_MODULE_GSYNCMGR 0 // GSYNC Manager 665 #define RMCFG_MODULE_OD 0 // Display component: Output Device 666 #define RMCFG_MODULE_DFP 0 // Display component: Display Flat Panel 667 #define RMCFG_MODULE_CRT 0 // Display component: Cathode ray tube 668 #define RMCFG_MODULE_DisplayPort 0 // Display component: DisplayPort 669 #define RMCFG_MODULE_DISPLAYPORT 0 // aka DisplayPort 670 #define RMCFG_MODULE_TMDS 0 // Display component: Transition Minimized Differential Signaling 671 #define RMCFG_MODULE_CL 1 // Core Logic 672 #define RMCFG_MODULE_RCDB 1 // RC Journal log DB 673 #define RMCFG_MODULE_GPUACCT 1 // GPU Accounting 674 #define RMCFG_MODULE_GRDBG 0 // Debugger Engine Object 675 #define RMCFG_MODULE_PSR 0 // Panel Self Refresh 676 #define RMCFG_MODULE_UVM 1 // Unified Virtual Memory - provides interface to separate UVM and verification support 677 #define RMCFG_MODULE_VGPUMGR 0 // Virtual GPU management 678 #define RMCFG_MODULE_KERNEL_VGPUMGR 1 // Virtual GPU management on Kernel(CPU) RM 679 #define RMCFG_MODULE_SEC2 0 // New secure falcon 680 #define RMCFG_MODULE_KERNEL_SEC2 1 // SEC2 on Kernel(CPU) RM. Used for booting Falcon cores. 681 #define RMCFG_MODULE_PMS 0 // PMU ModeSet object 682 #define RMCFG_MODULE_GCX 0 // Idle power states of GPU 683 #define RMCFG_MODULE_LSFM 0 // Light Secure Falcon Manager object 684 #define RMCFG_MODULE_ACR 0 // Programs MMU to protect the region 685 #define RMCFG_MODULE_REFCNT 1 // Reference Counting 686 #define RMCFG_MODULE_GPULOG 0 // Logger for logging GPU related data 687 #define RMCFG_MODULE_FECS 0 // Front-end context switch 688 #define RMCFG_MODULE_HYPERVISOR 1 // Hypervisor object to support its native API 689 #define RMCFG_MODULE_VRRMGR 0 // VRR Management object 690 #define RMCFG_MODULE_GPCCS 0 // GPC context switch 691 #define RMCFG_MODULE_MISSING 0 // MISSING (placeholder) Engine 692 #define RMCFG_MODULE_VMM 1 // virtual memory manager 693 #define RMCFG_MODULE_VASPACE 1 // virtual address space 694 #define RMCFG_MODULE_GVASPACE 1 // GPU virtual address space 695 #define RMCFG_MODULE_AVASPACE 0 // AMODEL virtual address space 696 #define RMCFG_MODULE_IOVASPACE 1 // IOMMU virtual address space 697 #define RMCFG_MODULE_FABRICVASPACE 1 // FABRIC virtual address space 698 #define RMCFG_MODULE_MMU 1 // Memory Management Unit- HW interface 699 #define RMCFG_MODULE_GMMU 0 // GPU Memory Management Unit 700 #define RMCFG_MODULE_KERNEL_GMMU 1 // GPU Memory Management Unit on Kernel(CPU) RM 701 #define RMCFG_MODULE_VMMU 0 // Virtual Memory Management Unit (for vGPU) 702 #define RMCFG_MODULE_GPUGRP 1 // Group of GPU(s) that may or may not be in SLI 703 #define RMCFG_MODULE_KERNEL_HWPM 1 // Hardware Performance Monitor on Kernel(CPU) RM 704 #define RMCFG_MODULE_HWPM 0 // Hardware Performance Monitor 705 #define RMCFG_MODULE_NVLINK 0 // NVLINK High-speed GPU interconnect 706 #define RMCFG_MODULE_KERNEL_NVLINK 1 // Nvlink on Kernel(CPU) RM 707 #define RMCFG_MODULE_IOCTRL 0 // NVLINK Ioctrl 708 #define RMCFG_MODULE_HSHUB 0 // High Speed Hub 709 #define RMCFG_MODULE_HSHUBMANAGER 0 // High Speed Hub Manager 710 #define RMCFG_MODULE_KERNEL_HSHUB 1 // High Speed Hub on Kernel(CPU) RM 711 #define RMCFG_MODULE_GPUMON 1 // GPU Monitoring 712 #define RMCFG_MODULE_GPUBOOSTMGR 1 // Sync Gpu Boost Manager 713 #define RMCFG_MODULE_GRIDDISPLAYLESS 0 // GRID Displayless 714 #define RMCFG_MODULE_WINDOW 0 // NvDisplay WINDOW channel 715 #define RMCFG_MODULE_RPC 1 // RPC Engine for VGPU 716 #define RMCFG_MODULE_RPCSTRUCTURECOPY 1 // RPC structure copying for VGPU 717 #define RMCFG_MODULE_NVJPG 0 // Video JPEG (NVJPG) Engine 718 #define RMCFG_MODULE_KERNEL_NVJPG 1 719 #define RMCFG_MODULE_KERNEL_FSP 1 // FSP on Kernel(CPU) RM 720 #define RMCFG_MODULE_GSP 0 // GPU system processor 721 #define RMCFG_MODULE_KERNEL_GSP 1 // GSP on Kernel(CPU) RM. Used for booting RM on GSP. 722 #define RMCFG_MODULE_OFA 0 // Optical Flow Accelarator 723 #define RMCFG_MODULE_KERNEL_OFA 1 724 #define RMCFG_MODULE_HOT_PLUG 0 // Display component: hot plug 725 #define RMCFG_MODULE_FABRIC 1 // NVLink Fabric 726 #define RMCFG_MODULE_GPUDB 1 // GPU DATABASE 727 #define RMCFG_MODULE_NNE 0 // Neural Net Engine (NNE) 728 #define RMCFG_MODULE_DCECLIENTRM 0 // DCE Client RM 729 #define RMCFG_MODULE_DCB 0 // Display Control Block for all display related data in VBIOS/DCB Image 730 #define RMCFG_MODULE_DISPMACRO 0 // DispMacro RM infrastructure for IED removal from VBIOS 731 #define RMCFG_MODULE_CONF_COMPUTE 1 // Confidential Compute 732 #define RMCFG_MODULE_DISP_MGR 0 // Lid- and dock-related disp code for NOTEBOOK 733 #define RMCFG_MODULE_PLATFORM 1 // Object for platform related features 734 #define RMCFG_MODULE_KERNEL_CCU 1 // Counter Collection Unit Kernel(CPU) RM 735 #define RMCFG_MODULE_SPDM 1 // Secure Protocol and Data Management (SPDM) on Kernel(CPU) RM 736 737 738 739 // 740 // API's - enabled or disabled 741 // 742 #define RMCFG_API_NV04_ALLOC 1 743 #define RMCFG_API_NVOS21_PARAMETERS 1 // aka NV04_ALLOC 744 #define RMCFG_API_NV_ESC_RM_ALLOC 1 // aka NV04_ALLOC 745 #define RMCFG_API_Nv04Alloc 1 // aka NV04_ALLOC 746 #define RMCFG_API_NvRmAlloc 1 // aka NV04_ALLOC 747 #define RMCFG_API_NV04_ALLOC_WITH_ACCESS 1 748 #define RMCFG_API_NVOS64_PARAMETERS 1 // aka NV04_ALLOC_WITH_ACCESS 749 #define RMCFG_API_NV_ESC_RM_ALLOC 1 // aka NV04_ALLOC_WITH_ACCESS 750 #define RMCFG_API_Nv04AllocWithAccess 1 // aka NV04_ALLOC_WITH_ACCESS 751 #define RMCFG_API_NvRmAllocWithAccess 1 // aka NV04_ALLOC_WITH_ACCESS 752 #define RMCFG_API_NV01_ALLOC_MEMORY 1 753 #define RMCFG_API_NVOS02_PARAMETERS 1 // aka NV01_ALLOC_MEMORY 754 #define RMCFG_API_NV_ESC_RM_ALLOC_MEMORY 1 // aka NV01_ALLOC_MEMORY 755 #define RMCFG_API_Nv01AllocMemory 1 // aka NV01_ALLOC_MEMORY 756 #define RMCFG_API_NvRmAllocMemory64 1 // aka NV01_ALLOC_MEMORY 757 #define RMCFG_API_NV01_ALLOC_OBJECT 1 758 #define RMCFG_API_NVOS05_PARAMETERS 1 // aka NV01_ALLOC_OBJECT 759 #define RMCFG_API_NV_ESC_RM_ALLOC_OBJECT 1 // aka NV01_ALLOC_OBJECT 760 #define RMCFG_API_Nv01AllocObject 1 // aka NV01_ALLOC_OBJECT 761 #define RMCFG_API_NvRmAllocObject 1 // aka NV01_ALLOC_OBJECT 762 #define RMCFG_API_NV01_FREE 1 763 #define RMCFG_API_NVOS00_PARAMETERS 1 // aka NV01_FREE 764 #define RMCFG_API_NV_ESC_RM_FREE 1 // aka NV01_FREE 765 #define RMCFG_API_Nv01Free 1 // aka NV01_FREE 766 #define RMCFG_API_NvRmFree 1 // aka NV01_FREE 767 #define RMCFG_API_NV04_VID_HEAP_CONTROL 1 768 #define RMCFG_API_NVOS32_PARAMETERS 1 // aka NV04_VID_HEAP_CONTROL 769 #define RMCFG_API_NV_ESC_RM_VID_HEAP_CONTROL 1 // aka NV04_VID_HEAP_CONTROL 770 #define RMCFG_API_Nv04VidHeapControl 1 // aka NV04_VID_HEAP_CONTROL 771 #define RMCFG_API_NvRmVidHeapControl 1 // aka NV04_VID_HEAP_CONTROL 772 #define RMCFG_API_NV01_CONFIG_GET 0 773 #define RMCFG_API_NVOS13_PARAMETERS 0 // aka NV01_CONFIG_GET 774 #define RMCFG_API_NV_ESC_RM_CONFIG_GET 0 // aka NV01_CONFIG_GET 775 #define RMCFG_API_Nv01ConfigGet 0 // aka NV01_CONFIG_GET 776 #define RMCFG_API_NvRmConfigGet 0 // aka NV01_CONFIG_GET 777 #define RMCFG_API_NV01_CONFIG_SET 0 778 #define RMCFG_API_NVOS14_PARAMETERS 0 // aka NV01_CONFIG_SET 779 #define RMCFG_API_NV_ESC_RM_CONFIG_SET 0 // aka NV01_CONFIG_SET 780 #define RMCFG_API_Nv01ConfigSet 0 // aka NV01_CONFIG_SET 781 #define RMCFG_API_NvRmConfigSet 0 // aka NV01_CONFIG_SET 782 #define RMCFG_API_NV04_CONFIG_GET_EX 0 783 #define RMCFG_API_NVOS_CONFIG_GET_EX_PARAMS 0 // aka NV04_CONFIG_GET_EX 784 #define RMCFG_API_NV_ESC_RM_CONFIG_GET_EX 0 // aka NV04_CONFIG_GET_EX 785 #define RMCFG_API_Nv04ConfigGetEx 0 // aka NV04_CONFIG_GET_EX 786 #define RMCFG_API_NvRmConfigGetEx 0 // aka NV04_CONFIG_GET_EX 787 #define RMCFG_API_NV04_CONFIG_SET_EX 0 788 #define RMCFG_API_NVOS_CONFIG_SET_EX_PARAMS 0 // aka NV04_CONFIG_SET_EX 789 #define RMCFG_API_NV_ESC_RM_CONFIG_SET_EX 0 // aka NV04_CONFIG_SET_EX 790 #define RMCFG_API_Nv04ConfigSetEx 0 // aka NV04_CONFIG_SET_EX 791 #define RMCFG_API_NvRmConfigSetEx 0 // aka NV04_CONFIG_SET_EX 792 #define RMCFG_API_NV04_I2C_ACCESS 1 793 #define RMCFG_API_NVOS_I2C_ACCESS_PARAMS 1 // aka NV04_I2C_ACCESS 794 #define RMCFG_API_NV_ESC_RM_I2C_ACCESS 1 // aka NV04_I2C_ACCESS 795 #define RMCFG_API_Nv04I2CAccess 1 // aka NV04_I2C_ACCESS 796 #define RMCFG_API_NvRmI2CAccess 1 // aka NV04_I2C_ACCESS 797 #define RMCFG_API_NV04_IDLE_CHANNELS 1 798 #define RMCFG_API_NVOS30_PARAMETERS 1 // aka NV04_IDLE_CHANNELS 799 #define RMCFG_API_NV_ESC_RM_IDLE_CHANNELS 1 // aka NV04_IDLE_CHANNELS 800 #define RMCFG_API_Nv04IdleChannels 1 // aka NV04_IDLE_CHANNELS 801 #define RMCFG_API_NvRmIdleChannels 1 // aka NV04_IDLE_CHANNELS 802 #define RMCFG_API_NV04_MAP_MEMORY 1 803 #define RMCFG_API_NVOS33_PARAMETERS 1 // aka NV04_MAP_MEMORY 804 #define RMCFG_API_NV_ESC_RM_MAP_MEMORY 1 // aka NV04_MAP_MEMORY 805 #define RMCFG_API_Nv04MapMemory 1 // aka NV04_MAP_MEMORY 806 #define RMCFG_API_NvRmMapMemory 1 // aka NV04_MAP_MEMORY 807 #define RMCFG_API_NV04_UNMAP_MEMORY 1 808 #define RMCFG_API_NVOS34_PARAMETERS 1 // aka NV04_UNMAP_MEMORY 809 #define RMCFG_API_NV_ESC_RM_UNMAP_MEMORY 1 // aka NV04_UNMAP_MEMORY 810 #define RMCFG_API_Nv04UnmapMemory 1 // aka NV04_UNMAP_MEMORY 811 #define RMCFG_API_NvRmUnmapMemory 1 // aka NV04_UNMAP_MEMORY 812 #define RMCFG_API_NV04_MAP_MEMORY_DMA 1 813 #define RMCFG_API_NVOS46_PARAMETERS 1 // aka NV04_MAP_MEMORY_DMA 814 #define RMCFG_API_NV_ESC_RM_MAP_MEMORY_DMA 1 // aka NV04_MAP_MEMORY_DMA 815 #define RMCFG_API_Nv04MapMemoryDma 1 // aka NV04_MAP_MEMORY_DMA 816 #define RMCFG_API_NvRmMapMemoryDma 1 // aka NV04_MAP_MEMORY_DMA 817 #define RMCFG_API_NV04_UNMAP_MEMORY_DMA 1 818 #define RMCFG_API_NVOS47_PARAMETERS 1 // aka NV04_UNMAP_MEMORY_DMA 819 #define RMCFG_API_NV_ESC_RM_UNMAP_MEMORY_DMA 1 // aka NV04_UNMAP_MEMORY_DMA 820 #define RMCFG_API_Nv04UnmapMemoryDma 1 // aka NV04_UNMAP_MEMORY_DMA 821 #define RMCFG_API_NvRmUnmapMemoryDma 1 // aka NV04_UNMAP_MEMORY_DMA 822 #define RMCFG_API_NV04_UNMAP_MEMORY_DMA2 1 823 #define RMCFG_API_NVOS47_PARAMETERS 1 // aka NV04_UNMAP_MEMORY_DMA2 824 #define RMCFG_API_NV_ESC_RM_UNMAP_MEMORY_DMA 1 // aka NV04_UNMAP_MEMORY_DMA2 825 #define RMCFG_API_Nv04UnmapMemoryDmaPartial 1 // aka NV04_UNMAP_MEMORY_DMA2 826 #define RMCFG_API_NvRmUnmapMemoryDmaPartial 1 // aka NV04_UNMAP_MEMORY_DMA2 827 #define RMCFG_API_NV04_ALLOC_CONTEXT_DMA 1 828 #define RMCFG_API_NVOS39_PARAMETERS 1 // aka NV04_ALLOC_CONTEXT_DMA 829 #define RMCFG_API_NV_ESC_RM_ALLOC_CONTEXT_DMA2 1 // aka NV04_ALLOC_CONTEXT_DMA 830 #define RMCFG_API_Nv04AllocContextDma 1 // aka NV04_ALLOC_CONTEXT_DMA 831 #define RMCFG_API_NvRmAllocContextDma2 1 // aka NV04_ALLOC_CONTEXT_DMA 832 #define RMCFG_API_NV04_BIND_CONTEXT_DMA 1 833 #define RMCFG_API_NVOS49_PARAMETERS 1 // aka NV04_BIND_CONTEXT_DMA 834 #define RMCFG_API_NV_ESC_RM_BIND_CONTEXT_DMA 1 // aka NV04_BIND_CONTEXT_DMA 835 #define RMCFG_API_Nv04BindContextDma 1 // aka NV04_BIND_CONTEXT_DMA 836 #define RMCFG_API_NvRmBindContextDma 1 // aka NV04_BIND_CONTEXT_DMA 837 #define RMCFG_API_NV04_CONTROL 1 838 #define RMCFG_API_NVOS54_PARAMETERS 1 // aka NV04_CONTROL 839 #define RMCFG_API_NV_ESC_RM_CONTROL 1 // aka NV04_CONTROL 840 #define RMCFG_API_Nv04Control 1 // aka NV04_CONTROL 841 #define RMCFG_API_NvRmControl 1 // aka NV04_CONTROL 842 #define RMCFG_API_NV04_DUP_OBJECT 1 843 #define RMCFG_API_NVOS55_PARAMETERS 1 // aka NV04_DUP_OBJECT 844 #define RMCFG_API_NV_ESC_RM_DUP_OBJECT 1 // aka NV04_DUP_OBJECT 845 #define RMCFG_API_Nv04DupObject 1 // aka NV04_DUP_OBJECT 846 #define RMCFG_API_NvRmDupObject 1 // aka NV04_DUP_OBJECT 847 #define RMCFG_API_NV04_DUP_OBJECT2 1 848 #define RMCFG_API_NVOS55_PARAMETERS 1 // aka NV04_DUP_OBJECT2 849 #define RMCFG_API_NV_ESC_RM_DUP_OBJECT 1 // aka NV04_DUP_OBJECT2 850 #define RMCFG_API_Nv04DupObject 1 // aka NV04_DUP_OBJECT2 851 #define RMCFG_API_NvRmDupObject2 1 // aka NV04_DUP_OBJECT2 852 #define RMCFG_API_NV04_SHARE_OBJECT 1 853 #define RMCFG_API_NVOS57_PARAMETERS 1 // aka NV04_SHARE_OBJECT 854 #define RMCFG_API_NV_ESC_RM_SHARE 1 // aka NV04_SHARE_OBJECT 855 #define RMCFG_API_Nv04Share 1 // aka NV04_SHARE_OBJECT 856 #define RMCFG_API_NvRmShare 1 // aka NV04_SHARE_OBJECT 857 #define RMCFG_API_NV04_ADD_VBLANK_CALLBACK 1 858 #define RMCFG_API_NVOS61_PARAMETERS 1 // aka NV04_ADD_VBLANK_CALLBACK 859 #define RMCFG_API_NV_ESC_RM_ADD_VBLANK_CALLBACK 1 // aka NV04_ADD_VBLANK_CALLBACK 860 #define RMCFG_API_Nv04AddVblankCallback 1 // aka NV04_ADD_VBLANK_CALLBACK 861 #define RMCFG_API_NvRmAddVblankCallback 1 // aka NV04_ADD_VBLANK_CALLBACK 862 #define RMCFG_API_NV04_ACCESS_REGISTRY 1 863 #define RMCFG_API_NvRmReadRegistryDword 1 // aka NV04_ACCESS_REGISTRY 864 #define RMCFG_API_NvRmWriteRegistryDword 1 // aka NV04_ACCESS_REGISTRY 865 #define RMCFG_API_NvRmGetNumRegistryEntries 1 // aka NV04_ACCESS_REGISTRY 866 #define RMCFG_API_NvRmDeleteRegistryEntry 1 // aka NV04_ACCESS_REGISTRY 867 #define RMCFG_API_NvRmReadRegistryEntry 1 // aka NV04_ACCESS_REGISTRY 868 #define RMCFG_API_NvRmReadRegistryBinary 1 // aka NV04_ACCESS_REGISTRY 869 #define RMCFG_API_NvRmWriteRegistryBinary 1 // aka NV04_ACCESS_REGISTRY 870 #define RMCFG_API_NVOS38_PARAMETERS 1 // aka NV04_ACCESS_REGISTRY 871 #define RMCFG_API_NV_ESC_RM_ACCESS_REGISTRY 1 // aka NV04_ACCESS_REGISTRY 872 #define RMCFG_API_NV04_GET_EVENT_DATA 1 873 #define RMCFG_API_NVOS41_PARAMETERS 1 // aka NV04_GET_EVENT_DATA 874 #define RMCFG_API_NV_ESC_RM_GET_EVENT_DATA 1 // aka NV04_GET_EVENT_DATA 875 #define RMCFG_API_NvRmGetEventData 1 // aka NV04_GET_EVENT_DATA 876 #define RMCFG_API_NV04_UPDATE_DEVICE_MAPPING_INFO 1 // Update Mapping Parameters (unix-only) 877 #define RMCFG_API_NVOS56_PARAMETERS 1 // aka NV04_UPDATE_DEVICE_MAPPING_INFO 878 #define RMCFG_API_NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO 1 // aka NV04_UPDATE_DEVICE_MAPPING_INFO 879 #define RMCFG_API_NVXX_CARD_INFO 1 880 #define RMCFG_API_nv_ioctl_card_info_t 1 // aka NVXX_CARD_INFO 881 #define RMCFG_API_NV_ESC_CARD_INFO 1 // aka NVXX_CARD_INFO 882 #define RMCFG_API_NVXX_ENV_INFO 1 883 #define RMCFG_API_nv_ioctl_env_info_t 1 // aka NVXX_ENV_INFO 884 #define RMCFG_API_NV_ESC_ENV_INFO 1 // aka NVXX_ENV_INFO 885 #define RMCFG_API_NVXX_ALLOC_OS_EVENT 1 886 #define RMCFG_API_nv_ioctl_alloc_os_event_t 1 // aka NVXX_ALLOC_OS_EVENT 887 #define RMCFG_API_NV_ESC_ALLOC_OS_EVENT 1 // aka NVXX_ALLOC_OS_EVENT 888 #define RMCFG_API_NvRmAllocOsEvent 1 // aka NVXX_ALLOC_OS_EVENT 889 #define RMCFG_API_NVXX_FREE_OS_EVENT 1 890 #define RMCFG_API_nv_ioctl_free_os_event_t 1 // aka NVXX_FREE_OS_EVENT 891 #define RMCFG_API_NV_ESC_FREE_OS_EVENT 1 // aka NVXX_FREE_OS_EVENT 892 #define RMCFG_API_NvRmFreeOsEvent 1 // aka NVXX_FREE_OS_EVENT 893 #define RMCFG_API_NVXX_STATUS_CODE 1 894 #define RMCFG_API_nv_ioctl_status_code_t 1 // aka NVXX_STATUS_CODE 895 #define RMCFG_API_NV_ESC_STATUS_CODE 1 // aka NVXX_STATUS_CODE 896 #define RMCFG_API_NVXX_CHECK_VERSION_STR 1 897 #define RMCFG_API_nv_ioctl_rm_api_version_t 1 // aka NVXX_CHECK_VERSION_STR 898 #define RMCFG_API_NV_ESC_CHECK_VERSION_STR 1 // aka NVXX_CHECK_VERSION_STR 899 #define RMCFG_API_NVXX_ATTACH_GPUS_TO_FD 1 900 #define RMCFG_API_NvU32 1 // aka NVXX_ATTACH_GPUS_TO_FD 901 #define RMCFG_API_NV_ESC_ATTACH_GPUS_TO_FD 1 // aka NVXX_ATTACH_GPUS_TO_FD 902 903 904 905 // Disable misspelling detection 906 #define __RMCFG_vet_enabled 0 907 908 909 910 911 912 913 914 915 // Make sure the specified feature is defined and not a misspelling 916 // by checking the "_def" forms above which are all set to '1' for 917 // each defined chip, feature, etc, irrespective of it's enable/disable 918 // state. 919 #define _RMCFG_vet(x) 0 920 #if __RMCFG_vet_enabled && defined(__GNUC__) // broken on MSVC 921 # undef _RMCFG_vet 922 # define _RMCFG_vet(x) ((__def_RMCFG ## x) ? 0 : (0 * (1/0))) 923 #endif 924 925 // 926 // Compile-time constant macros to help with enabling or disabling code based 927 // on whether a feature (or chip or class or engine or ...) is enabled. 928 // May be used by both C code ('if') and C-preprocessor directives ('#if') 929 // 930 931 #define RMCFG_CHIP_ENABLED(_chip) (RMCFG_CHIP_##_chip + _RMCFG_vet(_CHIP_ ## _chip)) 932 #define RMCFG_FEATURE_ENABLED(_feature) (RMCFG_FEATURE_##_feature + _RMCFG_vet(_FEATURE_ ## _feature)) 933 #define RMCFG_MODULE_ENABLED(_module) (RMCFG_MODULE_##_module + _RMCFG_vet(_MODULE_ ## _module)) 934 #define RMCFG_CLASS_ENABLED(_clss) (RMCFG_CLASS_##_clss + _RMCFG_vet(_CLASS_ ## _clss)) 935 #define RMCFG_API_ENABLED(_api) (RMCFG_API_##_api + _RMCFG_vet(_API_ ## _api)) 936 937 #endif // _RMCFG_H_ 938