1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DAC_P2060_H 25 #define DAC_P2060_H 26 27 /* ------------------------ Includes --------------------------------------- */ 28 #include "gpu/external_device/external_device.h" // DACEXTERNALDEVICE 29 #include "gpu/external_device/gsync.h" // GSYNCVIDEOMODE, GSYNCSYNCPOLARITY 30 #include "gpu/disp/kern_disp_max.h" 31 32 /* ------------------------ Macros & Defines ------------------------------- */ 33 34 // Display synchronization interface. (Framelock, Genlock, Swapready, etc) 35 #define NV_P2060_MAX_ASSOCIATED_GPUS 4 36 #define NV_P2060_MAX_IFACES_PER_GSYNC 4 37 #define NV_P2060_MAX_GPUS_PER_IFACE 1 38 #define NV_P2060_MAX_HEADS_PER_GPU 4 39 #define NV_P2060_MAX_MOSAIC_SLAVES 3 40 #define NV_P2060_MAX_MOSAIC_GROUPS 2 41 42 #define NV_P2060_IFACE_ONE 0 43 #define NV_P2060_IFACE_TWO 1 44 #define NV_P2060_IFACE_THREE 2 45 #define NV_P2060_IFACE_FOUR 3 46 47 #define NV_P2060_SYNC_SKEW_MAX_UNITS_FULL_SUPPORT 65535 // For FPGA with Rev >= 3. Refer Bug 1058215 48 #define NV_P2060_SYNC_SKEW_MAX_UNITS_LIMITED_SUPPORT 1 // For FPGA with Rev < 3. 49 #define NV_P2060_SYNC_SKEW_RESOLUTION 977 50 #define NV_P2060_START_DELAY_MAX_UNITS 65535 51 #define NV_P2060_START_DELAY_RESOLUTION 7800 52 #define NV_P2060_SYNC_INTERVAL_MAX_UNITS 7 53 #define NV_P2061_V204_SYNC_SKEW_RESOLUTION 7 // For 2061 V2.04+ 54 #define NV_P2061_V204_SYNC_SKEW_MAX_UNITS 0xFFFFFF // For 2061 V2.04+ 55 #define NV_P2061_V204_SYNC_SKEW_INVALID (NV_P2061_V204_SYNC_SKEW_MAX_UNITS + 1) 56 57 #define NV_P2060_WATCHDOG_COUNT_DOWN_VALUE 60 // 1 minute, assuming watchdog time interval is 1 second. 58 #define NV_P2060_FRAME_COUNT_TIMER_INTERVAL 5000000000LL // 5 sec 59 60 #define NV_P2060_MAX_GPU_FRAME_COUNT 65535 61 #define NV_P2060_MAX_GSYNC_FRAME_COUNT 16777215 // 2^24.Gsync frame count is a 24 bit register 62 63 #define P2061_FW_REV(pExtDev) ((pExtDev->deviceRev << 8) | (pExtDev->deviceExRev)) 64 /* ------------------------ Types definitions ------------------------------ */ 65 66 typedef struct EXTDEV_I2C_HANDLES 67 { 68 //Internal handles per GPU 69 70 NvHandle hClient; 71 NvHandle hDevice; 72 NvHandle hSubdevice; 73 NvHandle hSubscription; 74 NvU32 gpuId; 75 } EXTDEV_I2C_HANDLES; 76 77 typedef struct 78 { 79 NvU8 lossRegStatus; 80 NvU8 gainRegStatus; 81 NvU8 miscRegStatus; 82 DACEXTERNALDEVICE *pExtDevice; 83 }EXTDEV_INTR_DATA; 84 85 // note: NV_P2060_MAX_ASSOCIATED_GPUS = NV_P2060_MAX_IFACES_PER_GSYNC * NV_P2060_MAX_GPUS_PER_IFACE 86 87 struct DACP2060EXTERNALDEVICE 88 { 89 //Must be at top of struct 90 DACEXTERNALDEVICE ExternalDevice; 91 92 // Stuff for supporting the DisplaySync interface 93 NvU32 AssociatedCRTCs; // bit mask of crtcs ids associated. 94 GSYNCVIDEOMODE VideoMode; 95 GSYNCSYNCPOLARITY SyncPolarity; 96 NvU32 SyncStartDelay; 97 NvU32 SyncSkew; 98 NvU32 NSync; 99 NvU32 HouseSignal; 100 NvU32 UseHouseSync; 101 NvU32 Master; 102 NvU32 Slaves; 103 NvU32 EmitTestSignal; 104 NvU32 InterlaceMode; 105 NvU32 RefreshRate; // desired frame rate (units of .01Hz) 106 NvU32 DebugMask; 107 NvU32 gpuAttachMask; 108 NvU32 id; 109 NvU32 watchdogCountDownValue; 110 NvBool isNonFramelockInterruptEnabled; 111 NvU32 interruptEnabledInterface; 112 NvU32 tSwapRdyHi; /* Value of SWAP_LOCKOUT_START in accordance to the 113 * time in microseconds for which swap Rdy 114 * lines will remain high.(Provided via a regkey) 115 */ 116 NvU32 tSwapRdyHiLsrMinTime; /* Value of LSR_MIN_TIME in accordance to the time (in us) 117 * swap ready line will remain high.(Provided via a regkey) 118 */ 119 NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS mulDivSettings; // Cached multiplier-divider settings 120 121 NvU32 syncSkewResolutionInNs; // resolution in ns 122 NvU32 syncSkewMax; // max syncSkew setting in raw units 123 NvU32 lastUserSkewSent; // Remember the last Sync Skew value sent by the user 124 125 struct { 126 NvU32 currentFrameCount; // gpu frame count register value for current user query 127 NvU32 previousFrameCount; // gpu frame count register value for previous user query 128 NvU32 totalFrameCount; // equals to cached gsync frame count = gpu frame count + difference. 129 NvU32 numberOfRollbacks; // Max value of N where (Gsync Frame Count > N * Gpu frame count) 130 NvU32 frameTime; // Time to render one frame. 131 NvU64 lastFrameCounterQueryTime; 132 NvS32 initialDifference; // Difference between Gsync frame count and (numberOfRollbacks * Gpu framecount) 133 NvU32 iface; 134 NvU32 head; 135 NvU32 vActive; // Vertical Resolution for which system is framelocked. 136 NvBool bReCheck; // Enabled to verify initialDifference 1 sec after initialization. 137 NvBool enableFrmCmpMatchIntSlave; // Enable the frmCmpMatchInt for slave, if this bit is set. 138 NvBool isFrmCmpMatchIntMasterEnabled; // To enable frmCmpMatchInt for master when gsync framecount exceeds (2^24 - 1000) 139 } FrameCountData; 140 141 struct { 142 NvU32 Status1; 143 NvU64 lastSyncCheckTime; 144 NvU64 lastStereoToggleTime; 145 } Snapshot[NV_P2060_MAX_IFACES_PER_GSYNC]; 146 147 // These arrays refer to the state of heads with respect to their sync 148 // source, and their usage can be kind of confusing. This table 149 // describes how they should be set/used: 150 // 151 // Head[i] --> Is Head[i] the frame lock master, or a slave 152 // SyncSrc --> Where is the sync timing actually coming from (the 153 // master head or a house sync signal) 154 155 // 156 // Head[i] SyncSrc PM[i] PS[i] PSLS[i] 157 // -----------------------------------------+--------------------- 158 // Master Head[i] 1 0 0 159 // Master House 1 1 0 160 // Slave Head[!i] 0 0 1 161 // Slave House 0 1 0 162 // Slave External 0 1 0 163 // Neither X 0 0 0 164 // 165 // (the last row represents the case where the head has not been 166 // requested to lock). 167 168 struct { 169 struct { 170 NvU32 Master [OBJ_MAX_HEADS]; 171 NvU32 Slaved [OBJ_MAX_HEADS]; 172 NvU32 LocalSlave[OBJ_MAX_HEADS]; 173 } Sync; 174 175 struct { 176 NvU32 gpuId; 177 NvBool connected; 178 } GpuInfo; 179 180 struct { 181 NvU32 OrigLsrMinTime[OBJ_MAX_HEADS]; 182 NvBool saved; 183 } DsiFliplock; 184 185 struct { 186 NvU32 direction; 187 NvU32 mode; 188 NvBool saved; 189 } RasterSyncGpio; 190 191 NvBool SwapReadyRequested; 192 NvBool skipSwapBarrierWar; 193 194 NvU32 lastEventNotified; 195 NvU32 gainedSync; // Set when we gain sync after enabling framelock. 196 197 } Iface[NV_P2060_MAX_IFACES_PER_GSYNC]; 198 199 EXTDEV_I2C_HANDLES i2cHandles[NV_P2060_MAX_IFACES_PER_GSYNC]; 200 201 struct { 202 NvU32 gpuTimingSource; 203 NvU32 gpuTimingSlaves[NV_P2060_MAX_MOSAIC_SLAVES]; 204 NvU32 slaveGpuCount; 205 NvBool enabledMosaic; 206 } MosaicGroup[NV_P2060_MAX_MOSAIC_GROUPS]; 207 }; 208 209 PDACEXTERNALDEVICE extdevConstruct_P2060 (OBJGPU *, PDACEXTERNALDEVICE); 210 NvBool gsyncAttachExternalDevice_P2060 (OBJGPU *, PDACEXTERNALDEVICE*); 211 void extdevDestroy_P2060 (OBJGPU *, PDACEXTERNALDEVICE); 212 NvBool extdevGetDevice_P2060 (OBJGPU *, PDACEXTERNALDEVICE); 213 NvBool extdevInit_P2060 (OBJGPU *, PDACEXTERNALDEVICE); 214 void extdevDestroy_P2060 (OBJGPU *, PDACEXTERNALDEVICE); 215 void extdevService_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8, NvU8, NvBool); 216 NV_STATUS extdevWatchdog_P2060 (OBJGPU *, OBJTMR *, PDACEXTERNALDEVICE); // OBJTMR routine signature (TIMERPROC). 217 NvBool extdevSaveI2cHandles_P2060 (OBJGPU *, DACEXTERNALDEVICE *); 218 NV_STATUS gsyncFindGpuHandleLocation (DACEXTERNALDEVICE *, NvU32 , NvU32 *); 219 220 // P2060 hal ifaces 221 222 NvBool gsyncGpuCanBeMaster_P2060 (OBJGPU *, PDACEXTERNALDEVICE); 223 NV_STATUS gsyncGetSyncPolarity_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSYNCPOLARITY *); 224 NV_STATUS gsyncSetSyncPolarity_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSYNCPOLARITY); 225 NV_STATUS gsyncGetVideoMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCVIDEOMODE *); 226 NV_STATUS gsyncSetVideoMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCVIDEOMODE); 227 NV_STATUS gsyncGetNSync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); 228 NV_STATUS gsyncSetNSync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 229 NV_STATUS gsyncGetSyncSkew_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); 230 NV_STATUS gsyncSetSyncSkew_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 231 NV_STATUS gsyncGetUseHouse_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); 232 NV_STATUS gsyncSetUseHouse_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 233 NV_STATUS gsyncGetSyncStartDelay_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); 234 NV_STATUS gsyncSetSyncStartDelay_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 235 NV_STATUS gsyncRefSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, GSYNCSYNCSIGNAL, NvBool bRate, NvU32 *); 236 NV_STATUS gsyncRefMaster_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask, NvU32 *Refresh, NvBool retainMaster, NvBool skipSwapBarrierWar); 237 NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh); 238 NV_STATUS gsyncGetCplStatus_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *); 239 NV_STATUS gsyncGetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); 240 NV_STATUS gsyncSetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 241 NV_STATUS gsyncGetInterlaceMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); 242 NV_STATUS gsyncSetInterlaceMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 243 NV_STATUS gsyncRefSwapBarrier_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvBool *); 244 NV_STATUS gsyncGetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); 245 NV_STATUS gsyncSetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 246 NV_STATUS gsyncGetRevision_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCCAPSPARAMS *); 247 NV_STATUS gsyncOptimizeTimingParameters_P2060(OBJGPU *, GSYNCTIMINGPARAMS *); 248 NV_STATUS gsyncGetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); 249 NV_STATUS gsyncSetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 250 NV_STATUS gsyncSetMosaic_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *); 251 NV_STATUS gsyncConfigFlashGsync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); 252 NV_STATUS gsyncGetMulDiv_P2060 (OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); 253 NV_STATUS gsyncSetMulDiv_P2060 (OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); 254 NvBool gsyncSupportsLargeSyncSkew_P2060 (DACEXTERNALDEVICE *); 255 256 #endif 257