1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _GPU_ENGINE_TYPE_H_ 25 #define _GPU_ENGINE_TYPE_H_ 26 27 #include "class/cl2080.h" 28 #include "nvrangetypes.h" 29 #include "utils/nvbitvector.h" 30 #include "rmconfig.h" 31 32 typedef enum 33 { 34 RM_ENGINE_TYPE_NULL = (0x00000000), 35 RM_ENGINE_TYPE_GR0 = (0x00000001), 36 RM_ENGINE_TYPE_GR1 = (0x00000002), 37 RM_ENGINE_TYPE_GR2 = (0x00000003), 38 RM_ENGINE_TYPE_GR3 = (0x00000004), 39 RM_ENGINE_TYPE_GR4 = (0x00000005), 40 RM_ENGINE_TYPE_GR5 = (0x00000006), 41 RM_ENGINE_TYPE_GR6 = (0x00000007), 42 RM_ENGINE_TYPE_GR7 = (0x00000008), 43 RM_ENGINE_TYPE_COPY0 = (0x00000009), 44 RM_ENGINE_TYPE_COPY1 = (0x0000000a), 45 RM_ENGINE_TYPE_COPY2 = (0x0000000b), 46 RM_ENGINE_TYPE_COPY3 = (0x0000000c), 47 RM_ENGINE_TYPE_COPY4 = (0x0000000d), 48 RM_ENGINE_TYPE_COPY5 = (0x0000000e), 49 RM_ENGINE_TYPE_COPY6 = (0x0000000f), 50 RM_ENGINE_TYPE_COPY7 = (0x00000010), 51 RM_ENGINE_TYPE_COPY8 = (0x00000011), 52 RM_ENGINE_TYPE_COPY9 = (0x00000012), 53 RM_ENGINE_TYPE_RESERVED13 = (0x00000013), 54 RM_ENGINE_TYPE_RESERVED14 = (0x00000014), 55 RM_ENGINE_TYPE_RESERVED15 = (0x00000015), 56 RM_ENGINE_TYPE_RESERVED16 = (0x00000016), 57 RM_ENGINE_TYPE_RESERVED17 = (0x00000017), 58 RM_ENGINE_TYPE_RESERVED18 = (0x00000018), 59 RM_ENGINE_TYPE_RESERVED19 = (0x00000019), 60 RM_ENGINE_TYPE_RESERVED1a = (0x0000001a), 61 RM_ENGINE_TYPE_RESERVED1b = (0x0000001b), 62 RM_ENGINE_TYPE_RESERVED1c = (0x0000001c), 63 RM_ENGINE_TYPE_NVDEC0 = (0x0000001d), 64 RM_ENGINE_TYPE_NVDEC1 = (0x0000001e), 65 RM_ENGINE_TYPE_NVDEC2 = (0x0000001f), 66 RM_ENGINE_TYPE_NVDEC3 = (0x00000020), 67 RM_ENGINE_TYPE_NVDEC4 = (0x00000021), 68 RM_ENGINE_TYPE_NVDEC5 = (0x00000022), 69 RM_ENGINE_TYPE_NVDEC6 = (0x00000023), 70 RM_ENGINE_TYPE_NVDEC7 = (0x00000024), 71 RM_ENGINE_TYPE_NVENC0 = (0x00000025), 72 RM_ENGINE_TYPE_NVENC1 = (0x00000026), 73 RM_ENGINE_TYPE_NVENC2 = (0x00000027), 74 RM_ENGINE_TYPE_VP = (0x00000028), 75 RM_ENGINE_TYPE_ME = (0x00000029), 76 RM_ENGINE_TYPE_PPP = (0x0000002a), 77 RM_ENGINE_TYPE_MPEG = (0x0000002b), 78 RM_ENGINE_TYPE_SW = (0x0000002c), 79 RM_ENGINE_TYPE_TSEC = (0x0000002d), 80 RM_ENGINE_TYPE_VIC = (0x0000002e), 81 RM_ENGINE_TYPE_MP = (0x0000002f), 82 RM_ENGINE_TYPE_SEC2 = (0x00000030), 83 RM_ENGINE_TYPE_HOST = (0x00000031), 84 RM_ENGINE_TYPE_DPU = (0x00000032), 85 RM_ENGINE_TYPE_PMU = (0x00000033), 86 RM_ENGINE_TYPE_FBFLCN = (0x00000034), 87 RM_ENGINE_TYPE_NVJPEG0 = (0x00000035), 88 RM_ENGINE_TYPE_NVJPEG1 = (0x00000036), 89 RM_ENGINE_TYPE_NVJPEG2 = (0x00000037), 90 RM_ENGINE_TYPE_NVJPEG3 = (0x00000038), 91 RM_ENGINE_TYPE_NVJPEG4 = (0x00000039), 92 RM_ENGINE_TYPE_NVJPEG5 = (0x0000003a), 93 RM_ENGINE_TYPE_NVJPEG6 = (0x0000003b), 94 RM_ENGINE_TYPE_NVJPEG7 = (0x0000003c), 95 RM_ENGINE_TYPE_OFA0 = (0x0000003d), 96 RM_ENGINE_TYPE_RESERVED3e = (0x0000003e), 97 RM_ENGINE_TYPE_LAST = (0x0000003f), 98 } RM_ENGINE_TYPE; 99 100 // 101 // The duplicates in the RM_ENGINE_TYPE. Using define instead of putting them 102 // in the enum to make sure that each item in the enum has a unique number. 103 // 104 #define RM_ENGINE_TYPE_GRAPHICS RM_ENGINE_TYPE_GR0 105 #define RM_ENGINE_TYPE_BSP RM_ENGINE_TYPE_NVDEC0 106 #define RM_ENGINE_TYPE_MSENC RM_ENGINE_TYPE_NVENC0 107 #define RM_ENGINE_TYPE_CIPHER RM_ENGINE_TYPE_TSEC 108 #define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0 109 110 #define RM_ENGINE_TYPE_COPY_SIZE 10 111 #define RM_ENGINE_TYPE_NVENC_SIZE 3 112 #define RM_ENGINE_TYPE_NVJPEG_SIZE 8 113 #define RM_ENGINE_TYPE_NVDEC_SIZE 8 114 #define RM_ENGINE_TYPE_OFA_SIZE 1 115 #define RM_ENGINE_TYPE_GR_SIZE 8 116 117 // Indexed engines 118 #define RM_ENGINE_TYPE_COPY(i) (RM_ENGINE_TYPE_COPY0+(i)) 119 #define RM_ENGINE_TYPE_IS_COPY(i) (((i) >= RM_ENGINE_TYPE_COPY0) && ((i) < RM_ENGINE_TYPE_COPY(RM_ENGINE_TYPE_COPY_SIZE))) 120 #define RM_ENGINE_TYPE_COPY_IDX(i) ((i) - RM_ENGINE_TYPE_COPY0) 121 122 #define RM_ENGINE_TYPE_NVENC(i) (RM_ENGINE_TYPE_NVENC0+(i)) 123 #define RM_ENGINE_TYPE_IS_NVENC(i) (((i) >= RM_ENGINE_TYPE_NVENC0) && ((i) < RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE))) 124 #define RM_ENGINE_TYPE_NVENC_IDX(i) ((i) - RM_ENGINE_TYPE_NVENC0) 125 126 #define RM_ENGINE_TYPE_NVDEC(i) (RM_ENGINE_TYPE_NVDEC0+(i)) 127 #define RM_ENGINE_TYPE_IS_NVDEC(i) (((i) >= RM_ENGINE_TYPE_NVDEC0) && ((i) < RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE))) 128 #define RM_ENGINE_TYPE_NVDEC_IDX(i) ((i) - RM_ENGINE_TYPE_NVDEC0) 129 130 #define RM_ENGINE_TYPE_NVJPEG(i) (RM_ENGINE_TYPE_NVJPEG0+(i)) 131 #define RM_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= RM_ENGINE_TYPE_NVJPEG0) && ((i) < RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE))) 132 #define RM_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - RM_ENGINE_TYPE_NVJPEG0) 133 134 #define RM_ENGINE_TYPE_OFA(i) (RM_ENGINE_TYPE_OFA0+(i)) 135 #define RM_ENGINE_TYPE_IS_OFA(i) (((i) >= RM_ENGINE_TYPE_OFA0) && ((i) < RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE))) 136 #define RM_ENGINE_TYPE_OFA_IDX(i) ((i) - RM_ENGINE_TYPE_OFA0) 137 138 #define RM_ENGINE_TYPE_IS_VIDEO(i) (RM_ENGINE_TYPE_IS_NVENC(i) | \ 139 RM_ENGINE_TYPE_IS_NVDEC(i) | \ 140 RM_ENGINE_TYPE_IS_NVJPEG(i) | \ 141 RM_ENGINE_TYPE_IS_OFA(i)) 142 143 #define RM_ENGINE_TYPE_GR(i) (RM_ENGINE_TYPE_GR0 + (i)) 144 #define RM_ENGINE_TYPE_IS_GR(i) (((i) >= RM_ENGINE_TYPE_GR0) && ((i) < RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE))) 145 #define RM_ENGINE_TYPE_GR_IDX(i) ((i) - RM_ENGINE_TYPE_GR0) 146 147 #define RM_ENGINE_TYPE_IS_VALID(i) (((i) > (RM_ENGINE_TYPE_NULL)) && ((i) < (RM_ENGINE_TYPE_LAST))) 148 149 // Engine Range defines 150 #define RM_ENGINE_RANGE_GR() rangeMake(RM_ENGINE_TYPE_GR(0), RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE - 1)) 151 #define RM_ENGINE_RANGE_COPY() rangeMake(RM_ENGINE_TYPE_COPY(0), RM_ENGINE_TYPE_COPY(RM_ENGINE_TYPE_COPY_SIZE - 1)) 152 #define RM_ENGINE_RANGE_NVDEC() rangeMake(RM_ENGINE_TYPE_NVDEC(0), RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE - 1)) 153 #define RM_ENGINE_RANGE_NVENC() rangeMake(RM_ENGINE_TYPE_NVENC(0), RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE - 1)) 154 #define RM_ENGINE_RANGE_NVJPEG() rangeMake(RM_ENGINE_TYPE_NVJPEG(0), RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE - 1)) 155 #define RM_ENGINE_RANGE_OFA() rangeMake(RM_ENGINE_TYPE_OFA(0), RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE - 1)) 156 157 // Bit Vectors 158 MAKE_BITVECTOR(ENGTYPE_BIT_VECTOR, RM_ENGINE_TYPE_LAST); 159 160 #endif //_GPU_ENGINE_TYPE_H_ 161