1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef GSP_STATIC_CONFIG_H 25 #define GSP_STATIC_CONFIG_H 26 27 // 28 // This header describes the set of static GPU configuration information 29 // that is collected during GSP RM init and made available to the 30 // CPU RM (aka GSP client) via NV_RM_RPC_GET_GSP_STATIC_INFO() call. 31 32 #include "ctrl/ctrl0080/ctrl0080gpu.h" 33 #include "ctrl/ctrl0080/ctrl0080gr.h" 34 #include "ctrl/ctrl2080/ctrl2080bios.h" 35 #include "ctrl/ctrl2080/ctrl2080fb.h" 36 #include "ctrl/ctrl2080/ctrl2080gpu.h" 37 38 #include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE 39 #include "gpu/gpu_acpi_data.h" // ACPI_METHOD_DATA 40 #include "vgpu/rpc_headers.h" // MAX_GPC_COUNT 41 #include "platform/chipset/chipset.h" // BUSINFO 42 #include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX 43 44 // VF related info for GSP-RM 45 typedef struct GSP_VF_INFO 46 { 47 NvU32 totalVFs; 48 NvU32 firstVFOffset; 49 NvU64 FirstVFBar0Address; 50 NvU64 FirstVFBar1Address; 51 NvU64 FirstVFBar2Address; 52 NvBool b64bitBar0; 53 NvBool b64bitBar1; 54 NvBool b64bitBar2; 55 } GSP_VF_INFO; 56 57 typedef struct GspSMInfo_t 58 { 59 NvU32 version; 60 NvU32 regBankCount; 61 NvU32 regBankRegCount; 62 NvU32 maxWarpsPerSM; 63 NvU32 maxThreadsPerWarp; 64 NvU32 geomGsObufEntries; 65 NvU32 geomXbufEntries; 66 NvU32 maxSPPerSM; 67 NvU32 rtCoreCount; 68 } GspSMInfo; 69 70 // Fetched from GSP-RM into CPU-RM 71 typedef struct GspStaticConfigInfo_t 72 { 73 NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 74 NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo; 75 NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS gpcInfo; 76 NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS tpcInfo[MAX_GPC_COUNT]; 77 NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS zcullInfo[MAX_GPC_COUNT]; 78 NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo; 79 NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams; 80 81 NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps; 82 NvU32 sriovMaxGfid; 83 84 NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]; 85 86 GspSMInfo SM_info; 87 88 NvBool poisonFuseEnabled; 89 90 NvU64 fb_length; 91 NvU32 fbio_mask; 92 NvU32 fb_bus_width; 93 NvU32 fb_ram_type; 94 NvU32 fbp_mask; 95 NvU32 l2_cache_size; 96 97 NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; 98 NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; 99 100 NvU8 gpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 101 NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 102 NvU16 gpuNameString_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 103 NvBool bGpuInternalSku; 104 NvBool bIsQuadroGeneric; 105 NvBool bIsQuadroAd; 106 NvBool bIsNvidiaNvs; 107 NvBool bIsVgx; 108 NvBool bGeforceSmb; 109 NvBool bIsTitan; 110 NvBool bIsTesla; 111 NvBool bIsMobile; 112 NvBool bIsGc6Rtd3Allowed; 113 NvBool bIsGcOffRtd3Allowed; 114 NvBool bIsGcoffLegacyAllowed; 115 116 NvU64 bar1PdeBase; 117 NvU64 bar2PdeBase; 118 119 NvBool bVbiosValid; 120 NvU32 vbiosSubVendor; 121 NvU32 vbiosSubDevice; 122 123 NvBool bPageRetirementSupported; 124 125 NvBool bSplitVasBetweenServerClientRm; 126 127 NvBool bClRootportNeedsNosnoopWAR; 128 129 VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads; 130 VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution; 131 NvU64 displaylessMaxPixels; 132 133 // Client handle for internal RMAPI control. 134 NvHandle hInternalClient; 135 136 // Device handle for internal RMAPI control. 137 NvHandle hInternalDevice; 138 139 // Subdevice handle for internal RMAPI control. 140 NvHandle hInternalSubdevice; 141 142 NvBool bSelfHostedMode; 143 NvBool bAtsSupported; 144 145 NvBool bIsGpuUefi; 146 } GspStaticConfigInfo; 147 148 // Pushed from CPU-RM to GSP-RM 149 typedef struct GspSystemInfo 150 { 151 NvU64 gpuPhysAddr; 152 NvU64 gpuPhysFbAddr; 153 NvU64 gpuPhysInstAddr; 154 NvU64 nvDomainBusDeviceFunc; 155 NvU64 simAccessBufPhysAddr; 156 NvU64 notifyOpSharedSurfacePhysAddr; 157 NvU64 pcieAtomicsOpMask; 158 NvU64 consoleMemSize; 159 NvU64 maxUserVa; 160 NvU32 pciConfigMirrorBase; 161 NvU32 pciConfigMirrorSize; 162 NvU8 oorArch; 163 NvU64 clPdbProperties; 164 NvU32 Chipset; 165 NvBool bGpuBehindBridge; 166 NvBool bFlrSupported; 167 NvBool b64bBar0Supported; 168 NvBool bMnocAvailable; 169 NvBool bUpstreamL0sUnsupported; 170 NvBool bUpstreamL1Unsupported; 171 NvBool bUpstreamL1PorSupported; 172 NvBool bUpstreamL1PorMobileOnly; 173 NvBool bSystemHasMux; 174 NvU8 upstreamAddressValid; 175 BUSINFO FHBBusInfo; 176 BUSINFO chipsetIDInfo; 177 ACPI_METHOD_DATA acpiMethodData; 178 NvU32 hypervisorType; 179 NvBool bIsPassthru; 180 NvU64 sysTimerOffsetNs; 181 GSP_VF_INFO gspVFInfo; 182 NvBool isGridBuild; 183 } GspSystemInfo; 184 185 186 #endif /* GSP_STATIC_CONFIG_H */ 187