1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /*! 25 * @file 26 * 27 * Defines for watchdog component of kernel RC. 28 * 29 * Don't include this file directly, use kernel_rc.h. Watchdog will be split 30 * into its own component in future. Keeping defines in a separate file to aid 31 * that transition. See CORERM-2297 32 */ 33 #ifndef KERNEL_RC_WATCHDOG_PRIVATE_H 34 #define KERNEL_RC_WATCHDOG_PRIVATE_H 1 35 36 #include "kernel/gpu/disp/kern_disp_max.h" 37 38 #include "class/cl906f.h" // GF100_CHANNEL_GPFIFO 39 40 #include "nvgputypes.h" 41 #include "nvlimits.h" 42 #include "nvtypes.h" 43 44 45 #define WATCHDOG_RESET_QUEUE_SIZE (4) 46 47 // KernelWatchdog.flags 48 #define WATCHDOG_FLAGS_INITIALIZED NVBIT(0) // Fully initialized and ready 49 #define WATCHDOG_FLAGS_DISABLED NVBIT(1) // Disabled 50 #define WATCHDOG_FLAGS_ALLOC_UNCACHED_PCI NVBIT(2) // Alloc cached / uncached pushbuffer 51 52 /*! Volatile watchdog state that is destroyed when watchdog is shutdown */ 53 typedef struct { 54 NvHandle hClient; 55 NvU32 runlistId; 56 NvU32 flags; 57 NvU32 deviceReset[WATCHDOG_RESET_QUEUE_SIZE]; 58 /*! Read Pointer for fifoWatchDog */ 59 NvU32 deviceResetRd; 60 // RmResetWatchdog 61 NvU32 deviceResetWr; 62 /*! Number of watchdog invocations */ 63 NvU32 count; 64 /*! Countdown for running thwap and stomp tests */ 65 NvU32 channelTestCountdown; 66 /*! Reset value for ChannelTestTimer */ 67 NvU32 channelTestInterval; 68 /*! Masks for RC testing */ 69 NvU32 thwapChannelMask; 70 NvU32 thwapRepeatMask; 71 NvU32 stompChannelMask; 72 NvU32 stompRepeatMask; 73 /*! Mask of allocations to fail for testing RC. See nvcm.h */ 74 NvU32 allocFailMask; 75 /*! Array of NvU32 to hold last vblank counter */ 76 NvU32 oldVblank[OBJ_MAX_HEADS]; 77 /*! Number of times that Vblank has failed to advance */ 78 NvU32 vblankFailureCount[OBJ_MAX_HEADS]; 79 NvNotification *notifiers[NV_MAX_SUBDEVICES]; 80 NvNotification *errorContext; 81 NvNotification *notifierToken; 82 NvBool bHandleValid; 83 } KernelWatchdog; 84 85 86 /*! Persistent watchdog state preserved across watchdog shutdowns */ 87 typedef struct { 88 NvS32 enableRequestsRefCount; 89 NvS32 disableRequestsRefCount; 90 NvS32 softDisableRequestsRefCount; 91 92 /*! How long we wait for the notifier to come back after being run */ 93 NvU32 timeoutSecs; 94 /*! Seconds between when the Watchdog is run */ 95 NvU32 intervalSecs; 96 NvU64 notifyLimitTime; 97 NvU64 nextRunTime; 98 NvU64 resetLimitTime; 99 } KernelWatchdogPersistent; 100 101 102 /*! Watchdog channel info */ 103 typedef struct 104 { 105 Nv906fControl *pControlGPFifo[NV_MAX_SUBDEVICES]; 106 NvU64 pGpuAddr; 107 NvU8 *pCpuAddr; 108 // Class engine ID needed for SetObject on Fermi+ 109 NvU32 classEngineID; 110 NvU32 gpEntry0[2]; 111 NvU32 gpEntry1[2]; 112 NvU32 pbBytes; 113 NvU32 class2dSubch; 114 } KernelWatchdogChannelInfo; 115 116 #endif // ifndef KERNEL_RC_WATCHDOG_PRIVATE_H 117