1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __common_vgpu_mgr_h__ 25 #define __common_vgpu_mgr_h__ 26 27 #include "gpu/gpu.h" 28 #include "gpu/fifo/kernel_fifo.h" 29 #include "ctrl/ctrla081.h" 30 31 #include "containers/list.h" 32 33 #define MAX_VGPU_TYPES_PER_PGPU NVA081_MAX_VGPU_TYPES_PER_PGPU 34 #define VGPU_CONFIG_PARAMS_MAX_LENGTH 1024 35 #define VGPU_STRING_BUFFER_SIZE NVA081_VGPU_STRING_BUFFER_SIZE 36 #define VGPU_UUID_SIZE NVA081_VM_UUID_SIZE 37 #define VGPU_MAX_GFID 64 38 #define VGPU_SIGNATURE_SIZE NVA081_VGPU_SIGNATURE_SIZE 39 #define MAX_VGPU_DEVICES_PER_PGPU NVA081_MAX_VGPU_PER_PGPU 40 41 /* This structure represents the vGPU type's attributes */ 42 typedef struct 43 { 44 NvU32 vgpuTypeId; 45 NvU8 vgpuName[VGPU_STRING_BUFFER_SIZE]; 46 NvU8 vgpuClass[VGPU_STRING_BUFFER_SIZE]; 47 NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH]; 48 NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH]; 49 NvU32 maxInstance; 50 NvU32 numHeads; 51 NvU32 maxResolutionX; 52 NvU32 maxResolutionY; 53 NvU32 maxPixels; 54 NvU32 frlConfig; 55 NvU32 cudaEnabled; 56 NvU32 eccSupported; 57 NvU32 gpuInstanceSize; 58 NvU32 multiVgpuSupported; 59 NvU64 vdevId NV_ALIGN_BYTES(8); 60 NvU64 pdevId NV_ALIGN_BYTES(8); 61 NvU64 profileSize NV_ALIGN_BYTES(8); 62 NvU64 fbLength NV_ALIGN_BYTES(8); 63 NvU64 gspHeapSize NV_ALIGN_BYTES(8); 64 NvU64 fbReservation NV_ALIGN_BYTES(8); 65 NvU64 mappableVideoSize NV_ALIGN_BYTES(8); 66 NvU32 encoderCapacity; 67 NvU64 bar1Length NV_ALIGN_BYTES(8); 68 NvU32 frlEnable; 69 NvU32 gpuDirectSupported; 70 NvU32 nvlinkP2PSupported; 71 NvU32 multiVgpuExclusive; 72 NvU8 vgpuExtraParams[VGPU_CONFIG_PARAMS_MAX_LENGTH]; 73 NvU8 vgpuSignature[VGPU_SIGNATURE_SIZE]; 74 } VGPU_TYPE; 75 76 MAKE_LIST(VGPU_TYPE_LIST, VGPU_TYPE); 77 78 void 79 vgpuMgrFillVgpuType(NVA081_CTRL_VGPU_INFO *pVgpuInfo, VGPU_TYPE *pVgpuTypeNode); 80 81 NV_STATUS 82 vgpuMgrReserveSystemChannelIDs(OBJGPU *pGpu, 83 VGPU_TYPE *vgpuTypeInfo, 84 NvU32 gfid, 85 NvU32 *pChidOffset, 86 NvU32 *pChannelCount, 87 NvHandle hClient, 88 NvU32 numChannels, 89 NvU32 engineFifoListNumEntries, 90 FIFO_ENGINE_LIST *engineFifoList); 91 92 void 93 vgpuMgrFreeSystemChannelIDs(OBJGPU *pGpu, 94 NvU32 gfid, 95 NvU32 *pChidOffset, 96 NvU32 *pChannelCount, 97 NvHandle hClient, 98 NvU32 engineFifoListNumEntries, 99 FIFO_ENGINE_LIST *engineFifoList); 100 101 #endif // __common_vgpu_mgr_h__ 102