1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * @file 26 * @brief CPU module public interface. 27 */ 28 29 #ifndef _NVPORT_H_ 30 #error "This file cannot be included directly. Include nvport.h instead." 31 #endif 32 33 #ifndef _NVPORT_CPU_H_ 34 #define _NVPORT_CPU_H_ 35 /** 36 * @defgroup NVPORT_CPU CPU specifice operations. 37 * 38 * @brief This module contains cpu specific operations. 39 * 40 * @{ 41 */ 42 /** 43 * @brief Initialize global CPU module state. This function is called by 44 * @ref portInitialize. 45 */ 46 void portCpuInitialize(void); 47 48 /** 49 * @brief Clean up global CPU module state. This function is called by 50 * @ref portShutdown 51 */ 52 void portCpuShutdown(void); 53 54 /** 55 * @name Core Functions 56 * @{ 57 */ 58 /** 59 * @brief Read requested MSR 60 * 61 * @param [in] address Address of the MSR 62 * @param [out] *pValue Value of MSR 63 * 64 * @return NV_OK If successful. 65 */ 66 NV_STATUS portReadMsr(NvU32 address, NvU64 *pValue); 67 68 /** 69 * @brief Write value to requested MSR 70 * 71 * @param [in] address Address of the MSR 72 * @param [in] value Value to be written 73 * 74 * @return NV_OK If successful. 75 */ 76 NV_STATUS portWriteMsr(NvU32 address, NvU64 value); 77 78 /// @} End Core functions 79 80 /** 81 * @name Extended Functions 82 * @{ 83 */ 84 /** 85 * @name Intel X86 Structures, unions and enums. 86 * @{ 87 */ 88 89 /** 90 * @brief Structure representing Intel Processor's general 91 * features broken down into individual bit fields. 92 */ 93 typedef struct PORT_CPU_INTEL_X86_FEATURES 94 { 95 /// @{ 96 NvU32 SSE3 : 1; /**< Streaming SIMD Extensions 3.*/ 97 NvU32 PCLMULQDQ : 1; /**< PCLMULQDQ instruction.*/ 98 NvU32 DTES64 : 1; /**< 64-bit DS Area.*/ 99 NvU32 MONITOR : 1; /**< MONITOR/MWAIT.*/ 100 NvU32 DSCPL : 1; /**< CPL Qualified Debug Store.*/ 101 NvU32 VMX : 1; /**< Virtual Machine Extensions.*/ 102 NvU32 SMX : 1; /**< Safer Mode Extensions.*/ 103 NvU32 EIST : 1; /**< Enhanced Intel SpeedStep(R) technology*/ 104 NvU32 TM2 : 1; /**< Thermal Monitor 2.*/ 105 NvU32 SSSE3 : 1; /**< Supplemental Streaming SIMD Extensions 3*/ 106 NvU32 CNXTID : 1; /**< L1 Context ID*/ 107 NvU32 SDBG : 1; /**< IA32_DEBUG_INTERFACE MSR for silicon debug.*/ 108 NvU32 FMA : 1; /**< FMA extensions using YMM state.*/ 109 NvU32 CMPXCHG16B : 1; /**< CMPXCHG8B/CMPXCHG16B Compare and Exchange Bytes*/ 110 NvU32 xTPRUpdateControl : 1; /** supports changing 111 IA32_MISC_ENABLE[bit 23].*/ 112 NvU32 PDCM : 1; /**< Perfmon and Debug Capability: supports the performance 113 and debug feature indication MSR IA32_PERF_CAPABILITIES.*/ 114 NvU32 PCID : 1; /**< Process-context identifiers: Supports PCIDs and that 115 software may set CR4.PCIDE to 1.*/ 116 NvU32 DCA : 1; /**< Supports the ability to prefetch data from a memory mapped 117 device.*/ 118 NvU32 SSE41 : 1; /**< Supports SSE4.1.*/ 119 NvU32 SSE42 : 1; /**< Supports SSE4.2.*/ 120 NvU32 x2APIC : 1; /**< Support x2APIC.*/ 121 NvU32 MOVBE : 1; /**< Supports MOVBE instruction.*/ 122 NvU32 POPCNT : 1; /**< Supports the POPCNT instruction.*/ 123 NvU32 TSCDeadline : 1; /**< The processor's local APIC timer supports 124 one-shot operation using a TSC deadline value.*/ 125 NvU32 AES : 1; /**< Supports the AESNI instruction extensions.*/ 126 NvU32 XSAVE : 1; /**< Supports the XSAVE/XRSTOR processor extended states 127 feature, the XSETBV/XGETBV instructions, and XCR0.*/ 128 NvU32 OSXSAVE : 1; /**< the OS has set CR4.OSXSAVE[bit 18] to enable 129 XSETBV/XGETBV instructions to access XCR0 and to support 130 processor extended state management using 131 XSAVE/XRSTOR.*/ 132 NvU32 AVX : 1; /**< The processor supports the AVX instruction 133 extensions.*/ 134 NvU32 F16C : 1; /**< processor supports 16-bit floating-point conversion 135 instructions.*/ 136 NvU32 RDEND : 1; /**< Processor supports RDRAND instruction.*/ 137 NvU32 FPU : 1; /**< Floating Point Unit On-Chip.*/ 138 NvU32 VME : 1; /**< Virtual 8086 Mode Enhancements.*/ 139 NvU32 DE : 1; /**< Debugging Extensions.*/ 140 NvU32 PSE : 1; /**< Page Size Extension.*/ 141 NvU32 TSC : 1; /**< Time Stamp Counter.*/ 142 NvU32 MSR : 1; /**< Model Specific Registers RDMSR and WRMSR 143 Instructions.*/ 144 NvU32 PAE : 1; /**< Physical Address Extension.*/ 145 NvU32 MCE : 1; /**< Machine Check Exception.*/ 146 NvU32 CX8 : 1; /**< CMPXCHG8B Instruction.*/ 147 NvU32 APIC : 1; /**< APIC On-Chip.*/ 148 NvU32 SEP : 1; /**< SYSENTER and SYSEXIT Instructions.*/ 149 NvU32 MTRR : 1; /**< Memory Type Range Registers.*/ 150 NvU32 PGE : 1; /**< Page Global Bit*/ 151 NvU32 MCA : 1; /**< Machine Check Architecture.*/ 152 NvU32 CMOV : 1; /**< Conditional Move Instructions.*/ 153 NvU32 PAT : 1; /**< Page Attribute Table.*/ 154 NvU32 PSE36 : 1; /**< 36-Bit Page Size Extension.*/ 155 NvU32 PSN : 1; /**< 96-Bit Processor Serial Number.*/ 156 NvU32 CLFSH : 1; /**< CLFLUSH Instruction.*/ 157 NvU32 DEBUGS : 1; /**< Debug Store.*/ 158 NvU32 ACPI : 1; /**< Thermal Monitor and Software Controlled Clock 159 Facilities.*/ 160 NvU32 MMX : 1; /**< Intel MMX Technology.*/ 161 NvU32 FXSR : 1; /**< FXSAVE and FXRSTOR Instructions.*/ 162 NvU32 SSE : 1; /**< SSE Extensions.*/ 163 NvU32 SSE2 : 1; /**< SSE2 extensions.*/ 164 NvU32 SELFS : 1; /**< Self Snoop.*/ 165 NvU32 HTT : 1; /**< Max APIC IDs reserved field is Valid.*/ 166 NvU32 TM : 1; /**< Thermal Monitor.*/ 167 NvU32 PBE : 1; /**< Pending Break Enable.*/ 168 /// @} 169 } PORT_CPU_INTEL_X86_FEATURES; 170 171 /** 172 * @brief Enum representing Intel processor family information. 173 * 174 */ 175 typedef enum PORT_CPU_INTEL_FAMILY 176 { 177 PORT_CPU_INTEL_FAMILY_6 = 6, 178 PORT_CPU_INTEL_FAMILY_7 = 7 179 } PORT_CPU_INTEL_FAMILY; 180 181 /** 182 * @brief Enum representing Intel family 6 processor model information. 183 * 184 */ 185 typedef enum PORT_CPU_INTEL_FAMILY_6_MODEL 186 { 187 PORT_CPU_INTEL_FAMLLY_6_MODEL_SANDYBRIDGE = 42, 188 PORT_CPU_INTEL_FAMLLY_6_MODEL_SANDYBRIDGE_X = 45, 189 PORT_CPU_INTEL_FAMLLY_6_MODEL_IVYBRIDGE = 58, 190 PORT_CPU_INTEL_FAMLLY_6_MODEL_IVYBRIDGE_X = 62, 191 PORT_CPU_INTEL_FAMLLY_6_MODEL_HASWELL = 60, 192 PORT_CPU_INTEL_FAMLLY_6_MODEL_HASWELL_X = 63, 193 PORT_CPU_INTEL_FAMLLY_6_MODEL_HASWELL_ULT = 69, 194 PORT_CPU_INTEL_FAMLLY_6_MODEL_HASWELL_GT3 = 70, 195 PORT_CPU_INTEL_FAMLLY_6_MODEL_BROADWELL = 61, 196 PORT_CPU_INTEL_FAMLLY_6_MODEL_BROADWELL_GT3 = 71, 197 PORT_CPU_INTEL_FAMLLY_6_MODEL_BROADWELL_X = 79, 198 PORT_CPU_INTEL_FAMLLY_6_MODEL_SKYLAKE = 94, 199 PORT_CPU_INTEL_FAMLLY_6_MODEL_SKYLAKE_MOBILE = 78, 200 PORT_CPU_INTEL_FAMLLY_6_MODEL_KABYLAKE = 158, 201 PORT_CPU_INTEL_FAMLLY_6_MODEL_KABYLAKE_MOBILE = 142, 202 PORT_CPU_INTEL_FAMLLY_6_MODEL_SKYLAKE_X = 85, 203 PORT_CPU_INTEL_FAMLLY_6_MODEL_CANNONLAKE_MOBILE = 102, 204 PORT_CPU_INTEL_FAMILY_6_MODEL_COMETLAKE_MOBILE = 166, 205 PORT_CPU_INTEL_FAMILY_6_MODEL_COMETLAKE = 165, 206 PORT_CPU_INTEL_FAMILY_6_MODEL_TIGERLAKE_MOBILE = 140, 207 PORT_CPU_INTEL_FAMILY_6_MODEL_TIGERLAKE = 141, 208 } PORT_CPU_INTEL_FAMILY_6_MODEL; 209 210 /** 211 * @brief Union representing Intel processor family information. 212 * 213 */ 214 typedef union PORT_CPU_INTEL_MODEL 215 { 216 PORT_CPU_INTEL_FAMILY_6_MODEL family6; 217 } PORT_CPU_INTEL_MODEL; 218 219 /** 220 * @brief Enum representing Intel processor type information. 221 * 222 */ 223 typedef enum PORT_CPU_INTEL_PROCESSOR_TYPE 224 { 225 PORT_CPU_INTEL_PROCESSOR_TYPE_ORIGINAL_OEM = 0, 226 PORT_CPU_INTEL_PROCESSOR_TYPE_OVERDRIVE = 1, 227 PORT_CPU_INTEL_PROCESSOR_TYPE_DUAL_PROCESSOR = 2, 228 PORT_CPU_INTEL_PROCESSOR_TYPE_RESERVED = 3 229 } PORT_CPU_INTEL_PROCESSOR_TYPE; 230 231 /** 232 * @brief Structure representing Intel Processor's Threamal & Power Management 233 * features broken down into individual bit fields. 234 */ 235 typedef struct PORT_CPU_INTEL_TPM_FEATURES 236 { 237 /// @{ 238 NvU32 DTS : 1; /**< Digital Temperature Sensor is supported if set.*/ 239 NvU32 IntelTurboBoost : 1; /**< Intel Turbo Boost Technology available.*/ 240 NvU32 ARAT : 1; /**< APIC-Timer-always-running feature is supported 241 if set.*/ 242 NvU32 PLN : 1; /**< Power limit notification controls are supported 243 if set.*/ 244 NvU32 ECMD : 1; /**< Clock modulation duty cycle extension is supported 245 if set.*/ 246 NvU32 PTM : 1; /**< Package thermal management is supported if set.*/ 247 NvU32 HWP : 1; /**< HWP base registers (IA32_PM_ENABLE[bit 0], 248 IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) 249 are supported if set.*/ 250 NvU32 HWPNotification : 1; /**< IA32_HWP_INTERRUPT MSR is supported 251 if set.*/ 252 NvU32 HWPActivityWindow : 1; /**< IA32_HWP_REQUEST[bits 41:32] is 253 supported if set.*/ 254 NvU32 HWPEPP : 1; /**< HWP_Energy_Performance_Preference. 255 IA32_HWP_REQUEST[bits 31:24] is supported if set.*/ 256 NvU32 HWPPLR : 1; /**< HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR 257 is supported if set.*/ 258 NvU32 HDC : 1; /**< HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, 259 IA32_THREAD_STALL MSRs are supported if set.*/ 260 NvU32 IntelTurboBoostMaxTech30 : 1; /**< Intel(R) Turbo Boost Max Technology 261 3.0 available.*/ 262 NvU32 HWPCapabilities : 1; /**< Highest Performance change is supported 263 if set.*/ 264 NvU32 HWPPECI : 1; /**< HWP PECI override is supported if set.*/ 265 NvU32 FLEXHWP : 1; /**< Flexible HWP is supported if set.*/ 266 NvU32 FAM : 1; /**< Fast access mode for the IA32_HWP_REQUEST MSR is 267 supported if set.*/ 268 NvU32 ILPHWPRequest : 1; /**< Ignoring Idle Logical Processor HWP request 269 is supported if set.*/ 270 NvU32 NoOfInterruptThresholdsInDTS : 4; /**< Number of Interrupt Thresholds 271 in Digital Thermal Sensor.*/ 272 NvU32 HCFC : 1; /**< Hardware Coordination Feedback Capability 273 (Presence of IA32_MPERF and IA32_APERF). The capability to 274 provide a measure of delivered processor performance 275 (since last reset of the counters), as a percentage of the 276 expected processor performance when running at the TSC 277 frequency.*/ 278 NvU32 PEBP : 1; /**< The processor supports performance-energy bias 279 preference if CPUID.06H:ECX.SETBH[bit 3] is set and it also 280 implies the presence of a new architectural MSR called 281 IA32_ENERGY_PERF_BIAS (1B0H).*/ 282 /// @} 283 } PORT_CPU_INTEL_TPM_FEATURES; 284 285 /** 286 * @brief Structure representing Intel Processor's Architecture Performance 287 * monitering features broken down into individual bit fields. 288 */ 289 typedef struct PORT_CPU_INTEL_ARCH_PERF_MONITOR 290 { 291 /// @{ 292 NvU32 versionId; /**< Version ID of architectural performance monitoring.*/ 293 NvU32 noOfGPPerfMonitoringCounters; /**< Number of general-purpose 294 performance monitoring counter per 295 logical processor.*/ 296 NvU32 bitWidthOfGPCounters; /** Bit width of general-purpose, performance 297 monitoring counter.*/ 298 NvU32 coreCycleEvent : 1; /**< Core cycle event available if 1.*/ 299 NvU32 instructionRetiredEvent : 1; /**< Instruction retired event 300 available if 1.*/ 301 NvU32 referenceCycelEvent : 1; /**< Reference cycles event available if 1.*/ 302 NvU32 lastLevelCacheRefEvent : 1; /**< Last-level cache reference event 303 available if 1.*/ 304 NvU32 lastLevelCacheMissEvent : 1; /**< Last-level cache misses event not 305 available if 1.*/ 306 NvU32 branchInstructionRetiredEvent : 1; /**< Branch instruction retired 307 event not available if 1.*/ 308 NvU32 branchMispredictRetiredEvent : 1; /**< Branch mispredict retired event 309 not available if 1.*/ 310 NvU32 noOfFixedFuncPerfCounters; /**< Number of fixed-function performance 311 counters (if Version ID > 1).*/ 312 NvU32 bitWidthOfFixedFuncPerfCounters; /**< Bit width of fixed-function 313 performance counters 314 (if Version ID > 1).*/ 315 /// @} 316 } PORT_CPU_INTEL_ARCH_PERF_MONITOR; 317 318 /** 319 * @brief Structure representing Intel Processor version and features 320 * broken down into individual fields. 321 */ 322 typedef struct PORT_CPU_INTEL 323 { 324 /// @{ 325 PORT_CPU_INTEL_FAMILY family; /**< Family of the Processor.*/ 326 PORT_CPU_INTEL_MODEL model; /**< Model of the Processor.*/ 327 PORT_CPU_INTEL_PROCESSOR_TYPE processorType; /**< Processor Type.*/ 328 NvU8 steppingId; /**< Stepping ID of the Processor.*/ 329 NvU8 brandIndex; /**< Numerical Index of Brand String Index Table 330 entry.*/ 331 NvU8 localApicId; /** Local APIC ID of the Processor.*/ 332 NvU32 threadCountPerCore; /**< Threads Per Core.*/ 333 NvU32 physicalCoreCount; /**< Physical Cores Per Package.*/ 334 NvU32 logicalCoreCount; /**< Logical Cores Per Package.*/ 335 PORT_CPU_INTEL_X86_FEATURES features; /**< General Features.*/ 336 PORT_CPU_INTEL_TPM_FEATURES tpmFeatures; /**< Thermal and Power Management 337 Features.*/ 338 PORT_CPU_INTEL_ARCH_PERF_MONITOR archPerfMonitor; /**< Architecture 339 Performance Monitoring 340 Features.*/ 341 /// @} 342 } PORT_CPU_INTEL; 343 344 /// @} 345 346 /** 347 * @name AMD X86 Structures, unions and enums. 348 * @{ 349 */ 350 351 /** 352 * @brief Enum representing AMD processor family information. 353 * 354 */ 355 typedef enum PORT_CPU_AMD_FAMILY 356 { 357 PORT_CPU_AMD_FAMILY_0 = 0, 358 PORT_CPU_AMD_FAMILY_1 = 1, 359 PORT_CPU_AMD_FAMILY_ZEN3 = 25 360 } PORT_CPU_AMD_FAMILY; 361 362 /** 363 * @brief Enum representing AMD processor family 0 model information. 364 * 365 */ 366 typedef enum PORT_CPU_AMD_FAMILY_0_MODEL 367 { 368 PORT_CPU_AMD_FAMLLY_0_MODEL_X = 0, 369 } PORT_CPU_AMD_FAMILY_0_MODEL; 370 371 /** 372 * @brief Union representing AMD processor family wise model information. 373 * 374 */ 375 typedef union PORT_CPU_AMD_MODEL 376 { 377 PORT_CPU_AMD_FAMILY_0_MODEL family0; 378 } PORT_CPU_AMD_MODEL; 379 380 /** 381 * @brief Structure representing AMD Processor's Threamal & Power Management 382 * features broken down into individual bit fields. 383 */ 384 typedef struct PORT_CPU_AMD_TPM_FEATURES 385 { 386 /// @{ 387 NvU32 EffFreq : 1; /**< */ 388 /// @} 389 } PORT_CPU_AMD_TPM_FEATURES; 390 391 /** 392 * @brief Structure representing AMD Processor version and features 393 * broken down into individual fields. 394 */ 395 typedef struct PORT_CPU_AMD 396 { 397 /// @{ 398 PORT_CPU_AMD_FAMILY family; /**< Family of the Processor.*/ 399 PORT_CPU_AMD_MODEL model; /**< Model of the Processor.*/ 400 NvU8 steppingId; /**< Stepping ID of the Processor.*/ 401 NvU8 brandIndex; /**< Numerical Index of Brand String Index Table 402 entry.*/ 403 NvU8 localApicId; /** Local APIC ID of the Processor.*/ 404 NvU32 threadCountPerCore; /**< Threads Per Core.*/ 405 NvU32 physicalCoreCount; /**< Physical Cores Per Package.*/ 406 NvU32 logicalCoreCount; /**< Logical Cores Per Package.*/ 407 PORT_CPU_AMD_TPM_FEATURES tpmFeatures; /**< Thermal and Power Management 408 Features.*/ 409 /// @} 410 } PORT_CPU_AMD; 411 412 /// @} 413 414 /** 415 * @name Generic CPU Information Structures, unions and enums. 416 * @{ 417 */ 418 419 /** 420 *@brief Maximum length of Vendor ID Null terminated string. 421 */ 422 #define PORT_CPU_VENDOR_ID_LENGTH 20 423 424 /** 425 *@brief Enum represening the Processor Architecture Type. 426 */ 427 typedef enum PORT_CPU_TYPE 428 { 429 /// @{ 430 PORT_CPU_TYPE_INTEL_X86 = 0, /**< Intel X86/X86-64 Architecture.*/ 431 PORT_CPU_TYPE_AMD_X86 = 1, /**< AMD X86/AMD64 Architecture.*/ 432 PORT_CPU_TYPE_ARM = 2 /**< ARM Architecture.*/ 433 /// @} 434 } PORT_CPU_TYPE; 435 436 /** 437 *@brief Union represening the Abstract Processor data structure. 438 */ 439 typedef union PORT_CPU 440 { 441 PORT_CPU_AMD amd; 442 PORT_CPU_INTEL intel; 443 } PORT_CPU; 444 445 /** 446 * @brief Structure representing processor information broken down into 447 * individual fields. 448 */ 449 typedef struct PORT_CPU_INFORMATION 450 { 451 /// @{ 452 PORT_CPU_TYPE type; /**< Type of Architecture/CPU.*/ 453 char vendorId[PORT_CPU_VENDOR_ID_LENGTH]; /**< Null terminated Vendor Id 454 String.*/ 455 NvLength vendorIdLength; /**< Actual length of the null terminated Vendor 456 Id string.*/ 457 PORT_CPU cpu; /**< CPU specifice information.*/ 458 /// @} 459 } PORT_CPU_INFORMATION; 460 461 /** 462 * @brief Structure representing processor logical topology information broken 463 * down into individual fields. 464 */ 465 typedef struct PORT_CPU_LOGICAL_TOPOLOGY 466 { 467 /// @{ 468 NvU64 activeCpuCount; /**< Active Logical CPUs.*/ 469 NvU64 activeGroupCount; /**< Active Logical CPU Group count.*/ 470 NvU64 maxCpuCount; /**< Maximum Logical CPUs system can support*/ 471 NvU64 maxGroupCount; /**< Maximum Logical CPUs Groups system can support*/ 472 NvU64 maxCpuPerGroup; /**< Maximum Logical CPUs system can support per group*/ 473 /// @} 474 } PORT_CPU_LOGICAL_TOPOLOGY; 475 476 /** 477 * @brief Structure representing a BAR descriptor for a PCIe device 478 */ 479 typedef struct PORT_CPU_BAR_DESC 480 { 481 /// @{ 482 void *pBarAddr; /**< Starting virtual address of the BAR space */ 483 NvU64 physAddr; /**< Starting physical address of the BAR space */ 484 NvU32 barSize; /**< Size of BAR space */ 485 /// @} 486 } PORT_CPU_BAR_DESC; 487 488 /// @} End Generic CPU Information Structures, unions and enums. 489 490 /** 491 * @brief Get Logical Topology of CPU. 492 * @param[out] pCpuTopology PORT_CPU_LOGICAL_TOPOLOGY pointer. 493 * @return NV_OK If successful and cpu logical topology information 494 * in pCpuInfo structure. 495 */ 496 NV_STATUS portCpuGetLogicalTopology(PORT_CPU_LOGICAL_TOPOLOGY *pCpuTopology); 497 #define portCpuGetLogicalTopology_SUPPORTED (NVOS_IS_WINDOWS) 498 499 /** 500 * @brief Get CPU Logical Topology Information. 501 * @param[out] pCpuInfo PORT_CPU_INFORMATION pointer. 502 * @return NV_OK If successful and CPU Information in pCpuInfo structure. 503 */ 504 NV_STATUS portCpuGetInfo(PORT_CPU_INFORMATION* pCpuInfo); 505 #define portCpuGetInfo_SUPPORTED (_X86_ || _AMD64_) 506 507 /** 508 * @brief Get CPU information using CPUID Instruction (X86-64 Specifice) 509 * @param[out] pCpuInfo Pointer to array which return value 510 * cpuInfo[0] = EAX, 511 * cpuInfo[1] = EBX, 512 * cpuInfo[2] = ECX, 513 * cpuInfo[3] = EDX. 514 * @param[in] functionId Function Id of CPUID instruction to execute. 515 * @param[in] subfunctionId Sub-Function Id of CPUID instruction to execute. 516 * subfunctionId enables you to gather additional information about 517 * the processor 518 519 * @return NV_OK if successful, otherwise return errors. 520 */ 521 NV_STATUS portCpuExCpuId(NvU32* pCpuInfo, NvU32 functionId, 522 NvU32 subfunctionId); 523 #define portCpuExCpuId_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 524 /// @} End extended functions 525 526 /** 527 * @brief Retrieve the current value and frequency of the performance counter 528 * 529 * @param[out] pFreq A pointer to a variable to which this routine writes the 530 * performance counter frequency, in ticks per second. 531 * This parameter is optional and can be NULL if the caller 532 * does not need the counter frequency value. 533 * 534 * @return The performance counter value in units of ticks 535 */ 536 NvS64 portCpuExQueryPerformanceCounter(NvS64 *pFreq); 537 #define portCpuExQueryPerformanceCounter_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 538 539 /** 540 * @brief Enable PMC read feature 541 */ 542 void portCpuExEnablePmc(void); 543 #define portCpuExEnablePmc_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 544 545 /** 546 * @brief Read requested PMC register 547 * 548 * @param [in] address Address of the PMC register 549 * @param [out] *pValue Value of PMC register 550 * 551 * @return NV_OK If successful. 552 */ 553 NV_STATUS portCpuExReadPmc(NvU32 address, NvU64 *pValue); 554 #define portCpuExReadPmc_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 555 556 /** 557 * @brief Fill in BAR descriptor of Integrated memory controller 558 * 559 * @param [in] pImcBarDesc Pointer to BAR descriptor structure 560 * 561 * @return NV_OK If successful. 562 */ 563 NV_STATUS portCpuExAllocImcBarDesc(PORT_CPU_BAR_DESC *pImcBarDesc); 564 #define portCpuExAllocImcBarDesc_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 565 566 /** 567 * @brief Free BAR descriptor of Integrated memory controller 568 * 569 * @param [in] pImcBarDesc Pointer to BAR descriptor structure 570 * 571 * @return NV_OK If successful. 572 */ 573 NV_STATUS portCpuExFreeImcBarDesc(PORT_CPU_BAR_DESC *pImcBarDesc); 574 #define portCpuExFreeImcBarDesc_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 575 576 /** 577 * @brief Reset Performance monitoring counters 578 * 579 * @return NV_OK If successful. 580 */ 581 NV_STATUS portCpuExResetPmu(void); 582 #define portCpuExResetPmu_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 583 584 /** 585 * @brief Program Performance monitoring counters 586 * 587 * @param [in] numValidEvents Number of valid events in array pPerfEvents 588 * @param [in] pPerfEvents Array of events to be configured into general 589 * purpose performance monitoring counters(PMCs) 590 * 591 * @return NV_OK If successful. 592 */ 593 NV_STATUS portCpuExProgramPmu(NvU32 numValidEvents, NvU32 *pPerfEvents); 594 #define portCpuExProgramPmu_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 595 596 /** 597 * @brief Get number of DRAM reads in terms of bytes 598 * 599 * @param [out] pNumReads 600 * 601 * @return NV_OK If successful 602 */ 603 NV_STATUS portCpuExGetDRamReads(NvU64 *pNumReads); 604 #define portCpuExGetDRamReads_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 605 606 /** 607 * @brief Get number of DRAM writes in terms of bytes 608 * 609 * @param [out] pNumWrites 610 * 611 * @return NV_OK If successful 612 */ 613 NV_STATUS portCpuExGetDRamWrites(NvU64 *pNumWrites); 614 #define portCpuExGetDRamWrites_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 615 616 /** 617 * @brief Check if the given MSR is supported on the current processor 618 * 619 * @param [in] address Address of the MSR that needs to be checked 620 * 621 * @return NV_TRUE If MSR is supported 622 * NV_FALSE If MSR is not supported 623 */ 624 NvBool portCpuExIsMsrSupported(NvU32 address); 625 #define portCpuExIsMsrSupported_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 626 627 /** 628 * @brief Check if the current processor supports DRAM read/write request counting 629 * 630 * @return NV_TRUE If supported 631 * NV_FALSE If not supported 632 */ 633 NvBool portCpuExIsDramRwCountingSupported(void); 634 #define portCpuExIsDramRwCountingSupported_SUPPORTED (NVOS_IS_WINDOWS && !PORT_IS_MODS && (_X86_ || _AMD64_)) 635 636 #endif // _NVPORT_CPU_H_ 637 /// @} 638