1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 // 25 // This file provides common types for both UVM driver and RM's UVM interface. 26 // 27 28 #ifndef _NV_UVM_TYPES_H_ 29 #define _NV_UVM_TYPES_H_ 30 31 #include "nvtypes.h" 32 #include "nvstatus.h" 33 #include "nvgputypes.h" 34 #include "nvCpuUuid.h" 35 36 37 // 38 // Default Page Size if left "0" because in RM BIG page size is default & there 39 // are multiple BIG page sizes in RM. These defines are used as flags to "0" 40 // should be OK when user is not sure which pagesize allocation it wants 41 // 42 #define UVM_PAGE_SIZE_DEFAULT 0x0 43 #define UVM_PAGE_SIZE_4K 0x1000 44 #define UVM_PAGE_SIZE_64K 0x10000 45 #define UVM_PAGE_SIZE_128K 0x20000 46 #define UVM_PAGE_SIZE_2M 0x200000 47 #define UVM_PAGE_SIZE_512M 0x20000000 48 49 // 50 // When modifying flags, make sure they are compatible with the mirrored 51 // PMA_* flags in phys_mem_allocator.h. 52 // 53 // Input flags 54 #define UVM_PMA_ALLOCATE_DONT_EVICT NVBIT(0) 55 #define UVM_PMA_ALLOCATE_PINNED NVBIT(1) 56 #define UVM_PMA_ALLOCATE_SPECIFY_MINIMUM_SPEED NVBIT(2) 57 #define UVM_PMA_ALLOCATE_SPECIFY_ADDRESS_RANGE NVBIT(3) 58 #define UVM_PMA_ALLOCATE_SPECIFY_REGION_ID NVBIT(4) 59 #define UVM_PMA_ALLOCATE_PREFER_SLOWEST NVBIT(5) 60 #define UVM_PMA_ALLOCATE_CONTIGUOUS NVBIT(6) 61 #define UVM_PMA_ALLOCATE_PERSISTENT NVBIT(7) 62 #define UVM_PMA_ALLOCATE_PROTECTED_REGION NVBIT(8) 63 #define UVM_PMA_ALLOCATE_FORCE_ALIGNMENT NVBIT(9) 64 #define UVM_PMA_ALLOCATE_NO_ZERO NVBIT(10) 65 #define UVM_PMA_ALLOCATE_TURN_BLACKLIST_OFF NVBIT(11) 66 #define UVM_PMA_ALLOCATE_ALLOW_PARTIAL NVBIT(12) 67 68 // Output flags 69 #define UVM_PMA_ALLOCATE_RESULT_IS_ZERO NVBIT(0) 70 71 // Input flags to pmaFree 72 #define UVM_PMA_FREE_IS_ZERO NVBIT(0) 73 74 // 75 // Indicate that the PMA operation is being done from one of the PMA eviction 76 // callbacks. 77 // 78 // Notably this flag is currently used only by the UVM/RM interface and not 79 // mirrored in PMA. 80 // 81 #define UVM_PMA_CALLED_FROM_PMA_EVICTION 16384 82 83 #define UVM_UUID_LEN 16 84 #define UVM_SW_OBJ_SUBCHANNEL 5 85 86 typedef unsigned long long UvmGpuPointer; 87 88 // 89 // The following typedefs serve to explain the resources they point to. 90 // The actual resources remain RM internal and not exposed. 91 // 92 typedef struct uvmGpuSession_tag *uvmGpuSessionHandle; // gpuSessionHandle 93 typedef struct uvmGpuDevice_tag *uvmGpuDeviceHandle; // gpuDeviceHandle 94 typedef struct uvmGpuAddressSpace_tag *uvmGpuAddressSpaceHandle; // gpuAddressSpaceHandle 95 typedef struct uvmGpuTsg_tag *uvmGpuTsgHandle; // gpuTsgHandle 96 typedef struct uvmGpuChannel_tag *uvmGpuChannelHandle; // gpuChannelHandle 97 typedef struct uvmGpuCopyEngine_tag *uvmGpuCopyEngineHandle; // gpuObjectHandle 98 99 typedef struct UvmGpuMemoryInfo_tag 100 { 101 // Out: Memory layout. 102 NvU32 kind; 103 104 // Out: Set to TRUE, if the allocation is in sysmem. 105 NvBool sysmem; 106 107 // Out: Set to TRUE, if this allocation is treated as EGM. 108 // sysmem is also TRUE when egm is TRUE. 109 NvBool egm; 110 111 // Out: Set to TRUE, if the allocation is a constructed 112 // under a Device or Subdevice. 113 // All permutations of sysmem and deviceDescendant are valid. 114 // !sysmem && !deviceDescendant implies a fabric allocation. 115 NvBool deviceDescendant; 116 117 // Out: Page size associated with the phys alloc. 118 NvU64 pageSize; 119 120 // Out: Set to TRUE, if the allocation is contiguous. 121 NvBool contig; 122 123 // Out: Starting Addr if the allocation is contiguous. 124 // This is only valid if contig is NV_TRUE. 125 NvU64 physAddr; 126 127 // Out: Total size of the allocation. 128 NvU64 size; 129 130 // Out: Uuid of the GPU to which the allocation belongs. 131 // This is only valid if deviceDescendant is NV_TRUE. 132 // When egm is NV_TRUE, this is also the UUID of the GPU 133 // for which EGM is local. 134 // If the GPU has SMC enabled, the UUID is the GI UUID. 135 // Otherwise, it is the UUID for the physical GPU. 136 // Note: If the allocation is owned by a device in 137 // an SLI group and the allocation is broadcast 138 // across the SLI group, this UUID will be any one 139 // of the subdevices in the SLI group. 140 NvProcessorUuid uuid; 141 } UvmGpuMemoryInfo; 142 143 // Some resources must share the same virtual mappings across channels. A mapped 144 // resource must be shared by a channel iff: 145 // 146 // 1) The channel belongs to a TSG (UvmGpuChannelInstanceInfo::bTsgChannel is 147 // NV_TRUE). 148 // 149 // 2) The channel is in the same TSG as all other channels sharing that mapping 150 // (UvmGpuChannelInstanceInfo::tsgId matches among channels). 151 // 152 // 3) The channel is in the same GPU address space as the other channels 153 // sharing that mapping. 154 // 155 // 4) The resource handle(s) match those of the shared mapping 156 // (UvmGpuChannelResourceInfo::resourceDescriptor and 157 // UvmGpuChannelResourceInfo::resourceId). 158 typedef struct UvmGpuChannelResourceInfo_tag 159 { 160 // Out: Ptr to the RM memDesc of the channel resource. 161 NvP64 resourceDescriptor; 162 163 // Out: RM ID of the channel resource. 164 NvU32 resourceId; 165 166 // Out: Alignment needed for the resource allocation. 167 NvU64 alignment; 168 169 // Out: Info about the resource allocation. 170 UvmGpuMemoryInfo resourceInfo; 171 } UvmGpuChannelResourceInfo; 172 173 typedef struct UvmGpuPagingChannelInfo_tag 174 { 175 // Pointer to a shadown buffer mirroring the contents of the error notifier 176 // for the paging channel 177 NvNotification *shadowErrorNotifier; 178 } UvmGpuPagingChannelInfo; 179 180 typedef enum 181 { 182 UVM_GPU_CHANNEL_ENGINE_TYPE_GR = 1, 183 UVM_GPU_CHANNEL_ENGINE_TYPE_CE = 2, 184 UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2 = 3, 185 } UVM_GPU_CHANNEL_ENGINE_TYPE; 186 187 #define UVM_GPU_CHANNEL_MAX_RESOURCES 13 188 189 typedef struct UvmGpuChannelInstanceInfo_tag 190 { 191 // Out: Starting address of the channel instance. 192 NvU64 base; 193 194 // Out: Set to NV_TRUE, if the instance is in sysmem. 195 // Set to NV_FALSE, if the instance is in vidmem. 196 NvBool sysmem; 197 198 // Out: Hardware runlist ID. 199 NvU32 runlistId; 200 201 // Out: Hardware channel ID. 202 NvU32 chId; 203 204 // Out: NV_TRUE if the channel belongs to a subcontext or NV_FALSE if it 205 // belongs to a regular context. 206 NvBool bInSubctx; 207 208 // Out: ID of the subcontext to which the channel belongs. 209 NvU32 subctxId; 210 211 // Out: Whether the channel belongs to a TSG or not 212 NvBool bTsgChannel; 213 214 // Out: ID of the TSG to which the channel belongs 215 NvU32 tsgId; 216 217 // Out: Maximum number of subcontexts in the TSG to which the channel belongs 218 NvU32 tsgMaxSubctxCount; 219 220 // Out: Info of channel resources associated with the channel. 221 UvmGpuChannelResourceInfo resourceInfo[UVM_GPU_CHANNEL_MAX_RESOURCES]; 222 223 // Out: Number of valid entries in resourceInfo array. 224 NvU32 resourceCount; 225 226 // Out: Type of the engine the channel is bound to 227 NvU32 channelEngineType; 228 229 // Out: Channel handle to be used in the CLEAR_FAULTED method 230 NvU32 clearFaultedToken; 231 232 // Out: Address of the NV_CHRAM_CHANNEL register required to clear the 233 // ENG_FAULTED/PBDMA_FAULTED bits after servicing non-replayable faults on 234 // Ampere+ GPUs 235 volatile NvU32 *pChramChannelRegister; 236 237 // Out: Address of the Runlist PRI Base Register required to ring the 238 // doorbell after clearing the faulted bit. 239 volatile NvU32 *pRunlistPRIBaseRegister; 240 241 // Out: SMC engine id to which the GR channel is bound, or zero if the GPU 242 // does not support SMC or it is a CE channel 243 NvU32 smcEngineId; 244 245 // Out: Start of the VEID range assigned to the SMC engine the GR channel 246 // is bound to, or zero if the GPU does not support SMC or it is a CE 247 // channel 248 NvU32 smcEngineVeIdOffset; 249 } UvmGpuChannelInstanceInfo; 250 251 typedef struct UvmGpuChannelResourceBindParams_tag 252 { 253 // In: RM ID of the channel resource. 254 NvU32 resourceId; 255 256 // In: Starting VA at which the channel resource is mapped. 257 NvU64 resourceVa; 258 } UvmGpuChannelResourceBindParams; 259 260 typedef struct UvmGpuChannelInfo_tag 261 { 262 volatile unsigned *gpGet; 263 volatile unsigned *gpPut; 264 UvmGpuPointer *gpFifoEntries; 265 unsigned numGpFifoEntries; 266 unsigned channelClassNum; 267 268 // The errorNotifier is filled out when the channel hits an RC error. 269 NvNotification *errorNotifier; 270 271 NvU32 hwRunlistId; 272 NvU32 hwChannelId; 273 274 volatile unsigned *dummyBar1Mapping; 275 276 // These values are filled by nvUvmInterfaceCopyEngineAlloc. The work 277 // submission token requires the channel to be bound to a runlist and that 278 // happens after CE allocation. 279 volatile NvU32 *workSubmissionOffset; 280 281 // To be deprecated. See pWorkSubmissionToken below. 282 NvU32 workSubmissionToken; 283 284 // 285 // This is the memory location where the most recently updated work 286 // submission token for this channel will be written to. After submitting 287 // new work and updating GP_PUT with the appropriate fence, the token must 288 // be read from this location before writing it to the workSubmissionOffset 289 // to kick off the new work. 290 // 291 volatile NvU32 *pWorkSubmissionToken; 292 293 // GPU VAs of both GPFIFO and GPPUT are needed in Confidential Computing 294 // so a channel can be controlled via another channel (SEC2 or WLC/LCIC) 295 NvU64 gpFifoGpuVa; 296 NvU64 gpPutGpuVa; 297 NvU64 gpGetGpuVa; 298 // GPU VA of work submission offset is needed in Confidential Computing 299 // so CE channels can ring doorbell of other channels as required for 300 // WLC/LCIC work submission 301 NvU64 workSubmissionOffsetGpuVa; 302 } UvmGpuChannelInfo; 303 304 typedef enum 305 { 306 // This value must be passed by Pascal and pre-Pascal GPUs for those 307 // allocations for which a specific location cannot be enforced. 308 UVM_BUFFER_LOCATION_DEFAULT = 0, 309 310 UVM_BUFFER_LOCATION_SYS = 1, 311 UVM_BUFFER_LOCATION_VID = 2, 312 } UVM_BUFFER_LOCATION; 313 314 typedef struct UvmGpuTsgAllocParams_tag 315 { 316 // Interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE 317 NvU32 engineType; 318 319 // Index of the engine the TSG is bound to. 320 // Ignored if engineType is anything other than 321 // UVM_GPU_CHANNEL_ENGINE_TYPE_CE. 322 NvU32 engineIndex; 323 } UvmGpuTsgAllocParams; 324 325 typedef struct UvmGpuChannelAllocParams_tag 326 { 327 NvU32 numGpFifoEntries; 328 329 // The next two fields store UVM_BUFFER_LOCATION values 330 NvU32 gpFifoLoc; 331 NvU32 gpPutLoc; 332 } UvmGpuChannelAllocParams; 333 334 typedef struct UvmGpuPagingChannelAllocParams_tag 335 { 336 // Index of the LCE engine the channel will be bound to, a zero-based offset 337 // from NV2080_ENGINE_TYPE_COPY0. 338 NvU32 engineIndex; 339 } UvmGpuPagingChannelAllocParams; 340 341 // The max number of Copy Engines supported by a GPU. 342 // The gpu ops build has a static assert that this is the correct number. 343 #define UVM_COPY_ENGINE_COUNT_MAX 64 344 345 typedef struct 346 { 347 // True if the CE is supported at all 348 NvBool supported:1; 349 350 // True if the CE is synchronous with GR 351 NvBool grce:1; 352 353 // True if the CE shares physical CEs with any other CE 354 // 355 // The value returned by RM for this field may change when a GPU is 356 // registered with RM for the first time, so UVM needs to query it 357 // again each time a GPU is registered. 358 NvBool shared:1; 359 360 // True if the CE can give enhanced performance for SYSMEM reads over other CEs 361 NvBool sysmemRead:1; 362 363 // True if the CE can give enhanced performance for SYSMEM writes over other CEs 364 NvBool sysmemWrite:1; 365 366 // True if the CE can be used for SYSMEM transactions 367 NvBool sysmem:1; 368 369 // True if the CE can be used for P2P transactions using NVLINK 370 NvBool nvlinkP2p:1; 371 372 // True if the CE can be used for P2P transactions 373 NvBool p2p:1; 374 375 // Mask of physical CEs assigned to this LCE 376 // 377 // The value returned by RM for this field may change when a GPU is 378 // registered with RM for the first time, so UVM needs to query it 379 // again each time a GPU is registered. 380 NvU32 cePceMask; 381 } UvmGpuCopyEngineCaps; 382 383 typedef struct UvmGpuCopyEnginesCaps_tag 384 { 385 // Supported CEs may not be contiguous 386 UvmGpuCopyEngineCaps copyEngineCaps[UVM_COPY_ENGINE_COUNT_MAX]; 387 } UvmGpuCopyEnginesCaps; 388 389 typedef enum 390 { 391 UVM_LINK_TYPE_NONE, 392 UVM_LINK_TYPE_PCIE, 393 UVM_LINK_TYPE_NVLINK_1, 394 UVM_LINK_TYPE_NVLINK_2, 395 UVM_LINK_TYPE_NVLINK_3, 396 UVM_LINK_TYPE_NVLINK_4, 397 UVM_LINK_TYPE_C2C, 398 } UVM_LINK_TYPE; 399 400 typedef struct UvmGpuCaps_tag 401 { 402 // If numaEnabled is NV_TRUE, then the system address of allocated GPU 403 // memory can be converted to struct pages. See 404 // UvmGpuInfo::systemMemoryWindowStart. 405 NvBool numaEnabled; 406 NvU32 numaNodeId; 407 } UvmGpuCaps; 408 409 typedef struct UvmGpuAddressSpaceInfo_tag 410 { 411 NvU64 bigPageSize; 412 413 NvBool atsEnabled; 414 415 // Mapped registers that contain the current GPU time 416 volatile NvU32 *time0Offset; 417 volatile NvU32 *time1Offset; 418 419 // Maximum number of subcontexts supported under this GPU address space 420 NvU32 maxSubctxCount; 421 422 NvBool smcEnabled; 423 424 NvU32 smcSwizzId; 425 426 NvU32 smcGpcCount; 427 } UvmGpuAddressSpaceInfo; 428 429 typedef struct UvmGpuAllocInfo_tag 430 { 431 NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested 432 NvU64 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M 433 NvU64 alignment; // Virtual alignment 434 NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation 435 NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB 436 NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory 437 NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved 438 NvBool bUnprotected; // Allocation to be made in unprotected memory whenever 439 // SEV or GPU CC modes are enabled. Ignored otherwise 440 } UvmGpuAllocInfo; 441 442 typedef enum 443 { 444 UVM_VIRT_MODE_NONE = 0, // Baremetal or passthrough virtualization 445 UVM_VIRT_MODE_LEGACY = 1, // Virtualization without SRIOV support 446 UVM_VIRT_MODE_SRIOV_HEAVY = 2, // Virtualization with SRIOV Heavy configured 447 UVM_VIRT_MODE_SRIOV_STANDARD = 3, // Virtualization with SRIOV Standard configured 448 UVM_VIRT_MODE_COUNT = 4, 449 } UVM_VIRT_MODE; 450 451 // !!! The following enums (with UvmRm prefix) are defined and documented in 452 // mm/uvm/interface/uvm_types.h and must be mirrored. Please refer to that file 453 // for more details. 454 455 // UVM GPU mapping types 456 typedef enum 457 { 458 UvmRmGpuMappingTypeDefault = 0, 459 UvmRmGpuMappingTypeReadWriteAtomic = 1, 460 UvmRmGpuMappingTypeReadWrite = 2, 461 UvmRmGpuMappingTypeReadOnly = 3, 462 UvmRmGpuMappingTypeCount = 4 463 } UvmRmGpuMappingType; 464 465 // UVM GPU caching types 466 typedef enum 467 { 468 UvmRmGpuCachingTypeDefault = 0, 469 UvmRmGpuCachingTypeForceUncached = 1, 470 UvmRmGpuCachingTypeForceCached = 2, 471 UvmRmGpuCachingTypeCount = 3 472 } UvmRmGpuCachingType; 473 474 // UVM GPU format types 475 typedef enum { 476 UvmRmGpuFormatTypeDefault = 0, 477 UvmRmGpuFormatTypeBlockLinear = 1, 478 UvmRmGpuFormatTypeCount = 2 479 } UvmRmGpuFormatType; 480 481 // UVM GPU Element bits types 482 typedef enum { 483 UvmRmGpuFormatElementBitsDefault = 0, 484 UvmRmGpuFormatElementBits8 = 1, 485 UvmRmGpuFormatElementBits16 = 2, 486 // Cuda does not support 24-bit width 487 UvmRmGpuFormatElementBits32 = 4, 488 UvmRmGpuFormatElementBits64 = 5, 489 UvmRmGpuFormatElementBits128 = 6, 490 UvmRmGpuFormatElementBitsCount = 7 491 } UvmRmGpuFormatElementBits; 492 493 // UVM GPU Compression types 494 typedef enum { 495 UvmRmGpuCompressionTypeDefault = 0, 496 UvmRmGpuCompressionTypeEnabledNoPlc = 1, 497 UvmRmGpuCompressionTypeCount = 2 498 } UvmRmGpuCompressionType; 499 500 typedef struct UvmGpuExternalMappingInfo_tag 501 { 502 // In: GPU caching ability. 503 UvmRmGpuCachingType cachingType; 504 505 // In: Virtual permissions. 506 UvmRmGpuMappingType mappingType; 507 508 // In: RM virtual mapping memory format 509 UvmRmGpuFormatType formatType; 510 511 // In: RM virtual mapping element bits 512 UvmRmGpuFormatElementBits elementBits; 513 514 // In: RM virtual compression type 515 UvmRmGpuCompressionType compressionType; 516 517 // In: Size of the buffer to store PTEs (in bytes). 518 NvU64 pteBufferSize; 519 520 // In: Page size for mapping 521 // If this field is passed as 0, the page size 522 // of the allocation is used for mapping. 523 // nvUvmInterfaceGetExternalAllocPtes must pass 524 // this field as zero. 525 NvU64 mappingPageSize; 526 527 // In: Pointer to a buffer to store PTEs. 528 // Out: The interface will fill the buffer with PTEs 529 NvU64 *pteBuffer; 530 531 // Out: Number of PTEs filled in to the buffer. 532 NvU64 numWrittenPtes; 533 534 // Out: Number of PTEs remaining to be filled 535 // if the buffer is not sufficient to accommodate 536 // requested PTEs. 537 NvU64 numRemainingPtes; 538 539 // Out: PTE size (in bytes) 540 NvU32 pteSize; 541 } UvmGpuExternalMappingInfo; 542 543 typedef struct UvmGpuP2PCapsParams_tag 544 { 545 // Out: peerId[i] contains gpu[i]'s peer id of gpu[1 - i]. Only defined if 546 // the GPUs are direct peers. 547 NvU32 peerIds[2]; 548 549 // Out: peerId[i] contains gpu[i]'s EGM peer id of gpu[1 - i]. Only defined 550 // if the GPUs are direct peers and EGM enabled in the system. 551 NvU32 egmPeerIds[2]; 552 553 // Out: UVM_LINK_TYPE 554 NvU32 p2pLink; 555 556 // Out: optimalNvlinkWriteCEs[i] contains gpu[i]'s optimal CE for writing to 557 // gpu[1 - i]. The CE indexes are valid only if the GPUs are NVLink peers. 558 // 559 // The value returned by RM for this field may change when a GPU is 560 // registered with RM for the first time, so UVM needs to query it again 561 // each time a GPU is registered. 562 NvU32 optimalNvlinkWriteCEs[2]; 563 564 // Out: Maximum unidirectional bandwidth between the peers in megabytes per 565 // second, not taking into account the protocols overhead. The reported 566 // bandwidth for indirect peers is zero. 567 NvU32 totalLinkLineRateMBps; 568 569 // Out: True if the peers have a indirect link to communicate. On P9 570 // systems, this is true if peers are connected to different NPUs that 571 // forward the requests between them. 572 NvU32 indirectAccess : 1; 573 } UvmGpuP2PCapsParams; 574 575 // Platform-wide information 576 typedef struct UvmPlatformInfo_tag 577 { 578 // Out: ATS (Address Translation Services) is supported 579 NvBool atsSupported; 580 581 // Out: True if HW trusted execution, such as AMD's SEV-SNP or Intel's TDX, 582 // is enabled in the VM, indicating that Confidential Computing must be 583 // also enabled in the GPU(s); these two security features are either both 584 // enabled, or both disabled. 585 NvBool confComputingEnabled; 586 } UvmPlatformInfo; 587 588 typedef struct UvmGpuClientInfo_tag 589 { 590 NvHandle hClient; 591 592 NvHandle hSmcPartRef; 593 } UvmGpuClientInfo; 594 595 typedef enum 596 { 597 UVM_GPU_CONF_COMPUTE_MODE_NONE, 598 UVM_GPU_CONF_COMPUTE_MODE_APM, 599 UVM_GPU_CONF_COMPUTE_MODE_HCC, 600 UVM_GPU_CONF_COMPUTE_MODE_COUNT 601 } UvmGpuConfComputeMode; 602 603 typedef struct UvmGpuConfComputeCaps_tag 604 { 605 // Out: GPU's confidential compute mode 606 UvmGpuConfComputeMode mode; 607 } UvmGpuConfComputeCaps; 608 609 #define UVM_GPU_NAME_LENGTH 0x40 610 611 typedef struct UvmGpuInfo_tag 612 { 613 // Printable gpu name 614 char name[UVM_GPU_NAME_LENGTH]; 615 616 // Uuid of the physical GPU or GI UUID if nvUvmInterfaceGetGpuInfo() 617 // requested information for a valid SMC partition. 618 NvProcessorUuid uuid; 619 620 // Gpu architecture; NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_* 621 NvU32 gpuArch; 622 623 // Gpu implementation; NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_* 624 NvU32 gpuImplementation; 625 626 // Host (gpfifo) class; *_CHANNEL_GPFIFO_*, e.g. KEPLER_CHANNEL_GPFIFO_A 627 NvU32 hostClass; 628 629 // Copy engine (dma) class; *_DMA_COPY_*, e.g. KEPLER_DMA_COPY_A 630 NvU32 ceClass; 631 632 // Compute class; *_COMPUTE_*, e.g. KEPLER_COMPUTE_A 633 NvU32 computeClass; 634 635 // Set if GPU supports TCC Mode & is in TCC mode. 636 NvBool gpuInTcc; 637 638 // Number of subdevices in SLI group. 639 NvU32 subdeviceCount; 640 641 // Virtualization mode of this gpu. 642 NvU32 virtMode; // UVM_VIRT_MODE 643 644 // NV_TRUE if this is a simulated/emulated GPU. NV_FALSE, otherwise. 645 NvBool isSimulated; 646 647 // Number of GPCs 648 // If SMC is enabled, this is the currently configured number of GPCs for 649 // the given partition (also see the smcSwizzId field below). 650 NvU32 gpcCount; 651 652 // Maximum number of GPCs; NV_SCAL_LITTER_NUM_GPCS 653 // This number is independent of the partition configuration, and can be 654 // used to conservatively size GPU-global constructs. 655 NvU32 maxGpcCount; 656 657 // Number of TPCs 658 NvU32 tpcCount; 659 660 // Maximum number of TPCs per GPC 661 NvU32 maxTpcPerGpcCount; 662 663 // NV_TRUE if SMC is enabled on this GPU. 664 NvBool smcEnabled; 665 666 // SMC partition ID (unique per GPU); note: valid when first looked up in 667 // nvUvmInterfaceGetGpuInfo(), but not guaranteed to remain valid. 668 // nvUvmInterfaceDeviceCreate() re-verifies the swizzId and fails if it is 669 // no longer valid. 670 NvU32 smcSwizzId; 671 672 UvmGpuClientInfo smcUserClientInfo; 673 674 // Confidential Compute capabilities of this GPU 675 UvmGpuConfComputeCaps gpuConfComputeCaps; 676 677 // UVM_LINK_TYPE 678 NvU32 sysmemLink; 679 680 // See UvmGpuP2PCapsParams::totalLinkLineRateMBps 681 NvU32 sysmemLinkRateMBps; 682 683 // On coherent systems each GPU maps its memory to a window in the System 684 // Physical Address (SPA) space. The following fields describe that window. 685 // 686 // systemMemoryWindowSize > 0 indicates that the window is valid. meaning 687 // that GPU memory can be mapped by the CPU as cache-coherent by adding the 688 // GPU address to the window start. 689 NvU64 systemMemoryWindowStart; 690 NvU64 systemMemoryWindowSize; 691 692 // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch 693 // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, 694 // nvswitchMemoryWindowStart tells the base address for the GPU in the 695 // NVSwitch address space. It is used when creating PTEs of memory mappings 696 // to NVSwitch peers. 697 NvBool connectedToSwitch; 698 NvU64 nvswitchMemoryWindowStart; 699 700 // local EGM properties 701 // NV_TRUE if EGM is enabled 702 NvBool egmEnabled; 703 704 // Peer ID to reach local EGM when EGM is enabled 705 NvU8 egmPeerId; 706 707 // EGM base address to offset in the GMMU PTE entry for EGM mappings 708 NvU64 egmBaseAddr; 709 } UvmGpuInfo; 710 711 typedef struct UvmGpuFbInfo_tag 712 { 713 // Max physical address that can be allocated by UVM. This excludes internal 714 // RM regions that are not registered with PMA either. 715 NvU64 maxAllocatableAddress; 716 717 NvU32 heapSize; // RAM in KB available for user allocations 718 NvU32 reservedHeapSize; // RAM in KB reserved for internal RM allocation 719 NvBool bZeroFb; // Zero FB mode enabled. 720 NvU64 maxVidmemPageSize; // Largest GPU page size to access vidmem. 721 } UvmGpuFbInfo; 722 723 typedef struct UvmGpuEccInfo_tag 724 { 725 unsigned eccMask; 726 unsigned eccOffset; 727 void *eccReadLocation; 728 NvBool *eccErrorNotifier; 729 NvBool bEccEnabled; 730 } UvmGpuEccInfo; 731 732 typedef struct UvmPmaAllocationOptions_tag 733 { 734 NvU32 flags; 735 NvU32 minimumSpeed; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_MININUM_SPEED 736 NvU64 physBegin, physEnd; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_ADDRESS_RANGE 737 NvU32 regionId; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_REGION_ID 738 NvU64 alignment; // valid if flags & UVM_PMA_ALLOCATE_FORCE_ALIGNMENT 739 NvLength numPagesAllocated; // valid if flags & UVM_PMA_ALLOCATE_ALLOW_PARTIAL 740 741 NvU32 resultFlags; // valid if the allocation function returns NV_OK 742 } UvmPmaAllocationOptions; 743 744 // 745 // Mirrored in PMA (PMA_STATS) 746 // 747 typedef struct UvmPmaStatistics_tag 748 { 749 volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions 750 volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions 751 volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions 752 volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory 753 volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory 754 volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory 755 } UvmPmaStatistics; 756 757 /******************************************************************************* 758 uvmEventSuspend 759 This function will be called by the GPU driver to signal to UVM that the 760 system is about to enter a sleep state. When it is called, the 761 following assumptions/guarantees are valid/made: 762 763 * User channels have been preempted and disabled 764 * UVM channels are still running normally and will continue to do 765 so until after this function returns control 766 * User threads are still running, but can no longer issue system 767 system calls to the GPU driver 768 * Until exit from this function, UVM is allowed to make full use of 769 the GPUs under its control, as well as of the GPU driver 770 771 Upon return from this function, UVM may not access GPUs under its control 772 until the GPU driver calls uvmEventResume(). It may still receive 773 calls to uvmEventIsrTopHalf() during this time, which it should return 774 NV_ERR_NO_INTR_PENDING from. It will not receive any other calls. 775 */ 776 typedef NV_STATUS (*uvmEventSuspend_t) (void); 777 778 /******************************************************************************* 779 uvmEventResume 780 This function will be called by the GPU driver to signal to UVM that the 781 system has exited a previously entered sleep state. When it is called, 782 the following assumptions/guarantees are valid/made: 783 784 * UVM is again allowed to make full use of the GPUs under its 785 control, as well as of the GPU driver 786 * UVM channels are running normally 787 * User channels are still preempted and disabled 788 * User threads are again running, but still cannot issue system 789 calls to the GPU driver, nor submit new work 790 791 Upon return from this function, UVM is expected to be fully functional. 792 */ 793 typedef NV_STATUS (*uvmEventResume_t) (void); 794 795 /******************************************************************************* 796 uvmEventStartDevice 797 This function will be called by the GPU driver once it has finished its 798 initialization to tell the UVM driver that this physical GPU has come up. 799 */ 800 typedef NV_STATUS (*uvmEventStartDevice_t) (const NvProcessorUuid *pGpuUuidStruct); 801 802 /******************************************************************************* 803 uvmEventStopDevice 804 This function will be called by the GPU driver to let UVM know that a 805 physical GPU is going down. 806 */ 807 typedef NV_STATUS (*uvmEventStopDevice_t) (const NvProcessorUuid *pGpuUuidStruct); 808 809 /******************************************************************************* 810 uvmEventIsrTopHalf_t 811 This function will be called by the GPU driver to let UVM know 812 that an interrupt has occurred on the given physical GPU. 813 814 Returns: 815 NV_OK if the UVM driver handled the interrupt 816 NV_ERR_NO_INTR_PENDING if the interrupt is not for the UVM driver 817 */ 818 #if defined (__linux__) 819 typedef NV_STATUS (*uvmEventIsrTopHalf_t) (const NvProcessorUuid *pGpuUuidStruct); 820 #else 821 typedef void (*uvmEventIsrTopHalf_t) (void); 822 #endif 823 824 struct UvmOpsUvmEvents 825 { 826 uvmEventSuspend_t suspend; 827 uvmEventResume_t resume; 828 uvmEventStartDevice_t startDevice; 829 uvmEventStopDevice_t stopDevice; 830 uvmEventIsrTopHalf_t isrTopHalf; 831 }; 832 833 #define UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES 32 834 #define UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES 16 835 836 typedef union UvmFaultMetadataPacket_tag 837 { 838 struct { 839 NvU8 authTag[UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES]; 840 NvBool valid; 841 }; 842 // padding to 32Bytes 843 NvU8 _padding[32]; 844 } UvmFaultMetadataPacket; 845 846 // This struct shall not be accessed nor modified directly by UVM as it is 847 // entirely managed by the RM layer 848 typedef struct UvmCslContext_tag 849 { 850 struct ccslContext_t *ctx; 851 void *nvidia_stack; 852 } UvmCslContext; 853 854 typedef struct UvmGpuFaultInfo_tag 855 { 856 struct 857 { 858 // Fault buffer GET register mapping. 859 // 860 // When Confidential Computing is enabled, GET refers to the shadow 861 // buffer (see bufferAddress below), and not to the actual HW buffer. 862 // In this setup, writes of GET (by UVM) do not result on re-evaluation 863 // of any interrupt condition. 864 volatile NvU32* pFaultBufferGet; 865 866 // Fault buffer PUT register mapping. 867 // 868 // When Confidential Computing is enabled, PUT refers to the shadow 869 // buffer (see bufferAddress below), and not to the actual HW buffer. 870 // In this setup, writes of PUT (by GSP-RM) do not result on 871 // re-evaluation of any interrupt condition. 872 volatile NvU32* pFaultBufferPut; 873 874 // Note: this variable is deprecated since buffer overflow is not a 875 // separate register from future chips. 876 volatile NvU32* pFaultBufferInfo; 877 878 // Register mapping used to clear a replayable fault interrupt in 879 // Turing+ GPUs. 880 volatile NvU32* pPmcIntr; 881 882 // Register mapping used to enable replayable fault interrupts. 883 volatile NvU32* pPmcIntrEnSet; 884 885 // Register mapping used to disable replayable fault interrupts. 886 volatile NvU32* pPmcIntrEnClear; 887 888 // Register used to enable, or disable, faults on prefetches. 889 volatile NvU32* pPrefetchCtrl; 890 891 // Replayable fault interrupt mask identifier. 892 NvU32 replayableFaultMask; 893 894 // Fault buffer CPU mapping 895 void* bufferAddress; 896 // 897 // When Confidential Computing is disabled, the mapping points to the 898 // actual HW fault buffer. 899 // 900 // When Confidential Computing is enabled, the mapping points to a 901 // copy of the HW fault buffer. This "shadow buffer" is maintained 902 // by GSP-RM. 903 904 // Size, in bytes, of the fault buffer pointed by bufferAddress. 905 NvU32 bufferSize; 906 // Mapping pointing to the start of the fault buffer metadata containing 907 // a 16Byte authentication tag and a valid byte. Always NULL when 908 // Confidential Computing is disabled. 909 UvmFaultMetadataPacket *bufferMetadata; 910 911 // CSL context used for performing decryption of replayable faults when 912 // Confidential Computing is enabled. 913 UvmCslContext cslCtx; 914 } replayable; 915 struct 916 { 917 // Shadow buffer for non-replayable faults on cpu memory. Resman copies 918 // here the non-replayable faults that need to be handled by UVM 919 void* shadowBufferAddress; 920 921 // Execution context for the queue associated with the fault buffer 922 void* shadowBufferContext; 923 924 // Fault buffer size 925 NvU32 bufferSize; 926 927 // Preallocated stack for functions called from the UVM isr top half 928 void *isr_sp; 929 930 // Preallocated stack for functions called from the UVM isr bottom half 931 void *isr_bh_sp; 932 933 // Used only when Hopper Confidential Compute is enabled 934 // Register mappings obtained from RM 935 volatile NvU32* pFaultBufferPut; 936 937 // Used only when Hopper Confidential Compute is enabled 938 // Cached get index of the non-replayable shadow buffer 939 NvU32 shadowBufferGet; 940 941 // See replayable.bufferMetadata 942 UvmFaultMetadataPacket *shadowBufferMetadata; 943 } nonReplayable; 944 NvHandle faultBufferHandle; 945 struct Device *pDevice; 946 } UvmGpuFaultInfo; 947 948 struct Device; 949 950 typedef struct UvmGpuPagingChannel_tag 951 { 952 struct gpuDevice *device; 953 NvNotification *errorNotifier; 954 NvHandle channelHandle; 955 NvHandle errorNotifierHandle; 956 void *pushStreamSp; 957 struct Device *pDevice; 958 } UvmGpuPagingChannel, *UvmGpuPagingChannelHandle; 959 960 typedef struct UvmGpuAccessCntrInfo_tag 961 { 962 // Register mappings obtained from RM 963 // pointer to the Get register for the access counter buffer 964 volatile NvU32* pAccessCntrBufferGet; 965 // pointer to the Put register for the access counter buffer 966 volatile NvU32* pAccessCntrBufferPut; 967 // pointer to the Full register for the access counter buffer 968 volatile NvU32* pAccessCntrBufferFull; 969 // pointer to the hub interrupt 970 volatile NvU32* pHubIntr; 971 // pointer to interrupt enable register 972 volatile NvU32* pHubIntrEnSet; 973 // pointer to interrupt disable register 974 volatile NvU32* pHubIntrEnClear; 975 // mask for the access counter buffer 976 NvU32 accessCounterMask; 977 // access counter buffer cpu mapping and size 978 void* bufferAddress; 979 NvU32 bufferSize; 980 NvHandle accessCntrBufferHandle; 981 } UvmGpuAccessCntrInfo; 982 983 typedef enum 984 { 985 UVM_ACCESS_COUNTER_GRANULARITY_64K = 1, 986 UVM_ACCESS_COUNTER_GRANULARITY_2M = 2, 987 UVM_ACCESS_COUNTER_GRANULARITY_16M = 3, 988 UVM_ACCESS_COUNTER_GRANULARITY_16G = 4, 989 } UVM_ACCESS_COUNTER_GRANULARITY; 990 991 typedef enum 992 { 993 UVM_ACCESS_COUNTER_USE_LIMIT_NONE = 1, 994 UVM_ACCESS_COUNTER_USE_LIMIT_QTR = 2, 995 UVM_ACCESS_COUNTER_USE_LIMIT_HALF = 3, 996 UVM_ACCESS_COUNTER_USE_LIMIT_FULL = 4, 997 } UVM_ACCESS_COUNTER_USE_LIMIT; 998 999 typedef struct UvmGpuAccessCntrConfig_tag 1000 { 1001 NvU32 mimcGranularity; 1002 1003 NvU32 momcGranularity; 1004 1005 NvU32 mimcUseLimit; 1006 1007 NvU32 momcUseLimit; 1008 1009 NvU32 threshold; 1010 } UvmGpuAccessCntrConfig; 1011 1012 // 1013 // When modifying this enum, make sure they are compatible with the mirrored 1014 // MEMORY_PROTECTION enum in phys_mem_allocator.h. 1015 // 1016 typedef enum UvmPmaGpuMemoryType_tag 1017 { 1018 UVM_PMA_GPU_MEMORY_TYPE_UNPROTECTED = 0, 1019 UVM_PMA_GPU_MEMORY_TYPE_PROTECTED = 1 1020 } UVM_PMA_GPU_MEMORY_TYPE; 1021 1022 typedef UvmGpuChannelInfo gpuChannelInfo; 1023 typedef UvmGpuTsgAllocParams gpuTsgAllocParams; 1024 typedef UvmGpuChannelAllocParams gpuChannelAllocParams; 1025 typedef UvmGpuCaps gpuCaps; 1026 typedef UvmGpuCopyEngineCaps gpuCeCaps; 1027 typedef UvmGpuCopyEnginesCaps gpuCesCaps; 1028 typedef UvmGpuP2PCapsParams getP2PCapsParams; 1029 typedef UvmGpuAddressSpaceInfo gpuAddressSpaceInfo; 1030 typedef UvmGpuAllocInfo gpuAllocInfo; 1031 typedef UvmGpuInfo gpuInfo; 1032 typedef UvmGpuClientInfo gpuClientInfo; 1033 typedef UvmGpuAccessCntrInfo gpuAccessCntrInfo; 1034 typedef UvmGpuAccessCntrConfig gpuAccessCntrConfig; 1035 typedef UvmGpuFaultInfo gpuFaultInfo; 1036 typedef UvmGpuMemoryInfo gpuMemoryInfo; 1037 typedef UvmGpuExternalMappingInfo gpuExternalMappingInfo; 1038 typedef UvmGpuChannelResourceInfo gpuChannelResourceInfo; 1039 typedef UvmGpuChannelInstanceInfo gpuChannelInstanceInfo; 1040 typedef UvmGpuChannelResourceBindParams gpuChannelResourceBindParams; 1041 typedef UvmGpuFbInfo gpuFbInfo; 1042 typedef UvmGpuEccInfo gpuEccInfo; 1043 typedef UvmGpuPagingChannel *gpuPagingChannelHandle; 1044 typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo; 1045 typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams; 1046 typedef UvmPmaAllocationOptions gpuPmaAllocationOptions; 1047 1048 typedef struct UvmCslIv 1049 { 1050 NvU8 iv[12]; 1051 NvU8 fresh; 1052 } UvmCslIv; 1053 1054 typedef enum UvmCslOperation 1055 { 1056 UVM_CSL_OPERATION_ENCRYPT, 1057 UVM_CSL_OPERATION_DECRYPT 1058 } UvmCslOperation; 1059 1060 #endif // _NV_UVM_TYPES_H_ 1061