1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 // 25 // This file provides common types for both UVM driver and RM's UVM interface. 26 // 27 28 #ifndef _NV_UVM_TYPES_H_ 29 #define _NV_UVM_TYPES_H_ 30 31 #include "nvtypes.h" 32 #include "nvstatus.h" 33 #include "nvgputypes.h" 34 #include "nvCpuUuid.h" 35 36 37 // 38 // Default Page Size if left "0" because in RM BIG page size is default & there 39 // are multiple BIG page sizes in RM. These defines are used as flags to "0" 40 // should be OK when user is not sure which pagesize allocation it wants 41 // 42 #define UVM_PAGE_SIZE_DEFAULT 0x0 43 #define UVM_PAGE_SIZE_4K 0x1000 44 #define UVM_PAGE_SIZE_64K 0x10000 45 #define UVM_PAGE_SIZE_128K 0x20000 46 #define UVM_PAGE_SIZE_2M 0x200000 47 #define UVM_PAGE_SIZE_512M 0x20000000 48 49 // 50 // When modifying flags, make sure they are compatible with the mirrored 51 // PMA_* flags in phys_mem_allocator.h. 52 // 53 // Input flags 54 #define UVM_PMA_ALLOCATE_DONT_EVICT NVBIT(0) 55 #define UVM_PMA_ALLOCATE_PINNED NVBIT(1) 56 #define UVM_PMA_ALLOCATE_SPECIFY_MINIMUM_SPEED NVBIT(2) 57 #define UVM_PMA_ALLOCATE_SPECIFY_ADDRESS_RANGE NVBIT(3) 58 #define UVM_PMA_ALLOCATE_SPECIFY_REGION_ID NVBIT(4) 59 #define UVM_PMA_ALLOCATE_PREFER_SLOWEST NVBIT(5) 60 #define UVM_PMA_ALLOCATE_CONTIGUOUS NVBIT(6) 61 #define UVM_PMA_ALLOCATE_PERSISTENT NVBIT(7) 62 #define UVM_PMA_ALLOCATE_PROTECTED_REGION NVBIT(8) 63 #define UVM_PMA_ALLOCATE_FORCE_ALIGNMENT NVBIT(9) 64 #define UVM_PMA_ALLOCATE_NO_ZERO NVBIT(10) 65 #define UVM_PMA_ALLOCATE_TURN_BLACKLIST_OFF NVBIT(11) 66 #define UVM_PMA_ALLOCATE_ALLOW_PARTIAL NVBIT(12) 67 68 // Output flags 69 #define UVM_PMA_ALLOCATE_RESULT_IS_ZERO NVBIT(0) 70 71 // Input flags to pmaFree 72 #define UVM_PMA_FREE_IS_ZERO NVBIT(0) 73 74 // 75 // Indicate that the PMA operation is being done from one of the PMA eviction 76 // callbacks. 77 // 78 // Notably this flag is currently used only by the UVM/RM interface and not 79 // mirrored in PMA. 80 // 81 #define UVM_PMA_CALLED_FROM_PMA_EVICTION 16384 82 83 #define UVM_UUID_LEN 16 84 #define UVM_SW_OBJ_SUBCHANNEL 5 85 86 typedef unsigned long long UvmGpuPointer; 87 88 // 89 // The following typedefs serve to explain the resources they point to. 90 // The actual resources remain RM internal and not exposed. 91 // 92 typedef struct uvmGpuSession_tag *uvmGpuSessionHandle; // gpuSessionHandle 93 typedef struct uvmGpuDevice_tag *uvmGpuDeviceHandle; // gpuDeviceHandle 94 typedef struct uvmGpuAddressSpace_tag *uvmGpuAddressSpaceHandle; // gpuAddressSpaceHandle 95 typedef struct uvmGpuTsg_tag *uvmGpuTsgHandle; // gpuTsgHandle 96 typedef struct uvmGpuChannel_tag *uvmGpuChannelHandle; // gpuChannelHandle 97 typedef struct uvmGpuCopyEngine_tag *uvmGpuCopyEngineHandle; // gpuObjectHandle 98 99 typedef struct UvmGpuMemoryInfo_tag 100 { 101 // Out: Memory layout. 102 NvU32 kind; 103 104 // Out: Set to TRUE, if the allocation is in sysmem. 105 NvBool sysmem; 106 107 // Out: Set to TRUE, if this allocation is treated as EGM. 108 // sysmem is also TRUE when egm is TRUE. 109 NvBool egm; 110 111 // Out: Set to TRUE, if the allocation is a constructed 112 // under a Device or Subdevice. 113 // All permutations of sysmem and deviceDescendant are valid. 114 // !sysmem && !deviceDescendant implies a fabric allocation. 115 NvBool deviceDescendant; 116 117 // Out: Page size associated with the phys alloc. 118 NvU64 pageSize; 119 120 // Out: Set to TRUE, if the allocation is contiguous. 121 NvBool contig; 122 123 // Out: Starting Addr if the allocation is contiguous. 124 // This is only valid if contig is NV_TRUE. 125 NvU64 physAddr; 126 127 // Out: Total size of the allocation. 128 NvU64 size; 129 130 // Out: Uuid of the GPU to which the allocation belongs. 131 // This is only valid if deviceDescendant is NV_TRUE. 132 // When egm is NV_TRUE, this is also the UUID of the GPU 133 // for which EGM is local. 134 // Note: If the allocation is owned by a device in 135 // an SLI group and the allocation is broadcast 136 // across the SLI group, this UUID will be any one 137 // of the subdevices in the SLI group. 138 NvProcessorUuid uuid; 139 } UvmGpuMemoryInfo; 140 141 // Some resources must share the same virtual mappings across channels. A mapped 142 // resource must be shared by a channel iff: 143 // 144 // 1) The channel belongs to a TSG (UvmGpuChannelInstanceInfo::bTsgChannel is 145 // NV_TRUE). 146 // 147 // 2) The channel is in the same TSG as all other channels sharing that mapping 148 // (UvmGpuChannelInstanceInfo::tsgId matches among channels). 149 // 150 // 3) The channel is in the same GPU address space as the other channels 151 // sharing that mapping. 152 // 153 // 4) The resource handle(s) match those of the shared mapping 154 // (UvmGpuChannelResourceInfo::resourceDescriptor and 155 // UvmGpuChannelResourceInfo::resourceId). 156 typedef struct UvmGpuChannelResourceInfo_tag 157 { 158 // Out: Ptr to the RM memDesc of the channel resource. 159 NvP64 resourceDescriptor; 160 161 // Out: RM ID of the channel resource. 162 NvU32 resourceId; 163 164 // Out: Alignment needed for the resource allocation. 165 NvU64 alignment; 166 167 // Out: Info about the resource allocation. 168 UvmGpuMemoryInfo resourceInfo; 169 } UvmGpuChannelResourceInfo; 170 171 typedef struct UvmGpuPagingChannelInfo_tag 172 { 173 // Pointer to a shadown buffer mirroring the contents of the error notifier 174 // for the paging channel 175 NvNotification *shadowErrorNotifier; 176 } UvmGpuPagingChannelInfo; 177 178 typedef enum 179 { 180 UVM_GPU_CHANNEL_ENGINE_TYPE_GR = 1, 181 UVM_GPU_CHANNEL_ENGINE_TYPE_CE = 2, 182 UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2 = 3, 183 } UVM_GPU_CHANNEL_ENGINE_TYPE; 184 185 #define UVM_GPU_CHANNEL_MAX_RESOURCES 13 186 187 typedef struct UvmGpuChannelInstanceInfo_tag 188 { 189 // Out: Starting address of the channel instance. 190 NvU64 base; 191 192 // Out: Set to NV_TRUE, if the instance is in sysmem. 193 // Set to NV_FALSE, if the instance is in vidmem. 194 NvBool sysmem; 195 196 // Out: Hardware runlist ID. 197 NvU32 runlistId; 198 199 // Out: Hardware channel ID. 200 NvU32 chId; 201 202 // Out: NV_TRUE if the channel belongs to a subcontext or NV_FALSE if it 203 // belongs to a regular context. 204 NvBool bInSubctx; 205 206 // Out: ID of the subcontext to which the channel belongs. 207 NvU32 subctxId; 208 209 // Out: Whether the channel belongs to a TSG or not 210 NvBool bTsgChannel; 211 212 // Out: ID of the TSG to which the channel belongs 213 NvU32 tsgId; 214 215 // Out: Maximum number of subcontexts in the TSG to which the channel belongs 216 NvU32 tsgMaxSubctxCount; 217 218 // Out: Info of channel resources associated with the channel. 219 UvmGpuChannelResourceInfo resourceInfo[UVM_GPU_CHANNEL_MAX_RESOURCES]; 220 221 // Out: Number of valid entries in resourceInfo array. 222 NvU32 resourceCount; 223 224 // Out: Type of the engine the channel is bound to 225 NvU32 channelEngineType; 226 227 // Out: Channel handle to be used in the CLEAR_FAULTED method 228 NvU32 clearFaultedToken; 229 230 // Out: Address of the NV_CHRAM_CHANNEL register required to clear the 231 // ENG_FAULTED/PBDMA_FAULTED bits after servicing non-replayable faults on 232 // Ampere+ GPUs 233 volatile NvU32 *pChramChannelRegister; 234 235 // Out: Address of the Runlist PRI Base Register required to ring the 236 // doorbell after clearing the faulted bit. 237 volatile NvU32 *pRunlistPRIBaseRegister; 238 239 // Out: SMC engine id to which the GR channel is bound, or zero if the GPU 240 // does not support SMC or it is a CE channel 241 NvU32 smcEngineId; 242 243 // Out: Start of the VEID range assigned to the SMC engine the GR channel 244 // is bound to, or zero if the GPU does not support SMC or it is a CE 245 // channel 246 NvU32 smcEngineVeIdOffset; 247 } UvmGpuChannelInstanceInfo; 248 249 typedef struct UvmGpuChannelResourceBindParams_tag 250 { 251 // In: RM ID of the channel resource. 252 NvU32 resourceId; 253 254 // In: Starting VA at which the channel resource is mapped. 255 NvU64 resourceVa; 256 } UvmGpuChannelResourceBindParams; 257 258 typedef struct UvmGpuChannelInfo_tag 259 { 260 volatile unsigned *gpGet; 261 volatile unsigned *gpPut; 262 UvmGpuPointer *gpFifoEntries; 263 unsigned numGpFifoEntries; 264 unsigned channelClassNum; 265 266 // The errorNotifier is filled out when the channel hits an RC error. 267 NvNotification *errorNotifier; 268 269 NvU32 hwRunlistId; 270 NvU32 hwChannelId; 271 272 volatile unsigned *dummyBar1Mapping; 273 274 // These values are filled by nvUvmInterfaceCopyEngineAlloc. The work 275 // submission token requires the channel to be bound to a runlist and that 276 // happens after CE allocation. 277 volatile NvU32 *workSubmissionOffset; 278 279 // To be deprecated. See pWorkSubmissionToken below. 280 NvU32 workSubmissionToken; 281 282 // 283 // This is the memory location where the most recently updated work 284 // submission token for this channel will be written to. After submitting 285 // new work and updating GP_PUT with the appropriate fence, the token must 286 // be read from this location before writing it to the workSubmissionOffset 287 // to kick off the new work. 288 // 289 volatile NvU32 *pWorkSubmissionToken; 290 291 // GPU VAs of both GPFIFO and GPPUT are needed in Confidential Computing 292 // so a channel can be controlled via another channel (SEC2 or WLC/LCIC) 293 NvU64 gpFifoGpuVa; 294 NvU64 gpPutGpuVa; 295 NvU64 gpGetGpuVa; 296 // GPU VA of work submission offset is needed in Confidential Computing 297 // so CE channels can ring doorbell of other channels as required for 298 // WLC/LCIC work submission 299 NvU64 workSubmissionOffsetGpuVa; 300 } UvmGpuChannelInfo; 301 302 typedef enum 303 { 304 // This value must be passed by Pascal and pre-Pascal GPUs for those 305 // allocations for which a specific location cannot be enforced. 306 UVM_BUFFER_LOCATION_DEFAULT = 0, 307 308 UVM_BUFFER_LOCATION_SYS = 1, 309 UVM_BUFFER_LOCATION_VID = 2, 310 } UVM_BUFFER_LOCATION; 311 312 typedef struct UvmGpuTsgAllocParams_tag 313 { 314 // Interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE 315 NvU32 engineType; 316 317 // Index of the engine the TSG is bound to. 318 // Ignored if engineType is anything other than 319 // UVM_GPU_CHANNEL_ENGINE_TYPE_CE. 320 NvU32 engineIndex; 321 } UvmGpuTsgAllocParams; 322 323 typedef struct UvmGpuChannelAllocParams_tag 324 { 325 NvU32 numGpFifoEntries; 326 327 // The next two fields store UVM_BUFFER_LOCATION values 328 NvU32 gpFifoLoc; 329 NvU32 gpPutLoc; 330 } UvmGpuChannelAllocParams; 331 332 typedef struct UvmGpuPagingChannelAllocParams_tag 333 { 334 // Index of the LCE engine the channel will be bound to, a zero-based offset 335 // from NV2080_ENGINE_TYPE_COPY0. 336 NvU32 engineIndex; 337 } UvmGpuPagingChannelAllocParams; 338 339 // The max number of Copy Engines supported by a GPU. 340 // The gpu ops build has a static assert that this is the correct number. 341 #define UVM_COPY_ENGINE_COUNT_MAX 64 342 343 typedef struct 344 { 345 // True if the CE is supported at all 346 NvBool supported:1; 347 348 // True if the CE is synchronous with GR 349 NvBool grce:1; 350 351 // True if the CE shares physical CEs with any other CE 352 // 353 // The value returned by RM for this field may change when a GPU is 354 // registered with RM for the first time, so UVM needs to query it 355 // again each time a GPU is registered. 356 NvBool shared:1; 357 358 // True if the CE can give enhanced performance for SYSMEM reads over other CEs 359 NvBool sysmemRead:1; 360 361 // True if the CE can give enhanced performance for SYSMEM writes over other CEs 362 NvBool sysmemWrite:1; 363 364 // True if the CE can be used for SYSMEM transactions 365 NvBool sysmem:1; 366 367 // True if the CE can be used for P2P transactions using NVLINK 368 NvBool nvlinkP2p:1; 369 370 // True if the CE can be used for P2P transactions 371 NvBool p2p:1; 372 373 // Mask of physical CEs assigned to this LCE 374 // 375 // The value returned by RM for this field may change when a GPU is 376 // registered with RM for the first time, so UVM needs to query it 377 // again each time a GPU is registered. 378 NvU32 cePceMask; 379 } UvmGpuCopyEngineCaps; 380 381 typedef struct UvmGpuCopyEnginesCaps_tag 382 { 383 // Supported CEs may not be contiguous 384 UvmGpuCopyEngineCaps copyEngineCaps[UVM_COPY_ENGINE_COUNT_MAX]; 385 } UvmGpuCopyEnginesCaps; 386 387 typedef enum 388 { 389 UVM_LINK_TYPE_NONE, 390 UVM_LINK_TYPE_PCIE, 391 UVM_LINK_TYPE_NVLINK_1, 392 UVM_LINK_TYPE_NVLINK_2, 393 UVM_LINK_TYPE_NVLINK_3, 394 UVM_LINK_TYPE_NVLINK_4, 395 UVM_LINK_TYPE_C2C, 396 } UVM_LINK_TYPE; 397 398 typedef struct UvmGpuCaps_tag 399 { 400 // If numaEnabled is NV_TRUE, then the system address of allocated GPU 401 // memory can be converted to struct pages. See 402 // UvmGpuInfo::systemMemoryWindowStart. 403 NvBool numaEnabled; 404 NvU32 numaNodeId; 405 } UvmGpuCaps; 406 407 typedef struct UvmGpuAddressSpaceInfo_tag 408 { 409 NvU64 bigPageSize; 410 411 NvBool atsEnabled; 412 413 // Mapped registers that contain the current GPU time 414 volatile NvU32 *time0Offset; 415 volatile NvU32 *time1Offset; 416 417 // Maximum number of subcontexts supported under this GPU address space 418 NvU32 maxSubctxCount; 419 420 NvBool smcEnabled; 421 422 NvU32 smcSwizzId; 423 424 NvU32 smcGpcCount; 425 } UvmGpuAddressSpaceInfo; 426 427 typedef struct UvmGpuAllocInfo_tag 428 { 429 NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested 430 NvU64 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M 431 NvU64 alignment; // Virtual alignment 432 NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation 433 NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB 434 NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory 435 NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved 436 NvBool bUnprotected; // Allocation to be made in unprotected memory whenever 437 // SEV or GPU CC modes are enabled. Ignored otherwise 438 } UvmGpuAllocInfo; 439 440 typedef enum 441 { 442 UVM_VIRT_MODE_NONE = 0, // Baremetal or passthrough virtualization 443 UVM_VIRT_MODE_LEGACY = 1, // Virtualization without SRIOV support 444 UVM_VIRT_MODE_SRIOV_HEAVY = 2, // Virtualization with SRIOV Heavy configured 445 UVM_VIRT_MODE_SRIOV_STANDARD = 3, // Virtualization with SRIOV Standard configured 446 UVM_VIRT_MODE_COUNT = 4, 447 } UVM_VIRT_MODE; 448 449 // !!! The following enums (with UvmRm prefix) are defined and documented in 450 // mm/uvm/interface/uvm_types.h and must be mirrored. Please refer to that file 451 // for more details. 452 453 // UVM GPU mapping types 454 typedef enum 455 { 456 UvmRmGpuMappingTypeDefault = 0, 457 UvmRmGpuMappingTypeReadWriteAtomic = 1, 458 UvmRmGpuMappingTypeReadWrite = 2, 459 UvmRmGpuMappingTypeReadOnly = 3, 460 UvmRmGpuMappingTypeCount = 4 461 } UvmRmGpuMappingType; 462 463 // UVM GPU caching types 464 typedef enum 465 { 466 UvmRmGpuCachingTypeDefault = 0, 467 UvmRmGpuCachingTypeForceUncached = 1, 468 UvmRmGpuCachingTypeForceCached = 2, 469 UvmRmGpuCachingTypeCount = 3 470 } UvmRmGpuCachingType; 471 472 // UVM GPU format types 473 typedef enum { 474 UvmRmGpuFormatTypeDefault = 0, 475 UvmRmGpuFormatTypeBlockLinear = 1, 476 UvmRmGpuFormatTypeCount = 2 477 } UvmRmGpuFormatType; 478 479 // UVM GPU Element bits types 480 typedef enum { 481 UvmRmGpuFormatElementBitsDefault = 0, 482 UvmRmGpuFormatElementBits8 = 1, 483 UvmRmGpuFormatElementBits16 = 2, 484 // Cuda does not support 24-bit width 485 UvmRmGpuFormatElementBits32 = 4, 486 UvmRmGpuFormatElementBits64 = 5, 487 UvmRmGpuFormatElementBits128 = 6, 488 UvmRmGpuFormatElementBitsCount = 7 489 } UvmRmGpuFormatElementBits; 490 491 // UVM GPU Compression types 492 typedef enum { 493 UvmRmGpuCompressionTypeDefault = 0, 494 UvmRmGpuCompressionTypeEnabledNoPlc = 1, 495 UvmRmGpuCompressionTypeCount = 2 496 } UvmRmGpuCompressionType; 497 498 typedef struct UvmGpuExternalMappingInfo_tag 499 { 500 // In: GPU caching ability. 501 UvmRmGpuCachingType cachingType; 502 503 // In: Virtual permissions. 504 UvmRmGpuMappingType mappingType; 505 506 // In: RM virtual mapping memory format 507 UvmRmGpuFormatType formatType; 508 509 // In: RM virtual mapping element bits 510 UvmRmGpuFormatElementBits elementBits; 511 512 // In: RM virtual compression type 513 UvmRmGpuCompressionType compressionType; 514 515 // In: Size of the buffer to store PTEs (in bytes). 516 NvU64 pteBufferSize; 517 518 // In: Page size for mapping 519 // If this field is passed as 0, the page size 520 // of the allocation is used for mapping. 521 // nvUvmInterfaceGetExternalAllocPtes must pass 522 // this field as zero. 523 NvU64 mappingPageSize; 524 525 // In: Pointer to a buffer to store PTEs. 526 // Out: The interface will fill the buffer with PTEs 527 NvU64 *pteBuffer; 528 529 // Out: Number of PTEs filled in to the buffer. 530 NvU64 numWrittenPtes; 531 532 // Out: Number of PTEs remaining to be filled 533 // if the buffer is not sufficient to accommodate 534 // requested PTEs. 535 NvU64 numRemainingPtes; 536 537 // Out: PTE size (in bytes) 538 NvU32 pteSize; 539 } UvmGpuExternalMappingInfo; 540 541 typedef struct UvmGpuP2PCapsParams_tag 542 { 543 // Out: peerId[i] contains gpu[i]'s peer id of gpu[1 - i]. Only defined if 544 // the GPUs are direct peers. 545 NvU32 peerIds[2]; 546 547 // Out: UVM_LINK_TYPE 548 NvU32 p2pLink; 549 550 // Out: optimalNvlinkWriteCEs[i] contains gpu[i]'s optimal CE for writing to 551 // gpu[1 - i]. The CE indexes are valid only if the GPUs are NVLink peers. 552 // 553 // The value returned by RM for this field may change when a GPU is 554 // registered with RM for the first time, so UVM needs to query it again 555 // each time a GPU is registered. 556 NvU32 optimalNvlinkWriteCEs[2]; 557 558 // Out: Maximum unidirectional bandwidth between the peers in megabytes per 559 // second, not taking into account the protocols overhead. The reported 560 // bandwidth for indirect peers is zero. 561 NvU32 totalLinkLineRateMBps; 562 563 // Out: True if the peers have a indirect link to communicate. On P9 564 // systems, this is true if peers are connected to different NPUs that 565 // forward the requests between them. 566 NvU32 indirectAccess : 1; 567 } UvmGpuP2PCapsParams; 568 569 // Platform-wide information 570 typedef struct UvmPlatformInfo_tag 571 { 572 // Out: ATS (Address Translation Services) is supported 573 NvBool atsSupported; 574 575 // Out: AMD SEV (Secure Encrypted Virtualization) is enabled 576 NvBool sevEnabled; 577 } UvmPlatformInfo; 578 579 typedef struct UvmGpuClientInfo_tag 580 { 581 NvHandle hClient; 582 583 NvHandle hSmcPartRef; 584 } UvmGpuClientInfo; 585 586 typedef enum 587 { 588 UVM_GPU_CONF_COMPUTE_MODE_NONE, 589 UVM_GPU_CONF_COMPUTE_MODE_APM, 590 UVM_GPU_CONF_COMPUTE_MODE_HCC, 591 UVM_GPU_CONF_COMPUTE_MODE_COUNT 592 } UvmGpuConfComputeMode; 593 594 typedef struct UvmGpuConfComputeCaps_tag 595 { 596 // Out: GPU's confidential compute mode 597 UvmGpuConfComputeMode mode; 598 } UvmGpuConfComputeCaps; 599 600 #define UVM_GPU_NAME_LENGTH 0x40 601 602 typedef struct UvmGpuInfo_tag 603 { 604 // Printable gpu name 605 char name[UVM_GPU_NAME_LENGTH]; 606 607 // Uuid of this gpu 608 NvProcessorUuid uuid; 609 610 // Gpu architecture; NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_* 611 NvU32 gpuArch; 612 613 // Gpu implementation; NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_* 614 NvU32 gpuImplementation; 615 616 // Host (gpfifo) class; *_CHANNEL_GPFIFO_*, e.g. KEPLER_CHANNEL_GPFIFO_A 617 NvU32 hostClass; 618 619 // Copy engine (dma) class; *_DMA_COPY_*, e.g. KEPLER_DMA_COPY_A 620 NvU32 ceClass; 621 622 // Compute class; *_COMPUTE_*, e.g. KEPLER_COMPUTE_A 623 NvU32 computeClass; 624 625 // Set if GPU supports TCC Mode & is in TCC mode. 626 NvBool gpuInTcc; 627 628 // Number of subdevices in SLI group. 629 NvU32 subdeviceCount; 630 631 // Virtualization mode of this gpu. 632 NvU32 virtMode; // UVM_VIRT_MODE 633 634 // NV_TRUE if this is a simulated/emulated GPU. NV_FALSE, otherwise. 635 NvBool isSimulated; 636 637 // Number of GPCs 638 // If SMC is enabled, this is the currently configured number of GPCs for 639 // the given partition (also see the smcSwizzId field below). 640 NvU32 gpcCount; 641 642 // Maximum number of GPCs; NV_SCAL_LITTER_NUM_GPCS 643 // This number is independent of the partition configuration, and can be 644 // used to conservatively size GPU-global constructs. 645 NvU32 maxGpcCount; 646 647 // Number of TPCs 648 NvU32 tpcCount; 649 650 // Maximum number of TPCs per GPC 651 NvU32 maxTpcPerGpcCount; 652 653 // NV_TRUE if SMC is enabled on this GPU. 654 NvBool smcEnabled; 655 656 // SMC partition ID (unique per GPU); note: valid when first looked up in 657 // nvUvmInterfaceGetGpuInfo(), but not guaranteed to remain valid. 658 // nvUvmInterfaceDeviceCreate() re-verifies the swizzId and fails if it is 659 // no longer valid. 660 NvU32 smcSwizzId; 661 662 UvmGpuClientInfo smcUserClientInfo; 663 664 // Confidential Compute capabilities of this GPU 665 UvmGpuConfComputeCaps gpuConfComputeCaps; 666 667 // UVM_LINK_TYPE 668 NvU32 sysmemLink; 669 670 // See UvmGpuP2PCapsParams::totalLinkLineRateMBps 671 NvU32 sysmemLinkRateMBps; 672 673 // On coherent systems each GPU maps its memory to a window in the System 674 // Physical Address (SPA) space. The following fields describe that window. 675 // 676 // systemMemoryWindowSize > 0 indicates that the window is valid. meaning 677 // that GPU memory can be mapped by the CPU as cache-coherent by adding the 678 // GPU address to the window start. 679 NvU64 systemMemoryWindowStart; 680 NvU64 systemMemoryWindowSize; 681 682 // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch 683 // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, 684 // nvswitchMemoryWindowStart tells the base address for the GPU in the 685 // NVSwitch address space. It is used when creating PTEs of memory mappings 686 // to NVSwitch peers. 687 NvBool connectedToSwitch; 688 NvU64 nvswitchMemoryWindowStart; 689 690 // local EGM properties 691 NvBool egmEnabled; 692 NvU8 egmPeerId; 693 } UvmGpuInfo; 694 695 typedef struct UvmGpuFbInfo_tag 696 { 697 // Max physical address that can be allocated by UVM. This excludes internal 698 // RM regions that are not registered with PMA either. 699 NvU64 maxAllocatableAddress; 700 701 NvU32 heapSize; // RAM in KB available for user allocations 702 NvU32 reservedHeapSize; // RAM in KB reserved for internal RM allocation 703 NvBool bZeroFb; // Zero FB mode enabled. 704 } UvmGpuFbInfo; 705 706 typedef struct UvmGpuEccInfo_tag 707 { 708 unsigned eccMask; 709 unsigned eccOffset; 710 void *eccReadLocation; 711 NvBool *eccErrorNotifier; 712 NvBool bEccEnabled; 713 } UvmGpuEccInfo; 714 715 typedef struct UvmPmaAllocationOptions_tag 716 { 717 NvU32 flags; 718 NvU32 minimumSpeed; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_MININUM_SPEED 719 NvU64 physBegin, physEnd; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_ADDRESS_RANGE 720 NvU32 regionId; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_REGION_ID 721 NvU64 alignment; // valid if flags & UVM_PMA_ALLOCATE_FORCE_ALIGNMENT 722 NvLength numPagesAllocated; // valid if flags & UVM_PMA_ALLOCATE_ALLOW_PARTIAL 723 724 NvU32 resultFlags; // valid if the allocation function returns NV_OK 725 } UvmPmaAllocationOptions; 726 727 // 728 // Mirrored in PMA (PMA_STATS) 729 // 730 typedef struct UvmPmaStatistics_tag 731 { 732 volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions 733 volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions 734 volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions 735 volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory 736 volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory 737 volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory 738 } UvmPmaStatistics; 739 740 /******************************************************************************* 741 uvmEventSuspend 742 This function will be called by the GPU driver to signal to UVM that the 743 system is about to enter a sleep state. When it is called, the 744 following assumptions/guarantees are valid/made: 745 746 * User channels have been preempted and disabled 747 * UVM channels are still running normally and will continue to do 748 so until after this function returns control 749 * User threads are still running, but can no longer issue system 750 system calls to the GPU driver 751 * Until exit from this function, UVM is allowed to make full use of 752 the GPUs under its control, as well as of the GPU driver 753 754 Upon return from this function, UVM may not access GPUs under its control 755 until the GPU driver calls uvmEventResume(). It may still receive 756 calls to uvmEventIsrTopHalf() during this time, which it should return 757 NV_ERR_NO_INTR_PENDING from. It will not receive any other calls. 758 */ 759 typedef NV_STATUS (*uvmEventSuspend_t) (void); 760 761 /******************************************************************************* 762 uvmEventResume 763 This function will be called by the GPU driver to signal to UVM that the 764 system has exited a previously entered sleep state. When it is called, 765 the following assumptions/guarantees are valid/made: 766 767 * UVM is again allowed to make full use of the GPUs under its 768 control, as well as of the GPU driver 769 * UVM channels are running normally 770 * User channels are still preempted and disabled 771 * User threads are again running, but still cannot issue system 772 calls to the GPU driver, nor submit new work 773 774 Upon return from this function, UVM is expected to be fully functional. 775 */ 776 typedef NV_STATUS (*uvmEventResume_t) (void); 777 778 /******************************************************************************* 779 uvmEventStartDevice 780 This function will be called by the GPU driver once it has finished its 781 initialization to tell the UVM driver that this GPU has come up. 782 */ 783 typedef NV_STATUS (*uvmEventStartDevice_t) (const NvProcessorUuid *pGpuUuidStruct); 784 785 /******************************************************************************* 786 uvmEventStopDevice 787 This function will be called by the GPU driver to let UVM know that a GPU 788 is going down. 789 */ 790 typedef NV_STATUS (*uvmEventStopDevice_t) (const NvProcessorUuid *pGpuUuidStruct); 791 792 /******************************************************************************* 793 uvmEventIsrTopHalf_t 794 This function will be called by the GPU driver to let UVM know 795 that an interrupt has occurred. 796 797 Returns: 798 NV_OK if the UVM driver handled the interrupt 799 NV_ERR_NO_INTR_PENDING if the interrupt is not for the UVM driver 800 */ 801 #if defined (__linux__) 802 typedef NV_STATUS (*uvmEventIsrTopHalf_t) (const NvProcessorUuid *pGpuUuidStruct); 803 #else 804 typedef void (*uvmEventIsrTopHalf_t) (void); 805 #endif 806 807 struct UvmOpsUvmEvents 808 { 809 uvmEventSuspend_t suspend; 810 uvmEventResume_t resume; 811 uvmEventStartDevice_t startDevice; 812 uvmEventStopDevice_t stopDevice; 813 uvmEventIsrTopHalf_t isrTopHalf; 814 }; 815 816 #define UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES 32 817 #define UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES 16 818 819 typedef union UvmFaultMetadataPacket_tag 820 { 821 struct { 822 NvU8 authTag[UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES]; 823 NvBool valid; 824 }; 825 // padding to 32Bytes 826 NvU8 _padding[32]; 827 } UvmFaultMetadataPacket; 828 829 // This struct shall not be accessed nor modified directly by UVM as it is 830 // entirely managed by the RM layer 831 typedef struct UvmCslContext_tag 832 { 833 struct ccslContext_t *ctx; 834 void *nvidia_stack; 835 } UvmCslContext; 836 837 typedef struct UvmGpuFaultInfo_tag 838 { 839 struct 840 { 841 // Fault buffer GET register mapping. 842 // 843 // When Confidential Computing is enabled, GET refers to the shadow 844 // buffer (see bufferAddress below), and not to the actual HW buffer. 845 // In this setup, writes of GET (by UVM) do not result on re-evaluation 846 // of any interrupt condition. 847 volatile NvU32* pFaultBufferGet; 848 849 // Fault buffer PUT register mapping. 850 // 851 // When Confidential Computing is enabled, PUT refers to the shadow 852 // buffer (see bufferAddress below), and not to the actual HW buffer. 853 // In this setup, writes of PUT (by GSP-RM) do not result on 854 // re-evaluation of any interrupt condition. 855 volatile NvU32* pFaultBufferPut; 856 857 // Note: this variable is deprecated since buffer overflow is not a 858 // separate register from future chips. 859 volatile NvU32* pFaultBufferInfo; 860 861 // Register mapping used to clear a replayable fault interrupt in 862 // Turing+ GPUs. 863 volatile NvU32* pPmcIntr; 864 865 // Register mapping used to enable replayable fault interrupts. 866 volatile NvU32* pPmcIntrEnSet; 867 868 // Register mapping used to disable replayable fault interrupts. 869 volatile NvU32* pPmcIntrEnClear; 870 871 // Register used to enable, or disable, faults on prefetches. 872 volatile NvU32* pPrefetchCtrl; 873 874 // Replayable fault interrupt mask identifier. 875 NvU32 replayableFaultMask; 876 877 // Fault buffer CPU mapping 878 void* bufferAddress; 879 // 880 // When Confidential Computing is disabled, the mapping points to the 881 // actual HW fault buffer. 882 // 883 // When Confidential Computing is enabled, the mapping points to a 884 // copy of the HW fault buffer. This "shadow buffer" is maintained 885 // by GSP-RM. 886 887 // Size, in bytes, of the fault buffer pointed by bufferAddress. 888 NvU32 bufferSize; 889 // Mapping pointing to the start of the fault buffer metadata containing 890 // a 16Byte authentication tag and a valid byte. Always NULL when 891 // Confidential Computing is disabled. 892 UvmFaultMetadataPacket *bufferMetadata; 893 894 // CSL context used for performing decryption of replayable faults when 895 // Confidential Computing is enabled. 896 UvmCslContext cslCtx; 897 898 // Indicates whether UVM owns the replayable fault buffer. 899 // The value of this field is always NV_TRUE When Confidential Computing 900 // is disabled. 901 NvBool bUvmOwnsHwFaultBuffer; 902 } replayable; 903 struct 904 { 905 // Shadow buffer for non-replayable faults on cpu memory. Resman copies 906 // here the non-replayable faults that need to be handled by UVM 907 void* shadowBufferAddress; 908 909 // Execution context for the queue associated with the fault buffer 910 void* shadowBufferContext; 911 912 // Fault buffer size 913 NvU32 bufferSize; 914 915 // Preallocated stack for functions called from the UVM isr top half 916 void *isr_sp; 917 918 // Preallocated stack for functions called from the UVM isr bottom half 919 void *isr_bh_sp; 920 921 // Used only when Hopper Confidential Compute is enabled 922 // Register mappings obtained from RM 923 volatile NvU32* pFaultBufferPut; 924 925 // Used only when Hopper Confidential Compute is enabled 926 // Cached get index of the non-replayable shadow buffer 927 NvU32 shadowBufferGet; 928 929 // See replayable.bufferMetadata 930 UvmFaultMetadataPacket *shadowBufferMetadata; 931 } nonReplayable; 932 NvHandle faultBufferHandle; 933 struct Device *pDevice; 934 } UvmGpuFaultInfo; 935 936 struct Device; 937 938 typedef struct UvmGpuPagingChannel_tag 939 { 940 struct gpuDevice *device; 941 NvNotification *errorNotifier; 942 NvHandle channelHandle; 943 NvHandle errorNotifierHandle; 944 void *pushStreamSp; 945 struct Device *pDevice; 946 } UvmGpuPagingChannel, *UvmGpuPagingChannelHandle; 947 948 typedef struct UvmGpuAccessCntrInfo_tag 949 { 950 // Register mappings obtained from RM 951 // pointer to the Get register for the access counter buffer 952 volatile NvU32* pAccessCntrBufferGet; 953 // pointer to the Put register for the access counter buffer 954 volatile NvU32* pAccessCntrBufferPut; 955 // pointer to the Full register for the access counter buffer 956 volatile NvU32* pAccessCntrBufferFull; 957 // pointer to the hub interrupt 958 volatile NvU32* pHubIntr; 959 // pointer to interrupt enable register 960 volatile NvU32* pHubIntrEnSet; 961 // pointer to interrupt disable register 962 volatile NvU32* pHubIntrEnClear; 963 // mask for the access counter buffer 964 NvU32 accessCounterMask; 965 // access counter buffer cpu mapping and size 966 void* bufferAddress; 967 NvU32 bufferSize; 968 NvHandle accessCntrBufferHandle; 969 } UvmGpuAccessCntrInfo; 970 971 typedef enum 972 { 973 UVM_ACCESS_COUNTER_GRANULARITY_64K = 1, 974 UVM_ACCESS_COUNTER_GRANULARITY_2M = 2, 975 UVM_ACCESS_COUNTER_GRANULARITY_16M = 3, 976 UVM_ACCESS_COUNTER_GRANULARITY_16G = 4, 977 } UVM_ACCESS_COUNTER_GRANULARITY; 978 979 typedef enum 980 { 981 UVM_ACCESS_COUNTER_USE_LIMIT_NONE = 1, 982 UVM_ACCESS_COUNTER_USE_LIMIT_QTR = 2, 983 UVM_ACCESS_COUNTER_USE_LIMIT_HALF = 3, 984 UVM_ACCESS_COUNTER_USE_LIMIT_FULL = 4, 985 } UVM_ACCESS_COUNTER_USE_LIMIT; 986 987 typedef struct UvmGpuAccessCntrConfig_tag 988 { 989 NvU32 mimcGranularity; 990 991 NvU32 momcGranularity; 992 993 NvU32 mimcUseLimit; 994 995 NvU32 momcUseLimit; 996 997 NvU32 threshold; 998 } UvmGpuAccessCntrConfig; 999 1000 // 1001 // When modifying this enum, make sure they are compatible with the mirrored 1002 // MEMORY_PROTECTION enum in phys_mem_allocator.h. 1003 // 1004 typedef enum UvmPmaGpuMemoryType_tag 1005 { 1006 UVM_PMA_GPU_MEMORY_TYPE_UNPROTECTED = 0, 1007 UVM_PMA_GPU_MEMORY_TYPE_PROTECTED = 1 1008 } UVM_PMA_GPU_MEMORY_TYPE; 1009 1010 typedef UvmGpuChannelInfo gpuChannelInfo; 1011 typedef UvmGpuTsgAllocParams gpuTsgAllocParams; 1012 typedef UvmGpuChannelAllocParams gpuChannelAllocParams; 1013 typedef UvmGpuCaps gpuCaps; 1014 typedef UvmGpuCopyEngineCaps gpuCeCaps; 1015 typedef UvmGpuCopyEnginesCaps gpuCesCaps; 1016 typedef UvmGpuP2PCapsParams getP2PCapsParams; 1017 typedef UvmGpuAddressSpaceInfo gpuAddressSpaceInfo; 1018 typedef UvmGpuAllocInfo gpuAllocInfo; 1019 typedef UvmGpuInfo gpuInfo; 1020 typedef UvmGpuClientInfo gpuClientInfo; 1021 typedef UvmGpuAccessCntrInfo gpuAccessCntrInfo; 1022 typedef UvmGpuAccessCntrConfig gpuAccessCntrConfig; 1023 typedef UvmGpuFaultInfo gpuFaultInfo; 1024 typedef UvmGpuMemoryInfo gpuMemoryInfo; 1025 typedef UvmGpuExternalMappingInfo gpuExternalMappingInfo; 1026 typedef UvmGpuChannelResourceInfo gpuChannelResourceInfo; 1027 typedef UvmGpuChannelInstanceInfo gpuChannelInstanceInfo; 1028 typedef UvmGpuChannelResourceBindParams gpuChannelResourceBindParams; 1029 typedef UvmGpuFbInfo gpuFbInfo; 1030 typedef UvmGpuEccInfo gpuEccInfo; 1031 typedef UvmGpuPagingChannel *gpuPagingChannelHandle; 1032 typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo; 1033 typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams; 1034 typedef UvmPmaAllocationOptions gpuPmaAllocationOptions; 1035 1036 typedef struct UvmCslIv 1037 { 1038 NvU8 iv[12]; 1039 NvU8 fresh; 1040 } UvmCslIv; 1041 1042 typedef enum UvmCslOperation 1043 { 1044 UVM_CSL_OPERATION_ENCRYPT, 1045 UVM_CSL_OPERATION_DECRYPT 1046 } UvmCslOperation; 1047 1048 #endif // _NV_UVM_TYPES_H_ 1049