1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /* 25 * IMPORTANT NOTE: 26 * This file contains C functions shared between resman and plugin. 27 * Make sure that this file is included only once in resman and only once in plugin code. 28 * Else, make sure that all the functions in this file are static functions. 29 */ 30 31 /* 32 * The structures and functions are used in below sequence: 33 * 34 * Some call is made from guest RM to the RPC framework in RM. 35 * Step 1. Guest RM : copies the parameters from guest SDK structures to RPC structures (serialization) 36 * Step 2. Plugin : copies the parameters from RPC structures to host SDK structures (de-serialization) 37 * (Host RM side operations, like RM control, alloc, free etc.) 38 * Step 3. Plugin : copies the parameters from host SDK structures to RPC structures (serialization) 39 * Step 4. Guest RM : copies the parameters from RPC structures to guest SDK structures (de-serialization) 40 * The data is returned to the caller. 41 */ 42 43 /* 44 * Copy DMA Control Parameters structure element by element. 45 * Depending upon the cmd, copy parameters from pParams to params_in 46 */ 47 48 #include "ctrl/ctrl208f/ctrl208fdma.h" // NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS 49 #include "ctrl/ctrla16f.h" // NVA16F_CTRL_GET_CLASS_ENGINEID 50 #include "ctrl/ctrl90e6.h" // NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK 51 #include "ctrl/ctrl90f1.h" 52 #include "ctrl/ctrl90cd.h" 53 #include "ctrl/ctrl0080.h" 54 #include "nvctassert.h" 55 56 // Copy elements from RPC structures to SDK structures (Step 2 or step 4 listed above) 57 #ifdef VMIOP_BUILD 58 typedef vmiop_error_t return_t; 59 #define serialize_deserialize(u) serialize_##u##_HAL 60 #define getIpVersion() pObjRpcStructureCopy->ipVersion 61 #define SUCCESS_T vmiop_success 62 #define FAILURE_T vmiop_error_inval 63 #define COPY_INPUT_PARAMETERS 64 #if VMIOPLUGINCFG_FEATURE_ENABLED(PLATFORM_LDDM) 65 #define UMED_BUILD 66 #endif 67 #endif 68 69 #ifdef RESMAN_BUILD 70 typedef NV_STATUS return_t; 71 #define serialize_deserialize(u) deserialize_##u##_HAL 72 #define getIpVersion() pObjRpcStructureCopy->__nvoc_pbase_Object->ipVersion 73 #define SUCCESS_T NV_OK 74 #define FAILURE_T NV_ERR_INVALID_ARGUMENT 75 #define COPY_OUTPUT_PARAMETERS 76 #endif 77 78 #ifdef GSP_FW_BUILD 79 typedef NV_STATUS return_t; 80 #define SUCCESS_T NV_OK 81 #define FAILURE_T NV_ERR_INVALID_ARGUMENT 82 #define COPY_INPUT_PARAMETERS 83 #define vmiop_assert NV_ASSERT 84 #endif 85 86 #define NV_ADDR_UNKNOWN 0 // Address space is unknown 87 #define NV_ADDR_SYSMEM 1 // System memory (PCI) 88 #define NV_ADDR_FBMEM 2 // Frame buffer memory space 89 #define NV_ADDR_REGMEM 3 // NV register memory space 90 #define NV_ADDR_VIRTUAL 4 // Virtual address space only 91 #define NV_ADDR_FABRIC 5 // Multi-node fabric address space 92 93 #define NV2080_NOTIFIERS_MAXCOUNT_R525 178 94 #define NV2080_NOTIFIERS_MAXCOUNT_R470 162 95 96 #define NV_CHECK_AND_ALIGN_OFFSET(offset, bAlign) { \ 97 if (bAlign) { \ 98 offset = NV_ALIGN_UP(offset, sizeof(NvU64)); \ 99 } \ 100 } 101 102 #ifndef GSP_FW_BUILD 103 #ifdef BUILD_COMMON_RPCS 104 105 static 106 return_t deserialize_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01(NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams, 107 NvU8 *buffer, 108 NvU32 bufferSize, 109 NvU32 *offset) 110 { 111 #ifdef COPY_INPUT_PARAMETERS 112 NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 *src = (void*)(buffer); 113 NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *dest = pParams; 114 115 if (dest && src) { 116 dest->hResolution = src->hResolution; 117 dest->vResolution = src->vResolution; 118 dest->averageEncodeLatency = src->averageEncodeLatency; 119 dest->averageEncodeFps = src->averageEncodeFps; 120 dest->timestampBufferSize = 0; 121 } 122 else 123 return FAILURE_T; 124 #endif 125 return SUCCESS_T; 126 } 127 128 static 129 return_t deserialize_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01(NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *pParams, 130 NvU8 *buffer, 131 NvU32 bufferSize, 132 NvU32 *offset) 133 { 134 #ifdef COPY_INPUT_PARAMETERS 135 NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 *src = (void*)(buffer); 136 NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *dest = pParams; 137 138 if (src && dest) { 139 #ifdef VMIOP_BUILD 140 dest->engineID = deserialize_engineType(src->engineID); 141 #else 142 dest->engineID = src->engineID; 143 #endif 144 dest->subdeviceInstance = src->subdeviceInstance; 145 dest->resetReason = src->resetReason; 146 } 147 else 148 return FAILURE_T; 149 #endif 150 return SUCCESS_T; 151 } 152 153 static 154 return_t deserialize_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00(NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *pParams, 155 NvU8 *buffer, 156 NvU32 bufferSize, 157 NvU32 *offset) 158 { 159 NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 *src = (void*)(buffer); 160 NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *dest = pParams; 161 162 if (src && dest) { 163 dest->exceptType = src->exceptType; 164 #ifdef VMIOP_BUILD 165 dest->engineID = deserialize_engineType(src->engineID); 166 #else 167 dest->engineID = src->engineID; 168 #endif 169 } 170 else 171 return FAILURE_T; 172 173 return SUCCESS_T; 174 } 175 176 static 177 return_t deserialize_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09(NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *pParams, 178 NvU8 *buffer, 179 NvU32 bufferSize, 180 NvU32 *offset) 181 { 182 #ifdef COPY_INPUT_PARAMETERS 183 NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 *src = (void*)(buffer); 184 NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *dest = pParams; 185 186 if (src && dest) { 187 dest->faultType = src->faultType; 188 } 189 else 190 return FAILURE_T; 191 #endif 192 return SUCCESS_T; 193 } 194 195 static 196 return_t deserialize_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00(NV2080_CTRL_PERF_BOOST_PARAMS *pParams, 197 NvU8 *buffer, 198 NvU32 bufferSize, 199 NvU32 *offset) 200 { 201 NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 *src = (void*)(buffer); 202 NV2080_CTRL_PERF_BOOST_PARAMS *dest = pParams; 203 204 if (src && dest) { 205 dest->flags = src->flags; 206 dest->duration = src->duration; 207 } 208 else 209 return FAILURE_T; 210 211 return SUCCESS_T; 212 } 213 214 static 215 return_t deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *pParams, 216 NvU8 *buffer, 217 NvU32 bufferSize, 218 NvU32 *offset) 219 { 220 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 *src = (void*)(buffer); 221 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *dest = pParams; 222 223 if (src && dest) { 224 NvU32 i; 225 for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { 226 dest->value.colorFB[i] = src->value.colorFB[i]; 227 dest->value.colorDS[i] = src->value.colorDS[i]; 228 } 229 dest->value.depth = src->value.depth; 230 dest->value.stencil = src->value.stencil; // Changed in v04_00 231 dest->indexSize = src->indexSize; 232 dest->indexUsed = src->indexUsed; 233 dest->format = src->format; 234 dest->valType = src->valType; 235 } 236 else 237 return FAILURE_T; 238 239 return SUCCESS_T; 240 } 241 242 static 243 return_t deserialize_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *pParams, 244 NvU8 *buffer, 245 NvU32 bufferSize, 246 NvU32 *offset) 247 { 248 NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 *src = (void*)(buffer); 249 NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *dest = pParams; 250 251 if (src && dest) { 252 NvU32 i; 253 for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { 254 dest->colorFB[i] = src->colorFB[i]; 255 dest->colorDS[i] = src->colorDS[i]; 256 } 257 dest->format = src->format; 258 } 259 else 260 return FAILURE_T; 261 262 return SUCCESS_T; 263 } 264 265 static 266 return_t deserialize_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *pParams, 267 NvU8 *buffer, 268 NvU32 bufferSize, 269 NvU32 *offset) 270 { 271 NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 *src = (void*)(buffer); 272 NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *dest = pParams; 273 274 if (src && dest) { 275 dest->depth = src->depth; 276 dest->format = src->format; 277 } 278 else 279 return FAILURE_T; 280 281 return SUCCESS_T; 282 } 283 284 static 285 return_t deserialize_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *pParams, 286 NvU8 *buffer, 287 NvU32 bufferSize, 288 NvU32 *offset) 289 { 290 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 *src = (void*)(buffer); 291 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *dest = pParams; 292 293 if (src && dest) { 294 dest->bEnable = src->bEnable; 295 } 296 else 297 return FAILURE_T; 298 299 return SUCCESS_T; 300 } 301 302 static 303 return_t deserialize_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00(NVA06C_CTRL_TIMESLICE_PARAMS *pParams, 304 NvU8 *buffer, 305 NvU32 bufferSize, 306 NvU32 *offset) 307 { 308 NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 *src = (void*)(buffer); 309 NVA06C_CTRL_TIMESLICE_PARAMS *dest = pParams; 310 311 if (src && dest) { 312 dest->timesliceUs = src->timesliceUs; 313 } 314 else 315 return FAILURE_T; 316 317 return SUCCESS_T; 318 } 319 320 static 321 return_t deserialize_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *pParams, 322 NvU8 *buffer, 323 NvU32 bufferSize, 324 NvU32 *offset) 325 { 326 #ifdef COPY_INPUT_PARAMETERS 327 NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 *src = (void*)(buffer); 328 NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *dest = pParams; 329 NvU32 i; 330 331 if (src && dest) { 332 if (src->numChannels > NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES) { 333 return FAILURE_T; 334 } 335 336 dest->bDisable = src->bDisable; 337 dest->numChannels = src->numChannels; 338 dest->bOnlyDisableScheduling = src->bOnlyDisableScheduling; 339 dest->bRewindGpPut = src->bRewindGpPut; 340 dest->pRunlistPreemptEvent = NULL; // vGPU do not support guest kernel handles 341 342 for (i = 0; i < src->numChannels ; i++) 343 { 344 dest->hClientList[i] = src->hClientList[i]; 345 dest->hChannelList[i] = src->hChannelList[i]; 346 } 347 } 348 else 349 return FAILURE_T; 350 #endif 351 return SUCCESS_T; 352 } 353 354 static 355 return_t deserialize_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A(NVA06C_CTRL_PREEMPT_PARAMS *pParams, 356 NvU8 *buffer, 357 NvU32 bufferSize, 358 NvU32 *offset) 359 { 360 #ifdef COPY_INPUT_PARAMETERS 361 NVA06C_CTRL_PREEMPT_PARAMS_v09_0A *src = (void*)(buffer); 362 NVA06C_CTRL_PREEMPT_PARAMS *dest = pParams; 363 364 if (src && dest) { 365 dest->bWait = src->bWait; 366 dest->bManualTimeout = src->bManualTimeout; 367 dest->timeoutUs = src->timeoutUs; 368 } 369 else 370 return FAILURE_T; 371 #endif 372 return SUCCESS_T; 373 } 374 375 static 376 return_t deserialize_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams, 377 NvU8 *buffer, 378 NvU32 bufferSize, 379 NvU32 *offset) 380 { 381 #ifdef COPY_INPUT_PARAMETERS 382 NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *src = (void*)(buffer); 383 NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *dest = pParams; 384 385 if (src && dest) { 386 dest->tsgInterleaveLevel = src->tsgInterleaveLevel; 387 } 388 else 389 return FAILURE_T; 390 #endif 391 return SUCCESS_T; 392 } 393 394 static 395 return_t deserialize_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams, 396 NvU8 *buffer, 397 NvU32 bufferSize, 398 NvU32 *offset) 399 { 400 #ifdef COPY_INPUT_PARAMETERS 401 NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *src = (void*)(buffer); 402 NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *dest = pParams; 403 404 if (src && dest) { 405 dest->channelInterleaveLevel = src->channelInterleaveLevel; 406 } 407 else 408 return FAILURE_T; 409 #endif 410 return SUCCESS_T; 411 } 412 413 static 414 return_t deserialize_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *pParams, 415 NvU8 *buffer, 416 NvU32 bufferSize, 417 NvU32 *offset) 418 { 419 #ifdef COPY_INPUT_PARAMETERS 420 NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 *src = (void*)(buffer); 421 NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *dest = pParams; 422 423 if (src && dest) { 424 NvU32 i; 425 426 dest->flags = src->flags; 427 dest->hClient = src->hClient; 428 dest->hChannel = src->hChannel; 429 for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END; ++i) 430 dest->vMemPtrs[i] = src->vMemPtrs[i]; 431 dest->gfxpPreemptMode = src->gfxpPreemptMode; 432 dest->cilpPreemptMode = src->cilpPreemptMode; 433 dest->grRouteInfo.flags = src->grRouteInfo.flags; 434 dest->grRouteInfo.route = src->grRouteInfo.route; 435 } 436 else 437 return FAILURE_T; 438 #endif 439 return SUCCESS_T; 440 } 441 442 static 443 return_t deserialize_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01(NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *pParams, 444 NvU8 *buffer, 445 NvU32 bufferSize, 446 NvU32 *offset) 447 { 448 #ifdef COPY_INPUT_PARAMETERS 449 NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 *src = (void*)(buffer); 450 NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *dest = pParams; 451 452 if (src && dest) { 453 dest->flags = src->flags; 454 dest->hChannel = src->hChannel; 455 dest->gfxpPreemptMode = src->gfxpPreemptMode; 456 dest->cilpPreemptMode = src->cilpPreemptMode; 457 dest->grRouteInfo.flags = src->grRouteInfo.flags; 458 dest->grRouteInfo.route = src->grRouteInfo.route; 459 } 460 else 461 return FAILURE_T; 462 #endif 463 return SUCCESS_T; 464 } 465 466 static 467 return_t deserialize_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *pParams, 468 NvU8 *buffer, 469 NvU32 bufferSize, 470 NvU32 *offset) 471 { 472 NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 *src = (void*)(buffer); 473 NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *dest = pParams; 474 475 if (src && dest) { 476 dest->hClient = src->hClient; 477 dest->hChannel = src->hChannel; 478 dest->vMemPtr = src->vMemPtr; 479 dest->zcullMode = src->zcullMode; 480 } 481 else 482 return FAILURE_T; 483 484 return SUCCESS_T; 485 } 486 487 static 488 return_t deserialize_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *pParams, 489 NvU8 *buffer, 490 NvU32 bufferSize, 491 NvU32 *offset) 492 { 493 #ifdef COPY_INPUT_PARAMETERS 494 NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 *src = (void*)(buffer); 495 NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *dest = pParams; 496 497 if (src && dest) { 498 #ifdef VMIOP_BUILD 499 dest->engineType = deserialize_engineType(src->engineType); 500 #else 501 dest->engineType = src->engineType; 502 #endif 503 dest->hClient = src->hClient; 504 dest->ChID = src->ChID; 505 dest->hChanClient = src->hChanClient; 506 dest->hObject = src->hObject; 507 dest->hVirtMemory = src->hVirtMemory; 508 dest->physAddress = src->physAddress; 509 dest->physAttr = src->physAttr; 510 dest->hDmaHandle = src->hDmaHandle; 511 dest->index = src->index; 512 dest->size = src->size; 513 } 514 else 515 return FAILURE_T; 516 #endif 517 return SUCCESS_T; 518 } 519 520 static 521 return_t deserialize_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pParams, 522 NvU8 *buffer, 523 NvU32 bufferSize, 524 NvU32 *offset) 525 { 526 #ifdef COPY_INPUT_PARAMETERS 527 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 *src = (void*)(buffer); 528 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *dest = pParams; 529 530 if (src && dest) { 531 NvU32 i; 532 533 if (src->numLevelsToCopy > GMMU_FMT_MAX_LEVELS_v1A_12) { 534 return FAILURE_T; 535 } 536 537 dest->hSubDevice = src->hSubDevice; 538 dest->subDeviceId = src->subDeviceId; 539 dest->pageSize = src->pageSize; 540 dest->virtAddrLo = src->virtAddrLo; 541 dest->virtAddrHi = src->virtAddrHi; 542 dest->numLevelsToCopy = src->numLevelsToCopy; 543 544 for (i = 0; i < dest->numLevelsToCopy; i++) 545 { 546 dest->levels[i].physAddress = src->levels[i].physAddress; 547 dest->levels[i].aperture = src->levels[i].aperture; 548 dest->levels[i].size = src->levels[i].size; 549 dest->levels[i].pageShift = src->levels[i].pageShift; 550 } 551 } 552 else 553 return FAILURE_T; 554 #endif 555 return SUCCESS_T; 556 } 557 #endif 558 559 #ifdef BUILD_LEGACY_RPCS 560 #endif 561 562 #ifdef BUILD_COMMON_RPCS 563 564 static 565 return_t deserialize_GET_BRAND_CAPS_v25_12(NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *pParams, 566 NvU8 *buffer, 567 NvU32 bufferSize, 568 NvU32 *offset) 569 { 570 #ifdef COPY_OUTPUT_PARAMETERS 571 rpc_get_brand_caps_v25_12 *src = (void*)(buffer); 572 NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *dest = pParams; 573 574 if (src && dest) { 575 dest->brands = src->brands; 576 } 577 else 578 return FAILURE_T; 579 #endif 580 581 return SUCCESS_T; 582 } 583 584 static 585 return_t deserialize_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01(NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *pParams, 586 NvU8 *buffer, 587 NvU32 bufferSize, 588 NvU32 *offset) 589 { 590 #ifdef COPY_OUTPUT_PARAMETERS 591 NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 *src = (void*)(buffer); 592 NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *dest = pParams; 593 594 if (src && dest) { 595 dest->engines = src->engines; 596 } 597 else 598 return FAILURE_T; 599 #endif 600 return SUCCESS_T; 601 } 602 603 static 604 return_t deserialize_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00(NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *pParams, 605 NvU8 *buffer, 606 NvU32 bufferSize, 607 NvU32 *offset) 608 { 609 NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 *src = (void*)(buffer); 610 NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *dest = pParams; 611 612 if (src && dest) { 613 dest->hTargetChannel = src->hTargetChannel; 614 dest->numSMsToClear = src->numSMsToClear; 615 } 616 else 617 return FAILURE_T; 618 619 return SUCCESS_T; 620 } 621 622 static 623 return_t deserialize_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06(NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *pParams, 624 NvU8 *buffer, 625 NvU32 bufferSize, 626 NvU32 *offset, 627 NvU32 startingSMOffset) 628 { 629 NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 *src = (void*)(buffer); 630 NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *dest = pParams; 631 632 if (src && dest) { 633 #ifdef COPY_OUTPUT_PARAMETERS 634 NvU32 i, smIdDest; 635 #endif 636 637 if (src->numSMsToRead > VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06) { 638 return FAILURE_T; 639 } 640 641 #ifdef COPY_INPUT_PARAMETERS 642 dest->hTargetChannel = src->hTargetChannel; 643 dest->startingSM = src->startingSM; 644 dest->numSMsToRead = src->numSMsToRead; 645 #endif 646 #ifdef COPY_OUTPUT_PARAMETERS 647 for (i = 0; i < src->numSMsToRead; ++i) 648 { 649 smIdDest = startingSMOffset + i; 650 dest->smErrorStateArray[smIdDest].hwwGlobalEsr = src->smErrorStateArray[i].hwwGlobalEsr; 651 dest->smErrorStateArray[smIdDest].hwwWarpEsr = src->smErrorStateArray[i].hwwWarpEsr; 652 dest->smErrorStateArray[smIdDest].hwwWarpEsrPc = src->smErrorStateArray[i].hwwWarpEsrPc; 653 dest->smErrorStateArray[smIdDest].hwwGlobalEsrReportMask = src->smErrorStateArray[i].hwwGlobalEsrReportMask; 654 dest->smErrorStateArray[smIdDest].hwwWarpEsrReportMask = src->smErrorStateArray[i].hwwWarpEsrReportMask; 655 dest->smErrorStateArray[smIdDest].hwwEsrAddr = src->smErrorStateArray[i].hwwEsrAddr; 656 dest->smErrorStateArray[smIdDest].hwwWarpEsrPc64 = src->smErrorStateArray[i].hwwWarpEsrPc64; 657 /* New fields added in version v21_06 */ 658 dest->smErrorStateArray[smIdDest].hwwCgaEsr = src->smErrorStateArray[i].hwwCgaEsr; 659 dest->smErrorStateArray[smIdDest].hwwCgaEsrReportMask = src->smErrorStateArray[i].hwwCgaEsrReportMask; 660 } 661 dest->mmuFault.valid = src->mmuFault.valid; 662 dest->mmuFault.faultInfo = src->mmuFault.faultInfo; 663 dest->mmuFaultInfo = src->mmuFault.faultInfo; 664 #endif 665 } 666 else 667 return FAILURE_T; 668 669 return SUCCESS_T; 670 } 671 672 static 673 return_t deserialize_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00(NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *pParams, 674 NvU8 *buffer, 675 NvU32 bufferSize, 676 NvU32 *offset) 677 { 678 NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 *src = (void*)(buffer); 679 NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *dest = pParams; 680 681 if (src && dest) { 682 dest->exceptionMask = src->exceptionMask; 683 } 684 else 685 return FAILURE_T; 686 687 return SUCCESS_T; 688 } 689 690 static 691 return_t deserialize_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *pParams, 692 NvU8 *buffer, 693 NvU32 bufferSize, 694 NvU32 *offset) 695 { 696 #ifdef COPY_INPUT_PARAMETERS 697 NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 *src = (void*)(buffer); 698 NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *dest = pParams; 699 NvU32 i; 700 701 if (src && dest) 702 { 703 #ifdef VMIOP_BUILD 704 dest->engineType = deserialize_engineType(src->engineType); 705 #else 706 dest->engineType = src->engineType; 707 #endif 708 dest->hClient = src->hClient; 709 dest->ChID = src->ChID; 710 dest->hChanClient = src->hChanClient; 711 dest->hObject = src->hObject; 712 dest->hVirtMemory = src->hVirtMemory; 713 dest->virtAddress = src->virtAddress; 714 dest->size = src->size; 715 dest->entryCount = src->entryCount; 716 717 if (dest->entryCount > NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES) { 718 return FAILURE_T; 719 } 720 721 for (i = 0; i < dest->entryCount; i++) { 722 dest->promoteEntry[i].gpuPhysAddr = src->promoteEntry[i].gpuPhysAddr; 723 dest->promoteEntry[i].gpuVirtAddr = src->promoteEntry[i].gpuVirtAddr; 724 dest->promoteEntry[i].size = src->promoteEntry[i].size; 725 dest->promoteEntry[i].physAttr = src->promoteEntry[i].physAttr; 726 dest->promoteEntry[i].bufferId = src->promoteEntry[i].bufferId; 727 dest->promoteEntry[i].bInitialize = src->promoteEntry[i].bInitialize; 728 dest->promoteEntry[i].bNonmapped = src->promoteEntry[i].bNonmapped; 729 } 730 } 731 else 732 return FAILURE_T; 733 #endif 734 return SUCCESS_T; 735 } 736 737 static 738 return_t deserialize_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06(NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *pParams, 739 NvU8 *buffer, 740 NvU32 bufferSize, 741 NvU32 *offset) 742 { 743 NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 *src = (void*)(buffer); 744 NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *dest = pParams; 745 746 if (src && dest) { 747 #ifdef COPY_OUTPUT_PARAMETERS 748 dest->waitForEvent = src->waitForEvent; 749 dest->hResidentChannel = src->hResidentChannel; 750 #endif 751 } 752 else 753 return FAILURE_T; 754 755 return SUCCESS_T; 756 } 757 758 static 759 return_t deserialize_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *pParams, 760 NvU8 *buffer, 761 NvU32 bufferSize, 762 NvU32 *offset) 763 { 764 NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 *src = (void*)(buffer); 765 NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *dest = pParams; 766 767 if (src && dest) { 768 NvU32 idx = 0; 769 #ifdef COPY_INPUT_PARAMETERS 770 if (src->regOpCount > NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS) { 771 return FAILURE_T; 772 } 773 774 dest->bNonTransactional = src->bNonTransactional; 775 dest->regOpCount = src->regOpCount; 776 777 for (idx = 0; idx < src->regOpCount; idx++) 778 { 779 dest->regOps[idx].regOp = src->regOps[idx].regOp; 780 dest->regOps[idx].regType = src->regOps[idx].regType; 781 dest->regOps[idx].regQuad = src->regOps[idx].regQuad; 782 dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; 783 dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; 784 dest->regOps[idx].regOffset = src->regOps[idx].regOffset; 785 dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; 786 dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; 787 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 788 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 789 } 790 #endif 791 #ifdef COPY_OUTPUT_PARAMETERS 792 for (idx = 0; idx < src->regOpCount; idx++) 793 { 794 dest->regOps[idx].regStatus = src->regOps[idx].regStatus; 795 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 796 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 797 } 798 #endif 799 } 800 else 801 return FAILURE_T; 802 803 return SUCCESS_T; 804 } 805 806 static 807 return_t deserialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams, 808 NvU8 *buffer, 809 NvU32 bufferSize, 810 NvU32 *offset) 811 { 812 NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 *src = (void*)(buffer); 813 NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *dest = pParams; 814 815 if (src && dest) { 816 #ifdef COPY_INPUT_PARAMETERS 817 dest->action = src->action; 818 #endif 819 } 820 else 821 return FAILURE_T; 822 823 return SUCCESS_T; 824 } 825 826 static 827 return_t deserialize_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06(NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *pParams, 828 NvU8 *buffer, 829 NvU32 bufferSize, 830 NvU32 *offset) 831 { 832 NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 *src = (void*)(buffer); 833 NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *dest = pParams; 834 835 if (src && dest) { 836 #ifdef COPY_INPUT_PARAMETERS 837 dest->hTargetChannel = src->hTargetChannel; 838 dest->smID = src->smID; 839 #endif 840 #ifdef COPY_OUTPUT_PARAMETERS 841 dest->smErrorState.hwwGlobalEsr = src->smErrorState.hwwGlobalEsr; 842 dest->smErrorState.hwwWarpEsr = src->smErrorState.hwwWarpEsr; 843 dest->smErrorState.hwwWarpEsrPc = src->smErrorState.hwwWarpEsrPc; 844 dest->smErrorState.hwwGlobalEsrReportMask = src->smErrorState.hwwGlobalEsrReportMask; 845 dest->smErrorState.hwwWarpEsrReportMask = src->smErrorState.hwwWarpEsrReportMask; 846 dest->smErrorState.hwwEsrAddr = src->smErrorState.hwwEsrAddr; 847 dest->smErrorState.hwwWarpEsrPc64 = src->smErrorState.hwwWarpEsrPc64; 848 /* New fields added in version v21_06 */ 849 dest->smErrorState.hwwCgaEsr = src->smErrorState.hwwCgaEsr; 850 dest->smErrorState.hwwCgaEsrReportMask = src->smErrorState.hwwCgaEsrReportMask; 851 #endif 852 } 853 else 854 return FAILURE_T; 855 856 return SUCCESS_T; 857 } 858 859 static 860 return_t deserialize_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *pParams, 861 NvU8 *buffer, 862 NvU32 bufferSize, 863 NvU32 *offset) 864 { 865 NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 *src = (void*)(buffer); 866 NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *dest = pParams; 867 868 if (src && dest) { 869 #ifdef COPY_INPUT_PARAMETERS 870 dest->hTargetChannel = src->hTargetChannel; 871 dest->smID = src->smID; 872 #endif 873 } 874 else 875 return FAILURE_T; 876 877 return SUCCESS_T; 878 } 879 880 static 881 return_t deserialize_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *pParams, 882 NvU8 *buffer, 883 NvU32 bufferSize, 884 NvU32 *offset) 885 { 886 NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 *src = (void*)(buffer); 887 NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *dest = pParams; 888 889 if (src && dest) { 890 #ifdef COPY_INPUT_PARAMETERS 891 dest->action = src->action; 892 #endif 893 } 894 else 895 return FAILURE_T; 896 897 return SUCCESS_T; 898 } 899 900 static 901 return_t deserialize_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *pParams, 902 NvU8 *buffer, 903 NvU32 bufferSize, 904 NvU32 *offset) 905 { 906 NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 *src = (void*)(buffer); 907 NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *dest = pParams; 908 909 if (src && dest) { 910 #ifdef COPY_INPUT_PARAMETERS 911 dest->stopTriggerType = src->stopTriggerType; 912 #endif 913 } 914 else 915 return FAILURE_T; 916 917 return SUCCESS_T; 918 } 919 920 static 921 return_t deserialize_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00(NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *pParams, 922 NvU8 *buffer, 923 NvU32 bufferSize, 924 NvU32 *offset) 925 { 926 NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 *src = (void*)(buffer); 927 NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *dest = pParams; 928 929 if (src && dest) { 930 dest->hVASpace = src->hVASpace; 931 } 932 else 933 return FAILURE_T; 934 935 return SUCCESS_T; 936 } 937 938 static 939 return_t deserialize_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07(NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pParams, 940 NvU8 *buffer, 941 NvU32 bufferSize, 942 NvU32 *offset) 943 { 944 NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 *src = (void*)(buffer); 945 NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *dest = pParams; 946 947 if (src && dest) { 948 #ifdef COPY_INPUT_PARAMETERS 949 dest->ceEngineType = src->ceEngineType; 950 #endif 951 #ifdef COPY_OUTPUT_PARAMETERS 952 dest->pceMask = src->pceMask; 953 #endif 954 } 955 else 956 return FAILURE_T; 957 958 return SUCCESS_T; 959 } 960 961 static 962 return_t deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *pParams, 963 NvU8 *buffer, 964 NvU32 bufferSize, 965 NvU32 *offset) 966 { 967 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 *src = (void*)(buffer); 968 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *dest = pParams; 969 970 if (src && dest) { 971 ct_assert(NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE == 4); 972 973 #ifdef COPY_INPUT_PARAMETERS 974 dest->index = src->index; 975 dest->tableType = src->tableType; 976 #endif 977 #ifdef COPY_OUTPUT_PARAMETERS 978 NvU32 i; 979 for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { 980 dest->value.colorFB[i] = src->value.colorFB[i]; 981 dest->value.colorDS[i] = src->value.colorDS[i]; 982 } 983 dest->value.depth = src->value.depth; 984 dest->value.stencil = src->value.stencil; 985 dest->format = src->format; 986 dest->index = src->index; 987 dest->bIndexValid = src->bIndexValid; 988 dest->tableType = src->tableType; 989 #endif 990 } 991 else 992 return FAILURE_T; 993 994 return SUCCESS_T; 995 } 996 997 static 998 return_t deserialize_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00(NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *pParams, 999 NvU8 *buffer, 1000 NvU32 bufferSize, 1001 NvU32 *offset) 1002 { 1003 NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00 *src = (void*)(buffer); 1004 NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *dest = pParams; 1005 1006 if (src && dest) { 1007 #ifdef COPY_OUTPUT_PARAMETERS 1008 NvU32 i; 1009 1010 for (i = 0; i < NV2080_CTRL_BUS_MAX_NUM_GPUS; i++) { 1011 dest->nvlinkPeerIdMask[i] = src->nvlinkPeerIdMask[i]; 1012 } 1013 #endif 1014 } 1015 else 1016 return FAILURE_T; 1017 1018 return SUCCESS_T; 1019 } 1020 1021 static 1022 return_t deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams, 1023 NvU8 *buffer, 1024 NvU32 bufferSize, 1025 NvU32 *offset) 1026 { 1027 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 *src = (void*)(buffer); 1028 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *dest = pParams; 1029 1030 if (src && dest) { 1031 #ifdef COPY_OUTPUT_PARAMETERS 1032 NvU32 i; 1033 1034 dest->enabledLinkMask = src->enabledLinkMask; 1035 1036 FOR_EACH_INDEX_IN_MASK(32, i, src->enabledLinkMask) 1037 { 1038 NV2080_CTRL_NVLINK_DEVICE_INFO *deviceInfo_d = NULL; 1039 NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 *deviceInfo_s = NULL; 1040 1041 if (i >= NV2080_CTRL_NVLINK_MAX_LINKS_v23_04) 1042 break; 1043 1044 dest->linkInfo[i].capsTbl = src->linkInfo[i].capsTbl; 1045 dest->linkInfo[i].phyType = src->linkInfo[i].phyType; 1046 dest->linkInfo[i].subLinkWidth = src->linkInfo[i].subLinkWidth; 1047 dest->linkInfo[i].linkState = src->linkInfo[i].linkState; 1048 dest->linkInfo[i].rxSublinkStatus = src->linkInfo[i].rxSublinkStatus; 1049 dest->linkInfo[i].txSublinkStatus = src->linkInfo[i].txSublinkStatus; 1050 dest->linkInfo[i].nvlinkVersion = src->linkInfo[i].nvlinkVersion; 1051 dest->linkInfo[i].nciVersion = src->linkInfo[i].nciVersion; 1052 dest->linkInfo[i].phyVersion = src->linkInfo[i].phyVersion; 1053 dest->linkInfo[i].nvlinkLinkClockKHz = src->linkInfo[i].nvlinkLinkClockKHz; 1054 dest->linkInfo[i].nvlinkLineRateMbps = src->linkInfo[i].nvlinkLineRateMbps; 1055 dest->linkInfo[i].connected = src->linkInfo[i].connected; 1056 dest->linkInfo[i].remoteDeviceLinkNumber = src->linkInfo[i].remoteDeviceLinkNumber; 1057 dest->linkInfo[i].localDeviceLinkNumber = src->linkInfo[i].localDeviceLinkNumber; 1058 1059 deviceInfo_d = &dest->linkInfo[i].remoteDeviceInfo; 1060 deviceInfo_s = &src->linkInfo[i].remoteDeviceInfo; 1061 1062 deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags; 1063 deviceInfo_d->domain = deviceInfo_s->domain; 1064 deviceInfo_d->bus = deviceInfo_s->bus; 1065 deviceInfo_d->device = deviceInfo_s->device; 1066 deviceInfo_d->function = deviceInfo_s->function; 1067 deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId; 1068 deviceInfo_d->deviceType = deviceInfo_s->deviceType; 1069 portMemCopy(deviceInfo_d->deviceUUID, 1070 sizeof(deviceInfo_d->deviceUUID), 1071 deviceInfo_s->deviceUUID, 1072 sizeof(deviceInfo_s->deviceUUID)); 1073 1074 deviceInfo_d = &dest->linkInfo[i].localDeviceInfo; 1075 deviceInfo_s = &src->linkInfo[i].localDeviceInfo; 1076 1077 deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags; 1078 deviceInfo_d->domain = deviceInfo_s->domain; 1079 deviceInfo_d->bus = deviceInfo_s->bus; 1080 deviceInfo_d->device = deviceInfo_s->device; 1081 deviceInfo_d->function = deviceInfo_s->function; 1082 deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId; 1083 deviceInfo_d->deviceType = deviceInfo_s->deviceType; 1084 portMemCopy(deviceInfo_d->deviceUUID, 1085 sizeof(deviceInfo_d->deviceUUID), 1086 deviceInfo_s->deviceUUID, 1087 sizeof(deviceInfo_s->deviceUUID)); 1088 } 1089 FOR_EACH_INDEX_IN_MASK_END; 1090 #endif 1091 } 1092 else 1093 return FAILURE_T; 1094 1095 return SUCCESS_T; 1096 } 1097 1098 static 1099 return_t deserialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *pParams, 1100 NvU8 *buffer, 1101 NvU32 bufferSize, 1102 NvU32 *offset) 1103 { 1104 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D *src = (void*)(buffer); 1105 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *dest = pParams; 1106 1107 if (src && dest) { 1108 #ifdef COPY_INPUT_PARAMETERS 1109 memcpy(dest->gpuIds, src->gpuIds, (sizeof(NvU32) * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)); 1110 dest->gpuCount = src->gpuCount; 1111 #endif 1112 #ifdef COPY_OUTPUT_PARAMETERS 1113 dest->p2pCaps = src->p2pCaps; 1114 dest->p2pOptimalReadCEs = src->p2pOptimalReadCEs; 1115 dest->p2pOptimalWriteCEs = src->p2pOptimalWriteCEs; 1116 portMemCopy(dest->p2pCapsStatus, NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D, 1117 src->p2pCapsStatus, NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D); 1118 #endif 1119 } 1120 else 1121 return FAILURE_T; 1122 1123 return SUCCESS_T; 1124 } 1125 1126 static 1127 return_t deserialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *pParams, 1128 NvU8 *buffer, 1129 NvU32 bufferSize, 1130 NvU32 *offset) 1131 { 1132 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A *src = (void*)(buffer); 1133 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *dest = pParams; 1134 1135 if (src && dest) { 1136 if (src->grpACount == 0 || 1137 src->grpACount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS || 1138 src->grpBCount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS) { 1139 return FAILURE_T; 1140 } 1141 1142 #ifdef COPY_INPUT_PARAMETERS 1143 NvU32 idx = 0; 1144 1145 dest->grpACount = src->grpACount; 1146 dest->grpBCount = src->grpBCount; 1147 1148 for (idx = 0; idx < NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS; idx++) { 1149 dest->gpuIdGrpA[idx] = src->gpuIdGrpA[idx]; 1150 dest->gpuIdGrpB[idx] = src->gpuIdGrpB[idx]; 1151 } 1152 #endif 1153 #ifdef COPY_OUTPUT_PARAMETERS 1154 NvU32 grpAIdx = 0, grpBIdx= 0; 1155 NvBool bReflexive = NV_FALSE; 1156 1157 // Check for the reflexive case 1158 if (src->grpBCount == 0) { 1159 bReflexive = NV_TRUE; 1160 } 1161 1162 for (grpAIdx = 0; grpAIdx < src->grpACount; grpAIdx++) { 1163 for (grpBIdx = 0; bReflexive ? grpBIdx <= grpAIdx : grpBIdx < src->grpBCount; grpBIdx++) { 1164 dest->p2pCaps[grpAIdx][grpBIdx] = src->p2pCaps[grpAIdx].array[grpBIdx]; 1165 dest->a2bOptimalReadCes[grpAIdx][grpBIdx] = src->a2bOptimalReadCes[grpAIdx].array[grpBIdx]; 1166 dest->a2bOptimalWriteCes[grpAIdx][grpBIdx] = src->a2bOptimalWriteCes[grpAIdx].array[grpBIdx]; 1167 dest->b2aOptimalReadCes[grpAIdx][grpBIdx] = src->b2aOptimalReadCes[grpAIdx].array[grpBIdx]; 1168 dest->b2aOptimalWriteCes[grpAIdx][grpBIdx] = src->b2aOptimalWriteCes[grpAIdx].array[grpBIdx]; 1169 } 1170 } 1171 #endif 1172 } 1173 else 1174 return FAILURE_T; 1175 1176 return SUCCESS_T; 1177 } 1178 1179 static 1180 return_t deserialize_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02(NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams, 1181 NvU8 *buffer, 1182 NvU32 bufferSize, 1183 NvU32 *offset) 1184 { 1185 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 *src = (void*)(buffer); 1186 NV2080_CTRL_GET_P2P_CAPS_PARAMS *dest = pParams; 1187 1188 if (src && dest) { 1189 #ifdef COPY_INPUT_PARAMETERS 1190 if (!src->bAllCaps && (src->peerGpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)) 1191 return FAILURE_T; 1192 1193 dest->bAllCaps = src->bAllCaps; 1194 dest->bUseUuid = src->bUseUuid; 1195 1196 if (!src->bAllCaps) 1197 { 1198 NvU32 i; 1199 dest->peerGpuCount = src->peerGpuCount; 1200 1201 for (i = 0; i < src->peerGpuCount; ++i) 1202 { 1203 portMemCopy(dest->peerGpuCaps[i].gpuUuid, 1204 VM_UUID_SIZE_v21_02, 1205 src->peerGpuCaps[i].gpuUuid, 1206 VM_UUID_SIZE_v21_02); 1207 } 1208 } 1209 #endif 1210 #ifdef COPY_OUTPUT_PARAMETERS 1211 NvU32 i; 1212 1213 if (src->peerGpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS) 1214 return FAILURE_T; 1215 1216 if (src->bAllCaps) 1217 { 1218 dest->peerGpuCount = src->peerGpuCount; 1219 } 1220 1221 for (i = 0; i < src->peerGpuCount; ++i) 1222 { 1223 if (src->bAllCaps) 1224 { 1225 portMemCopy(dest->peerGpuCaps[i].gpuUuid, 1226 VM_UUID_SIZE_v21_02, 1227 src->peerGpuCaps[i].gpuUuid, 1228 VM_UUID_SIZE_v21_02); 1229 } 1230 1231 dest->peerGpuCaps[i].p2pCaps = src->peerGpuCaps[i].p2pCaps; 1232 dest->peerGpuCaps[i].p2pOptimalReadCEs = src->peerGpuCaps[i].p2pOptimalReadCEs; 1233 dest->peerGpuCaps[i].p2pOptimalWriteCEs = src->peerGpuCaps[i].p2pOptimalWriteCEs; 1234 portMemCopy(dest->peerGpuCaps[i].p2pCapsStatus, 1235 sizeof(dest->peerGpuCaps[i].p2pCapsStatus), 1236 src->peerGpuCaps[i].p2pCapsStatus, 1237 sizeof(src->peerGpuCaps[i].p2pCapsStatus)); 1238 dest->peerGpuCaps[i].busPeerId = src->peerGpuCaps[i].busPeerId; 1239 } 1240 #endif 1241 } 1242 else 1243 return FAILURE_T; 1244 1245 return SUCCESS_T; 1246 } 1247 1248 static 1249 return_t deserialize_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F(NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *pParams, 1250 NvU8 *buffer, 1251 NvU32 bufferSize, 1252 NvU32 *offset) 1253 { 1254 #ifdef COPY_INPUT_PARAMETERS 1255 NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F *src = (void*)(buffer); 1256 NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *dest = pParams; 1257 1258 if (src && dest) 1259 { 1260 dest->ctxsw = src->ctxsw; 1261 } 1262 else 1263 return FAILURE_T; 1264 #endif 1265 1266 return SUCCESS_T; 1267 } 1268 1269 static 1270 return_t deserialize_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F(NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *pParams, 1271 NvU8 *buffer, 1272 NvU32 bufferSize, 1273 NvU32 *offset) 1274 { 1275 #ifdef COPY_INPUT_PARAMETERS 1276 NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F *src = (void*)(buffer); 1277 NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *dest = pParams; 1278 1279 if (src && dest) 1280 { 1281 dest->ctxsw = src->ctxsw; 1282 } 1283 else 1284 return FAILURE_T; 1285 #endif 1286 1287 return SUCCESS_T; 1288 } 1289 1290 static 1291 return_t deserialize_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F(NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *pParams, 1292 NvU8 *buffer, 1293 NvU32 bufferSize, 1294 NvU32 *offset) 1295 { 1296 NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F *src = (void*)(buffer); 1297 NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *dest = pParams; 1298 NvU32 idx = 0; 1299 1300 if (src && dest) 1301 { 1302 if (src->regOpCount > NVB0CC_REGOPS_MAX_COUNT) { 1303 return FAILURE_T; 1304 } 1305 1306 #ifdef COPY_INPUT_PARAMETERS 1307 dest->regOpCount = src->regOpCount; 1308 dest->mode = src->mode; 1309 for (idx = 0; idx < src->regOpCount; idx++) 1310 { 1311 dest->regOps[idx].regOp = src->regOps[idx].regOp; 1312 dest->regOps[idx].regType = src->regOps[idx].regType; 1313 dest->regOps[idx].regQuad = src->regOps[idx].regQuad; 1314 dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; 1315 dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; 1316 dest->regOps[idx].regOffset = src->regOps[idx].regOffset; 1317 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 1318 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 1319 dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; 1320 dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; 1321 } 1322 #endif 1323 #ifdef COPY_OUTPUT_PARAMETERS 1324 dest->bPassed = src->bPassed; 1325 dest->bDirect = src->bDirect; 1326 for (idx = 0; idx < src->regOpCount; idx++) 1327 { 1328 dest->regOps[idx].regStatus = src->regOps[idx].regStatus; 1329 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 1330 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 1331 } 1332 #endif 1333 } 1334 else 1335 return FAILURE_T; 1336 1337 return SUCCESS_T; 1338 } 1339 1340 static 1341 return_t deserialize_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams, 1342 NvU8 *buffer, 1343 NvU32 bufferSize, 1344 NvU32 *offset) 1345 { 1346 NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 *src = (void*)(buffer); 1347 NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *dest = pParams; 1348 1349 if (src && dest) 1350 { 1351 #ifdef COPY_INPUT_PARAMETERS 1352 dest->hMemPmaBuffer = src->hMemPmaBuffer; 1353 dest->pmaBufferOffset = src->pmaBufferOffset; 1354 dest->pmaBufferSize = src->pmaBufferSize; 1355 dest->hMemPmaBytesAvailable = src->hMemPmaBytesAvailable; 1356 dest->pmaBytesAvailableOffset = src->pmaBytesAvailableOffset; 1357 dest->ctxsw = src->ctxsw; 1358 #endif 1359 #ifdef COPY_OUTPUT_PARAMETERS 1360 dest->pmaChannelIdx = src->pmaChannelIdx; 1361 dest->pmaBufferVA = src->pmaBufferVA; 1362 #endif 1363 } 1364 else 1365 return FAILURE_T; 1366 1367 return SUCCESS_T; 1368 } 1369 1370 static 1371 return_t deserialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams, 1372 NvU8 *buffer, 1373 NvU32 bufferSize, 1374 NvU32 *offset) 1375 { 1376 NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 *src = (void*)(buffer); 1377 NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *dest = pParams; 1378 1379 if (src && dest) 1380 { 1381 #ifdef COPY_INPUT_PARAMETERS 1382 dest->bytesConsumed = src->bytesConsumed; 1383 dest->bUpdateAvailableBytes = src->bUpdateAvailableBytes; 1384 dest->bWait = src->bWait; 1385 dest->bReturnPut = src->bReturnPut; 1386 dest->pmaChannelIdx = src->pmaChannelIdx; 1387 #endif 1388 #ifdef COPY_OUTPUT_PARAMETERS 1389 dest->bytesAvailable = src->bytesAvailable; 1390 dest->putPtr = src->putPtr; 1391 #endif 1392 } 1393 else 1394 return FAILURE_T; 1395 1396 return SUCCESS_T; 1397 } 1398 1399 static 1400 return_t deserialize_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pParams, 1401 NvU8 *buffer, 1402 NvU32 bufferSize, 1403 NvU32 *offset) 1404 { 1405 NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 *src = (void*)(buffer); 1406 NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *dest = pParams; 1407 1408 if (src && dest) { 1409 NvU32 idx = 0; 1410 #ifdef COPY_INPUT_PARAMETERS 1411 if (src->regOpCount > NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07) { 1412 return FAILURE_T; 1413 } 1414 1415 dest->bNonTransactional = src->bNonTransactional; 1416 dest->regOpCount = src->regOpCount; 1417 dest->hClientTarget = src->hClientTarget; 1418 dest->hChannelTarget = src->hChannelTarget; 1419 1420 for (idx = 0; idx < src->regOpCount; idx++) 1421 { 1422 dest->regOps[idx].regOp = src->regOps[idx].regOp; 1423 dest->regOps[idx].regType = src->regOps[idx].regType; 1424 dest->regOps[idx].regQuad = src->regOps[idx].regQuad; 1425 dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; 1426 dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; 1427 dest->regOps[idx].regOffset = src->regOps[idx].regOffset; 1428 dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; 1429 dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; 1430 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 1431 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 1432 dest->smIds[idx] = src->smIds[idx]; 1433 } 1434 #endif 1435 #ifdef COPY_OUTPUT_PARAMETERS 1436 for (idx = 0; idx < src->regOpCount; idx++) 1437 { 1438 dest->regOps[idx].regStatus = src->regOps[idx].regStatus; 1439 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 1440 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 1441 } 1442 #endif 1443 } 1444 else 1445 return FAILURE_T; 1446 1447 return SUCCESS_T; 1448 } 1449 #endif 1450 1451 #ifdef BUILD_LEGACY_RPCS 1452 1453 #endif 1454 1455 #ifdef BUILD_COMMON_RPCS 1456 static 1457 return_t deserialize_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00(NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *pParams, 1458 NvU8 *buffer, 1459 NvU32 bufferSize, 1460 NvU32 *offset) 1461 { 1462 NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 *src = (void*)(buffer); 1463 NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *dest = pParams; 1464 1465 if (src && dest) 1466 { 1467 dest->hChannel = src->hChannel; 1468 dest->property = src->property; 1469 dest->value = src->value; 1470 } 1471 else 1472 return FAILURE_T; 1473 1474 return SUCCESS_T; 1475 } 1476 #endif 1477 1478 #ifdef BUILD_LEGACY_RPCS 1479 #endif 1480 1481 #ifdef BUILD_COMMON_RPCS 1482 static 1483 return_t deserialize_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v1A_1C( 1484 NV2080_CTRL_GPU_EVICT_CTX_PARAMS *pParams, 1485 NvU8 *buffer, 1486 NvU32 bufferSize, 1487 NvU32 *offset) 1488 { 1489 NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 *src = (void*)(buffer); 1490 NV2080_CTRL_GPU_EVICT_CTX_PARAMS *dest = pParams; 1491 1492 if (src && dest) 1493 { 1494 #ifdef COPY_INPUT_PARAMETERS 1495 #ifdef VMIOP_BUILD 1496 dest->engineType = deserialize_engineType(src->engineType); 1497 #else 1498 dest->engineType = src->engineType; 1499 #endif 1500 dest->hClient = src->hClient; 1501 dest->ChID = src->ChID; 1502 dest->hChanClient = src->hChanClient; 1503 dest->hObject = src->hObject; 1504 #endif 1505 } 1506 else 1507 return FAILURE_T; 1508 1509 return SUCCESS_T; 1510 } 1511 1512 static 1513 return_t deserialize_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D(NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *pParams, 1514 NvU8 *buffer, 1515 NvU32 bufferSize, 1516 NvU32 *offset) 1517 { 1518 NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D *src = (void*)(buffer); 1519 NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *dest = pParams; 1520 NvU32 idx = 0; 1521 1522 if (src && dest) 1523 { 1524 if (src->numQueries > NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D) { 1525 return FAILURE_T; 1526 } 1527 #ifdef COPY_INPUT_PARAMETERS 1528 dest->numQueries = src->numQueries; 1529 #endif 1530 for (idx = 0; idx < dest->numQueries; idx++) { 1531 #ifdef COPY_INPUT_PARAMETERS 1532 dest->queries[idx].queryType = src->queries[idx].queryType; 1533 #endif 1534 #ifdef COPY_OUTPUT_PARAMETERS 1535 dest->queries[idx].status = src->queries[idx].status; 1536 #endif 1537 switch(dest->queries[idx].queryType) 1538 { 1539 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT: { 1540 #ifdef COPY_OUTPUT_PARAMETERS 1541 dest->queries[idx].queryData.gpcCountData.gpcCount = src->queries[idx].queryData.gpcCountData.gpcCount; 1542 #endif 1543 break; 1544 } 1545 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP: { 1546 #ifdef COPY_INPUT_PARAMETERS 1547 dest->queries[idx].queryData.chipletGpcMapData.gpcId = src->queries[idx].queryData.chipletGpcMapData.gpcId; 1548 #endif 1549 #ifdef COPY_OUTPUT_PARAMETERS 1550 dest->queries[idx].queryData.chipletGpcMapData.chipletGpcMap = src->queries[idx].queryData.chipletGpcMapData.chipletGpcMap; 1551 #endif 1552 break; 1553 } 1554 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK: { 1555 #ifdef COPY_INPUT_PARAMETERS 1556 dest->queries[idx].queryData.tpcMaskData.gpcId = src->queries[idx].queryData.tpcMaskData.gpcId; 1557 #endif 1558 #ifdef COPY_OUTPUT_PARAMETERS 1559 dest->queries[idx].queryData.tpcMaskData.tpcMask = src->queries[idx].queryData.tpcMaskData.tpcMask; 1560 #endif 1561 break; 1562 } 1563 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK: { 1564 #ifdef COPY_INPUT_PARAMETERS 1565 dest->queries[idx].queryData.ppcMaskData.gpcId = src->queries[idx].queryData.ppcMaskData.gpcId; 1566 #endif 1567 #ifdef COPY_OUTPUT_PARAMETERS 1568 dest->queries[idx].queryData.ppcMaskData.ppcMask = src->queries[idx].queryData.ppcMaskData.ppcMask; 1569 #endif 1570 break; 1571 } 1572 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP: { 1573 #ifdef COPY_INPUT_PARAMETERS 1574 dest->queries[idx].queryData.partitionGpcMapData.swizzId = src->queries[idx].queryData.partitionGpcMapData.swizzId; 1575 dest->queries[idx].queryData.partitionGpcMapData.gpcId = src->queries[idx].queryData.partitionGpcMapData.gpcId; 1576 #endif 1577 #ifdef COPY_OUTPUT_PARAMETERS 1578 dest->queries[idx].queryData.partitionGpcMapData.chipletGpcMap = src->queries[idx].queryData.partitionGpcMapData.chipletGpcMap; 1579 #endif 1580 break; 1581 } 1582 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK: { 1583 #ifdef COPY_OUTPUT_PARAMETERS 1584 dest->queries[idx].queryData.syspipeMaskData.chipletSyspipeMask = src->queries[idx].queryData.syspipeMaskData.chipletSyspipeMask; 1585 #endif 1586 break; 1587 } 1588 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS: { 1589 #ifdef COPY_INPUT_PARAMETERS 1590 dest->queries[idx].queryData.partitionChipletSyspipeData.swizzId = src->queries[idx].queryData.partitionChipletSyspipeData.swizzId; 1591 #endif 1592 #ifdef COPY_OUTPUT_PARAMETERS 1593 dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount = src->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount; 1594 1595 if (dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount > NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D) { 1596 return FAILURE_T; 1597 } 1598 1599 for (idx = 0; idx < dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount; idx++) 1600 dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeId[idx] = src->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeId[idx]; 1601 #endif 1602 break; 1603 } 1604 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK: { 1605 #ifdef COPY_INPUT_PARAMETERS 1606 dest->queries[idx].queryData.dmGpcMaskData.swizzId = src->queries[idx].queryData.dmGpcMaskData.swizzId; 1607 dest->queries[idx].queryData.dmGpcMaskData.grIdx = src->queries[idx].queryData.dmGpcMaskData.grIdx; 1608 #endif 1609 #ifdef COPY_OUTPUT_PARAMETERS 1610 dest->queries[idx].queryData.dmGpcMaskData.gpcEnMask = src->queries[idx].queryData.dmGpcMaskData.gpcEnMask; 1611 #endif 1612 break; 1613 } 1614 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID: { 1615 #ifdef COPY_OUTPUT_PARAMETERS 1616 dest->queries[idx].queryData.partitionSyspipeIdData.syspipeId = src->queries[idx].queryData.partitionSyspipeIdData.syspipeId; 1617 #endif 1618 break; 1619 } 1620 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK: { 1621 #ifdef COPY_INPUT_PARAMETERS 1622 dest->queries[idx].queryData.ropMaskData.gpcId = src->queries[idx].queryData.ropMaskData.gpcId; 1623 #endif 1624 #ifdef COPY_OUTPUT_PARAMETERS 1625 dest->queries[idx].queryData.ropMaskData.ropMask = src->queries[idx].queryData.ropMaskData.ropMask; 1626 #endif 1627 break; 1628 } 1629 default: 1630 { 1631 // Unknown query 1632 return FAILURE_T; 1633 } 1634 } 1635 } 1636 } 1637 else 1638 return FAILURE_T; 1639 1640 return SUCCESS_T; 1641 } 1642 1643 static 1644 return_t deserialize_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00(NV2080_CTRL_FB_GET_FS_INFO_PARAMS *pParams, 1645 NvU8 *buffer, 1646 NvU32 bufferSize, 1647 NvU32 *offset) 1648 { 1649 NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 *src = (void*)(buffer); 1650 NV2080_CTRL_FB_GET_FS_INFO_PARAMS *dest = pParams; 1651 NvU32 idx = 0; 1652 1653 if (src && dest) 1654 { 1655 if (src->numQueries > NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00) { 1656 return FAILURE_T; 1657 } 1658 1659 #ifdef COPY_INPUT_PARAMETERS 1660 dest->numQueries = src->numQueries; 1661 #endif 1662 for (idx = 0; idx < dest->numQueries; idx++) { 1663 #ifdef COPY_INPUT_PARAMETERS 1664 dest->queries[idx].queryType = src->queries[idx].queryType; 1665 #endif 1666 #ifdef COPY_OUTPUT_PARAMETERS 1667 dest->queries[idx].status = src->queries[idx].status; 1668 #endif 1669 switch(dest->queries[idx].queryType) 1670 { 1671 case NV2080_CTRL_FB_FS_INFO_INVALID_QUERY: { 1672 #ifdef COPY_OUTPUT_PARAMETERS 1673 NvU32 i = 0; 1674 for (i = 0; i < NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D; i++) { 1675 dest->queries[idx].queryParams.inv.data[i] = src->queries[idx].queryParams.inv.data[i]; 1676 } 1677 #endif 1678 break; 1679 } 1680 case NV2080_CTRL_FB_FS_INFO_FBP_MASK: { 1681 #ifdef COPY_INPUT_PARAMETERS 1682 dest->queries[idx].queryParams.fbp.swizzId = src->queries[idx].queryParams.fbp.swizzId; 1683 #endif 1684 #ifdef COPY_OUTPUT_PARAMETERS 1685 dest->queries[idx].queryParams.fbp.fbpEnMask = src->queries[idx].queryParams.fbp.fbpEnMask; 1686 #endif 1687 break; 1688 } 1689 case NV2080_CTRL_FB_FS_INFO_LTC_MASK: { 1690 #ifdef COPY_INPUT_PARAMETERS 1691 dest->queries[idx].queryParams.ltc.fbpIndex = src->queries[idx].queryParams.ltc.fbpIndex; 1692 #endif 1693 #ifdef COPY_OUTPUT_PARAMETERS 1694 dest->queries[idx].queryParams.ltc.ltcEnMask = src->queries[idx].queryParams.ltc.ltcEnMask; 1695 #endif 1696 break; 1697 } 1698 case NV2080_CTRL_FB_FS_INFO_LTS_MASK: { 1699 #ifdef COPY_INPUT_PARAMETERS 1700 dest->queries[idx].queryParams.lts.fbpIndex = src->queries[idx].queryParams.lts.fbpIndex; 1701 #endif 1702 #ifdef COPY_OUTPUT_PARAMETERS 1703 dest->queries[idx].queryParams.lts.ltsEnMask = src->queries[idx].queryParams.lts.ltsEnMask; 1704 #endif 1705 1706 break; 1707 } 1708 case NV2080_CTRL_FB_FS_INFO_FBPA_MASK: { 1709 #ifdef COPY_INPUT_PARAMETERS 1710 dest->queries[idx].queryParams.fbpa.fbpIndex = src->queries[idx].queryParams.fbpa.fbpIndex; 1711 #endif 1712 #ifdef COPY_OUTPUT_PARAMETERS 1713 dest->queries[idx].queryParams.fbpa.fbpaEnMask = src->queries[idx].queryParams.fbpa.fbpaEnMask; 1714 #endif 1715 break; 1716 } 1717 case NV2080_CTRL_FB_FS_INFO_ROP_MASK: { 1718 #ifdef COPY_INPUT_PARAMETERS 1719 dest->queries[idx].queryParams.rop.fbpIndex = src->queries[idx].queryParams.rop.fbpIndex; 1720 #endif 1721 #ifdef COPY_OUTPUT_PARAMETERS 1722 dest->queries[idx].queryParams.rop.ropEnMask = src->queries[idx].queryParams.rop.ropEnMask; 1723 #endif 1724 break; 1725 } 1726 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK: { 1727 #ifdef COPY_INPUT_PARAMETERS 1728 dest->queries[idx].queryParams.dmLtc.fbpIndex = src->queries[idx].queryParams.dmLtc.fbpIndex; 1729 dest->queries[idx].queryParams.dmLtc.swizzId = src->queries[idx].queryParams.dmLtc.swizzId; 1730 #endif 1731 #ifdef COPY_OUTPUT_PARAMETERS 1732 dest->queries[idx].queryParams.dmLtc.ltcEnMask = src->queries[idx].queryParams.dmLtc.ltcEnMask; 1733 #endif 1734 break; 1735 } 1736 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK: { 1737 #ifdef COPY_INPUT_PARAMETERS 1738 dest->queries[idx].queryParams.dmLts.fbpIndex = src->queries[idx].queryParams.dmLts.fbpIndex; 1739 dest->queries[idx].queryParams.dmLts.swizzId = src->queries[idx].queryParams.dmLts.swizzId; 1740 #endif 1741 #ifdef COPY_OUTPUT_PARAMETERS 1742 dest->queries[idx].queryParams.dmLts.ltsEnMask = src->queries[idx].queryParams.dmLts.ltsEnMask; 1743 #endif 1744 break; 1745 } 1746 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK: { 1747 #ifdef COPY_INPUT_PARAMETERS 1748 dest->queries[idx].queryParams.dmFbpa.fbpIndex = src->queries[idx].queryParams.dmFbpa.fbpIndex; 1749 dest->queries[idx].queryParams.dmFbpa.swizzId = src->queries[idx].queryParams.dmFbpa.swizzId; 1750 #endif 1751 #ifdef COPY_OUTPUT_PARAMETERS 1752 dest->queries[idx].queryParams.dmFbpa.fbpaEnMask = src->queries[idx].queryParams.dmFbpa.fbpaEnMask; 1753 #endif 1754 break; 1755 } 1756 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK: { 1757 #ifdef COPY_INPUT_PARAMETERS 1758 dest->queries[idx].queryParams.dmRop.fbpIndex = src->queries[idx].queryParams.dmRop.fbpIndex; 1759 dest->queries[idx].queryParams.dmRop.swizzId = src->queries[idx].queryParams.dmRop.swizzId; 1760 #endif 1761 #ifdef COPY_OUTPUT_PARAMETERS 1762 dest->queries[idx].queryParams.dmRop.ropEnMask = src->queries[idx].queryParams.dmRop.ropEnMask; 1763 #endif 1764 break; 1765 } 1766 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK: { 1767 #ifdef COPY_INPUT_PARAMETERS 1768 dest->queries[idx].queryParams.dmFbpaSubp.fbpIndex = src->queries[idx].queryParams.dmFbpaSubp.fbpIndex; 1769 dest->queries[idx].queryParams.dmFbpaSubp.swizzId = src->queries[idx].queryParams.dmFbpaSubp.swizzId; 1770 #endif 1771 #ifdef COPY_OUTPUT_PARAMETERS 1772 dest->queries[idx].queryParams.dmFbpaSubp.fbpaSubpEnMask = src->queries[idx].queryParams.dmFbpaSubp.fbpaSubpEnMask; 1773 #endif 1774 break; 1775 } 1776 case NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK: { 1777 #ifdef COPY_INPUT_PARAMETERS 1778 dest->queries[idx].queryParams.fbpaSubp.fbpIndex = src->queries[idx].queryParams.fbpaSubp.fbpIndex; 1779 #endif 1780 #ifdef COPY_OUTPUT_PARAMETERS 1781 dest->queries[idx].queryParams.fbpaSubp.fbpaSubpEnMask = src->queries[idx].queryParams.fbpaSubp.fbpaSubpEnMask; 1782 #endif 1783 break; 1784 } 1785 case NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP: { 1786 #ifdef COPY_INPUT_PARAMETERS 1787 dest->queries[idx].queryParams.fbpLogicalMap.fbpIndex = src->queries[idx].queryParams.fbpLogicalMap.fbpIndex; 1788 #endif 1789 #ifdef COPY_OUTPUT_PARAMETERS 1790 dest->queries[idx].queryParams.fbpLogicalMap.fbpLogicalIndex = src->queries[idx].queryParams.fbpLogicalMap.fbpLogicalIndex; 1791 #endif 1792 break; 1793 } 1794 default: 1795 { 1796 // Unknown query 1797 return FAILURE_T; 1798 } 1799 } 1800 } 1801 } 1802 else 1803 return FAILURE_T; 1804 1805 return SUCCESS_T; 1806 } 1807 1808 #ifdef VMIOP_BUILD 1809 1810 static 1811 return_t deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams, 1812 NvU8 *buffer, 1813 NvU32 bufferSize, 1814 NvU32 *offset) 1815 { 1816 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06 *src = (void*)(buffer); 1817 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *dest = pParams; 1818 1819 if (src && dest) 1820 { 1821 #ifdef COPY_INPUT_PARAMETERS 1822 dest->flags = src->flags; 1823 #endif 1824 1825 #ifdef COPY_OUTPUT_PARAMETERS 1826 { 1827 NvU32 i; 1828 1829 dest->bFatalPoisonError = src->bFatalPoisonError; 1830 1831 for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06; i++) 1832 { 1833 dest->units[i].enabled = src->units[i].enabled; 1834 dest->units[i].scrubComplete = src->units[i].scrubComplete; 1835 dest->units[i].supported = src->units[i].supported; 1836 dest->units[i].dbe.count = src->units[i].dbe.count; 1837 dest->units[i].dbeNonResettable.count = src->units[i].dbeNonResettable.count; 1838 dest->units[i].sbe.count = src->units[i].sbe.count; 1839 dest->units[i].sbeNonResettable.count = src->units[i].sbeNonResettable.count; 1840 } 1841 } 1842 #endif 1843 } 1844 else 1845 return FAILURE_T; 1846 1847 return SUCCESS_T; 1848 } 1849 1850 #endif // VMIOP_BUILD 1851 1852 return_t deserialize_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E( 1853 NVA06F_CTRL_STOP_CHANNEL_PARAMS *pParams, 1854 NvU8 *buffer, 1855 NvU32 bufferSize, 1856 NvU32 *offset) 1857 { 1858 NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E *src = (void*)(buffer); 1859 NVA06F_CTRL_STOP_CHANNEL_PARAMS *dest = pParams; 1860 1861 if (src && dest) 1862 { 1863 #ifdef COPY_INPUT_PARAMETERS 1864 dest->bImmediate = src->bImmediate; 1865 #endif 1866 } 1867 else 1868 return FAILURE_T; 1869 1870 return SUCCESS_T; 1871 } 1872 1873 return_t deserialize_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F(NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *pParams, 1874 NvU8 *buffer, 1875 NvU32 bufferSize, 1876 NvU32 *offset) 1877 { 1878 #ifdef COPY_INPUT_PARAMETERS 1879 NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F *src = (void*)(buffer); 1880 NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *dest = pParams; 1881 1882 if (src && dest) 1883 { 1884 dest->pmaChannelIdx = src->pmaChannelIdx; 1885 } 1886 else 1887 return FAILURE_T; 1888 1889 #endif 1890 return SUCCESS_T; 1891 } 1892 1893 static 1894 return_t deserialize_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F(NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *pParams, 1895 NvU8 *buffer, 1896 NvU32 bufferSize, 1897 NvU32 *offset) 1898 { 1899 #ifdef COPY_INPUT_PARAMETERS 1900 NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F *src = (void*)(buffer); 1901 NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *dest = pParams; 1902 1903 if (src && dest) 1904 { 1905 dest->hChannel = src->hChannel; 1906 dest->samplingMode = src->samplingMode; 1907 dest->grRouteInfo.flags = src->grRouteInfo.flags; 1908 dest->grRouteInfo.route = src->grRouteInfo.route; 1909 1910 } 1911 else 1912 return FAILURE_T; 1913 1914 #endif 1915 return SUCCESS_T; 1916 } 1917 1918 static 1919 return_t deserialize_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F(NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *pParams, 1920 NvU8 *buffer, 1921 NvU32 bufferSize, 1922 NvU32 *offset) 1923 { 1924 #ifdef COPY_INPUT_PARAMETERS 1925 NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F *src = (void*)(buffer); 1926 NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *dest = pParams; 1927 1928 if (src && dest) 1929 { 1930 dest->bSetMaxFreq = src->bSetMaxFreq; 1931 } 1932 else 1933 return FAILURE_T; 1934 1935 #endif 1936 return SUCCESS_T; 1937 } 1938 1939 static 1940 return_t deserialize_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F(NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *pParams, 1941 NvU8 *buffer, 1942 NvU32 bufferSize, 1943 NvU32 *offset) 1944 { 1945 #ifdef COPY_OUTPUT_PARAMETERS 1946 NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F *src = (void*)(buffer); 1947 NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *dest = pParams; 1948 NvU32 i = 0; 1949 1950 if (src && dest) 1951 { 1952 dest->rm.clientActiveMask = src->rm.clientActiveMask; 1953 dest->rm.bRegkeyLimitRatedTdp = src->rm.bRegkeyLimitRatedTdp; 1954 dest->output = src->output; 1955 1956 for (i = 0; i < NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F; i++) 1957 { 1958 dest->inputs[i] = src->inputs[i]; 1959 } 1960 } 1961 else 1962 return FAILURE_T; 1963 1964 #endif 1965 return SUCCESS_T; 1966 } 1967 1968 static 1969 return_t deserialize_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F(NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pParams, 1970 NvU8 *buffer, 1971 NvU32 bufferSize, 1972 NvU32 *offset) 1973 { 1974 #ifdef COPY_INPUT_PARAMETERS 1975 NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F *src = (void*)(buffer); 1976 NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *dest = pParams; 1977 1978 if (src && dest) 1979 { 1980 dest->client = src->client; 1981 dest->input = src->input; 1982 } 1983 else 1984 return FAILURE_T; 1985 1986 #endif 1987 return SUCCESS_T; 1988 } 1989 1990 static 1991 return_t deserialize_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23( 1992 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *pParams, 1993 NvU8 *buffer, 1994 NvU32 bufferSize, 1995 NvU32 *offset) 1996 { 1997 #ifdef COPY_INPUT_PARAMETERS 1998 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 *src = (void*)(buffer); 1999 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *dest = pParams; 2000 2001 if (src && dest) 2002 { 2003 dest->base = src->base; 2004 dest->size = src->size; 2005 dest->addressSpace = src->addressSpace; 2006 dest->cacheAttrib = src->cacheAttrib; 2007 } 2008 else 2009 return FAILURE_T; 2010 2011 #endif 2012 return SUCCESS_T; 2013 } 2014 2015 return_t deserialize_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02(NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *pParams, 2016 NvU8 *buffer, 2017 NvU32 bufferSize, 2018 NvU32 *offset) 2019 { 2020 #ifdef COPY_INPUT_PARAMETERS 2021 NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 *src = (void*)(buffer); 2022 NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *dest = pParams; 2023 2024 if (src && dest) 2025 { 2026 dest->smID = src->smID; 2027 dest->bSingleStep = src->bSingleStep; 2028 } 2029 else 2030 return FAILURE_T; 2031 2032 #endif 2033 return SUCCESS_T; 2034 } 2035 2036 return_t deserialize_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *pParams, 2037 NvU8 *buffer, 2038 NvU32 bufferSize, 2039 NvU32 *offset) 2040 { 2041 #ifdef COPY_INPUT_PARAMETERS 2042 NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 *src = (void*)(buffer); 2043 NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *dest = pParams; 2044 2045 if (src && dest) 2046 { 2047 dest->hChannelGroup = src->hChannelGroup; 2048 dest->mode = src->mode; 2049 dest->bEnableAllTpcs = src->bEnableAllTpcs; 2050 dest->grRouteInfo.flags = src->grRouteInfo.flags; 2051 dest->grRouteInfo.route = src->grRouteInfo.route; 2052 } 2053 else 2054 return FAILURE_T; 2055 2056 #endif 2057 return SUCCESS_T; 2058 } 2059 2060 return_t 2061 deserialize_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07( 2062 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *pParams, 2063 NvU8 *buffer, 2064 NvU32 bufferSize, 2065 NvU32 *offset) 2066 { 2067 #ifdef COPY_INPUT_PARAMETERS 2068 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 *src = 2069 (void*)(buffer); 2070 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *dest = pParams; 2071 2072 if (src && dest) 2073 { 2074 NvU32 i; 2075 2076 if (src->numValidEntries > 2077 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07) 2078 { 2079 return FAILURE_T; 2080 } 2081 2082 dest->numValidEntries = src->numValidEntries; 2083 2084 for (i = 0; i < src->numValidEntries; ++i) 2085 { 2086 dest->bar2Addr[i] = src->bar2Addr[i]; 2087 dest->methodBufferMemdesc[i].base = 2088 src->methodBufferMemdesc[i].base; 2089 dest->methodBufferMemdesc[i].size = 2090 src->methodBufferMemdesc[i].size; 2091 dest->methodBufferMemdesc[i].alignment = 2092 src->methodBufferMemdesc[i].alignment; 2093 dest->methodBufferMemdesc[i].addressSpace = 2094 src->methodBufferMemdesc[i].addressSpace; 2095 dest->methodBufferMemdesc[i].cpuCacheAttrib = 2096 src->methodBufferMemdesc[i].cpuCacheAttrib; 2097 } 2098 } 2099 else 2100 return FAILURE_T; 2101 2102 #endif 2103 return SUCCESS_T; 2104 } 2105 2106 return_t deserialize_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08(NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *pParams, 2107 NvU8 *buffer, 2108 NvU32 bufferSize, 2109 NvU32 *offset) 2110 { 2111 #ifdef COPY_INPUT_PARAMETERS 2112 NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 *src = (void*)(buffer); 2113 NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *dest = pParams; 2114 2115 if (src && dest) 2116 { 2117 dest->pmaChannelIdx = src->pmaChannelIdx; 2118 dest->bMembytesPollingRequired = src->bMembytesPollingRequired; 2119 } 2120 else 2121 return FAILURE_T; 2122 2123 #endif 2124 return SUCCESS_T; 2125 } 2126 2127 return_t deserialize_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06(NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *pParams, 2128 NvU8 *buffer, 2129 NvU32 bufferSize, 2130 NvU32 *offset) 2131 { 2132 #ifdef COPY_OUTPUT_PARAMETERS 2133 NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 *src = (void*)(buffer); 2134 NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *dest = pParams; 2135 2136 if (src && dest) 2137 { 2138 dest->bMode = src->bMode; 2139 } 2140 else 2141 return FAILURE_T; 2142 2143 #endif 2144 return SUCCESS_T; 2145 } 2146 #endif 2147 2148 #ifdef BUILD_LEGACY_RPCS 2149 return_t deserialize_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A( 2150 NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *pParams, 2151 NvU8 *buffer, 2152 NvU32 bufferSize, 2153 NvU32 *offset) 2154 { 2155 NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A *src = (void*)(buffer); 2156 NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *dest = pParams; 2157 2158 if (src && dest) 2159 { 2160 #ifdef COPY_INPUT_PARAMETERS 2161 dest->hChannel = src->hChannel; 2162 #endif 2163 #ifdef COPY_OUTPUT_PARAMETERS 2164 dest->totalBufferSize = src->totalBufferSize; 2165 #endif 2166 } 2167 else 2168 return FAILURE_T; 2169 2170 return SUCCESS_T; 2171 } 2172 #endif 2173 2174 #ifdef BUILD_LEGACY_RPCS 2175 return_t deserialize_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A( 2176 NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *pParams, 2177 NvU8 *buffer, 2178 NvU32 bufferSize, 2179 NvU32 *offset) 2180 { 2181 NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A *src = (void*)(buffer); 2182 NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *dest = pParams; 2183 2184 if (src && dest) 2185 { 2186 #ifdef COPY_INPUT_PARAMETERS 2187 dest->hUserClient = src->hUserClient; 2188 dest->hChannel = src->hChannel; 2189 #endif 2190 #ifdef COPY_OUTPUT_PARAMETERS 2191 dest->alignment = src->alignment; 2192 dest->size = src->size; 2193 dest->bufferHandle = src->bufferHandle; 2194 dest->pageCount = src->pageCount; 2195 dest->physAddr = src->physAddr; 2196 dest->aperture = src->aperture; 2197 dest->kind = src->kind; 2198 dest->pageSize = src->pageSize; 2199 dest->bIsContigous = src->bIsContigous; 2200 dest->bDeviceDescendant = src->bDeviceDescendant; 2201 portMemCopy(dest->uuid, sizeof(dest->uuid), 2202 src->uuid, sizeof(src->uuid)); 2203 #endif 2204 } 2205 else 2206 return FAILURE_T; 2207 2208 return SUCCESS_T; 2209 } 2210 #endif 2211 2212 #ifdef BUILD_COMMON_RPCS 2213 return_t deserialize_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_v1F_05( 2214 NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *pParams, 2215 NvU8 *buffer, 2216 NvU32 bufferSize, 2217 NvU32 *offset) 2218 { 2219 #ifdef COPY_INPUT_PARAMETERS 2220 NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 *src = (void*)(buffer); 2221 NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *dest = pParams; 2222 2223 if (src && dest) 2224 { 2225 dest->bZbcSurfacesExist = src->bZbcSurfacesExist; 2226 } 2227 else 2228 return FAILURE_T; 2229 #endif 2230 2231 return SUCCESS_T; 2232 } 2233 #endif 2234 2235 #ifdef BUILD_COMMON_RPCS 2236 static 2237 return_t deserialize_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C( 2238 NV00F8_CTRL_DESCRIBE_PARAMS *pParams, 2239 NvU8 *buffer, 2240 NvU32 bufferSize, 2241 NvU32 *offset) 2242 { 2243 NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C *src = (void*)(buffer); 2244 NV00F8_CTRL_DESCRIBE_PARAMS *dest = pParams; 2245 2246 if (src && dest) 2247 { 2248 #ifdef COPY_INPUT_PARAMETERS 2249 dest->offset = src->offset; 2250 #endif 2251 #ifdef COPY_OUTPUT_PARAMETERS 2252 NvU32 i; 2253 2254 portMemSet(dest, 0, sizeof(*dest)); 2255 2256 dest->totalPfns = src->totalPfns; 2257 for (i = 0; i < NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE; i++) 2258 { 2259 dest->pfnArray[i] = src->pfnArray[i]; 2260 } 2261 dest->numPfns = src->numPfns; 2262 #endif 2263 } 2264 else 2265 return FAILURE_T; 2266 2267 return SUCCESS_T; 2268 } 2269 2270 static 2271 return_t deserialize_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C( 2272 NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *pParams, 2273 NvU8 *buffer, 2274 NvU32 bufferSize, 2275 NvU32 *offset) 2276 { 2277 NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C *src = (void*)(buffer); 2278 NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *dest = pParams; 2279 2280 if (src && dest) 2281 { 2282 #ifdef COPY_OUTPUT_PARAMETERS 2283 dest->totalSize = src->totalSize; 2284 dest->freeSize = src->freeSize; 2285 #endif 2286 } 2287 else 2288 return FAILURE_T; 2289 2290 return SUCCESS_T; 2291 } 2292 2293 return_t deserialize_NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_v1F_0D(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams, 2294 NvU8 *buffer, 2295 NvU32 bufferSize, 2296 NvU32 *offset) 2297 { 2298 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B *src = (void *) buffer; 2299 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *dest = pParams; 2300 2301 if (src && dest) 2302 { 2303 #ifdef COPY_OUTPUT_PARAMETERS 2304 dest->eccMask = src->eccMask; 2305 dest->nvlinkMask = src->nvlinkMask; 2306 #endif 2307 } 2308 else 2309 return FAILURE_T; 2310 2311 return SUCCESS_T; 2312 } 2313 #endif 2314 2315 #ifdef BUILD_COMMON_RPCS 2316 #endif 2317 2318 #ifdef BUILD_COMMON_RPCS 2319 return_t deserialize_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C(NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams, 2320 NvU8 *buffer, 2321 NvU32 bufferSize, 2322 NvU32 *offset) 2323 { 2324 #ifdef COPY_INPUT_PARAMETERS 2325 NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C *src = (void*)(buffer); 2326 NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *dest = pParams; 2327 2328 if (src && dest) 2329 { 2330 dest->pmaChannelIdx = src->pmaChannelIdx; 2331 dest->pmaBufferVA = src->pmaBufferVA; 2332 dest->pmaBufferSize = src->pmaBufferSize; 2333 dest->membytesVA = src->membytesVA; 2334 dest->hwpmIBPA = src->hwpmIBPA; 2335 dest->hwpmIBAperture = src->hwpmIBAperture; 2336 } 2337 else 2338 return FAILURE_T; 2339 #endif 2340 return SUCCESS_T; 2341 } 2342 2343 return_t deserialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE_v24_05(NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *pParams, 2344 NvU8 *buffer, 2345 NvU32 bufferSize, 2346 NvU32 *offset) 2347 { 2348 NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 *src = (void *) buffer; 2349 NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *dest = pParams; 2350 NvU32 i; 2351 2352 if (src && dest) 2353 { 2354 if (src->execPartCount > NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05) { 2355 return FAILURE_T; 2356 } 2357 #ifdef COPY_INPUT_PARAMETERS 2358 dest->bQuery = src->bQuery; 2359 dest->execPartCount = src->execPartCount; 2360 2361 for (i = 0; i < dest->execPartCount; i++) { 2362 dest->execPartInfo[i].gpcCount = src->execPartInfo[i].gpcCount; 2363 2364 //Added in version v24_05 2365 dest->execPartInfo[i].gfxGpcCount = src->execPartInfo[i].gfxGpcCount; 2366 2367 dest->execPartInfo[i].veidCount = src->execPartInfo[i].veidCount; 2368 dest->execPartInfo[i].ceCount = src->execPartInfo[i].ceCount; 2369 dest->execPartInfo[i].nvEncCount = src->execPartInfo[i].nvEncCount; 2370 dest->execPartInfo[i].nvDecCount = src->execPartInfo[i].nvDecCount; 2371 dest->execPartInfo[i].nvJpgCount = src->execPartInfo[i].nvJpgCount; 2372 dest->execPartInfo[i].ofaCount = src->execPartInfo[i].ofaCount; 2373 dest->execPartInfo[i].sharedEngFlag = src->execPartInfo[i].sharedEngFlag; 2374 dest->execPartInfo[i].smCount = src->execPartInfo[i].smCount; 2375 dest->execPartInfo[i].spanStart = src->execPartInfo[i].spanStart; 2376 dest->execPartInfo[i].computeSize = src->execPartInfo[i].computeSize; 2377 } 2378 #endif 2379 2380 #ifdef COPY_OUTPUT_PARAMETERS 2381 for (i = 0; i < src->execPartCount; i++) { 2382 dest->execPartId[i] = src->execPartId[i]; 2383 dest->execPartInfo[i].computeSize = src->execPartInfo[i].computeSize; 2384 } 2385 #endif 2386 } 2387 else 2388 return FAILURE_T; 2389 2390 return SUCCESS_T; 2391 } 2392 2393 return_t deserialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE_v1F_0A(NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *pParams, 2394 NvU8 *buffer, 2395 NvU32 bufferSize, 2396 NvU32 *offset) 2397 { 2398 NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 *src = (void *) buffer; 2399 NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *dest = pParams; 2400 2401 if (src && dest) 2402 { 2403 #ifdef COPY_INPUT_PARAMETERS 2404 NvU32 i; 2405 2406 if (src->execPartCount > NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05) { 2407 return FAILURE_T; 2408 } 2409 2410 dest->execPartCount = src->execPartCount; 2411 for (i = 0; i < dest->execPartCount; i++) { 2412 dest->execPartId[i] = src->execPartId[i]; 2413 } 2414 #endif 2415 } 2416 else 2417 return FAILURE_T; 2418 2419 return SUCCESS_T; 2420 } 2421 2422 return_t deserialize_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_v1F_0A(NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *pParams, 2423 NvU8 *buffer, 2424 NvU32 bufferSize, 2425 NvU32 *offset) 2426 { 2427 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 *src = (void *) buffer; 2428 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *dest = pParams; 2429 2430 if (src && dest) 2431 { 2432 #ifdef COPY_OUTPUT_PARAMETERS 2433 dest->workSubmitToken = src->workSubmitToken; 2434 #endif 2435 } 2436 else 2437 return FAILURE_T; 2438 2439 return SUCCESS_T; 2440 } 2441 2442 return_t deserialize_NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_v1F_0A(NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *pParams, 2443 NvU8 *buffer, 2444 NvU32 bufferSize, 2445 NvU32 *offset) 2446 { 2447 NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 *src = (void *) buffer; 2448 NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *dest = pParams; 2449 2450 if (src && dest) 2451 { 2452 #ifdef COPY_INPUT_PARAMETERS 2453 dest->index = src->index; 2454 #endif 2455 } 2456 else 2457 return FAILURE_T; 2458 2459 return SUCCESS_T; 2460 } 2461 2462 return_t deserialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams, 2463 NvU8 *buffer, 2464 NvU32 bufferSize, 2465 NvU32 *offset) 2466 { 2467 #ifdef COPY_INPUT_PARAMETERS 2468 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 *src = (void*)(buffer); 2469 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *dest = pParams; 2470 if (src && dest) 2471 { 2472 dest->connectionType = src->connectionType; 2473 dest->peerId = src->peerId; 2474 dest->bSpaAccessOnly = src->bSpaAccessOnly; 2475 dest->bUseUuid = src->bUseUuid; 2476 2477 portMemCopy(dest->remoteGpuUuid, 2478 VM_UUID_SIZE_v21_02, 2479 src->remoteGpuUuid, 2480 VM_UUID_SIZE_v21_02); 2481 } 2482 else 2483 return FAILURE_T; 2484 #endif 2485 return SUCCESS_T; 2486 } 2487 2488 return_t deserialize_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams, 2489 NvU8 *buffer, 2490 NvU32 bufferSize, 2491 NvU32 *offset) 2492 { 2493 #ifdef COPY_INPUT_PARAMETERS 2494 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 *src = (void*)(buffer); 2495 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *dest = pParams; 2496 2497 if (src && dest) 2498 { 2499 dest->connectionType = src->connectionType; 2500 dest->peerId = src->peerId; 2501 dest->bUseUuid = src->bUseUuid; 2502 2503 portMemCopy(dest->remoteGpuUuid, 2504 VM_UUID_SIZE_v21_02, 2505 src->remoteGpuUuid, 2506 VM_UUID_SIZE_v21_02); 2507 } 2508 else 2509 return FAILURE_T; 2510 #endif 2511 return SUCCESS_T; 2512 } 2513 2514 #ifndef UMED_BUILD 2515 return_t deserialize_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11(NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, 2516 NvU8 *buffer, 2517 NvU32 bufferSize, 2518 NvU32 *offset) 2519 { 2520 NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 *src = (void*)(buffer); 2521 NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *dest = pParams; 2522 if (src && dest) 2523 { 2524 NvU32 i; 2525 if (src->gpuInfoListSize > NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11) { 2526 return FAILURE_T; 2527 } 2528 2529 #ifdef COPY_INPUT_PARAMETERS 2530 dest->gpuInfoListSize = src->gpuInfoListSize; 2531 #endif 2532 2533 for (i = 0; i < NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11; i++) { 2534 #ifdef COPY_INPUT_PARAMETERS 2535 dest->gpuInfoList[i].index = src->gpuInfoList[i].index; 2536 #endif 2537 dest->gpuInfoList[i].data = src->gpuInfoList[i].data; 2538 } 2539 } 2540 else 2541 return FAILURE_T; 2542 return SUCCESS_T; 2543 } 2544 #endif // UMED_BUILD 2545 2546 return_t deserialize_NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK_v21_05( 2547 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *pParams, 2548 NvU8 *buffer, 2549 NvU32 bufferSize, 2550 NvU32 *offset) 2551 { 2552 #ifdef COPY_INPUT_PARAMETERS 2553 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 *src = (void*)(buffer); 2554 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *dest = pParams; 2555 2556 if (src && dest) 2557 { 2558 dest->imbPhysAddr = src->imbPhysAddr; 2559 dest->addrSpace = src->addrSpace; 2560 dest->flaAction = src->flaAction; 2561 } 2562 else 2563 return FAILURE_T; 2564 #endif 2565 return SUCCESS_T; 2566 } 2567 2568 return_t deserialize_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *pParams, 2569 NvU8 *buffer, 2570 NvU32 bufferSize, 2571 NvU32 *offset) 2572 { 2573 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 *src = (void*)(buffer); 2574 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *dest = pParams; 2575 2576 if (src && dest) 2577 { 2578 #ifdef COPY_OUTPUT_PARAMETERS 2579 dest->numCredits = src->numCredits; 2580 #endif 2581 } 2582 else 2583 return FAILURE_T; 2584 return SUCCESS_T; 2585 } 2586 2587 return_t deserialize_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *pParams, 2588 NvU8 *buffer, 2589 NvU32 bufferSize, 2590 NvU32 *offset) 2591 { 2592 NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 *src = (void*)(buffer); 2593 NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *dest = pParams; 2594 2595 if (src && dest) 2596 { 2597 NvU32 i; 2598 if (src->numEntries > NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08) { 2599 return FAILURE_T; 2600 } 2601 #ifdef COPY_OUTPUT_PARAMETERS 2602 dest->statusInfo.status = src->statusInfo.status; 2603 dest->statusInfo.entryIndex = src->statusInfo.entryIndex; 2604 for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { 2605 dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; 2606 } 2607 2608 #endif 2609 #ifdef COPY_INPUT_PARAMETERS 2610 dest->pmaChannelIdx = src->pmaChannelIdx; 2611 dest->numEntries = src->numEntries; 2612 2613 for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { 2614 dest->creditInfo[i].chipletType = src->creditInfo[i].chipletType; 2615 dest->creditInfo[i].chipletIndex = src->creditInfo[i].chipletIndex; 2616 } 2617 #endif 2618 } 2619 else 2620 return FAILURE_T; 2621 return SUCCESS_T; 2622 } 2623 2624 return_t deserialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *pParams, 2625 NvU8 *buffer, 2626 NvU32 bufferSize, 2627 NvU32 *offset) 2628 { 2629 NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 *src = (void*)(buffer); 2630 NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *dest = pParams; 2631 2632 if (src && dest) 2633 { 2634 #ifdef COPY_OUTPUT_PARAMETERS 2635 dest->statusInfo.status = src->statusInfo.status; 2636 dest->statusInfo.entryIndex = src->statusInfo.entryIndex; 2637 #endif 2638 #ifdef COPY_INPUT_PARAMETERS 2639 NvU32 i; 2640 dest->pmaChannelIdx = src->pmaChannelIdx; 2641 dest->numEntries = src->numEntries; 2642 2643 if (src->numEntries > NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08) { 2644 return FAILURE_T; 2645 } 2646 2647 for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { 2648 dest->creditInfo[i].chipletType = src->creditInfo[i].chipletType; 2649 dest->creditInfo[i].chipletIndex = src->creditInfo[i].chipletIndex; 2650 dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; 2651 } 2652 #endif 2653 } 2654 else 2655 return FAILURE_T; 2656 return SUCCESS_T; 2657 } 2658 2659 #ifndef UMED_BUILD 2660 return_t deserialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *pParams, 2661 NvU8 *buffer, 2662 NvU32 bufferSize, 2663 NvU32 *offset) 2664 { 2665 NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 *src = (void*)(buffer); 2666 NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *dest = pParams; 2667 2668 if (src && dest) { 2669 dest->value = src->value; 2670 } 2671 else 2672 return FAILURE_T; 2673 2674 return SUCCESS_T; 2675 } 2676 #endif 2677 2678 #endif 2679 #endif //GSP_FW_BUILD 2680 2681 #undef COPY_INPUT_PARAMETERS 2682 #undef COPY_OUTPUT_PARAMETERS 2683 2684 // Copy elements from SDK structures to RPC structures (Step 1 or step 3 listed above) 2685 #ifdef VMIOP_BUILD 2686 #define COPY_OUTPUT_PARAMETERS 2687 #endif 2688 2689 #ifdef RESMAN_BUILD 2690 #define COPY_INPUT_PARAMETERS 2691 #endif 2692 2693 #ifdef GSP_FW_BUILD 2694 #define COPY_OUTPUT_PARAMETERS 2695 #endif 2696 2697 #ifndef GSP_FW_BUILD 2698 #ifdef BUILD_COMMON_RPCS 2699 2700 static 2701 return_t serialize_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01(NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams, 2702 NvU8 *buffer, 2703 NvU32 bufferSize, 2704 NvU32 *offset) 2705 { 2706 #ifdef COPY_INPUT_PARAMETERS 2707 NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *src = pParams; 2708 NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 *dest = (void*)(buffer); 2709 2710 if (src && dest) { 2711 dest->hResolution = src->hResolution; 2712 dest->vResolution = src->vResolution; 2713 dest->averageEncodeLatency = src->averageEncodeLatency; 2714 dest->averageEncodeFps = src->averageEncodeFps; 2715 dest->timestampBufferSize = 0; 2716 } 2717 else 2718 return FAILURE_T; 2719 #endif 2720 return SUCCESS_T; 2721 } 2722 2723 static 2724 return_t serialize_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01(NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *pParams, 2725 NvU8 *buffer, 2726 NvU32 bufferSize, 2727 NvU32 *offset) 2728 { 2729 #ifdef COPY_INPUT_PARAMETERS 2730 NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *src = pParams; 2731 NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 *dest = (void*)(buffer); 2732 2733 if (src && dest) { 2734 #ifdef VMIOP_BUILD 2735 dest->engineID = serialize_engineType(src->engineID); 2736 #else 2737 dest->engineID = src->engineID; 2738 #endif 2739 dest->subdeviceInstance = src->subdeviceInstance; 2740 dest->resetReason = src->resetReason; 2741 } 2742 else 2743 return FAILURE_T; 2744 #endif 2745 return SUCCESS_T; 2746 } 2747 2748 static 2749 return_t serialize_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00(NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *pParams, 2750 NvU8 *buffer, 2751 NvU32 bufferSize, 2752 NvU32 *offset) 2753 { 2754 NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *src = pParams; 2755 NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 *dest = (void*)(buffer); 2756 2757 if (src && dest) { 2758 dest->exceptType = src->exceptType; 2759 #ifdef VMIOP_BUILD 2760 dest->engineID = serialize_engineType(src->engineID); 2761 #else 2762 dest->engineID = src->engineID; 2763 #endif 2764 } 2765 else 2766 return FAILURE_T; 2767 return SUCCESS_T; 2768 } 2769 2770 static 2771 return_t serialize_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09(NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *pParams, 2772 NvU8 *buffer, 2773 NvU32 bufferSize, 2774 NvU32 *offset) 2775 { 2776 #ifdef COPY_INPUT_PARAMETERS 2777 NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *src = pParams; 2778 NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 *dest = (void*)(buffer); 2779 2780 if (src && dest) { 2781 dest->faultType = src->faultType; 2782 } 2783 else 2784 return FAILURE_T; 2785 #endif 2786 return SUCCESS_T; 2787 } 2788 2789 static 2790 return_t serialize_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00(NV2080_CTRL_PERF_BOOST_PARAMS *pParams, 2791 NvU8 *buffer, 2792 NvU32 bufferSize, 2793 NvU32 *offset) 2794 { 2795 NV2080_CTRL_PERF_BOOST_PARAMS *src = pParams; 2796 NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 *dest = (void*)(buffer); 2797 2798 if (src && dest) { 2799 dest->flags = src->flags; 2800 dest->duration = src->duration; 2801 } 2802 else 2803 return FAILURE_T; 2804 2805 return SUCCESS_T; 2806 } 2807 2808 static 2809 return_t serialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *pParams, 2810 NvU8 *buffer, 2811 NvU32 bufferSize, 2812 NvU32 *offset) 2813 { 2814 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *src = pParams; 2815 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 *dest = (void*)(buffer); 2816 2817 if (src && dest) { 2818 NvU32 i; 2819 for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { 2820 dest->value.colorFB[i] = src->value.colorFB[i]; 2821 dest->value.colorDS[i] = src->value.colorDS[i]; 2822 } 2823 dest->value.depth = src->value.depth; 2824 dest->value.stencil = src->value.stencil; // Changed in v04_00 2825 dest->indexSize = src->indexSize; 2826 dest->indexUsed = src->indexUsed; 2827 dest->format = src->format; 2828 dest->valType = src->valType; 2829 } 2830 else 2831 return FAILURE_T; 2832 2833 return SUCCESS_T; 2834 } 2835 2836 static 2837 return_t serialize_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *pParams, 2838 NvU8 *buffer, 2839 NvU32 bufferSize, 2840 NvU32 *offset) 2841 { 2842 NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *src = pParams; 2843 NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 *dest = (void*)(buffer); 2844 2845 if (src && dest) { 2846 NvU32 i; 2847 for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { 2848 dest->colorFB[i] = src->colorFB[i]; 2849 dest->colorDS[i] = src->colorDS[i]; 2850 } 2851 dest->format = src->format; 2852 } 2853 else 2854 return FAILURE_T; 2855 2856 return SUCCESS_T; 2857 } 2858 2859 static 2860 return_t serialize_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *pParams, 2861 NvU8 *buffer, 2862 NvU32 bufferSize, 2863 NvU32 *offset) 2864 { 2865 NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *src = pParams; 2866 NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 *dest = (void*)(buffer); 2867 2868 if (src && dest) { 2869 dest->depth = src->depth; 2870 dest->format = src->format; 2871 } 2872 else 2873 return FAILURE_T; 2874 2875 return SUCCESS_T; 2876 } 2877 2878 static 2879 return_t serialize_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *pParams, 2880 NvU8 *buffer, 2881 NvU32 bufferSize, 2882 NvU32 *offset) 2883 { 2884 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *src = pParams; 2885 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 *dest = (void*)(buffer); 2886 2887 if (src && dest) { 2888 dest->bEnable = src->bEnable; 2889 } 2890 else 2891 return FAILURE_T; 2892 2893 return SUCCESS_T; 2894 } 2895 2896 static 2897 return_t serialize_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00(NVA06C_CTRL_TIMESLICE_PARAMS *pParams, 2898 NvU8 *buffer, 2899 NvU32 bufferSize, 2900 NvU32 *offset) 2901 { 2902 NVA06C_CTRL_TIMESLICE_PARAMS *src = pParams; 2903 NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 *dest = (void*)(buffer); 2904 2905 if (src && dest) { 2906 dest->timesliceUs = src->timesliceUs; 2907 } 2908 else 2909 return FAILURE_T; 2910 2911 return SUCCESS_T; 2912 } 2913 2914 static 2915 return_t serialize_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *pParams, 2916 NvU8 *buffer, 2917 NvU32 bufferSize, 2918 NvU32 *offset) 2919 { 2920 #ifdef COPY_INPUT_PARAMETERS 2921 NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *src = pParams; 2922 NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 *dest = (void*)(buffer); 2923 NvU32 i; 2924 2925 if (src && dest) { 2926 if (src->numChannels > NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES) { 2927 return FAILURE_T; 2928 } 2929 dest->bDisable = src->bDisable; 2930 dest->numChannels = src->numChannels; 2931 dest->bOnlyDisableScheduling = src->bOnlyDisableScheduling; 2932 dest->bRewindGpPut = src->bRewindGpPut; 2933 dest->pRunlistPreemptEvent = 0; // vGPU do not support guest kernel handles 2934 2935 for (i = 0; i < src->numChannels ; i++) 2936 { 2937 dest->hClientList[i] = src->hClientList[i]; 2938 dest->hChannelList[i] = src->hChannelList[i]; 2939 } 2940 } 2941 else 2942 return FAILURE_T; 2943 #endif 2944 return SUCCESS_T; 2945 } 2946 2947 static 2948 return_t serialize_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A(NVA06C_CTRL_PREEMPT_PARAMS *pParams, 2949 NvU8 *buffer, 2950 NvU32 bufferSize, 2951 NvU32 *offset) 2952 { 2953 #ifdef COPY_INPUT_PARAMETERS 2954 NVA06C_CTRL_PREEMPT_PARAMS *src = pParams; 2955 NVA06C_CTRL_PREEMPT_PARAMS_v09_0A *dest = (void*)(buffer); 2956 2957 if (src && dest) { 2958 dest->bWait = src->bWait; 2959 dest->bManualTimeout = src->bManualTimeout; 2960 dest->timeoutUs = src->timeoutUs; 2961 } 2962 else 2963 return FAILURE_T; 2964 #endif 2965 return SUCCESS_T; 2966 } 2967 2968 static 2969 return_t serialize_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams, 2970 NvU8 *buffer, 2971 NvU32 bufferSize, 2972 NvU32 *offset) 2973 { 2974 #ifdef COPY_INPUT_PARAMETERS 2975 NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *src = pParams; 2976 NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *dest = (void*)(buffer); 2977 2978 if (src && dest) { 2979 dest->tsgInterleaveLevel = src->tsgInterleaveLevel; 2980 } 2981 else 2982 return FAILURE_T; 2983 #endif 2984 return SUCCESS_T; 2985 } 2986 2987 static 2988 return_t serialize_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams, 2989 NvU8 *buffer, 2990 NvU32 bufferSize, 2991 NvU32 *offset) 2992 { 2993 #ifdef COPY_INPUT_PARAMETERS 2994 NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *src = pParams; 2995 NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *dest = (void*)(buffer); 2996 2997 if (src && dest) { 2998 dest->channelInterleaveLevel = src->channelInterleaveLevel; 2999 } 3000 else 3001 return FAILURE_T; 3002 #endif 3003 return SUCCESS_T; 3004 } 3005 3006 static 3007 return_t serialize_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *pParams, 3008 NvU8 *buffer, 3009 NvU32 bufferSize, 3010 NvU32 *offset) 3011 { 3012 #ifdef COPY_INPUT_PARAMETERS 3013 NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *src = pParams; 3014 NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 *dest = (void*)(buffer); 3015 3016 if (src && dest) { 3017 NvU32 i; 3018 3019 dest->flags = src->flags; 3020 dest->hClient = src->hClient; 3021 dest->hChannel = src->hChannel; 3022 for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END; ++i) 3023 dest->vMemPtrs[i] = src->vMemPtrs[i]; 3024 dest->gfxpPreemptMode = src->gfxpPreemptMode; 3025 dest->cilpPreemptMode = src->cilpPreemptMode; 3026 dest->grRouteInfo.flags = src->grRouteInfo.flags; 3027 dest->grRouteInfo.route = src->grRouteInfo.route; 3028 } 3029 else 3030 return FAILURE_T; 3031 #endif 3032 return SUCCESS_T; 3033 } 3034 3035 static 3036 return_t serialize_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01(NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *pParams, 3037 NvU8 *buffer, 3038 NvU32 bufferSize, 3039 NvU32 *offset) 3040 { 3041 #ifdef COPY_INPUT_PARAMETERS 3042 NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *src = pParams; 3043 NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 *dest = (void*)(buffer); 3044 3045 if (src && dest) { 3046 dest->flags = src->flags; 3047 dest->hChannel = src->hChannel; 3048 dest->gfxpPreemptMode = src->gfxpPreemptMode; 3049 dest->cilpPreemptMode = src->cilpPreemptMode; 3050 dest->grRouteInfo.flags = src->grRouteInfo.flags; 3051 dest->grRouteInfo.route = src->grRouteInfo.route; 3052 } 3053 else 3054 return FAILURE_T; 3055 #endif 3056 return SUCCESS_T; 3057 } 3058 3059 static 3060 return_t serialize_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *pParams, 3061 NvU8 *buffer, 3062 NvU32 bufferSize, 3063 NvU32 *offset) 3064 { 3065 NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *src = pParams; 3066 NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 *dest = (void*)(buffer); 3067 3068 if (src && dest) { 3069 dest->hClient = src->hClient; 3070 dest->hChannel = src->hChannel; 3071 dest->vMemPtr = src->vMemPtr; 3072 dest->zcullMode = src->zcullMode; 3073 } 3074 else 3075 return FAILURE_T; 3076 3077 return SUCCESS_T; 3078 } 3079 3080 static 3081 return_t serialize_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *pParams, 3082 NvU8 *buffer, 3083 NvU32 bufferSize, 3084 NvU32 *offset) 3085 { 3086 #ifdef COPY_INPUT_PARAMETERS 3087 NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *src = pParams; 3088 NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 *dest = (void*)(buffer); 3089 3090 if (src && dest) { 3091 #ifdef VMIOP_BUILD 3092 dest->engineType = serialize_engineType(src->engineType); 3093 #else 3094 dest->engineType = src->engineType; 3095 #endif 3096 dest->hClient = src->hClient; 3097 dest->ChID = src->ChID; 3098 dest->hChanClient = src->hChanClient; 3099 dest->hObject = src->hObject; 3100 dest->hVirtMemory = src->hVirtMemory; 3101 dest->physAddress = src->physAddress; 3102 dest->physAttr = src->physAttr; 3103 dest->hDmaHandle = src->hDmaHandle; 3104 dest->index = src->index; 3105 dest->size = src->size; 3106 } 3107 else 3108 return FAILURE_T; 3109 #endif 3110 return SUCCESS_T; 3111 } 3112 3113 static 3114 return_t serialize_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pParams, 3115 NvU8 *buffer, 3116 NvU32 bufferSize, 3117 NvU32 *offset) 3118 { 3119 #ifdef COPY_INPUT_PARAMETERS 3120 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *src = pParams; 3121 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 *dest = (void*)(buffer); 3122 3123 if (src && dest) { 3124 NvU32 i; 3125 3126 if (src->numLevelsToCopy > GMMU_FMT_MAX_LEVELS_v1A_12) { 3127 return FAILURE_T; 3128 } 3129 3130 dest->hSubDevice = src->hSubDevice; 3131 dest->subDeviceId = src->subDeviceId; 3132 dest->pageSize = src->pageSize; 3133 dest->virtAddrLo = src->virtAddrLo; 3134 dest->virtAddrHi = src->virtAddrHi; 3135 dest->numLevelsToCopy = src->numLevelsToCopy; 3136 3137 for (i = 0; i < dest->numLevelsToCopy; i++) 3138 { 3139 dest->levels[i].physAddress = src->levels[i].physAddress; 3140 dest->levels[i].aperture = src->levels[i].aperture; 3141 dest->levels[i].size = src->levels[i].size; 3142 dest->levels[i].pageShift = src->levels[i].pageShift; 3143 } 3144 } 3145 else 3146 return FAILURE_T; 3147 #endif 3148 return SUCCESS_T; 3149 } 3150 #endif 3151 3152 #ifdef BUILD_LEGACY_RPCS 3153 #endif 3154 3155 #ifdef BUILD_COMMON_RPCS 3156 3157 static 3158 return_t serialize_GET_BRAND_CAPS_v25_12(NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *pParams, 3159 NvU8 *buffer, 3160 NvU32 bufferSize, 3161 NvU32 *offset) 3162 { 3163 #ifdef COPY_OUTPUT_PARAMETERS 3164 NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *src = pParams; 3165 rpc_get_brand_caps_v25_12 *dest = (void*)(buffer); 3166 3167 if (src && dest) { 3168 dest->brands = src->brands; 3169 } 3170 else 3171 return FAILURE_T; 3172 #endif 3173 3174 return SUCCESS_T; 3175 } 3176 3177 static 3178 return_t serialize_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01(NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *pParams, 3179 NvU8 *buffer, 3180 NvU32 bufferSize, 3181 NvU32 *offset) 3182 { 3183 #ifdef COPY_OUTPUT_PARAMETERS 3184 NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *src = pParams; 3185 NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 *dest = (void*)(buffer); 3186 3187 if (src && dest) { 3188 dest->engines = src->engines; 3189 } 3190 else 3191 return FAILURE_T; 3192 #endif 3193 return SUCCESS_T; 3194 } 3195 3196 static 3197 return_t serialize_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00(NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *pParams, 3198 NvU8 *buffer, 3199 NvU32 bufferSize, 3200 NvU32 *offset) 3201 { 3202 NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *src = pParams; 3203 NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 *dest = (void*)(buffer); 3204 3205 if (src && dest) { 3206 dest->hTargetChannel = src->hTargetChannel; 3207 dest->numSMsToClear = src->numSMsToClear; 3208 } 3209 else 3210 return FAILURE_T; 3211 3212 return SUCCESS_T; 3213 } 3214 3215 static 3216 return_t serialize_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06(NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *pParams, 3217 NvU8 *buffer, 3218 NvU32 bufferSize, 3219 NvU32 *offset) 3220 { 3221 NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *src = pParams; 3222 NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 *dest = (void*)(buffer); 3223 3224 if (src && dest) { 3225 #ifdef COPY_OUTPUT_PARAMETERS 3226 NvU32 i; 3227 #endif 3228 3229 #ifdef COPY_INPUT_PARAMETERS 3230 dest->hTargetChannel = src->hTargetChannel; 3231 #endif 3232 #ifdef COPY_OUTPUT_PARAMETERS 3233 if (src->numSMsToRead > VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06) { 3234 return FAILURE_T; 3235 } 3236 3237 for (i = 0; i < src->numSMsToRead; ++i) 3238 { 3239 dest->smErrorStateArray[i].hwwGlobalEsr = src->smErrorStateArray[i].hwwGlobalEsr; 3240 dest->smErrorStateArray[i].hwwWarpEsr = src->smErrorStateArray[i].hwwWarpEsr; 3241 dest->smErrorStateArray[i].hwwWarpEsrPc = src->smErrorStateArray[i].hwwWarpEsrPc; 3242 dest->smErrorStateArray[i].hwwGlobalEsrReportMask = src->smErrorStateArray[i].hwwGlobalEsrReportMask; 3243 dest->smErrorStateArray[i].hwwWarpEsrReportMask = src->smErrorStateArray[i].hwwWarpEsrReportMask; 3244 dest->smErrorStateArray[i].hwwEsrAddr = src->smErrorStateArray[i].hwwEsrAddr; 3245 dest->smErrorStateArray[i].hwwWarpEsrPc64 = src->smErrorStateArray[i].hwwWarpEsrPc64; 3246 /* New fields added in version v21_06 */ 3247 dest->smErrorStateArray[i].hwwCgaEsr = src->smErrorStateArray[i].hwwCgaEsr; 3248 dest->smErrorStateArray[i].hwwCgaEsrReportMask = src->smErrorStateArray[i].hwwCgaEsrReportMask; 3249 } 3250 dest->mmuFault.valid = src->mmuFault.valid; 3251 dest->mmuFault.faultInfo = src->mmuFault.faultInfo; 3252 dest->mmuFaultInfo = src->mmuFault.faultInfo; 3253 #endif 3254 } 3255 else 3256 return FAILURE_T; 3257 3258 return SUCCESS_T; 3259 } 3260 3261 static 3262 return_t serialize_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00(NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *pParams, 3263 NvU8 *buffer, 3264 NvU32 bufferSize, 3265 NvU32 *offset) 3266 { 3267 NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *src = pParams; 3268 NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 *dest = (void*)(buffer); 3269 3270 if (src && dest) { 3271 dest->exceptionMask = src->exceptionMask; 3272 } 3273 else 3274 return FAILURE_T; 3275 3276 return SUCCESS_T; 3277 } 3278 3279 static 3280 return_t serialize_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *pParams, 3281 NvU8 *buffer, 3282 NvU32 bufferSize, 3283 NvU32 *offset) 3284 { 3285 #ifdef COPY_INPUT_PARAMETERS 3286 NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *src = pParams; 3287 NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 *dest = (void*)(buffer); 3288 NvU32 i; 3289 3290 if (src && dest) 3291 { 3292 #ifdef VMIOP_BUILD 3293 dest->engineType = serialize_engineType(src->engineType); 3294 #else 3295 dest->engineType = src->engineType; 3296 #endif 3297 dest->hClient = src->hClient; 3298 dest->ChID = src->ChID; 3299 dest->hChanClient = src->hChanClient; 3300 dest->hObject = src->hObject; 3301 dest->hVirtMemory = src->hVirtMemory; 3302 dest->virtAddress = src->virtAddress; 3303 dest->size = src->size; 3304 dest->entryCount = src->entryCount; 3305 3306 if (dest->entryCount > NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES) { 3307 return FAILURE_T; 3308 } 3309 3310 for (i = 0; i < dest->entryCount; i++) { 3311 dest->promoteEntry[i].gpuPhysAddr = src->promoteEntry[i].gpuPhysAddr; 3312 dest->promoteEntry[i].gpuVirtAddr = src->promoteEntry[i].gpuVirtAddr; 3313 dest->promoteEntry[i].size = src->promoteEntry[i].size; 3314 dest->promoteEntry[i].physAttr = src->promoteEntry[i].physAttr; 3315 dest->promoteEntry[i].bufferId = src->promoteEntry[i].bufferId; 3316 dest->promoteEntry[i].bInitialize = src->promoteEntry[i].bInitialize; 3317 dest->promoteEntry[i].bNonmapped = src->promoteEntry[i].bNonmapped; 3318 } 3319 } 3320 else 3321 return FAILURE_T; 3322 #endif 3323 return SUCCESS_T; 3324 } 3325 3326 static 3327 return_t serialize_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06(NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *pParams, 3328 NvU8 *buffer, 3329 NvU32 bufferSize, 3330 NvU32 *offset) 3331 { 3332 NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *src = pParams; 3333 NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 *dest = (void*)(buffer); 3334 3335 if (src && dest) { 3336 #ifdef COPY_OUTPUT_PARAMETERS 3337 dest->waitForEvent = src->waitForEvent; 3338 dest->hResidentChannel = src->hResidentChannel; 3339 #endif 3340 } 3341 else 3342 return FAILURE_T; 3343 3344 return SUCCESS_T; 3345 } 3346 3347 static 3348 return_t serialize_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *pParams, 3349 NvU8 *buffer, 3350 NvU32 bufferSize, 3351 NvU32 *offset) 3352 { 3353 NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *src = pParams; 3354 NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 *dest = (void*)(buffer); 3355 3356 if (src && dest) { 3357 NvU32 idx = 0; 3358 #ifdef COPY_INPUT_PARAMETERS 3359 if (src->regOpCount > NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS) { 3360 return FAILURE_T; 3361 } 3362 3363 dest->bNonTransactional = src->bNonTransactional; 3364 dest->regOpCount = src->regOpCount; 3365 3366 for (idx = 0; idx < src->regOpCount; idx++) 3367 { 3368 dest->regOps[idx].regOp = src->regOps[idx].regOp; 3369 dest->regOps[idx].regType = src->regOps[idx].regType; 3370 dest->regOps[idx].regQuad = src->regOps[idx].regQuad; 3371 dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; 3372 dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; 3373 dest->regOps[idx].regOffset = src->regOps[idx].regOffset; 3374 dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; 3375 dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; 3376 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 3377 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 3378 } 3379 #endif 3380 #ifdef COPY_OUTPUT_PARAMETERS 3381 for (idx = 0; idx < src->regOpCount; idx++) 3382 { 3383 dest->regOps[idx].regStatus = src->regOps[idx].regStatus; 3384 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 3385 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 3386 } 3387 #endif 3388 } 3389 else 3390 return FAILURE_T; 3391 3392 return SUCCESS_T; 3393 } 3394 3395 static 3396 return_t serialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams, 3397 NvU8 *buffer, 3398 NvU32 bufferSize, 3399 NvU32 *offset) 3400 { 3401 NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *src = pParams; 3402 NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 *dest = (void*)(buffer); 3403 3404 if (src && dest) { 3405 #ifdef COPY_INPUT_PARAMETERS 3406 dest->action = src->action; 3407 #endif 3408 } 3409 else 3410 return FAILURE_T; 3411 3412 return SUCCESS_T; 3413 } 3414 3415 static 3416 return_t serialize_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06(NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *pParams, 3417 NvU8 *buffer, 3418 NvU32 bufferSize, 3419 NvU32 *offset) 3420 { 3421 NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *src = pParams; 3422 NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 *dest = (void*)(buffer); 3423 3424 if (src && dest) { 3425 #ifdef COPY_INPUT_PARAMETERS 3426 dest->hTargetChannel = src->hTargetChannel; 3427 dest->smID = src->smID; 3428 #endif 3429 #ifdef COPY_OUTPUT_PARAMETERS 3430 dest->smErrorState.hwwGlobalEsr = src->smErrorState.hwwGlobalEsr; 3431 dest->smErrorState.hwwWarpEsr = src->smErrorState.hwwWarpEsr; 3432 dest->smErrorState.hwwWarpEsrPc = src->smErrorState.hwwWarpEsrPc; 3433 dest->smErrorState.hwwGlobalEsrReportMask = src->smErrorState.hwwGlobalEsrReportMask; 3434 dest->smErrorState.hwwWarpEsrReportMask = src->smErrorState.hwwWarpEsrReportMask; 3435 dest->smErrorState.hwwEsrAddr = src->smErrorState.hwwEsrAddr; 3436 dest->smErrorState.hwwWarpEsrPc64 = src->smErrorState.hwwWarpEsrPc64; 3437 /* New fields added in version v21_06 */ 3438 dest->smErrorState.hwwCgaEsr = src->smErrorState.hwwCgaEsr; 3439 dest->smErrorState.hwwCgaEsrReportMask = src->smErrorState.hwwCgaEsrReportMask; 3440 #endif 3441 } 3442 else 3443 return FAILURE_T; 3444 3445 return SUCCESS_T; 3446 } 3447 3448 static 3449 return_t serialize_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *pParams, 3450 NvU8 *buffer, 3451 NvU32 bufferSize, 3452 NvU32 *offset) 3453 { 3454 NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *src = pParams; 3455 NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 *dest = (void*)(buffer); 3456 3457 if (src && dest) { 3458 #ifdef COPY_INPUT_PARAMETERS 3459 dest->hTargetChannel = src->hTargetChannel; 3460 dest->smID = src->smID; 3461 #endif 3462 } 3463 else 3464 return FAILURE_T; 3465 3466 return SUCCESS_T; 3467 } 3468 3469 static 3470 return_t serialize_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *pParams, 3471 NvU8 *buffer, 3472 NvU32 bufferSize, 3473 NvU32 *offset) 3474 { 3475 NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *src = pParams; 3476 NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 *dest = (void*)(buffer); 3477 3478 if (src && dest) { 3479 #ifdef COPY_INPUT_PARAMETERS 3480 dest->action = src->action; 3481 #endif 3482 } 3483 else 3484 return FAILURE_T; 3485 3486 return SUCCESS_T; 3487 } 3488 3489 static 3490 return_t serialize_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *pParams, 3491 NvU8 *buffer, 3492 NvU32 bufferSize, 3493 NvU32 *offset) 3494 { 3495 NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *src = pParams; 3496 NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 *dest = (void*)(buffer); 3497 3498 if (src && dest) { 3499 #ifdef COPY_INPUT_PARAMETERS 3500 dest->stopTriggerType = src->stopTriggerType; 3501 #endif 3502 } 3503 else 3504 return FAILURE_T; 3505 3506 return SUCCESS_T; 3507 } 3508 3509 static 3510 return_t serialize_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00(NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *pParams, 3511 NvU8 *buffer, 3512 NvU32 bufferSize, 3513 NvU32 *offset) 3514 { 3515 NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *src = pParams; 3516 NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 *dest = (void*)(buffer); 3517 3518 if (src && dest) { 3519 dest->hVASpace = src->hVASpace; 3520 } 3521 else 3522 return FAILURE_T; 3523 3524 return SUCCESS_T; 3525 } 3526 3527 static 3528 return_t serialize_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07(NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pParams, 3529 NvU8 *buffer, 3530 NvU32 bufferSize, 3531 NvU32 *offset) 3532 { 3533 NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *src = pParams; 3534 NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 *dest = (void*)(buffer); 3535 3536 if (src && dest) { 3537 #ifdef COPY_INPUT_PARAMETERS 3538 dest->ceEngineType = src->ceEngineType; 3539 #endif 3540 #ifdef COPY_OUTPUT_PARAMETERS 3541 dest->pceMask = src->pceMask; 3542 #endif 3543 } 3544 else 3545 return FAILURE_T; 3546 3547 return SUCCESS_T; 3548 } 3549 3550 static 3551 return_t serialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *pParams, 3552 NvU8 *buffer, 3553 NvU32 bufferSize, 3554 NvU32 *offset) 3555 { 3556 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *src = pParams; 3557 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 *dest = (void*)(buffer); 3558 3559 if (src && dest) { 3560 ct_assert(NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE == 4); 3561 3562 #ifdef COPY_INPUT_PARAMETERS 3563 dest->index = src->index; 3564 dest->tableType = src->tableType; 3565 #endif 3566 #ifdef COPY_OUTPUT_PARAMETERS 3567 NvU32 i; 3568 for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { 3569 dest->value.colorFB[i] = src->value.colorFB[i]; 3570 dest->value.colorDS[i] = src->value.colorDS[i]; 3571 } 3572 dest->value.depth = src->value.depth; 3573 dest->value.stencil = src->value.stencil; 3574 dest->format = src->format; 3575 dest->index = src->index; 3576 dest->bIndexValid = src->bIndexValid; 3577 dest->tableType = src->tableType; 3578 #endif 3579 } 3580 else 3581 return FAILURE_T; 3582 3583 return SUCCESS_T; 3584 } 3585 3586 static 3587 return_t serialize_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00(NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *pParams, 3588 NvU8 *buffer, 3589 NvU32 bufferSize, 3590 NvU32 *offset) 3591 { 3592 NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *src = pParams; 3593 NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00 *dest = (void*)(buffer); 3594 3595 if (src && dest) { 3596 #ifdef COPY_OUTPUT_PARAMETERS 3597 NvU32 i; 3598 3599 for (i = 0; i < NV2080_CTRL_BUS_MAX_NUM_GPUS; i++) { 3600 dest->nvlinkPeerIdMask[i] = src->nvlinkPeerIdMask[i]; 3601 } 3602 #endif 3603 } 3604 else 3605 return FAILURE_T; 3606 3607 return SUCCESS_T; 3608 } 3609 3610 static 3611 return_t serialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams, 3612 NvU8 *buffer, 3613 NvU32 bufferSize, 3614 NvU32 *offset) 3615 { 3616 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *src = pParams; 3617 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 *dest = (void*)(buffer); 3618 3619 if (src && dest) { 3620 #ifdef COPY_OUTPUT_PARAMETERS 3621 NvU32 i; 3622 3623 dest->enabledLinkMask = src->enabledLinkMask; 3624 3625 FOR_EACH_INDEX_IN_MASK(32, i, src->enabledLinkMask) 3626 { 3627 NV2080_CTRL_NVLINK_DEVICE_INFO *deviceInfo_s = NULL; 3628 NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 *deviceInfo_d = NULL; 3629 3630 if (i >= NV2080_CTRL_NVLINK_MAX_LINKS_v23_04) 3631 break; 3632 3633 dest->linkInfo[i].capsTbl = src->linkInfo[i].capsTbl; 3634 dest->linkInfo[i].phyType = src->linkInfo[i].phyType; 3635 dest->linkInfo[i].subLinkWidth = src->linkInfo[i].subLinkWidth; 3636 dest->linkInfo[i].linkState = src->linkInfo[i].linkState; 3637 dest->linkInfo[i].rxSublinkStatus = src->linkInfo[i].rxSublinkStatus; 3638 dest->linkInfo[i].txSublinkStatus = src->linkInfo[i].txSublinkStatus; 3639 dest->linkInfo[i].nvlinkVersion = src->linkInfo[i].nvlinkVersion; 3640 dest->linkInfo[i].nciVersion = src->linkInfo[i].nciVersion; 3641 dest->linkInfo[i].phyVersion = src->linkInfo[i].phyVersion; 3642 dest->linkInfo[i].nvlinkLinkClockKHz = src->linkInfo[i].nvlinkLinkClockKHz; 3643 dest->linkInfo[i].nvlinkLineRateMbps = src->linkInfo[i].nvlinkLineRateMbps; 3644 dest->linkInfo[i].connected = src->linkInfo[i].connected; 3645 dest->linkInfo[i].remoteDeviceLinkNumber = src->linkInfo[i].remoteDeviceLinkNumber; 3646 dest->linkInfo[i].localDeviceLinkNumber = src->linkInfo[i].localDeviceLinkNumber; 3647 3648 deviceInfo_d = &dest->linkInfo[i].localDeviceInfo; 3649 deviceInfo_s = &src->linkInfo[i].localDeviceInfo; 3650 3651 deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags; 3652 deviceInfo_d->domain = deviceInfo_s->domain; 3653 deviceInfo_d->bus = deviceInfo_s->bus; 3654 deviceInfo_d->device = deviceInfo_s->device; 3655 deviceInfo_d->function = deviceInfo_s->function; 3656 deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId; 3657 deviceInfo_d->deviceType = deviceInfo_s->deviceType; 3658 portMemCopy(deviceInfo_d->deviceUUID, 3659 sizeof(deviceInfo_d->deviceUUID), 3660 deviceInfo_s->deviceUUID, 3661 sizeof(deviceInfo_s->deviceUUID)); 3662 3663 deviceInfo_d = &dest->linkInfo[i].remoteDeviceInfo; 3664 deviceInfo_s = &src->linkInfo[i].remoteDeviceInfo; 3665 3666 deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags; 3667 deviceInfo_d->domain = deviceInfo_s->domain; 3668 deviceInfo_d->bus = deviceInfo_s->bus; 3669 deviceInfo_d->device = deviceInfo_s->device; 3670 deviceInfo_d->function = deviceInfo_s->function; 3671 deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId; 3672 deviceInfo_d->deviceType = deviceInfo_s->deviceType; 3673 portMemCopy(deviceInfo_d->deviceUUID, 3674 sizeof(deviceInfo_d->deviceUUID), 3675 deviceInfo_s->deviceUUID, 3676 sizeof(deviceInfo_s->deviceUUID)); 3677 } 3678 FOR_EACH_INDEX_IN_MASK_END; 3679 #endif 3680 } 3681 else 3682 return FAILURE_T; 3683 3684 return SUCCESS_T; 3685 } 3686 3687 static 3688 return_t serialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *pParams, 3689 NvU8 *buffer, 3690 NvU32 bufferSize, 3691 NvU32 *offset) 3692 { 3693 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *src = pParams; 3694 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D *dest = (void*)(buffer); 3695 3696 if (src && dest) { 3697 #ifdef COPY_INPUT_PARAMETERS 3698 portMemCopy(dest->gpuIds, (sizeof(NvU32) * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS), 3699 src->gpuIds, (sizeof(NvU32) * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)); 3700 dest->gpuCount = src->gpuCount; 3701 #endif 3702 #ifdef COPY_OUTPUT_PARAMETERS 3703 dest->p2pCaps = src->p2pCaps; 3704 dest->p2pOptimalReadCEs = src->p2pOptimalReadCEs; 3705 dest->p2pOptimalWriteCEs = src->p2pOptimalWriteCEs; 3706 memcpy(dest->p2pCapsStatus, src->p2pCapsStatus, NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D); 3707 #endif 3708 } 3709 else 3710 return FAILURE_T; 3711 3712 return SUCCESS_T; 3713 } 3714 3715 static 3716 return_t serialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *pParams, 3717 NvU8 *buffer, 3718 NvU32 bufferSize, 3719 NvU32 *offset) 3720 { 3721 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *src = pParams; 3722 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A *dest = (void*)(buffer); 3723 3724 if (src && dest) { 3725 if (src->grpACount == 0 || 3726 src->grpACount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS || 3727 src->grpBCount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS) { 3728 return FAILURE_T; 3729 } 3730 3731 #ifdef COPY_INPUT_PARAMETERS 3732 NvU32 idx = 0; 3733 3734 dest->grpACount = src->grpACount; 3735 dest->grpBCount = src->grpBCount; 3736 3737 for (idx = 0; idx < NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS; idx++) { 3738 dest->gpuIdGrpA[idx] = src->gpuIdGrpA[idx]; 3739 dest->gpuIdGrpB[idx] = src->gpuIdGrpB[idx]; 3740 } 3741 #endif 3742 #ifdef COPY_OUTPUT_PARAMETERS 3743 NvU32 grpAIdx = 0, grpBIdx= 0; 3744 3745 NvBool bReflexive = NV_FALSE; 3746 3747 // Check for the reflexive case 3748 if (src->grpBCount == 0) { 3749 bReflexive = NV_TRUE; 3750 } 3751 3752 for (grpAIdx = 0; grpAIdx < src->grpACount; grpAIdx++) { 3753 for (grpBIdx = 0; bReflexive ? grpBIdx <= grpAIdx : grpBIdx < src->grpBCount; grpBIdx++) { 3754 dest->p2pCaps[grpAIdx].array[grpBIdx] = src->p2pCaps[grpAIdx][grpBIdx]; 3755 dest->a2bOptimalReadCes[grpAIdx].array[grpBIdx] = src->a2bOptimalReadCes[grpAIdx][grpBIdx]; 3756 dest->a2bOptimalWriteCes[grpAIdx].array[grpBIdx] = src->a2bOptimalWriteCes[grpAIdx][grpBIdx]; 3757 dest->b2aOptimalReadCes[grpAIdx].array[grpBIdx] = src->b2aOptimalReadCes[grpAIdx][grpBIdx]; 3758 dest->b2aOptimalWriteCes[grpAIdx].array[grpBIdx] = src->b2aOptimalWriteCes[grpAIdx][grpBIdx]; 3759 } 3760 } 3761 #endif 3762 } 3763 else 3764 return FAILURE_T; 3765 3766 return SUCCESS_T; 3767 } 3768 3769 static 3770 return_t serialize_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02(NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams, 3771 NvU8 *buffer, 3772 NvU32 bufferSize, 3773 NvU32 *offset) 3774 { 3775 NV2080_CTRL_GET_P2P_CAPS_PARAMS *src = pParams; 3776 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 *dest = (void*)(buffer); 3777 3778 if (src && dest) { 3779 #ifdef COPY_INPUT_PARAMETERS 3780 if (!src->bAllCaps && (src->peerGpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)) 3781 return FAILURE_T; 3782 3783 dest->bAllCaps = src->bAllCaps; 3784 dest->bUseUuid = src->bUseUuid; 3785 3786 if (!src->bAllCaps) 3787 { 3788 NvU32 i; 3789 dest->peerGpuCount = src->peerGpuCount; 3790 3791 for (i = 0; i < src->peerGpuCount; ++i) 3792 { 3793 portMemCopy(dest->peerGpuCaps[i].gpuUuid, 3794 VM_UUID_SIZE_v21_02, 3795 src->peerGpuCaps[i].gpuUuid, 3796 VM_UUID_SIZE_v21_02); 3797 } 3798 } 3799 #endif 3800 #ifdef COPY_OUTPUT_PARAMETERS 3801 NvU32 i; 3802 3803 if (src->peerGpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS) 3804 return FAILURE_T; 3805 3806 if (src->bAllCaps) 3807 { 3808 dest->peerGpuCount = src->peerGpuCount; 3809 } 3810 3811 for (i = 0; i < src->peerGpuCount; ++i) 3812 { 3813 if (src->bAllCaps) 3814 { 3815 portMemCopy(dest->peerGpuCaps[i].gpuUuid, 3816 VM_UUID_SIZE_v21_02, 3817 src->peerGpuCaps[i].gpuUuid, 3818 VM_UUID_SIZE_v21_02); 3819 } 3820 3821 dest->peerGpuCaps[i].p2pCaps = src->peerGpuCaps[i].p2pCaps; 3822 dest->peerGpuCaps[i].p2pOptimalReadCEs = src->peerGpuCaps[i].p2pOptimalReadCEs; 3823 dest->peerGpuCaps[i].p2pOptimalWriteCEs = src->peerGpuCaps[i].p2pOptimalWriteCEs; 3824 portMemCopy(dest->peerGpuCaps[i].p2pCapsStatus, 3825 sizeof(dest->peerGpuCaps[i].p2pCapsStatus), 3826 src->peerGpuCaps[i].p2pCapsStatus, 3827 sizeof(src->peerGpuCaps[i].p2pCapsStatus)); 3828 dest->peerGpuCaps[i].busPeerId = src->peerGpuCaps[i].busPeerId; 3829 } 3830 #endif 3831 } 3832 else 3833 return FAILURE_T; 3834 3835 return SUCCESS_T; 3836 } 3837 3838 static 3839 return_t serialize_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F(NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *pParams, 3840 NvU8 *buffer, 3841 NvU32 bufferSize, 3842 NvU32 *offset) 3843 { 3844 #ifdef COPY_INPUT_PARAMETERS 3845 NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F *dest = (void*)(buffer); 3846 NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *src = pParams; 3847 3848 if (src && dest) 3849 { 3850 dest->ctxsw = src->ctxsw; 3851 } 3852 else 3853 return FAILURE_T; 3854 3855 #endif 3856 return SUCCESS_T; 3857 } 3858 3859 static 3860 return_t serialize_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F(NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *pParams, 3861 NvU8 *buffer, 3862 NvU32 bufferSize, 3863 NvU32 *offset) 3864 { 3865 #ifdef COPY_INPUT_PARAMETERS 3866 NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F *dest = (void*)(buffer); 3867 NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *src = pParams; 3868 if (src && dest) 3869 { 3870 dest->ctxsw = src->ctxsw; 3871 } 3872 else 3873 return FAILURE_T; 3874 #endif 3875 3876 return SUCCESS_T; 3877 } 3878 3879 static 3880 return_t serialize_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F(NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *pParams, 3881 NvU8 *buffer, 3882 NvU32 bufferSize, 3883 NvU32 *offset) 3884 { 3885 NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F *dest = (void*)(buffer); 3886 NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *src = pParams; 3887 NvU32 idx = 0; 3888 3889 if (src && dest) 3890 { 3891 if (src->regOpCount > NVB0CC_REGOPS_MAX_COUNT) { 3892 return FAILURE_T; 3893 } 3894 3895 #ifdef COPY_INPUT_PARAMETERS 3896 dest->regOpCount = src->regOpCount; 3897 dest->mode = src->mode; 3898 for (idx = 0; idx < src->regOpCount; idx++) 3899 { 3900 dest->regOps[idx].regOp = src->regOps[idx].regOp; 3901 dest->regOps[idx].regType = src->regOps[idx].regType; 3902 dest->regOps[idx].regQuad = src->regOps[idx].regQuad; 3903 dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; 3904 dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; 3905 dest->regOps[idx].regOffset = src->regOps[idx].regOffset; 3906 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 3907 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 3908 dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; 3909 dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; 3910 } 3911 #endif 3912 #ifdef COPY_OUTPUT_PARAMETERS 3913 dest->bPassed = src->bPassed; 3914 dest->bDirect = src->bDirect; 3915 for (idx = 0; idx < src->regOpCount; idx++) 3916 { 3917 dest->regOps[idx].regStatus = src->regOps[idx].regStatus; 3918 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 3919 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 3920 } 3921 #endif 3922 } 3923 else 3924 return FAILURE_T; 3925 3926 return SUCCESS_T; 3927 } 3928 3929 static 3930 return_t serialize_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams, 3931 NvU8 *buffer, 3932 NvU32 bufferSize, 3933 NvU32 *offset) 3934 { 3935 NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 *dest = (void*)(buffer); 3936 NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *src = pParams; 3937 3938 if (src && dest) 3939 { 3940 #ifdef COPY_INPUT_PARAMETERS 3941 dest->hMemPmaBuffer = src->hMemPmaBuffer; 3942 dest->pmaBufferOffset = src->pmaBufferOffset; 3943 dest->pmaBufferSize = src->pmaBufferSize; 3944 dest->hMemPmaBytesAvailable = src->hMemPmaBytesAvailable; 3945 dest->pmaBytesAvailableOffset = src->pmaBytesAvailableOffset; 3946 dest->ctxsw = src->ctxsw; 3947 #endif 3948 #ifdef COPY_OUTPUT_PARAMETERS 3949 dest->pmaChannelIdx = src->pmaChannelIdx; 3950 dest->pmaBufferVA = src->pmaBufferVA; 3951 #endif 3952 } 3953 else 3954 return FAILURE_T; 3955 3956 return SUCCESS_T; 3957 } 3958 3959 static 3960 return_t serialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams, 3961 NvU8 *buffer, 3962 NvU32 bufferSize, 3963 NvU32 *offset) 3964 { 3965 NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 *dest = (void*)(buffer); 3966 NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *src = pParams; 3967 3968 if (src && dest) 3969 { 3970 #ifdef COPY_INPUT_PARAMETERS 3971 dest->bytesConsumed = src->bytesConsumed; 3972 dest->bUpdateAvailableBytes = src->bUpdateAvailableBytes; 3973 dest->bWait = src->bWait; 3974 dest->bReturnPut = src->bReturnPut; 3975 dest->pmaChannelIdx = src->pmaChannelIdx; 3976 #endif 3977 #ifdef COPY_OUTPUT_PARAMETERS 3978 dest->bytesAvailable = src->bytesAvailable; 3979 dest->putPtr = src->putPtr; 3980 #endif 3981 } 3982 else 3983 return FAILURE_T; 3984 3985 return SUCCESS_T; 3986 } 3987 3988 static 3989 return_t serialize_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pParams, 3990 NvU8 *buffer, 3991 NvU32 bufferSize, 3992 NvU32 *offset){ 3993 NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *src = pParams; 3994 NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 *dest = (void*)(buffer); 3995 3996 if (src && dest) { 3997 NvU32 idx = 0; 3998 #ifdef COPY_INPUT_PARAMETERS 3999 if (src->regOpCount > NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07) { 4000 return FAILURE_T; 4001 } 4002 4003 dest->bNonTransactional = src->bNonTransactional; 4004 dest->regOpCount = src->regOpCount; 4005 dest->hClientTarget = src->hClientTarget; 4006 dest->hChannelTarget = src->hChannelTarget; 4007 4008 for (idx = 0; idx < src->regOpCount; idx++) 4009 { 4010 dest->regOps[idx].regOp = src->regOps[idx].regOp; 4011 dest->regOps[idx].regType = src->regOps[idx].regType; 4012 dest->regOps[idx].regQuad = src->regOps[idx].regQuad; 4013 dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; 4014 dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; 4015 dest->regOps[idx].regOffset = src->regOps[idx].regOffset; 4016 dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; 4017 dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; 4018 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 4019 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 4020 dest->smIds[idx] = src->smIds[idx]; 4021 } 4022 #endif 4023 #ifdef COPY_OUTPUT_PARAMETERS 4024 for (idx = 0; idx < src->regOpCount; idx++) 4025 { 4026 dest->regOps[idx].regStatus = src->regOps[idx].regStatus; 4027 dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; 4028 dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; 4029 } 4030 #endif 4031 } 4032 else 4033 return FAILURE_T; 4034 4035 return SUCCESS_T; 4036 } 4037 #endif 4038 4039 #ifdef BUILD_LEGACY_RPCS 4040 4041 #endif 4042 4043 #ifdef BUILD_COMMON_RPCS 4044 static 4045 return_t serialize_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00(NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *pParams, 4046 NvU8 *buffer, 4047 NvU32 bufferSize, 4048 NvU32 *offset) 4049 { 4050 NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *src = pParams; 4051 NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 *dest = (void*)(buffer); 4052 4053 if (src && dest) 4054 { 4055 dest->hChannel = src->hChannel; 4056 dest->property = src->property; 4057 dest->value = src->value; 4058 } 4059 else 4060 return FAILURE_T; 4061 4062 return SUCCESS_T; 4063 } 4064 #endif 4065 4066 #ifdef BUILD_LEGACY_RPCS 4067 return_t serialize_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A(NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS *pParams, 4068 NvU8 *buffer, 4069 NvU32 bufferSize, 4070 NvU32 *offset) 4071 { 4072 NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A *dest = (void*)(buffer); 4073 NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS *src = pParams; 4074 4075 if (src && dest) 4076 { 4077 #ifdef COPY_INPUT_PARAMETERS 4078 dest->hUserClient = src->hUserClient; 4079 dest->hChannel = src->hChannel; 4080 #endif 4081 #ifdef COPY_OUTPUT_PARAMETERS 4082 NvU32 i; 4083 4084 if ((src->bufferCount == 0) || (src->bufferCount > GR_MAX_RPC_CTX_BUFFER_COUNT)) 4085 return FAILURE_T; 4086 4087 for (i = 0; i < src->bufferCount; i++) { 4088 dest->ctxBufferInfo[i].alignment = src->ctxBufferInfo[i].alignment; 4089 dest->ctxBufferInfo[i].size = src->ctxBufferInfo[i].size; 4090 dest->ctxBufferInfo[i].bufferHandle = src->ctxBufferInfo[i].bufferHandle; 4091 dest->ctxBufferInfo[i].pageCount = src->ctxBufferInfo[i].pageCount; 4092 dest->ctxBufferInfo[i].physAddr = src->ctxBufferInfo[i].physAddr; 4093 dest->ctxBufferInfo[i].bufferType = src->ctxBufferInfo[i].bufferType; 4094 dest->ctxBufferInfo[i].aperture = src->ctxBufferInfo[i].aperture; 4095 dest->ctxBufferInfo[i].kind = src->ctxBufferInfo[i].kind; 4096 dest->ctxBufferInfo[i].pageSize = src->ctxBufferInfo[i].pageSize; 4097 dest->ctxBufferInfo[i].bIsContigous = src->ctxBufferInfo[i].bIsContigous; 4098 dest->ctxBufferInfo[i].bGlobalBuffer = src->ctxBufferInfo[i].bGlobalBuffer; 4099 dest->ctxBufferInfo[i].bLocalBuffer = src->ctxBufferInfo[i].bLocalBuffer; 4100 dest->ctxBufferInfo[i].bDeviceDescendant = src->ctxBufferInfo[i].bDeviceDescendant; 4101 portMemCopy(dest->ctxBufferInfo[i].uuid, sizeof(dest->ctxBufferInfo[i].uuid), 4102 src->ctxBufferInfo[i].uuid, sizeof(src->ctxBufferInfo[i].uuid)); 4103 } 4104 4105 dest->bufferCount = src->bufferCount; 4106 #endif 4107 } 4108 else 4109 return FAILURE_T; 4110 4111 return SUCCESS_T; 4112 } 4113 4114 #endif 4115 4116 #ifdef BUILD_COMMON_RPCS 4117 static 4118 return_t serialize_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v1A_1C( 4119 NV2080_CTRL_GPU_EVICT_CTX_PARAMS *pParams, 4120 NvU8 *buffer, 4121 NvU32 bufferSize, 4122 NvU32 *offset) 4123 { 4124 NV2080_CTRL_GPU_EVICT_CTX_PARAMS *src = pParams; 4125 NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 *dest = (void*)(buffer); 4126 4127 if (src && dest) 4128 { 4129 #ifdef COPY_INPUT_PARAMETERS 4130 #ifdef VMIOP_BUILD 4131 dest->engineType = serialize_engineType(src->engineType); 4132 #else 4133 dest->engineType = src->engineType; 4134 #endif 4135 dest->hClient = src->hClient; 4136 dest->ChID = src->ChID; 4137 dest->hChanClient = src->hChanClient; 4138 dest->hObject = src->hObject; 4139 #endif 4140 } 4141 else 4142 return FAILURE_T; 4143 4144 return SUCCESS_T; 4145 } 4146 4147 static 4148 return_t serialize_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D(NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *pParams, 4149 NvU8 *buffer, 4150 NvU32 bufferSize, 4151 NvU32 *offset) 4152 { 4153 NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D *dest = (void*)(buffer); 4154 NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *src = pParams; 4155 NvU32 idx = 0; 4156 4157 if (src && dest) 4158 { 4159 if (src->numQueries > NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D) { 4160 return FAILURE_T; 4161 } 4162 #ifdef COPY_INPUT_PARAMETERS 4163 dest->numQueries = src->numQueries; 4164 #endif 4165 for (idx = 0; idx < dest->numQueries; idx++) { 4166 #ifdef COPY_INPUT_PARAMETERS 4167 dest->queries[idx].queryType = src->queries[idx].queryType; 4168 #endif 4169 #ifdef COPY_OUTPUT_PARAMETERS 4170 dest->queries[idx].status = src->queries[idx].status; 4171 #endif 4172 switch(dest->queries[idx].queryType) 4173 { 4174 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT: { 4175 #ifdef COPY_OUTPUT_PARAMETERS 4176 dest->queries[idx].queryData.gpcCountData.gpcCount = src->queries[idx].queryData.gpcCountData.gpcCount; 4177 #endif 4178 break; 4179 } 4180 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP: { 4181 #ifdef COPY_INPUT_PARAMETERS 4182 dest->queries[idx].queryData.chipletGpcMapData.gpcId = src->queries[idx].queryData.chipletGpcMapData.gpcId; 4183 #endif 4184 #ifdef COPY_OUTPUT_PARAMETERS 4185 dest->queries[idx].queryData.chipletGpcMapData.chipletGpcMap = src->queries[idx].queryData.chipletGpcMapData.chipletGpcMap; 4186 #endif 4187 break; 4188 } 4189 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK: { 4190 #ifdef COPY_INPUT_PARAMETERS 4191 dest->queries[idx].queryData.tpcMaskData.gpcId = src->queries[idx].queryData.tpcMaskData.gpcId; 4192 #endif 4193 #ifdef COPY_OUTPUT_PARAMETERS 4194 dest->queries[idx].queryData.tpcMaskData.tpcMask = src->queries[idx].queryData.tpcMaskData.tpcMask; 4195 #endif 4196 break; 4197 } 4198 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK: { 4199 #ifdef COPY_INPUT_PARAMETERS 4200 dest->queries[idx].queryData.ppcMaskData.gpcId = src->queries[idx].queryData.ppcMaskData.gpcId; 4201 #endif 4202 #ifdef COPY_OUTPUT_PARAMETERS 4203 dest->queries[idx].queryData.ppcMaskData.ppcMask = src->queries[idx].queryData.ppcMaskData.ppcMask; 4204 #endif 4205 break; 4206 } 4207 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP: { 4208 #ifdef COPY_INPUT_PARAMETERS 4209 dest->queries[idx].queryData.partitionGpcMapData.swizzId = src->queries[idx].queryData.partitionGpcMapData.swizzId; 4210 dest->queries[idx].queryData.partitionGpcMapData.gpcId = src->queries[idx].queryData.partitionGpcMapData.gpcId; 4211 #endif 4212 #ifdef COPY_OUTPUT_PARAMETERS 4213 dest->queries[idx].queryData.partitionGpcMapData.chipletGpcMap = src->queries[idx].queryData.partitionGpcMapData.chipletGpcMap; 4214 #endif 4215 break; 4216 } 4217 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK: { 4218 #ifdef COPY_OUTPUT_PARAMETERS 4219 dest->queries[idx].queryData.syspipeMaskData.chipletSyspipeMask = src->queries[idx].queryData.syspipeMaskData.chipletSyspipeMask; 4220 #endif 4221 break; 4222 } 4223 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS: { 4224 #ifdef COPY_INPUT_PARAMETERS 4225 dest->queries[idx].queryData.partitionChipletSyspipeData.swizzId = src->queries[idx].queryData.partitionChipletSyspipeData.swizzId; 4226 #endif 4227 #ifdef COPY_OUTPUT_PARAMETERS 4228 dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount = src->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount; 4229 4230 if (dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount > NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D) { 4231 return FAILURE_T; 4232 } 4233 4234 for (idx = 0; idx < dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount; idx++) 4235 dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeId[idx] = src->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeId[idx]; 4236 #endif 4237 break; 4238 } 4239 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK: { 4240 #ifdef COPY_INPUT_PARAMETERS 4241 dest->queries[idx].queryData.dmGpcMaskData.swizzId = src->queries[idx].queryData.dmGpcMaskData.swizzId; 4242 dest->queries[idx].queryData.dmGpcMaskData.grIdx = src->queries[idx].queryData.dmGpcMaskData.grIdx; 4243 #endif 4244 #ifdef COPY_OUTPUT_PARAMETERS 4245 dest->queries[idx].queryData.dmGpcMaskData.gpcEnMask = src->queries[idx].queryData.dmGpcMaskData.gpcEnMask; 4246 #endif 4247 break; 4248 } 4249 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID: { 4250 #ifdef COPY_OUTPUT_PARAMETERS 4251 dest->queries[idx].queryData.partitionSyspipeIdData.syspipeId = src->queries[idx].queryData.partitionSyspipeIdData.syspipeId; 4252 #endif 4253 break; 4254 } 4255 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK: { 4256 #ifdef COPY_INPUT_PARAMETERS 4257 dest->queries[idx].queryData.ropMaskData.gpcId = src->queries[idx].queryData.ropMaskData.gpcId; 4258 #endif 4259 #ifdef COPY_OUTPUT_PARAMETERS 4260 dest->queries[idx].queryData.ropMaskData.ropMask = src->queries[idx].queryData.ropMaskData.ropMask; 4261 #endif 4262 break; 4263 } 4264 default: 4265 { 4266 // Unknown query 4267 return FAILURE_T; 4268 } 4269 } 4270 } 4271 } 4272 else 4273 return FAILURE_T; 4274 4275 return SUCCESS_T; 4276 } 4277 4278 static 4279 return_t serialize_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00(NV2080_CTRL_FB_GET_FS_INFO_PARAMS *pParams, 4280 NvU8 *buffer, 4281 NvU32 bufferSize, 4282 NvU32 *offset) 4283 { 4284 NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 *dest = (void*)(buffer); 4285 NV2080_CTRL_FB_GET_FS_INFO_PARAMS *src = pParams; 4286 NvU32 idx = 0; 4287 4288 if (src && dest) 4289 { 4290 if (src->numQueries > NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00) { 4291 return FAILURE_T; 4292 } 4293 4294 #ifdef COPY_INPUT_PARAMETERS 4295 dest->numQueries = src->numQueries; 4296 #endif 4297 for (idx = 0; idx < dest->numQueries; idx++) { 4298 #ifdef COPY_INPUT_PARAMETERS 4299 dest->queries[idx].queryType = src->queries[idx].queryType; 4300 #endif 4301 #ifdef COPY_OUTPUT_PARAMETERS 4302 dest->queries[idx].status = src->queries[idx].status; 4303 #endif 4304 switch(dest->queries[idx].queryType) 4305 { 4306 case NV2080_CTRL_FB_FS_INFO_INVALID_QUERY: { 4307 #ifdef COPY_OUTPUT_PARAMETERS 4308 NvU32 i = 0; 4309 for (i = 0; i < NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D; i++) { 4310 dest->queries[idx].queryParams.inv.data[i] = src->queries[idx].queryParams.inv.data[i]; 4311 } 4312 #endif 4313 break; 4314 } 4315 case NV2080_CTRL_FB_FS_INFO_FBP_MASK: { 4316 #ifdef COPY_INPUT_PARAMETERS 4317 dest->queries[idx].queryParams.fbp.swizzId = src->queries[idx].queryParams.fbp.swizzId; 4318 #endif 4319 #ifdef COPY_OUTPUT_PARAMETERS 4320 dest->queries[idx].queryParams.fbp.fbpEnMask = src->queries[idx].queryParams.fbp.fbpEnMask; 4321 #endif 4322 break; 4323 } 4324 case NV2080_CTRL_FB_FS_INFO_LTC_MASK: { 4325 #ifdef COPY_INPUT_PARAMETERS 4326 dest->queries[idx].queryParams.ltc.fbpIndex = src->queries[idx].queryParams.ltc.fbpIndex; 4327 #endif 4328 #ifdef COPY_OUTPUT_PARAMETERS 4329 dest->queries[idx].queryParams.ltc.ltcEnMask = src->queries[idx].queryParams.ltc.ltcEnMask; 4330 #endif 4331 break; 4332 } 4333 case NV2080_CTRL_FB_FS_INFO_LTS_MASK: { 4334 #ifdef COPY_INPUT_PARAMETERS 4335 dest->queries[idx].queryParams.lts.fbpIndex = src->queries[idx].queryParams.lts.fbpIndex; 4336 #endif 4337 #ifdef COPY_OUTPUT_PARAMETERS 4338 dest->queries[idx].queryParams.lts.ltsEnMask = src->queries[idx].queryParams.lts.ltsEnMask; 4339 #endif 4340 4341 break; 4342 } 4343 case NV2080_CTRL_FB_FS_INFO_FBPA_MASK: { 4344 #ifdef COPY_INPUT_PARAMETERS 4345 dest->queries[idx].queryParams.fbpa.fbpIndex = src->queries[idx].queryParams.fbpa.fbpIndex; 4346 #endif 4347 #ifdef COPY_OUTPUT_PARAMETERS 4348 dest->queries[idx].queryParams.fbpa.fbpaEnMask = src->queries[idx].queryParams.fbpa.fbpaEnMask; 4349 #endif 4350 break; 4351 } 4352 case NV2080_CTRL_FB_FS_INFO_ROP_MASK: { 4353 #ifdef COPY_INPUT_PARAMETERS 4354 dest->queries[idx].queryParams.rop.fbpIndex = src->queries[idx].queryParams.rop.fbpIndex; 4355 #endif 4356 #ifdef COPY_OUTPUT_PARAMETERS 4357 dest->queries[idx].queryParams.rop.ropEnMask = src->queries[idx].queryParams.rop.ropEnMask; 4358 #endif 4359 break; 4360 } 4361 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK: { 4362 #ifdef COPY_INPUT_PARAMETERS 4363 dest->queries[idx].queryParams.dmLtc.fbpIndex = src->queries[idx].queryParams.dmLtc.fbpIndex; 4364 dest->queries[idx].queryParams.dmLtc.swizzId = src->queries[idx].queryParams.dmLtc.swizzId; 4365 #endif 4366 #ifdef COPY_OUTPUT_PARAMETERS 4367 dest->queries[idx].queryParams.dmLtc.ltcEnMask = src->queries[idx].queryParams.dmLtc.ltcEnMask; 4368 #endif 4369 break; 4370 } 4371 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK: { 4372 #ifdef COPY_INPUT_PARAMETERS 4373 dest->queries[idx].queryParams.dmLts.fbpIndex = src->queries[idx].queryParams.dmLts.fbpIndex; 4374 dest->queries[idx].queryParams.dmLts.swizzId = src->queries[idx].queryParams.dmLts.swizzId; 4375 #endif 4376 #ifdef COPY_OUTPUT_PARAMETERS 4377 dest->queries[idx].queryParams.dmLts.ltsEnMask = src->queries[idx].queryParams.dmLts.ltsEnMask; 4378 #endif 4379 break; 4380 } 4381 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK: { 4382 #ifdef COPY_INPUT_PARAMETERS 4383 dest->queries[idx].queryParams.dmFbpa.fbpIndex = src->queries[idx].queryParams.dmFbpa.fbpIndex; 4384 dest->queries[idx].queryParams.dmFbpa.swizzId = src->queries[idx].queryParams.dmFbpa.swizzId; 4385 #endif 4386 #ifdef COPY_OUTPUT_PARAMETERS 4387 dest->queries[idx].queryParams.dmFbpa.fbpaEnMask = src->queries[idx].queryParams.dmFbpa.fbpaEnMask; 4388 #endif 4389 break; 4390 } 4391 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK: { 4392 #ifdef COPY_INPUT_PARAMETERS 4393 dest->queries[idx].queryParams.dmRop.fbpIndex = src->queries[idx].queryParams.dmRop.fbpIndex; 4394 dest->queries[idx].queryParams.dmRop.swizzId = src->queries[idx].queryParams.dmRop.swizzId; 4395 #endif 4396 #ifdef COPY_OUTPUT_PARAMETERS 4397 dest->queries[idx].queryParams.dmRop.ropEnMask = src->queries[idx].queryParams.dmRop.ropEnMask; 4398 #endif 4399 break; 4400 } 4401 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK: { 4402 #ifdef COPY_INPUT_PARAMETERS 4403 dest->queries[idx].queryParams.dmFbpaSubp.fbpIndex = src->queries[idx].queryParams.dmFbpaSubp.fbpIndex; 4404 dest->queries[idx].queryParams.dmFbpaSubp.swizzId = src->queries[idx].queryParams.dmFbpaSubp.swizzId; 4405 #endif 4406 #ifdef COPY_OUTPUT_PARAMETERS 4407 dest->queries[idx].queryParams.dmFbpaSubp.fbpaSubpEnMask = src->queries[idx].queryParams.dmFbpaSubp.fbpaSubpEnMask; 4408 #endif 4409 break; 4410 } 4411 case NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK: { 4412 #ifdef COPY_INPUT_PARAMETERS 4413 dest->queries[idx].queryParams.fbpaSubp.fbpIndex = src->queries[idx].queryParams.fbpaSubp.fbpIndex; 4414 #endif 4415 #ifdef COPY_OUTPUT_PARAMETERS 4416 dest->queries[idx].queryParams.fbpaSubp.fbpaSubpEnMask = src->queries[idx].queryParams.fbpaSubp.fbpaSubpEnMask; 4417 #endif 4418 break; 4419 } 4420 case NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP: { 4421 #ifdef COPY_INPUT_PARAMETERS 4422 dest->queries[idx].queryParams.fbpLogicalMap.fbpIndex = src->queries[idx].queryParams.fbpLogicalMap.fbpIndex; 4423 #endif 4424 #ifdef COPY_OUTPUT_PARAMETERS 4425 dest->queries[idx].queryParams.fbpLogicalMap.fbpLogicalIndex = src->queries[idx].queryParams.fbpLogicalMap.fbpLogicalIndex; 4426 #endif 4427 break; 4428 } 4429 default: 4430 { 4431 // Unknown query 4432 return FAILURE_T; 4433 } 4434 } 4435 } 4436 } 4437 else 4438 return FAILURE_T; 4439 4440 return SUCCESS_T; 4441 } 4442 4443 #ifdef VMIOP_BUILD 4444 4445 static 4446 return_t serialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams, 4447 NvU8 *buffer, 4448 NvU32 bufferSize, 4449 NvU32 *offset) 4450 { 4451 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06 *dest = (void*)(buffer); 4452 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *src = pParams; 4453 4454 if (src && dest) 4455 { 4456 #ifdef COPY_INPUT_PARAMETERS 4457 dest->flags = src->flags; 4458 #endif 4459 4460 #ifdef COPY_OUTPUT_PARAMETERS 4461 { 4462 NvU32 i; 4463 4464 dest->bFatalPoisonError = src->bFatalPoisonError; 4465 4466 for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06; i++) 4467 { 4468 dest->units[i].enabled = src->units[i].enabled; 4469 dest->units[i].scrubComplete = src->units[i].scrubComplete; 4470 dest->units[i].supported = src->units[i].supported; 4471 dest->units[i].dbe.count = src->units[i].dbe.count; 4472 dest->units[i].dbeNonResettable.count = src->units[i].dbeNonResettable.count; 4473 dest->units[i].sbe.count = src->units[i].sbe.count; 4474 dest->units[i].sbeNonResettable.count = src->units[i].sbeNonResettable.count; 4475 } 4476 } 4477 #endif 4478 } 4479 else 4480 return FAILURE_T; 4481 4482 return SUCCESS_T; 4483 } 4484 4485 #endif // VMIOP_BUILD 4486 4487 return_t serialize_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E( 4488 NVA06F_CTRL_STOP_CHANNEL_PARAMS *pParams, 4489 NvU8 *buffer, 4490 NvU32 bufferSize, 4491 NvU32 *offset) 4492 { 4493 NVA06F_CTRL_STOP_CHANNEL_PARAMS *src = pParams; 4494 NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E *dest = (void*)(buffer); 4495 4496 if (src && dest) 4497 { 4498 #ifdef COPY_INPUT_PARAMETERS 4499 dest->bImmediate = src->bImmediate; 4500 #endif 4501 } 4502 else 4503 return FAILURE_T; 4504 4505 return SUCCESS_T; 4506 } 4507 4508 return_t serialize_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F(NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *pParams, 4509 NvU8 *buffer, 4510 NvU32 bufferSize, 4511 NvU32 *offset) 4512 { 4513 #ifdef COPY_INPUT_PARAMETERS 4514 NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F *dest = (void*)(buffer); 4515 NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *src = pParams; 4516 4517 if (src && dest) 4518 { 4519 dest->pmaChannelIdx = src->pmaChannelIdx; 4520 } 4521 else 4522 return FAILURE_T; 4523 4524 #endif 4525 return SUCCESS_T; 4526 } 4527 4528 static 4529 return_t serialize_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F(NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *pParams, 4530 NvU8 *buffer, 4531 NvU32 bufferSize, 4532 NvU32 *offset) 4533 { 4534 #ifdef COPY_INPUT_PARAMETERS 4535 NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F *dest = (void*)(buffer); 4536 NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *src = pParams; 4537 4538 if (src && dest) 4539 { 4540 dest->hChannel = src->hChannel; 4541 dest->samplingMode = src->samplingMode; 4542 dest->grRouteInfo.flags = src->grRouteInfo.flags; 4543 dest->grRouteInfo.route = src->grRouteInfo.route; 4544 } 4545 else 4546 return FAILURE_T; 4547 4548 #endif 4549 return SUCCESS_T; 4550 } 4551 4552 static 4553 return_t serialize_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F(NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *pParams, 4554 NvU8 *buffer, 4555 NvU32 bufferSize, 4556 NvU32 *offset) 4557 { 4558 #ifdef COPY_INPUT_PARAMETERS 4559 NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F *dest = (void*)(buffer); 4560 NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *src = pParams; 4561 4562 if (src && dest) 4563 { 4564 dest->bSetMaxFreq = src->bSetMaxFreq; 4565 } 4566 else 4567 return FAILURE_T; 4568 4569 #endif 4570 return SUCCESS_T; 4571 } 4572 4573 static 4574 return_t serialize_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F(NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *pParams, 4575 NvU8 *buffer, 4576 NvU32 bufferSize, 4577 NvU32 *offset) 4578 { 4579 #ifdef COPY_OUTPUT_PARAMETERS 4580 NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F *dest = (void*)(buffer); 4581 NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *src = pParams; 4582 NvU32 i = 0; 4583 4584 if (src && dest) 4585 { 4586 dest->rm.clientActiveMask = src->rm.clientActiveMask; 4587 dest->rm.bRegkeyLimitRatedTdp = src->rm.bRegkeyLimitRatedTdp; 4588 dest->output = src->output; 4589 4590 for (i = 0; i < NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F; i++) 4591 { 4592 dest->inputs[i] = src->inputs[i]; 4593 } 4594 } 4595 else 4596 return FAILURE_T; 4597 4598 #endif 4599 return SUCCESS_T; 4600 } 4601 4602 static 4603 return_t serialize_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F(NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pParams, 4604 NvU8 *buffer, 4605 NvU32 bufferSize, 4606 NvU32 *offset) 4607 { 4608 #ifdef COPY_INPUT_PARAMETERS 4609 NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F *dest = (void*)(buffer); 4610 NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *src = pParams; 4611 4612 if (src && dest) 4613 { 4614 dest->client = src->client; 4615 dest->input = src->input; 4616 } 4617 else 4618 return FAILURE_T; 4619 4620 #endif 4621 return SUCCESS_T; 4622 } 4623 4624 static 4625 return_t serialize_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23( 4626 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *pParams, 4627 NvU8 *buffer, 4628 NvU32 bufferSize, 4629 NvU32 *offset) 4630 { 4631 #ifdef COPY_INPUT_PARAMETERS 4632 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 *dest = (void*)(buffer); 4633 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *src = pParams; 4634 4635 if (src && dest) 4636 { 4637 dest->base = src->base; 4638 dest->size = src->size; 4639 dest->addressSpace = src->addressSpace; 4640 dest->cacheAttrib = src->cacheAttrib; 4641 } 4642 else 4643 return FAILURE_T; 4644 4645 #endif 4646 return SUCCESS_T; 4647 } 4648 4649 return_t serialize_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02(NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *pParams, 4650 NvU8 *buffer, 4651 NvU32 bufferSize, 4652 NvU32 *offset) 4653 { 4654 #ifdef COPY_INPUT_PARAMETERS 4655 NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 *dest = (void*)(buffer); 4656 NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *src = pParams; 4657 4658 if (src && dest) 4659 { 4660 dest->smID = src->smID; 4661 dest->bSingleStep = src->bSingleStep; 4662 } 4663 else 4664 return FAILURE_T; 4665 4666 #endif 4667 return SUCCESS_T; 4668 } 4669 4670 return_t serialize_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *pParams, 4671 NvU8 *buffer, 4672 NvU32 bufferSize, 4673 NvU32 *offset) 4674 { 4675 #ifdef COPY_INPUT_PARAMETERS 4676 NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 *dest = (void*)(buffer); 4677 NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *src = pParams; 4678 4679 if (src && dest) 4680 { 4681 dest->hChannelGroup = src->hChannelGroup; 4682 dest->mode = src->mode; 4683 dest->bEnableAllTpcs = src->bEnableAllTpcs; 4684 dest->grRouteInfo.flags = src->grRouteInfo.flags; 4685 dest->grRouteInfo.route = src->grRouteInfo.route; 4686 } 4687 else 4688 return FAILURE_T; 4689 4690 #endif 4691 return SUCCESS_T; 4692 } 4693 4694 return_t 4695 serialize_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07( 4696 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *pParams, 4697 NvU8 *buffer, 4698 NvU32 bufferSize, 4699 NvU32 *offset) 4700 { 4701 #ifdef COPY_INPUT_PARAMETERS 4702 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 *dest = 4703 (void*)(buffer); 4704 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *src = pParams; 4705 4706 if (src && dest) 4707 { 4708 NvU32 i; 4709 if (src->numValidEntries > 4710 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07) 4711 { 4712 return FAILURE_T; 4713 } 4714 4715 dest->numValidEntries = src->numValidEntries; 4716 4717 for (i = 0; i < src->numValidEntries; ++i) 4718 { 4719 dest->bar2Addr[i] = src->bar2Addr[i]; 4720 dest->methodBufferMemdesc[i].base = 4721 src->methodBufferMemdesc[i].base; 4722 dest->methodBufferMemdesc[i].size = 4723 src->methodBufferMemdesc[i].size; 4724 dest->methodBufferMemdesc[i].alignment = 4725 src->methodBufferMemdesc[i].alignment; 4726 dest->methodBufferMemdesc[i].addressSpace = 4727 src->methodBufferMemdesc[i].addressSpace; 4728 dest->methodBufferMemdesc[i].cpuCacheAttrib = 4729 src->methodBufferMemdesc[i].cpuCacheAttrib; 4730 } 4731 } 4732 else 4733 return FAILURE_T; 4734 4735 #endif 4736 return SUCCESS_T; 4737 } 4738 4739 return_t serialize_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08(NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *pParams, 4740 NvU8 *buffer, 4741 NvU32 bufferSize, 4742 NvU32 *offset) 4743 { 4744 #ifdef COPY_INPUT_PARAMETERS 4745 NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 *dest = (void*)(buffer); 4746 NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *src = pParams; 4747 4748 if (src && dest) 4749 { 4750 dest->pmaChannelIdx = src->pmaChannelIdx; 4751 dest->bMembytesPollingRequired = src->bMembytesPollingRequired; 4752 } 4753 else 4754 return FAILURE_T; 4755 4756 #endif 4757 return SUCCESS_T; 4758 } 4759 4760 return_t serialize_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06(NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *pParams, 4761 NvU8 *buffer, 4762 NvU32 bufferSize, 4763 NvU32 *offset) 4764 { 4765 #ifdef COPY_OUTPUT_PARAMETERS 4766 NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 *dest = (void*)(buffer); 4767 NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *src = pParams; 4768 4769 if (src && dest) 4770 { 4771 dest->bMode = src->bMode; 4772 } 4773 else 4774 return FAILURE_T; 4775 4776 #endif 4777 return SUCCESS_T; 4778 } 4779 #endif 4780 4781 #ifdef BUILD_LEGACY_RPCS 4782 return_t serialize_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A( 4783 NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *pParams, 4784 NvU8 *buffer, 4785 NvU32 bufferSize, 4786 NvU32 *offset) 4787 { 4788 NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A *dest = (void*)(buffer); 4789 NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *src = pParams; 4790 4791 if (src && dest) 4792 { 4793 #ifdef COPY_INPUT_PARAMETERS 4794 dest->hChannel = src->hChannel; 4795 #endif 4796 #ifdef COPY_OUTPUT_PARAMETERS 4797 dest->totalBufferSize = src->totalBufferSize; 4798 #endif 4799 } 4800 else 4801 return FAILURE_T; 4802 4803 return SUCCESS_T; 4804 } 4805 #endif 4806 4807 #ifdef BUILD_LEGACY_RPCS 4808 return_t serialize_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A( 4809 NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *pParams, 4810 NvU8 *buffer, 4811 NvU32 bufferSize, 4812 NvU32 *offset) 4813 { 4814 NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A *dest = (void*)(buffer); 4815 NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *src = pParams; 4816 4817 if (src && dest) 4818 { 4819 #ifdef COPY_INPUT_PARAMETERS 4820 dest->hUserClient = src->hUserClient; 4821 dest->hChannel = src->hChannel; 4822 #endif 4823 #ifdef COPY_OUTPUT_PARAMETERS 4824 dest->alignment = src->alignment; 4825 dest->size = src->size; 4826 dest->bufferHandle = src->bufferHandle; 4827 dest->pageCount = src->pageCount; 4828 dest->physAddr = src->physAddr; 4829 dest->aperture = src->aperture; 4830 dest->kind = src->kind; 4831 dest->pageSize = src->pageSize; 4832 dest->bIsContigous = src->bIsContigous; 4833 dest->bDeviceDescendant = src->bDeviceDescendant; 4834 portMemCopy(dest->uuid, sizeof(dest->uuid), 4835 src->uuid, sizeof(src->uuid)); 4836 #endif 4837 } 4838 else 4839 return FAILURE_T; 4840 4841 return SUCCESS_T; 4842 } 4843 #endif 4844 4845 #ifdef BUILD_COMMON_RPCS 4846 static 4847 return_t serialize_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C( 4848 NV00F8_CTRL_DESCRIBE_PARAMS *pParams, 4849 NvU8 *buffer, 4850 NvU32 bufferSize, 4851 NvU32 *offset) 4852 { 4853 NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C *dest = (void*)(buffer); 4854 NV00F8_CTRL_DESCRIBE_PARAMS *src = pParams; 4855 4856 if (src && dest) 4857 { 4858 #ifdef COPY_INPUT_PARAMETERS 4859 dest->offset = src->offset; 4860 #endif 4861 #ifdef COPY_OUTPUT_PARAMETERS 4862 NvU32 i; 4863 dest->totalPfns = src->totalPfns; 4864 for (i = 0; i <NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE; i++) 4865 { 4866 dest->pfnArray[i] = src->pfnArray[i]; 4867 } 4868 dest->numPfns = src->numPfns; 4869 #endif 4870 } 4871 else 4872 return FAILURE_T; 4873 4874 return SUCCESS_T; 4875 } 4876 4877 static 4878 return_t serialize_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C( 4879 NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *pParams, 4880 NvU8 *buffer, 4881 NvU32 bufferSize, 4882 NvU32 *offset) 4883 { 4884 NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C *dest = (void*)(buffer); 4885 NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *src = pParams; 4886 4887 if (src && dest) 4888 { 4889 #ifdef COPY_OUTPUT_PARAMETERS 4890 dest->totalSize = src->totalSize; 4891 dest->freeSize = src->freeSize; 4892 #endif 4893 } 4894 else 4895 return FAILURE_T; 4896 4897 return SUCCESS_T; 4898 } 4899 4900 return_t serialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE_v24_05(NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *pParams, 4901 NvU8 *buffer, 4902 NvU32 bufferSize, 4903 NvU32 *offset) 4904 { 4905 NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 *dest = (void *) buffer; 4906 NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *src = pParams; 4907 NvU32 i; 4908 4909 if (src && dest) 4910 { 4911 if (src->execPartCount > NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05) { 4912 return FAILURE_T; 4913 } 4914 4915 #ifdef COPY_INPUT_PARAMETERS 4916 dest->bQuery = src->bQuery; 4917 dest->execPartCount = src->execPartCount; 4918 4919 for (i = 0; i < dest->execPartCount; i++) { 4920 dest->execPartInfo[i].gpcCount = src->execPartInfo[i].gpcCount; 4921 4922 // Added in version v24_05 4923 dest->execPartInfo[i].gfxGpcCount = src->execPartInfo[i].gfxGpcCount; 4924 4925 dest->execPartInfo[i].veidCount = src->execPartInfo[i].veidCount; 4926 dest->execPartInfo[i].ceCount = src->execPartInfo[i].ceCount; 4927 dest->execPartInfo[i].nvEncCount = src->execPartInfo[i].nvEncCount; 4928 dest->execPartInfo[i].nvDecCount = src->execPartInfo[i].nvDecCount; 4929 dest->execPartInfo[i].nvJpgCount = src->execPartInfo[i].nvJpgCount; 4930 dest->execPartInfo[i].ofaCount = src->execPartInfo[i].ofaCount; 4931 dest->execPartInfo[i].sharedEngFlag = src->execPartInfo[i].sharedEngFlag; 4932 dest->execPartInfo[i].smCount = src->execPartInfo[i].smCount; 4933 dest->execPartInfo[i].spanStart = src->execPartInfo[i].spanStart; 4934 dest->execPartInfo[i].computeSize = src->execPartInfo[i].computeSize; 4935 } 4936 #endif 4937 4938 #ifdef COPY_OUTPUT_PARAMETERS 4939 for (i = 0; i < src->execPartCount; i++) { 4940 dest->execPartId[i] = src->execPartId[i]; 4941 dest->execPartInfo[i].computeSize = src->execPartInfo[i].computeSize; 4942 } 4943 #endif 4944 } 4945 else 4946 return FAILURE_T; 4947 4948 return SUCCESS_T; 4949 } 4950 4951 return_t serialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE_v1F_0A(NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *pParams, 4952 NvU8 *buffer, 4953 NvU32 bufferSize, 4954 NvU32 *offset) 4955 { 4956 NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 *dest = (void *) buffer; 4957 NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *src = pParams; 4958 4959 if (src && dest) 4960 { 4961 #ifdef COPY_INPUT_PARAMETERS 4962 NvU32 i; 4963 4964 if (src->execPartCount > NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05) { 4965 return FAILURE_T; 4966 } 4967 4968 dest->execPartCount = src->execPartCount; 4969 for (i = 0; i < dest->execPartCount; i++) { 4970 dest->execPartId[i] = src->execPartId[i]; 4971 } 4972 #endif 4973 } 4974 else 4975 return FAILURE_T; 4976 4977 return SUCCESS_T; 4978 } 4979 4980 return_t serialize_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_v1F_0A(NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *pParams, 4981 NvU8 *buffer, 4982 NvU32 bufferSize, 4983 NvU32 *offset) 4984 { 4985 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 *dest = (void *) buffer; 4986 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *src = pParams; 4987 4988 if (src && dest) 4989 { 4990 #ifdef COPY_OUTPUT_PARAMETERS 4991 dest->workSubmitToken = src->workSubmitToken; 4992 #endif 4993 } 4994 else 4995 return FAILURE_T; 4996 4997 return SUCCESS_T; 4998 } 4999 5000 return_t serialize_NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_v1F_0A(NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *pParams, 5001 NvU8 *buffer, 5002 NvU32 bufferSize, 5003 NvU32 *offset) 5004 { 5005 5006 NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 *dest = (void *) buffer; 5007 NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *src = pParams; 5008 5009 if (src && dest) 5010 { 5011 #ifdef COPY_INPUT_PARAMETERS 5012 dest->index = src->index; 5013 #endif 5014 } 5015 else 5016 return FAILURE_T; 5017 5018 return SUCCESS_T; 5019 } 5020 5021 return_t serialize_NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_v1F_0D(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams, 5022 NvU8 *buffer, 5023 NvU32 bufferSize, 5024 NvU32 *offset) 5025 { 5026 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B *dest = (void *) buffer; 5027 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *src = pParams; 5028 5029 if (src && dest) 5030 { 5031 #ifdef COPY_OUTPUT_PARAMETERS 5032 dest->eccMask = src->eccMask; 5033 dest->nvlinkMask = src->nvlinkMask; 5034 #endif 5035 } 5036 else 5037 return FAILURE_T; 5038 5039 return SUCCESS_T; 5040 } 5041 5042 #endif 5043 5044 #ifdef BUILD_COMMON_RPCS 5045 return_t serialize_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_v1F_05( 5046 NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *pParams, 5047 NvU8 *buffer, 5048 NvU32 bufferSize, 5049 NvU32 *offset) 5050 { 5051 #ifdef COPY_INPUT_PARAMETERS 5052 NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 *dest = (void*)(buffer); 5053 NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *src = pParams; 5054 5055 if (src && dest) 5056 { 5057 dest->bZbcSurfacesExist = src->bZbcSurfacesExist; 5058 } 5059 else 5060 return FAILURE_T; 5061 #endif 5062 return SUCCESS_T; 5063 } 5064 #endif 5065 5066 #ifdef BUILD_COMMON_RPCS 5067 return_t serialize_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C(NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams, 5068 NvU8 *buffer, 5069 NvU32 bufferSize, 5070 NvU32 *offset) 5071 { 5072 #ifdef COPY_INPUT_PARAMETERS 5073 NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C *dest = (void*)(buffer); 5074 NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *src = pParams; 5075 5076 if (src && dest) 5077 { 5078 dest->pmaChannelIdx = src->pmaChannelIdx; 5079 dest->pmaBufferVA = src->pmaBufferVA; 5080 dest->pmaBufferSize = src->pmaBufferSize; 5081 dest->membytesVA = src->membytesVA; 5082 dest->hwpmIBPA = src->hwpmIBPA; 5083 dest->hwpmIBAperture = src->hwpmIBAperture; 5084 } 5085 else 5086 return FAILURE_T; 5087 #endif 5088 return SUCCESS_T; 5089 } 5090 5091 #ifdef BUILD_COMMON_RPCS 5092 return_t serialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams, 5093 NvU8 *buffer, 5094 NvU32 bufferSize, 5095 NvU32 *offset) 5096 { 5097 #ifdef COPY_INPUT_PARAMETERS 5098 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 *dest = (void*)(buffer); 5099 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *src = pParams; 5100 5101 if (src && dest) 5102 { 5103 dest->connectionType = src->connectionType; 5104 dest->peerId = src->peerId; 5105 dest->bSpaAccessOnly = src->bSpaAccessOnly; 5106 dest->bUseUuid = src->bUseUuid; 5107 5108 portMemCopy(dest->remoteGpuUuid, 5109 VM_UUID_SIZE_v21_02, 5110 src->remoteGpuUuid, 5111 VM_UUID_SIZE_v21_02); 5112 } 5113 else 5114 return FAILURE_T; 5115 #endif 5116 return SUCCESS_T; 5117 } 5118 #endif 5119 5120 #ifdef BUILD_COMMON_RPCS 5121 return_t serialize_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams, 5122 NvU8 *buffer, 5123 NvU32 bufferSize, 5124 NvU32 *offset) 5125 { 5126 #ifdef COPY_INPUT_PARAMETERS 5127 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 *dest = (void*)(buffer); 5128 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *src = pParams; 5129 5130 if (src && dest) 5131 { 5132 dest->connectionType = src->connectionType; 5133 dest->peerId = src->peerId; 5134 dest->bUseUuid = src->bUseUuid; 5135 5136 portMemCopy(dest->remoteGpuUuid, 5137 VM_UUID_SIZE_v21_02, 5138 src->remoteGpuUuid, 5139 VM_UUID_SIZE_v21_02); 5140 } 5141 else 5142 return FAILURE_T; 5143 #endif 5144 return SUCCESS_T; 5145 } 5146 5147 #ifndef UMED_BUILD 5148 return_t serialize_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11(NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, 5149 NvU8 *buffer, 5150 NvU32 bufferSize, 5151 NvU32 *offset) 5152 { 5153 NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 *dest = (void*)(buffer); 5154 NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *src = pParams; 5155 5156 if (src && dest) 5157 { 5158 NvU32 i; 5159 if (src->gpuInfoListSize > NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11) { 5160 return FAILURE_T; 5161 } 5162 5163 #ifdef COPY_INPUT_PARAMETERS 5164 dest->gpuInfoListSize = src->gpuInfoListSize; 5165 #endif 5166 5167 for (i = 0; i < NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11; i++) { 5168 #ifdef COPY_INPUT_PARAMETERS 5169 dest->gpuInfoList[i].index = src->gpuInfoList[i].index; 5170 #endif 5171 dest->gpuInfoList[i].data = src->gpuInfoList[i].data; 5172 } 5173 } 5174 else 5175 return FAILURE_T; 5176 return SUCCESS_T; 5177 } 5178 #endif // UMED_BUILD 5179 5180 return_t serialize_NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK_v21_05( 5181 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *pParams, 5182 NvU8 *buffer, 5183 NvU32 bufferSize, 5184 NvU32 *offset) 5185 { 5186 #ifdef COPY_INPUT_PARAMETERS 5187 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 *dest = (void*)(buffer); 5188 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *src = pParams; 5189 5190 if (src && dest) 5191 { 5192 dest->imbPhysAddr = src->imbPhysAddr; 5193 dest->addrSpace = src->addrSpace; 5194 dest->flaAction = src->flaAction; 5195 } 5196 else 5197 return FAILURE_T; 5198 #endif 5199 return SUCCESS_T; 5200 } 5201 5202 return_t serialize_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *pParams, 5203 NvU8 *buffer, 5204 NvU32 bufferSize, 5205 NvU32 *offset) 5206 { 5207 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 *dest = (void*)(buffer); 5208 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *src = pParams; 5209 if (src && dest) 5210 { 5211 #ifdef COPY_OUTPUT_PARAMETERS 5212 dest->numCredits = src->numCredits; 5213 #endif 5214 } 5215 else 5216 return FAILURE_T; 5217 return SUCCESS_T; 5218 } 5219 5220 return_t serialize_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *pParams, 5221 NvU8 *buffer, 5222 NvU32 bufferSize, 5223 NvU32 *offset) 5224 { 5225 NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 *dest = (void*)(buffer); 5226 NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *src = pParams; 5227 if (src && dest) 5228 { 5229 NvU32 i; 5230 if (src->numEntries > NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08) { 5231 return FAILURE_T; 5232 } 5233 #ifdef COPY_OUTPUT_PARAMETERS 5234 dest->statusInfo.status = src->statusInfo.status; 5235 dest->statusInfo.entryIndex = src->statusInfo.entryIndex; 5236 for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { 5237 dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; 5238 } 5239 #endif 5240 #ifdef COPY_INPUT_PARAMETERS 5241 dest->pmaChannelIdx = src->pmaChannelIdx; 5242 dest->numEntries = src->numEntries; 5243 5244 for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { 5245 dest->creditInfo[i].chipletType = src->creditInfo[i].chipletType; 5246 dest->creditInfo[i].chipletIndex = src->creditInfo[i].chipletIndex; 5247 dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; 5248 } 5249 #endif 5250 } 5251 else 5252 return FAILURE_T; 5253 return SUCCESS_T; 5254 } 5255 5256 return_t serialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *pParams, 5257 NvU8 *buffer, 5258 NvU32 bufferSize, 5259 NvU32 *offset) 5260 { 5261 NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 *dest = (void*)(buffer); 5262 NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *src = pParams; 5263 5264 if (src && dest) 5265 { 5266 #ifdef COPY_OUTPUT_PARAMETERS 5267 dest->statusInfo.status = src->statusInfo.status; 5268 dest->statusInfo.entryIndex = src->statusInfo.entryIndex; 5269 #endif 5270 #ifdef COPY_INPUT_PARAMETERS 5271 NvU32 i; 5272 dest->pmaChannelIdx = src->pmaChannelIdx; 5273 dest->numEntries = src->numEntries; 5274 5275 if (src->numEntries > NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08) { 5276 return FAILURE_T; 5277 } 5278 5279 for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { 5280 dest->creditInfo[i].chipletType = src->creditInfo[i].chipletType; 5281 dest->creditInfo[i].chipletIndex = src->creditInfo[i].chipletIndex; 5282 dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; 5283 } 5284 #endif 5285 } 5286 else 5287 return FAILURE_T; 5288 return SUCCESS_T; 5289 } 5290 5291 #ifndef UMED_BUILD 5292 return_t serialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *pParams, 5293 NvU8 *buffer, 5294 NvU32 bufferSize, 5295 NvU32 *offset) 5296 { 5297 NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *src = pParams; 5298 NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 *dest = (void*)(buffer); 5299 5300 if (src && dest) { 5301 dest->value = src->value; 5302 } 5303 else 5304 return FAILURE_T; 5305 5306 return SUCCESS_T; 5307 } 5308 #endif 5309 5310 #endif 5311 #endif 5312 #endif //GSP_FW_BUILD 5313 5314 #if defined(BUILD_COMMON_RPCS) 5315 static 5316 return_t serialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams, 5317 NvU8 *buffer, 5318 NvU32 bufferSize, 5319 NvU32 *offset) 5320 { 5321 NV2080_CTRL_FB_GET_INFO_V2_PARAMS *src = pParams; 5322 NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A *dest = (void*)(buffer); 5323 5324 if (src && dest) 5325 { 5326 NvU32 i; 5327 5328 if ((src->fbInfoListSize == 0) || 5329 (src->fbInfoListSize > NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A)) { 5330 return FAILURE_T; 5331 } 5332 5333 dest->fbInfoListSize = src->fbInfoListSize; 5334 5335 for (i = 0; i < src->fbInfoListSize; i++) { 5336 dest->fbInfoList[i].index = src->fbInfoList[i].index; 5337 dest->fbInfoList[i].data = src->fbInfoList[i].data; 5338 } 5339 } 5340 else 5341 return FAILURE_T; 5342 5343 return SUCCESS_T; 5344 } 5345 5346 static 5347 return_t deserialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams, 5348 NvU8 *buffer, 5349 NvU32 bufferSize, 5350 NvU32 *offset) 5351 { 5352 NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A *src = (void*)(buffer); 5353 NV2080_CTRL_FB_GET_INFO_V2_PARAMS *dest = pParams; 5354 5355 if (src && dest) 5356 { 5357 NvU32 i; 5358 5359 if ((src->fbInfoListSize == 0) || 5360 (src->fbInfoListSize > NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A)) { 5361 return FAILURE_T; 5362 } 5363 5364 dest->fbInfoListSize = src->fbInfoListSize; 5365 5366 for (i = 0; i < src->fbInfoListSize; i++) { 5367 dest->fbInfoList[i].index = src->fbInfoList[i].index; 5368 dest->fbInfoList[i].data = src->fbInfoList[i].data; 5369 } 5370 } 5371 else 5372 return FAILURE_T; 5373 5374 return SUCCESS_T; 5375 } 5376 #endif // defined(BUILD_COMMON_RPCS) 5377 5378 #ifndef GSP_FW_BUILD 5379 #ifdef BUILD_COMMON_RPCS 5380 #ifndef RESMAN_BUILD 5381 /** 5382 * Copy static info from `buffer` to local VGPU_STATIC_INFO `pVSI` or vice versa. 5383 * This routine is built into host (VMIOP) and guest (RM). 5384 * VGPU host populates its local VGPU_STATIC_INFO struct and uses this function to serialize 5385 * struct members into `buffer`. 5386 * VGPU guest calls GET_CONSOLIDATED_STATIC_INFO RPC to receive `buffer`, and calls this routine 5387 * to deserialize struct members from `buffer` into guest's VGPU_STATIC_INFO. 5388 * 5389 * Serialization and deserialization happens according to negotiated RPC protocol version. 5390 * Struct members in VGPU_STATIC_INFO must not be reordered. Any additions to 5391 * VGPU_STATIC_INFO should be done at the end of the struct, and handled in this function by 5392 * checking for protocol version. 5393 */ 5394 static NV_STATUS consolidated_static_info_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy, 5395 VGPU_STATIC_INFO *pVSI, 5396 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset, 5397 NvBool bAlignOffset) 5398 { 5399 NV_STATUS status = NVOS_STATUS_SUCCESS; 5400 5401 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5402 status = serialize_deserialize(NV2080_CTRL_CLK_GET_DOMAINS_PARAMS)(pObjRpcStructureCopy, 5403 &pVSI->clkDomains, 5404 buffer, 5405 bufferSize, 5406 offset); 5407 if (status != NVOS_STATUS_SUCCESS) { 5408 return status; 5409 } 5410 5411 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5412 status = serialize_deserialize(NV2080_CTRL_CLK_GET_PUBLIC_DOMAINS_PARAMS)(pObjRpcStructureCopy, 5413 &pVSI->clkPublicDomains, 5414 buffer, 5415 bufferSize, 5416 offset); 5417 if (status != NVOS_STATUS_SUCCESS) { 5418 return status; 5419 } 5420 5421 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5422 status = serialize_deserialize(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS)(pObjRpcStructureCopy, 5423 NULL, 5424 buffer, 5425 bufferSize, 5426 offset); 5427 if (status != NVOS_STATUS_SUCCESS) { 5428 return status; 5429 } 5430 5431 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5432 status = serialize_deserialize(NV2080_CTRL_PERF_GET_TABLE_INFO_PARAMS)(pObjRpcStructureCopy, 5433 &pVSI->perfTableInfo, 5434 buffer, 5435 bufferSize, 5436 offset); 5437 if (status != NVOS_STATUS_SUCCESS) { 5438 return status; 5439 } 5440 5441 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5442 status = serialize_deserialize(vgpuPstateInfo)(pObjRpcStructureCopy, 5443 &pVSI->pstateInfo, 5444 buffer, 5445 bufferSize, 5446 offset); 5447 if (status != NVOS_STATUS_SUCCESS) { 5448 return status; 5449 } 5450 5451 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5452 status = serialize_deserialize(VGPU_DISPLAYLESS_INFO)(pObjRpcStructureCopy, 5453 pVSI, 5454 buffer, 5455 bufferSize, 5456 offset); 5457 if (status != NVOS_STATUS_SUCCESS) { 5458 return status; 5459 } 5460 5461 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5462 status = serialize_deserialize(VGPU_STATIC_INFO)(pObjRpcStructureCopy, 5463 pVSI, 5464 buffer, 5465 bufferSize, 5466 offset); 5467 if (status != NVOS_STATUS_SUCCESS) { 5468 return status; 5469 } 5470 5471 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5472 status = serialize_deserialize(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS)(pObjRpcStructureCopy, 5473 &pVSI->mcEngineNotificationIntrVectors, 5474 buffer, 5475 bufferSize, 5476 offset); 5477 if (status != NVOS_STATUS_SUCCESS) { 5478 return status; 5479 } 5480 5481 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5482 status = serialize_deserialize(VGPU_STATIC_INFO2)(pObjRpcStructureCopy, 5483 pVSI, 5484 buffer, 5485 bufferSize, 5486 offset); 5487 if (status != NVOS_STATUS_SUCCESS) { 5488 return status; 5489 } 5490 5491 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5492 status = serialize_deserialize(NV2080_CTRL_CLK_GET_PUBLIC_DOMAIN_INFO_V2_PARAMS)(pObjRpcStructureCopy, 5493 &pVSI->clkPublicDomainInfo, 5494 buffer, 5495 bufferSize, 5496 offset); 5497 if (status != NVOS_STATUS_SUCCESS) { 5498 return status; 5499 } 5500 5501 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5502 status = serialize_deserialize(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS)(pObjRpcStructureCopy, 5503 &pVSI->grZcullInfo, 5504 buffer, 5505 bufferSize, 5506 offset); 5507 if (status != NVOS_STATUS_SUCCESS) { 5508 return status; 5509 } 5510 5511 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5512 status = serialize_deserialize(VGPU_STATIC_PROPERTIES)(pObjRpcStructureCopy, 5513 &pVSI->vgpuStaticProperties, 5514 buffer, 5515 bufferSize, 5516 offset); 5517 if (status != NVOS_STATUS_SUCCESS) { 5518 return status; 5519 } 5520 5521 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5522 status = serialize_deserialize(VGPU_FIFO_GET_DEVICE_INFO_TABLE)(pObjRpcStructureCopy, 5523 &pVSI->fifoDeviceInfoTable, 5524 buffer, 5525 bufferSize, 5526 offset); 5527 if (status != NVOS_STATUS_SUCCESS) { 5528 return status; 5529 } 5530 5531 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5532 status = serialize_deserialize(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES)(pObjRpcStructureCopy, 5533 &pVSI->fbDynamicBlacklistedPages, 5534 buffer, 5535 bufferSize, 5536 offset); 5537 if (status != NVOS_STATUS_SUCCESS) { 5538 return status; 5539 } 5540 5541 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5542 status = serialize_deserialize(VGPU_BSP_GET_CAPS)(pObjRpcStructureCopy, 5543 &pVSI->vgpuBspCaps, 5544 buffer, 5545 bufferSize, 5546 offset); 5547 if (status != NVOS_STATUS_SUCCESS) { 5548 return status; 5549 } 5550 5551 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5552 status = serialize_deserialize(NV2080_CTRL_PERF_VPSTATES_INFO)(pObjRpcStructureCopy, 5553 &pVSI->perfVpstatesInfo, 5554 buffer, 5555 bufferSize, 5556 offset); 5557 if (status != NVOS_STATUS_SUCCESS) { 5558 return status; 5559 } 5560 5561 if (getIpVersion() < 0x1A0D0000) { 5562 goto end; 5563 } 5564 5565 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5566 status = serialize_deserialize(VGPU_GET_LATENCY_BUFFER_SIZE)(pObjRpcStructureCopy, 5567 &pVSI->fifoLatencyBufferSize, 5568 buffer, 5569 bufferSize, 5570 offset); 5571 if (status != NVOS_STATUS_SUCCESS) { 5572 return status; 5573 } 5574 5575 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5576 status = serialize_deserialize(VGPU_CE_GET_CAPS_V2)(pObjRpcStructureCopy, 5577 &pVSI->ceCaps, 5578 buffer, 5579 bufferSize, 5580 offset); 5581 if (status != NVOS_STATUS_SUCCESS) { 5582 return status; 5583 } 5584 5585 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5586 status = serialize_deserialize(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS)(pObjRpcStructureCopy, 5587 &pVSI->nvlinkCaps, 5588 buffer, 5589 bufferSize, 5590 offset); 5591 if (status != NVOS_STATUS_SUCCESS) { 5592 return status; 5593 } 5594 5595 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5596 status = serialize_deserialize(VGPU_FB_GET_LTC_INFO_FOR_FBP)(pObjRpcStructureCopy, 5597 &pVSI->fbLtcInfoForFbp, 5598 buffer, 5599 bufferSize, 5600 offset); 5601 if (status != NVOS_STATUS_SUCCESS) { 5602 return status; 5603 } 5604 5605 if (getIpVersion() < 0x1A0F0000) { 5606 goto end; 5607 } 5608 5609 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5610 status = serialize_deserialize(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS)(pObjRpcStructureCopy, 5611 &pVSI->busGetInfoV2, 5612 buffer, 5613 bufferSize, 5614 offset); 5615 if (status != NVOS_STATUS_SUCCESS) { 5616 return status; 5617 } 5618 5619 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5620 status = serialize_deserialize(NV2080_CTRL_FLA_GET_RANGE_PARAMS)(pObjRpcStructureCopy, 5621 &pVSI->flaInfo, 5622 buffer, 5623 bufferSize, 5624 offset); 5625 if (status != NVOS_STATUS_SUCCESS) { 5626 return status; 5627 } 5628 5629 if (getIpVersion() < 0x1A190000) { 5630 goto end; 5631 } 5632 5633 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5634 status = serialize_deserialize(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS)(pObjRpcStructureCopy, 5635 &pVSI->vgpuConfig, 5636 buffer, 5637 bufferSize, 5638 offset); 5639 if (status != NVOS_STATUS_SUCCESS) { 5640 return status; 5641 } 5642 5643 if (getIpVersion() < 0x1A1F0000) { 5644 goto end; 5645 } 5646 5647 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5648 status = serialize_deserialize(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS)(pObjRpcStructureCopy, 5649 &pVSI->grSmIssueRateModifier, 5650 buffer, 5651 bufferSize, 5652 offset); 5653 if (status != NVOS_STATUS_SUCCESS) { 5654 return status; 5655 } 5656 5657 if (getIpVersion() < 0x1E090000) { 5658 goto end; 5659 } 5660 5661 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5662 status = serialize_deserialize(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS)(pObjRpcStructureCopy, 5663 &pVSI->mcStaticIntrTable, 5664 buffer, 5665 bufferSize, 5666 offset); 5667 if (status != NVOS_STATUS_SUCCESS) { 5668 return status; 5669 } 5670 5671 if (getIpVersion() < 0x1F080000) { 5672 goto end; 5673 } 5674 5675 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5676 status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS)(pObjRpcStructureCopy, 5677 &pVSI->pcieSupportedGpuAtomics, 5678 buffer, 5679 bufferSize, 5680 offset); 5681 if (status != NVOS_STATUS_SUCCESS) { 5682 return status; 5683 } 5684 5685 if (getIpVersion() < 0x210A0000) { 5686 goto end; 5687 } 5688 5689 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5690 status = serialize_deserialize(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS)(pObjRpcStructureCopy, 5691 &pVSI->ceGetAllCaps, 5692 buffer, 5693 bufferSize, 5694 offset); 5695 if (status != NVOS_STATUS_SUCCESS) { 5696 return status; 5697 } 5698 5699 if (getIpVersion() < 0x22010000) { 5700 goto end; 5701 } 5702 5703 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5704 status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS)(pObjRpcStructureCopy, 5705 &pVSI->c2cInfo, 5706 buffer, 5707 bufferSize, 5708 offset); 5709 if (status != NVOS_STATUS_SUCCESS) { 5710 return status; 5711 } 5712 5713 if (getIpVersion() < 0x23020000) { 5714 goto end; 5715 } 5716 5717 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5718 status = serialize_deserialize(NV2080_CTRL_PERF_PSTATES_INFO)(pObjRpcStructureCopy, 5719 &pVSI->perfpstatesInfo, 5720 buffer, 5721 bufferSize, 5722 offset); 5723 if (status != NVOS_STATUS_SUCCESS) { 5724 return status; 5725 } 5726 5727 if (getIpVersion() < 0x25000000) { 5728 goto end; 5729 } 5730 5731 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5732 status = serialize_deserialize(NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS)(pObjRpcStructureCopy, 5733 &pVSI->nvencCaps, 5734 buffer, 5735 bufferSize, 5736 offset); 5737 if (status != NVOS_STATUS_SUCCESS) { 5738 return status; 5739 } 5740 5741 if (getIpVersion() < 0x25010000) { 5742 goto end; 5743 } 5744 5745 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5746 status = serialize_deserialize(NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS)(pObjRpcStructureCopy, 5747 &pVSI->constructedFalconInfo, 5748 buffer, 5749 bufferSize, 5750 offset); 5751 if (status != NVOS_STATUS_SUCCESS) { 5752 return status; 5753 } 5754 5755 if (getIpVersion() < 0x25030000) { 5756 goto end; 5757 } 5758 5759 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5760 status = serialize_deserialize(VGPU_P2P_CAPABILITY_PARAMS)(pObjRpcStructureCopy, 5761 &pVSI->p2pCaps, 5762 buffer, 5763 bufferSize, 5764 offset); 5765 if (status != NVOS_STATUS_SUCCESS) { 5766 return status; 5767 } 5768 5769 if (getIpVersion() < 0x25050000) { 5770 goto end; 5771 } 5772 5773 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5774 status = serialize_deserialize(NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS)(pObjRpcStructureCopy, 5775 &pVSI->deviceInfoTable, 5776 buffer, 5777 bufferSize, 5778 offset); 5779 if (status != NVOS_STATUS_SUCCESS) { 5780 return status; 5781 } 5782 5783 if (getIpVersion() < 0x25060000) { 5784 goto end; 5785 } 5786 5787 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5788 status = serialize_deserialize(NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS)(pObjRpcStructureCopy, 5789 &pVSI->memsysStaticConfig, 5790 buffer, 5791 bufferSize, 5792 offset); 5793 if (status != NVOS_STATUS_SUCCESS) { 5794 return status; 5795 } 5796 5797 if (getIpVersion() < 0x250B0000) { 5798 goto end; 5799 } 5800 5801 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5802 status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS)(pObjRpcStructureCopy, 5803 &pVSI->busGetPcieReqAtomicsCaps, 5804 buffer, 5805 bufferSize, 5806 offset); 5807 if (status != NVOS_STATUS_SUCCESS) { 5808 return status; 5809 } 5810 5811 end: 5812 return status; 5813 } 5814 #endif // RESMAN_BUILD 5815 5816 static NV_STATUS static_data_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy, 5817 VGPU_STATIC_INFO *pVSI, 5818 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset, 5819 NvBool bAlignOffset) 5820 { 5821 NV_STATUS status = NVOS_STATUS_SUCCESS; 5822 5823 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5824 status = serialize_deserialize(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS)(pObjRpcStructureCopy, 5825 (NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *)&pVSI->execPartitionInfo, 5826 buffer, 5827 bufferSize, 5828 offset); 5829 if (status != NVOS_STATUS_SUCCESS) { 5830 return status; 5831 } 5832 5833 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5834 status = serialize_deserialize(VGPU_STATIC_DATA)(pObjRpcStructureCopy, 5835 pVSI, 5836 buffer, 5837 bufferSize, 5838 offset); 5839 if (status != NVOS_STATUS_SUCCESS) { 5840 return status; 5841 } 5842 5843 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5844 status = serialize_deserialize(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS)(pObjRpcStructureCopy, 5845 &pVSI->eccStatus, 5846 buffer, 5847 bufferSize, 5848 offset); 5849 if (status != NVOS_STATUS_SUCCESS) { 5850 return status; 5851 } 5852 5853 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5854 status = serialize_deserialize(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS)(pObjRpcStructureCopy, 5855 &pVSI->vgxSystemInfo, 5856 buffer, 5857 bufferSize, 5858 offset); 5859 if (status != NVOS_STATUS_SUCCESS) { 5860 return status; 5861 } 5862 5863 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5864 status = serialize_deserialize(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS)(pObjRpcStructureCopy, 5865 &pVSI->gidInfo, 5866 buffer, 5867 bufferSize, 5868 offset); 5869 if (status != NVOS_STATUS_SUCCESS) { 5870 return status; 5871 } 5872 5873 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5874 status = serialize_deserialize(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS)(pObjRpcStructureCopy, 5875 &pVSI->SKUInfo, 5876 buffer, 5877 bufferSize, 5878 offset); 5879 if (status != NVOS_STATUS_SUCCESS) { 5880 return status; 5881 } 5882 5883 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5884 status = serialize_deserialize(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS)(pObjRpcStructureCopy, 5885 &pVSI->fbRegionInfoParams, 5886 buffer, 5887 bufferSize, 5888 offset); 5889 if (status != NVOS_STATUS_SUCCESS) { 5890 return status; 5891 } 5892 5893 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5894 status = serialize_deserialize(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS)(pObjRpcStructureCopy, 5895 &pVSI->ciProfiles, 5896 buffer, 5897 bufferSize, 5898 offset); 5899 if (status != NVOS_STATUS_SUCCESS) { 5900 return status; 5901 } 5902 5903 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5904 status = serialize_deserialize(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS)(pObjRpcStructureCopy, 5905 &pVSI->zbcTableSizes[0], 5906 buffer, 5907 bufferSize, 5908 offset); 5909 if (status != NVOS_STATUS_SUCCESS) { 5910 return status; 5911 } 5912 5913 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5914 status = serialize_deserialize(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS)(pObjRpcStructureCopy, 5915 NULL, 5916 buffer, 5917 bufferSize, 5918 offset); 5919 if (status != NVOS_STATUS_SUCCESS) { 5920 return status; 5921 } 5922 5923 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5924 status = serialize_deserialize(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS)(pObjRpcStructureCopy, 5925 &pVSI->mcEngineNotificationIntrVectors, 5926 buffer, 5927 bufferSize, 5928 offset); 5929 if (status != NVOS_STATUS_SUCCESS) { 5930 return status; 5931 } 5932 5933 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5934 status = serialize_deserialize(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS)(pObjRpcStructureCopy, 5935 &pVSI->grZcullInfo, 5936 buffer, 5937 bufferSize, 5938 offset); 5939 if (status != NVOS_STATUS_SUCCESS) { 5940 return status; 5941 } 5942 5943 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5944 status = serialize_deserialize(VGPU_STATIC_PROPERTIES)(pObjRpcStructureCopy, 5945 &pVSI->vgpuStaticProperties, 5946 buffer, 5947 bufferSize, 5948 offset); 5949 if (status != NVOS_STATUS_SUCCESS) { 5950 return status; 5951 } 5952 5953 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5954 status = serialize_deserialize(VGPU_FIFO_GET_DEVICE_INFO_TABLE)(pObjRpcStructureCopy, 5955 &pVSI->fifoDeviceInfoTable, 5956 buffer, 5957 bufferSize, 5958 offset); 5959 if (status != NVOS_STATUS_SUCCESS) { 5960 return status; 5961 } 5962 5963 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5964 status = serialize_deserialize(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES)(pObjRpcStructureCopy, 5965 &pVSI->fbDynamicBlacklistedPages, 5966 buffer, 5967 bufferSize, 5968 offset); 5969 if (status != NVOS_STATUS_SUCCESS) { 5970 return status; 5971 } 5972 5973 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5974 status = serialize_deserialize(VGPU_BSP_GET_CAPS)(pObjRpcStructureCopy, 5975 &pVSI->vgpuBspCaps, 5976 buffer, 5977 bufferSize, 5978 offset); 5979 if (status != NVOS_STATUS_SUCCESS) { 5980 return status; 5981 } 5982 5983 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5984 status = serialize_deserialize(VGPU_GET_LATENCY_BUFFER_SIZE)(pObjRpcStructureCopy, 5985 &pVSI->fifoLatencyBufferSize, 5986 buffer, 5987 bufferSize, 5988 offset); 5989 if (status != NVOS_STATUS_SUCCESS) { 5990 return status; 5991 } 5992 5993 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 5994 status = serialize_deserialize(VGPU_CE_GET_CAPS_V2)(pObjRpcStructureCopy, 5995 &pVSI->ceCaps, 5996 buffer, 5997 bufferSize, 5998 offset); 5999 if (status != NVOS_STATUS_SUCCESS) { 6000 return status; 6001 } 6002 6003 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6004 status = serialize_deserialize(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS)(pObjRpcStructureCopy, 6005 &pVSI->nvlinkCaps, 6006 buffer, 6007 bufferSize, 6008 offset); 6009 if (status != NVOS_STATUS_SUCCESS) { 6010 return status; 6011 } 6012 6013 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6014 status = serialize_deserialize(VGPU_FB_GET_LTC_INFO_FOR_FBP)(pObjRpcStructureCopy, 6015 &pVSI->fbLtcInfoForFbp, 6016 buffer, 6017 bufferSize, 6018 offset); 6019 if (status != NVOS_STATUS_SUCCESS) { 6020 return status; 6021 } 6022 6023 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6024 status = serialize_deserialize(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS)(pObjRpcStructureCopy, 6025 &pVSI->busGetInfoV2, 6026 buffer, 6027 bufferSize, 6028 offset); 6029 if (status != NVOS_STATUS_SUCCESS) { 6030 return status; 6031 } 6032 6033 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6034 status = serialize_deserialize(NV2080_CTRL_FLA_GET_RANGE_PARAMS)(pObjRpcStructureCopy, 6035 &pVSI->flaInfo, 6036 buffer, 6037 bufferSize, 6038 offset); 6039 if (status != NVOS_STATUS_SUCCESS) { 6040 return status; 6041 } 6042 6043 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6044 status = serialize_deserialize(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS)(pObjRpcStructureCopy, 6045 &pVSI->vgpuConfig, 6046 buffer, 6047 bufferSize, 6048 offset); 6049 if (status != NVOS_STATUS_SUCCESS) { 6050 return status; 6051 } 6052 6053 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6054 status = serialize_deserialize(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS)(pObjRpcStructureCopy, 6055 &pVSI->grSmIssueRateModifier, 6056 buffer, 6057 bufferSize, 6058 offset); 6059 if (status != NVOS_STATUS_SUCCESS) { 6060 return status; 6061 } 6062 6063 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6064 status = serialize_deserialize(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS)(pObjRpcStructureCopy, 6065 &pVSI->mcStaticIntrTable, 6066 buffer, 6067 bufferSize, 6068 offset); 6069 if (status != NVOS_STATUS_SUCCESS) { 6070 return status; 6071 } 6072 6073 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6074 status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS)(pObjRpcStructureCopy, 6075 &pVSI->pcieSupportedGpuAtomics, 6076 buffer, 6077 bufferSize, 6078 offset); 6079 if (status != NVOS_STATUS_SUCCESS) { 6080 return status; 6081 } 6082 6083 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6084 status = serialize_deserialize(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS)(pObjRpcStructureCopy, 6085 &pVSI->ceGetAllCaps, 6086 buffer, 6087 bufferSize, 6088 offset); 6089 if (status != NVOS_STATUS_SUCCESS) { 6090 return status; 6091 } 6092 6093 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6094 status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS)(pObjRpcStructureCopy, 6095 &pVSI->c2cInfo, 6096 buffer, 6097 bufferSize, 6098 offset); 6099 if (status != NVOS_STATUS_SUCCESS) { 6100 return status; 6101 } 6102 6103 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6104 status = serialize_deserialize(NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS)(pObjRpcStructureCopy, 6105 &pVSI->nvencCaps, 6106 buffer, 6107 bufferSize, 6108 offset); 6109 if (status != NVOS_STATUS_SUCCESS) { 6110 return status; 6111 } 6112 6113 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6114 status = serialize_deserialize(NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS)(pObjRpcStructureCopy, 6115 &pVSI->constructedFalconInfo, 6116 buffer, 6117 bufferSize, 6118 offset); 6119 if (status != NVOS_STATUS_SUCCESS) { 6120 return status; 6121 } 6122 6123 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6124 status = serialize_deserialize(VGPU_P2P_CAPABILITY_PARAMS)(pObjRpcStructureCopy, 6125 &pVSI->p2pCaps, 6126 buffer, 6127 bufferSize, 6128 offset); 6129 if (status != NVOS_STATUS_SUCCESS) { 6130 return status; 6131 } 6132 6133 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6134 status = serialize_deserialize(NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS)(pObjRpcStructureCopy, 6135 &pVSI->deviceInfoTable, 6136 buffer, 6137 bufferSize, 6138 offset); 6139 if (status != NVOS_STATUS_SUCCESS) { 6140 return status; 6141 } 6142 6143 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6144 status = serialize_deserialize(NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS)(pObjRpcStructureCopy, 6145 &pVSI->memsysStaticConfig, 6146 buffer, 6147 bufferSize, 6148 offset); 6149 if (status != NVOS_STATUS_SUCCESS) { 6150 return status; 6151 } 6152 6153 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6154 status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS)(pObjRpcStructureCopy, 6155 &pVSI->busGetPcieReqAtomicsCaps, 6156 buffer, 6157 bufferSize, 6158 offset); 6159 if (status != NVOS_STATUS_SUCCESS) { 6160 return status; 6161 } 6162 6163 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6164 status = serialize_deserialize(GPU_PARTITION_INFO)(pObjRpcStructureCopy, 6165 &pVSI->gpuPartitionInfo, 6166 buffer, 6167 bufferSize, 6168 offset); 6169 if (status != NVOS_STATUS_SUCCESS) { 6170 return status; 6171 } 6172 6173 if (getIpVersion() < 0x25130000) { 6174 goto end; 6175 } 6176 6177 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6178 status = serialize_deserialize(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS)(pObjRpcStructureCopy, 6179 &pVSI->masterGetVfErrCntIntMsk, 6180 buffer, 6181 bufferSize, 6182 offset); 6183 if (status != NVOS_STATUS_SUCCESS) { 6184 return status; 6185 } 6186 end: 6187 return status; 6188 } 6189 6190 static NV_STATUS consolidated_gr_static_info_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy, 6191 VGPU_STATIC_INFO *pVSI, 6192 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset, 6193 NvBool bAlignOffset) 6194 { 6195 NV_STATUS status = NVOS_STATUS_SUCCESS; 6196 6197 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6198 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS)(pObjRpcStructureCopy, 6199 &pVSI->grInfoParams, 6200 buffer, 6201 bufferSize, 6202 offset); 6203 if (status != NVOS_STATUS_SUCCESS) { 6204 goto end; 6205 } 6206 6207 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6208 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS)(pObjRpcStructureCopy, 6209 &pVSI->globalSmOrder, 6210 buffer, 6211 bufferSize, 6212 offset); 6213 if (status != NVOS_STATUS_SUCCESS) { 6214 goto end; 6215 } 6216 6217 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6218 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS)(pObjRpcStructureCopy, 6219 &pVSI->ropInfoParams, 6220 buffer, 6221 bufferSize, 6222 offset); 6223 if (status != NVOS_STATUS_SUCCESS) { 6224 goto end; 6225 } 6226 6227 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6228 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS)(pObjRpcStructureCopy, 6229 &pVSI->ppcMaskParams, 6230 buffer, 6231 bufferSize, 6232 offset); 6233 if (status != NVOS_STATUS_SUCCESS) { 6234 goto end; 6235 } 6236 6237 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6238 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS)(pObjRpcStructureCopy, 6239 &pVSI->ctxBuffInfo, 6240 buffer, 6241 bufferSize, 6242 offset); 6243 if (status != NVOS_STATUS_SUCCESS) { 6244 goto end; 6245 } 6246 6247 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6248 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS)(pObjRpcStructureCopy, 6249 &pVSI->smIssueRateModifier, 6250 buffer, 6251 bufferSize, 6252 offset); 6253 if (status != NVOS_STATUS_SUCCESS) { 6254 goto end; 6255 } 6256 6257 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6258 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS)(pObjRpcStructureCopy, 6259 &pVSI->floorsweepMaskParams, 6260 buffer, 6261 bufferSize, 6262 offset); 6263 if (status != NVOS_STATUS_SUCCESS) { 6264 goto end; 6265 } 6266 6267 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6268 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS)(pObjRpcStructureCopy, 6269 &pVSI->zcullInfoParams, 6270 buffer, 6271 bufferSize, 6272 offset); 6273 if (status != NVOS_STATUS_SUCCESS) { 6274 goto end; 6275 } 6276 6277 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6278 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS)(pObjRpcStructureCopy, 6279 &pVSI->fecsRecordSize, 6280 buffer, 6281 bufferSize, 6282 offset); 6283 if (status != NVOS_STATUS_SUCCESS) { 6284 goto end; 6285 } 6286 6287 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6288 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS)(pObjRpcStructureCopy, 6289 &pVSI->fecsTraceDefines, 6290 buffer, 6291 bufferSize, 6292 offset); 6293 if (status != NVOS_STATUS_SUCCESS) { 6294 goto end; 6295 } 6296 6297 NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) 6298 status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS)(pObjRpcStructureCopy, 6299 &pVSI->pdbTableParams, 6300 buffer, 6301 bufferSize, 6302 offset); 6303 if (status != NVOS_STATUS_SUCCESS) { 6304 goto end; 6305 } 6306 6307 end: 6308 return status; 6309 } 6310 #endif 6311 #endif 6312 6313 #if defined(CROSS_BRANCH_CONVERT) 6314 6315 typedef struct { 6316 NvU32 outType; 6317 } GUEST_HOST_MAPPING; 6318 6319 /* 6320 * guest_to_host_enginetype_v1A_00 is used to convert engine type from r460 to 6321 * r470. refer sdk/nvidia/inc/class/cl2080.h for definition. 6322 */ 6323 const GUEST_HOST_MAPPING guest_to_host_enginetype_v1A_00[] = 6324 { 6325 // Out Engine Type In Engine Type 6326 { NV2080_ENGINE_TYPE_NULL }, // 0x0 6327 { NV2080_ENGINE_TYPE_GR0 }, // 0x1 6328 { NV2080_ENGINE_TYPE_GR1 }, // 0x2 6329 { NV2080_ENGINE_TYPE_GR2 }, // 0x3 6330 { NV2080_ENGINE_TYPE_GR3 }, // 0x4 6331 { NV2080_ENGINE_TYPE_GR4 }, // 0x5 6332 { NV2080_ENGINE_TYPE_GR5 }, // 0x6 6333 { NV2080_ENGINE_TYPE_GR6 }, // 0x7 6334 { NV2080_ENGINE_TYPE_GR7 }, // 0x8 6335 { NV2080_ENGINE_TYPE_COPY0 }, // 0x9 6336 { NV2080_ENGINE_TYPE_COPY1 }, // 0xa 6337 { NV2080_ENGINE_TYPE_COPY2 }, // 0xb 6338 { NV2080_ENGINE_TYPE_COPY3 }, // 0xc 6339 { NV2080_ENGINE_TYPE_COPY4 }, // 0xd 6340 { NV2080_ENGINE_TYPE_COPY5 }, // 0xe 6341 { NV2080_ENGINE_TYPE_COPY6 }, // 0xf 6342 { NV2080_ENGINE_TYPE_COPY7 }, // 0x10 6343 { NV2080_ENGINE_TYPE_COPY8 }, // 0x11 6344 { NV2080_ENGINE_TYPE_COPY9 }, // 0x12 6345 { NV2080_ENGINE_TYPE_NVDEC0 }, // 0x13 6346 { NV2080_ENGINE_TYPE_NVDEC1 }, // 0x14 6347 { NV2080_ENGINE_TYPE_NVDEC2 }, // 0x15 6348 { NV2080_ENGINE_TYPE_NVDEC3 }, // 0x16 6349 { NV2080_ENGINE_TYPE_NVDEC4 }, // 0x17 6350 { NV2080_ENGINE_TYPE_NVENC0 }, // 0x18 6351 { NV2080_ENGINE_TYPE_NVENC1 }, // 0x19 6352 { NV2080_ENGINE_TYPE_NVENC2 }, // 0x1a 6353 { NV2080_ENGINE_TYPE_VP }, // 0x1b 6354 { NV2080_ENGINE_TYPE_ME }, // 0x1c 6355 { NV2080_ENGINE_TYPE_PPP }, // 0x1d 6356 { NV2080_ENGINE_TYPE_MPEG }, // 0x1e 6357 { NV2080_ENGINE_TYPE_SW }, // 0x1f 6358 { NV2080_ENGINE_TYPE_CIPHER }, // 0x20 6359 { NV2080_ENGINE_TYPE_VIC }, // 0x21 6360 { NV2080_ENGINE_TYPE_MP }, // 0x22 6361 { NV2080_ENGINE_TYPE_SEC2 }, // 0x23 6362 { NV2080_ENGINE_TYPE_HOST }, // 0x24 6363 { NV2080_ENGINE_TYPE_DPU }, // 0x25 6364 { NV2080_ENGINE_TYPE_PMU }, // 0x26 6365 { NV2080_ENGINE_TYPE_FBFLCN }, // 0x27 6366 { NV2080_ENGINE_TYPE_NVJPG }, // 0x28 6367 { NV2080_ENGINE_TYPE_OFA0 }, // 0x29 6368 { NV2080_ENGINE_TYPE_LAST_v1A_00 }, // 0x2a 6369 }; 6370 6371 // Convert a guest engineType to a host engineType. 6372 NvU32 deserialize_engineType(NvU32 inEngineType) 6373 { 6374 6375 if (vgx_internal_version_curr.major_number >= 0x1B) { 6376 return inEngineType; 6377 } 6378 if (inEngineType >= 0x2a) { 6379 return NV2080_ENGINE_TYPE_NULL; 6380 } 6381 return guest_to_host_enginetype_v1A_00[inEngineType].outType; 6382 } 6383 6384 /* 6385 * host_to_guest_enginetype_v1A_00 is used to convert engine type from r470 to 6386 * r460. refer sdk/nvidia/inc/class/cl2080.h for definition. 6387 * unsupported/invalid engines are returned with NV2080_ENGINE_TYPE_NULL (this 6388 * is considered invalid in RM) 6389 */ 6390 const GUEST_HOST_MAPPING host_to_guest_enginetype_v1A_00[] = 6391 { 6392 // Out Engine Type In Engine Type 6393 { 0x0 }, // NV2080_ENGINE_TYPE_NULL 6394 { 0x1 }, // NV2080_ENGINE_TYPE_GR0 6395 { 0x2 }, // NV2080_ENGINE_TYPE_GR1 6396 { 0x3 }, // NV2080_ENGINE_TYPE_GR2 6397 { 0x4 }, // NV2080_ENGINE_TYPE_GR3 6398 { 0x5 }, // NV2080_ENGINE_TYPE_GR4 6399 { 0x6 }, // NV2080_ENGINE_TYPE_GR5 6400 { 0x7 }, // NV2080_ENGINE_TYPE_GR6 6401 { 0x8 }, // NV2080_ENGINE_TYPE_GR7 6402 { 0x9 }, // NV2080_ENGINE_TYPE_COPY0 6403 { 0xa }, // NV2080_ENGINE_TYPE_COPY1 6404 { 0xb }, // NV2080_ENGINE_TYPE_COPY2 6405 { 0xc }, // NV2080_ENGINE_TYPE_COPY3 6406 { 0xd }, // NV2080_ENGINE_TYPE_COPY4 6407 { 0xe }, // NV2080_ENGINE_TYPE_COPY5 6408 { 0xf }, // NV2080_ENGINE_TYPE_COPY6 6409 { 0x10 }, // NV2080_ENGINE_TYPE_COPY7 6410 { 0x11 }, // NV2080_ENGINE_TYPE_COPY8 6411 { 0x12 }, // NV2080_ENGINE_TYPE_COPY9 6412 { 0x13 }, // NV2080_ENGINE_TYPE_NVDEC0 6413 { 0x14 }, // NV2080_ENGINE_TYPE_NVDEC1 6414 { 0x15 }, // NV2080_ENGINE_TYPE_NVDEC2 6415 { 0x16 }, // NV2080_ENGINE_TYPE_NVDEC3 6416 { 0x17 }, // NV2080_ENGINE_TYPE_NVDEC4 6417 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVDEC5 6418 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVDEC6 6419 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVDEC7 6420 { 0x18 }, // NV2080_ENGINE_TYPE_NVENC0 6421 { 0x19 }, // NV2080_ENGINE_TYPE_NVENC1 6422 { 0x1a }, // NV2080_ENGINE_TYPE_NVENC2 6423 { 0x1b }, // NV2080_ENGINE_TYPE_VP 6424 { 0x1c }, // NV2080_ENGINE_TYPE_ME 6425 { 0x1d }, // NV2080_ENGINE_TYPE_PPP 6426 { 0x1e }, // NV2080_ENGINE_TYPE_MPEG 6427 { 0x1f }, // NV2080_ENGINE_TYPE_SW 6428 { 0x20 }, // NV2080_ENGINE_TYPE_CIPHER 6429 { 0x21 }, // NV2080_ENGINE_TYPE_VIC 6430 { 0x22 }, // NV2080_ENGINE_TYPE_MP 6431 { 0x23 }, // NV2080_ENGINE_TYPE_SEC2 6432 { 0x24 }, // NV2080_ENGINE_TYPE_HOST 6433 { 0x25 }, // NV2080_ENGINE_TYPE_DPU 6434 { 0x26 }, // NV2080_ENGINE_TYPE_PMU 6435 { 0x27 }, // NV2080_ENGINE_TYPE_FBFLCN 6436 { 0x28 }, // NV2080_ENGINE_TYPE_NVJPEG0 6437 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG1 6438 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG2 6439 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG3 6440 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG4 6441 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG5 6442 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG6 6443 { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG7 6444 { 0x29 }, // NV2080_ENGINE_TYPE_OFA0 6445 { 0x2a }, // NV2080_ENGINE_TYPE_LAST 6446 }; 6447 6448 // Convert a host engineType to a guest engineType. 6449 NvU32 serialize_engineType(NvU32 inEngineType) 6450 { 6451 6452 if (vgx_internal_version_curr.major_number >= 0x1B) { 6453 return inEngineType; 6454 } 6455 if (inEngineType >= 0x34) { 6456 return NV2080_ENGINE_TYPE_NULL; 6457 } 6458 return host_to_guest_enginetype_v1A_00[inEngineType].outType; 6459 } 6460 6461 // Convert a host engineList to a guest engineList. 6462 NvU64 searilize_engineCap(NvU64 inEngineCap) 6463 { 6464 6465 if (vgx_internal_version_curr.major_number >= 0x1B) { 6466 return inEngineCap; 6467 } 6468 NvU64 outEngineCap= 0, i = 0; 6469 FOR_EACH_INDEX_IN_MASK(64, i, inEngineCap) 6470 { 6471 outEngineCap = outEngineCap | NVBIT64(serialize_engineType(i)); 6472 } FOR_EACH_INDEX_IN_MASK_END; 6473 return outEngineCap; 6474 } 6475 6476 // Convert a host notifier index to a guest notifier index. 6477 NvU32 serialize_notifier(NvU32 inNotifier) 6478 { 6479 if (vgx_internal_version_curr.major_number > 0x21) { 6480 return inNotifier; 6481 } 6482 6483 if (vgx_internal_version_curr.major_number == 0x21 && 6484 (REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R525)) { 6485 return NV2080_NOTIFIERS_MAXCOUNT_R525; 6486 } 6487 6488 if (vgx_internal_version_curr.major_number == 0x1C && 6489 (REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R470)) { 6490 return NV2080_NOTIFIERS_MAXCOUNT_R470; 6491 } 6492 6493 return inNotifier; 6494 } 6495 6496 // Convert a guest notifier index to a host notifier index. 6497 NvU32 deserialize_notifier(NvU32 inNotifier) 6498 { 6499 if (vgx_internal_version_curr.major_number > 0x21) { 6500 return inNotifier; 6501 } 6502 6503 if (vgx_internal_version_curr.major_number == 0x21 && 6504 (REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R525)) { 6505 return NV2080_NOTIFIERS_MAXCOUNT; 6506 } 6507 6508 if (vgx_internal_version_curr.major_number == 0x1C && 6509 (REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R470)) { 6510 return NV2080_NOTIFIERS_MAXCOUNT; 6511 } 6512 6513 return inNotifier; 6514 } 6515 6516 /* 6517 * rcmask table is used to convert ROBUST_CHANNEL_* macros from r470 to r460. 6518 * eg, ROBUST_CHANNEL_COPY0_ENGINE is defined as 22 in r470 and 19 in r460. 6519 */ 6520 const GUEST_HOST_MAPPING host_to_guest_rcmask_v1A_00[] = 6521 { 6522 // Out rcmask // In rcmask 6523 { 0 }, // 0 6524 { 1 }, // 1 6525 { 2 }, // 2 6526 { 3 }, // 3 6527 { 4 }, // 4 6528 { 5 }, // 5 6529 { 6 }, // 6 6530 { 7 }, // 7 6531 { 8 }, // 8 6532 { 9 }, // 9 6533 { 10 }, // 10 6534 { 11 }, // 11 6535 { 12 }, // 12 6536 { 13 }, // 13 6537 { 14 }, // 14 6538 { 15 }, // 15 6539 { 16 }, // 16 6540 { 17 }, // 17 6541 { 18 }, // 18 6542 { 0 }, // 19 6543 { 0 }, // 20 6544 { 0 }, // 21 6545 { 19 }, // 22 6546 { 20 }, // 23 6547 { 21 }, // 24 6548 { 22 }, // 25 6549 { 23 }, // 26 6550 { 24 }, // 27 6551 { 25 }, // 28 6552 { 26 }, // 29 6553 { 27 }, // 30 6554 { 28 }, // 31 6555 { 29 }, // 32 6556 { 0 }, // 33 6557 { 0 }, // 34 6558 { 0 }, // 35 6559 { 0 }, // 36 6560 { 0 }, // 37 6561 { 0 }, // 38 6562 { 0 }, // 39 6563 { 30 }, // 40 6564 { 31 }, // 41 6565 { 32 }, // 42 6566 { 33 }, // 43 6567 { 34 }, // 44 6568 { 35 }, // 45 6569 { 36 }, // 46 6570 { 37 }, // 47 6571 { 38 }, // 48 6572 { 39 }, // 49 6573 6574 }; 6575 6576 // Convert a host rcmask to a guest rcmask. 6577 NvU32 serialize_rcmask(NvU32 inType) 6578 { 6579 6580 if (vgx_internal_version_curr.major_number >= 0x1B) { 6581 return inType; 6582 } 6583 if (inType > 49) { 6584 return 0; 6585 } 6586 return host_to_guest_rcmask_v1A_00[inType].outType; 6587 } 6588 6589 typedef struct { 6590 NvU32 inType; 6591 NvU32 outType; 6592 } GUEST_HOST_MAPPING_TUPLE; 6593 6594 /* 6595 * mcbit table is used to convert MC_ENGINE_IDX_* macros from r470 to r460. 6596 * Please refer engine_idx.h for definition. 6597 * eg, MC_ENGINE_IDX_BSP is defined as 56 in r470 and 49 in r460. 6598 */ 6599 const GUEST_HOST_MAPPING_TUPLE host_to_guest_mcbit_v1A_00[] = 6600 { 6601 // Host mcbit Guest mcbit 6602 { 0, 0 }, 6603 { 1, 1 }, 6604 { 2, 2 }, 6605 { 3, 3 }, 6606 { 4, 4 }, 6607 { 5, 5 }, 6608 { 6, 6 }, 6609 { 7, 7 }, 6610 { 8, 8 }, 6611 { 9, 9 }, 6612 { 10, 10 }, 6613 { 11, 11 }, 6614 { 12, 12 }, 6615 { 13, 13 }, 6616 { 14, 14 }, 6617 { 15, 15 }, 6618 { 16, 16 }, 6619 { 17, 17 }, 6620 { 18, 18 }, 6621 { 19, 19 }, 6622 { 20, 20 }, 6623 { 21, 21 }, 6624 { 22, 22 }, 6625 { 23, 23 }, 6626 { 24, 24 }, 6627 { 25, 25 }, 6628 { 26, 26 }, 6629 { 27, 27 }, 6630 { 28, 28 }, 6631 { 29, 30 }, 6632 { 30, 31 }, 6633 { 31, 32 }, 6634 { 32, 0 }, 6635 { 33, 0 }, 6636 { 34, 34 }, 6637 { 35, 35 }, 6638 { 36, 36 }, 6639 { 37, 37 }, 6640 { 38, 38 }, 6641 { 39, 0 }, 6642 { 40, 40 }, 6643 { 41, 41 }, 6644 { 42, 42 }, 6645 { 43, 0 }, 6646 { 44, 0 }, 6647 { 45, 0 }, 6648 { 46, 0 }, 6649 { 47, 0 }, 6650 { 48, 0 }, 6651 { 49, 0 }, 6652 { 50, 43 }, 6653 { 51, 44 }, 6654 { 52, 45 }, 6655 { 53, 46 }, 6656 { 54, 47 }, 6657 { 55, 48 }, 6658 { 56, 49 }, 6659 { 57, 50 }, 6660 { 58, 51 }, 6661 { 59, 52 }, 6662 { 60, 53 }, 6663 { 61, 0 }, 6664 { 62, 0 }, 6665 { 63, 0 }, 6666 { 64, 54 }, 6667 { 65, 55 }, 6668 { 66, 56 }, 6669 { 67, 57 }, 6670 { 68, 58 }, 6671 { 69, 59 }, 6672 { 70, 60 }, 6673 { 71, 61 }, 6674 { 72, 62 }, 6675 { 73, 63 }, 6676 { 74, 64 }, 6677 { 75, 65 }, 6678 { 76, 66 }, 6679 { 77, 67 }, 6680 { 78, 68 }, 6681 { 79, 69 }, 6682 { 80, 70 }, 6683 { 81, 71 }, 6684 { 82, 72 }, 6685 { 146, 104 }, 6686 { 147, 105 }, 6687 { 148, 106 }, 6688 { 149, 107 }, 6689 { 150, 108 }, 6690 { 151, 109 }, 6691 { 152, 110 }, 6692 { 153, 111 }, 6693 { 154, 112 }, 6694 { 155, 113 }, 6695 }; 6696 6697 NvU32 get_index(NvU32 inType) { 6698 NvU32 index = 0, l = 0; 6699 NvU32 r = (sizeof(host_to_guest_mcbit_v1A_00) / (sizeof(NvU32) * 2)) - 1; 6700 6701 do { 6702 index = (l + r) / 2; 6703 if (inType == host_to_guest_mcbit_v1A_00[index].inType) { 6704 break; 6705 } 6706 if (r <= l) { 6707 index = 0; 6708 break; 6709 } 6710 if (inType > host_to_guest_mcbit_v1A_00[index].inType) { 6711 l = index + 1; 6712 continue; 6713 } 6714 if (inType < host_to_guest_mcbit_v1A_00[index].inType) { 6715 r = index - 1; 6716 continue; 6717 } 6718 } while(1); 6719 6720 return index; 6721 } 6722 6723 // Convert a host rcmask to a guest rcmask. 6724 NvU32 serialize_mcbit(NvU32 inType) 6725 { 6726 6727 if (vgx_internal_version_curr.major_number >= 0x1B) { 6728 return inType; 6729 } 6730 if (inType > 155) { 6731 return 0; 6732 } 6733 return host_to_guest_mcbit_v1A_00[get_index(inType)].outType; 6734 } 6735 6736 #endif 6737 #undef COPY_INPUT_PARAMETERS 6738 #undef COPY_OUTPUT_PARAMETERS 6739