1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __vgpu_rpc_nv_headers_h__ 25 #define __vgpu_rpc_nv_headers_h__ 26 27 #include "ctrl/ctrl0080/ctrl0080perf.h" 28 #include "ctrl/ctrl2080/ctrl2080perf.h" 29 #include "ctrl/ctrl2080/ctrl2080internal.h" 30 #include "nvstatus.h" 31 32 #define MAX_GPC_COUNT 32 33 34 /* 35 * Maximum number of RegOps that can be accommodated within one RPC call 36 * due to RPC message buffer size being limited to 4k 37 */ 38 #define VGPU_MAX_REGOPS_PER_RPC 100 39 40 #define VGPU_RESERVED_HANDLE_BASE 0xCAF3F000 41 #define VGPU_RESERVED_HANDLE_RANGE 0x1000 42 43 #define VGPU_CALC_PARAM_OFFSET(prev_offset, prev_params) (prev_offset + NV_ALIGN_UP(sizeof(prev_params), sizeof(NvU32))) 44 45 /* 46 * Message header (in buffer addressed by ring entry) 47 * 48 * If message is invalid (bad length or signature), signature and length 49 * are forced to be valid (if in range of descriptor) and result is set to 50 * NV_VGPU_RESULT_INVALID_MESSAGE_FORMAT. Otherwise, signature, length, and 51 * function are always unchanged and result is always set. 52 * 53 * The function message header, if defined, immediately follows the main message 54 * header. 55 */ 56 #define NV_VGPU_MSG_HEADER_VERSION_MAJOR 31:24 /* R---D */ 57 #define NV_VGPU_MSG_HEADER_VERSION_MINOR 23:16 /* R---D */ 58 #define NV_VGPU_MSG_HEADER_VERSION_MAJOR_TOT 0x00000003 /* R---D */ 59 #define NV_VGPU_MSG_HEADER_VERSION_MINOR_TOT 0x00000000 /* R---D */ 60 /* signature must equal valid value */ 61 #define NV_VGPU_MSG_SIGNATURE_VALID 0x43505256 /* RW--V */ 62 63 #include "rpc_global_enums.h" 64 65 /* result code */ 66 /* codes below 0xFF000000 must match exactly the NV_STATUS codes in nvos.h */ 67 #define NV_VGPU_MSG_RESULT__RM NV_ERR_GENERIC:0x00000000 /* RW--D */ 68 #define NV_VGPU_MSG_RESULT_SUCCESS NV_OK 69 #define NV_VGPU_MSG_RESULT_CARD_NOT_PRESENT NV_ERR_CARD_NOT_PRESENT 70 #define NV_VGPU_MSG_RESULT_DUAL_LINK_INUSE NV_ERR_DUAL_LINK_INUSE 71 #define NV_VGPU_MSG_RESULT_GENERIC NV_ERR_GENERIC 72 #define NV_VGPU_MSG_RESULT_GPU_NOT_FULL_POWER NV_ERR_GPU_NOT_FULL_POWER 73 #define NV_VGPU_MSG_RESULT_IN_USE NV_ERR_IN_USE 74 #define NV_VGPU_MSG_RESULT_INSUFFICIENT_RESOURCES NV_ERR_INSUFFICIENT_RESOURCES 75 #define NV_VGPU_MSG_RESULT_INVALID_ACCESS_TYPE NV_ERR_INVALID_ACCESS_TYPE 76 #define NV_VGPU_MSG_RESULT_INVALID_ARGUMENT NV_ERR_INVALID_ARGUMENT 77 #define NV_VGPU_MSG_RESULT_INVALID_BASE NV_ERR_INVALID_BASE 78 #define NV_VGPU_MSG_RESULT_INVALID_CHANNEL NV_ERR_INVALID_CHANNEL 79 #define NV_VGPU_MSG_RESULT_INVALID_CLASS NV_ERR_INVALID_CLASS 80 #define NV_VGPU_MSG_RESULT_INVALID_CLIENT NV_ERR_INVALID_CLIENT 81 #define NV_VGPU_MSG_RESULT_INVALID_COMMAND NV_ERR_INVALID_COMMAND 82 #define NV_VGPU_MSG_RESULT_INVALID_DATA NV_ERR_INVALID_DATA 83 #define NV_VGPU_MSG_RESULT_INVALID_DEVICE NV_ERR_INVALID_DEVICE 84 #define NV_VGPU_MSG_RESULT_INVALID_DMA_SPECIFIER NV_ERR_INVALID_DMA_SPECIFIER 85 #define NV_VGPU_MSG_RESULT_INVALID_EVENT NV_ERR_INVALID_EVENT 86 #define NV_VGPU_MSG_RESULT_INVALID_FLAGS NV_ERR_INVALID_FLAGS 87 #define NV_VGPU_MSG_RESULT_INVALID_FUNCTION NV_ERR_INVALID_FUNCTION 88 #define NV_VGPU_MSG_RESULT_INVALID_HEAP NV_ERR_INVALID_HEAP 89 #define NV_VGPU_MSG_RESULT_INVALID_INDEX NV_ERR_INVALID_INDEX 90 #define NV_VGPU_MSG_RESULT_INVALID_LIMIT NV_ERR_INVALID_LIMIT 91 #define NV_VGPU_MSG_RESULT_INVALID_METHOD NV_ERR_INVALID_METHOD 92 #define NV_VGPU_MSG_RESULT_INVALID_OBJECT_BUFFER NV_ERR_INVALID_OBJECT_BUFFER 93 #define NV_VGPU_MSG_RESULT_INVALID_OBJECT_ERROR NV_ERR_INVALID_OBJECT 94 #define NV_VGPU_MSG_RESULT_INVALID_OBJECT_HANDLE NV_ERR_INVALID_OBJECT_HANDLE 95 #define NV_VGPU_MSG_RESULT_INVALID_OBJECT_NEW NV_ERR_INVALID_OBJECT_NEW 96 #define NV_VGPU_MSG_RESULT_INVALID_OBJECT_OLD NV_ERR_INVALID_OBJECT_OLD 97 #define NV_VGPU_MSG_RESULT_INVALID_OBJECT_PARENT NV_ERR_INVALID_OBJECT_PARENT 98 #define NV_VGPU_MSG_RESULT_INVALID_OFFSET NV_ERR_INVALID_OFFSET 99 #define NV_VGPU_MSG_RESULT_INVALID_OWNER NV_ERR_INVALID_OWNER 100 #define NV_VGPU_MSG_RESULT_INVALID_PARAM_STRUCT NV_ERR_INVALID_PARAM_STRUCT 101 #define NV_VGPU_MSG_RESULT_INVALID_PARAMETER NV_ERR_INVALID_PARAMETER 102 #define NV_VGPU_MSG_RESULT_INVALID_POINTER NV_ERR_INVALID_POINTER 103 #define NV_VGPU_MSG_RESULT_INVALID_REGISTRY_KEY NV_ERR_INVALID_REGISTRY_KEY 104 #define NV_VGPU_MSG_RESULT_INVALID_STATE NV_ERR_INVALID_STATE 105 #define NV_VGPU_MSG_RESULT_INVALID_STRING_LENGTH NV_ERR_INVALID_STRING_LENGTH 106 #define NV_VGPU_MSG_RESULT_INVALID_XLATE NV_ERR_INVALID_XLATE 107 #define NV_VGPU_MSG_RESULT_IRQ_NOT_FIRING NV_ERR_IRQ_NOT_FIRING 108 #define NV_VGPU_MSG_RESULT_MULTIPLE_MEMORY_TYPES NV_ERR_MULTIPLE_MEMORY_TYPES 109 #define NV_VGPU_MSG_RESULT_NOT_SUPPORTED NV_ERR_NOT_SUPPORTED 110 #define NV_VGPU_MSG_RESULT_OPERATING_SYSTEM NV_ERR_OPERATING_SYSTEM 111 #define NV_VGPU_MSG_RESULT_PROTECTION_FAULT NV_ERR_PROTECTION_FAULT 112 #define NV_VGPU_MSG_RESULT_TIMEOUT NV_ERR_TIMEOUT 113 #define NV_VGPU_MSG_RESULT_TOO_MANY_PRIMARIES NV_ERR_TOO_MANY_PRIMARIES 114 #define NV_VGPU_MSG_RESULT_IRQ_EDGE_TRIGGERED NV_ERR_IRQ_EDGE_TRIGGERED 115 #define NV_VGPU_MSG_RESULT_GUEST_HOST_DRIVER_MISMATCH NV_ERR_LIB_RM_VERSION_MISMATCH 116 117 /* 118 * codes above 0xFF000000 and below 0xFF100000 must match one-for-one 119 * the vmiop_error_t codes in vmioplugin.h, with 0xFF000000 added. 120 */ 121 #define NV_VGPU_MSG_RESULT__VMIOP 0xFF000007:0xFF000000 /* RW--D */ 122 #define NV_VGPU_MSG_RESULT_VMIOP_INVAL 0xFF000001 /* RW--V */ 123 #define NV_VGPU_MSG_RESULT_VMIOP_RESOURCE 0xFF000002 /* RW--V */ 124 #define NV_VGPU_MSG_RESULT_VMIOP_RANGE 0xFF000003 /* RW--V */ 125 #define NV_VGPU_MSG_RESULT_VMIOP_READ_ONLY 0xFF000004 /* RW--V */ 126 #define NV_VGPU_MSG_RESULT_VMIOP_NOT_FOUND 0xFF000005 /* RW--V */ 127 #define NV_VGPU_MSG_RESULT_VMIOP_NO_ADDRESS_SPACE 0xFF000006 /* RW--V */ 128 #define NV_VGPU_MSG_RESULT_VMIOP_TIMEOUT 0xFF000007 /* RW--V */ 129 /* RPC-specific error codes */ 130 #define NV_VGPU_MSG_RESULT__RPC 0xFF100007:0xFF100000 /* RW--D */ 131 #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION 0xFF100001 /* RW--V */ 132 #define NV_VGPU_MSG_RESULT_RPC_INVALID_MESSAGE_FORMAT 0xFF100002 /* RW--V */ 133 #define NV_VGPU_MSG_RESULT_RPC_HANDLE_NOT_FOUND 0xFF100003 /* RW--V */ 134 #define NV_VGPU_MSG_RESULT_RPC_HANDLE_EXISTS 0xFF100004 /* RW--V */ 135 #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_RM_ERROR 0xFF100005 /* RW--V */ 136 #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_VMIOP_ERROR 0xFF100006 /* RW--V */ 137 #define NV_VGPU_MSG_RESULT_RPC_RESERVED_HANDLE 0xFF100007 /* RW--V */ 138 /* RPC-specific code in result for incomplete request */ 139 #define NV_VGPU_MSG_RESULT_RPC_PENDING 0xFFFFFFFF /* RW--V */ 140 /* shared union field */ 141 #define NV_VGPU_MSG_UNION_INIT 0x00000000 /* RW--V */ 142 143 /* 144 * common PTEDESC message defines (used w/ ALLOC_MEMORY, ALLOC_VIDMEM, FILL_PTE_MEM) 145 */ 146 #define NV_VGPU_PTEDESC_INIT 0x00000000 /* RWI-V */ 147 #define NV_VGPU_PTEDESC__PROD 0x00000000 /* RW--V */ 148 #define NV_VGPU_PTEDESC_IDR_NONE 0x00000000 /* RW--V */ 149 #define NV_VGPU_PTEDESC_IDR_SINGLE 0x00000001 /* RW--V */ 150 #define NV_VGPU_PTEDESC_IDR_DOUBLE 0x00000002 /* RW--V */ 151 #define NV_VGPU_PTEDESC_IDR_TRIPLE 0x00000003 /* RW--V */ 152 153 #define NV_VGPU_PTE_PAGE_SIZE 0x1000 /* R---V */ 154 #define NV_VGPU_PTE_SIZE 4 /* R---V */ 155 #define NV_VGPU_PTE_INDEX_SHIFT 10 /* R---V */ 156 #define NV_VGPU_PTE_INDEX_MASK 0x3FF /* R---V */ 157 158 #define NV_VGPU_PTE_64_PAGE_SIZE 0x1000 /* R---V */ 159 #define NV_VGPU_PTE_64_SIZE 8 /* R---V */ 160 #define NV_VGPU_PTE_64_INDEX_SHIFT 9 /* R---V */ 161 #define NV_VGPU_PTE_64_INDEX_MASK 0x1FF /* R---V */ 162 163 /* 164 * LOG message 165 */ 166 #define NV_VGPU_LOG_LEVEL_FATAL 0x00000000 /* RW--V */ 167 #define NV_VGPU_LOG_LEVEL_ERROR 0x00000001 /* RW--V */ 168 #define NV_VGPU_LOG_LEVEL_NOTICE 0x00000002 /* RW--V */ 169 #define NV_VGPU_LOG_LEVEL_STATUS 0x00000003 /* RW--V */ 170 #define NV_VGPU_LOG_LEVEL_DEBUG 0x00000004 /* RW--V */ 171 172 /* 173 * Enums specifying the BAR number that we are going to update its PDE 174 */ 175 typedef enum 176 { 177 NV_RPC_UPDATE_PDE_BAR_1, 178 NV_RPC_UPDATE_PDE_BAR_2, 179 NV_RPC_UPDATE_PDE_BAR_INVALID, 180 } NV_RPC_UPDATE_PDE_BAR_TYPE; 181 182 /* 183 * UVM method stream guest pages operation 184 */ 185 typedef enum 186 { 187 NV_RPC_GUEST_PAGE_MAP, 188 NV_RPC_GUEST_PAGE_UNMAP, 189 } NV_RPC_GUEST_PAGE_OPERATION; 190 191 /* 192 * UVM method stream guest page size 193 */ 194 typedef enum 195 { 196 NV_RPC_GUEST_PAGE_SIZE_4K, 197 NV_RPC_GUEST_PAGE_SIZE_UNSUPPORTED, 198 } NV_RPC_GUEST_PAGE_SIZE; 199 200 /* 201 * UVM paging channel VASPACE operation 202 */ 203 typedef enum 204 { 205 UVM_PAGING_CHANNEL_VASPACE_ALLOC, 206 UVM_PAGING_CHANNEL_VASPACE_FREE, 207 } UVM_PAGING_CHANNEL_VASPACE_OPERATION; 208 209 typedef struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS 210 { 211 NvU32 headIndex; 212 NvU32 maxHResolution; 213 NvU32 maxVResolution; 214 } VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS; 215 216 typedef struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS 217 { 218 NvU32 numHeads; 219 NvU32 maxNumHeads; 220 } VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS; 221 222 223 /* 224 * Maximum guest pages that can be mapped for UVM method stream 225 */ 226 #define UVM_METHOD_STREAM_MAX_GUEST_PAGES_v1C_05 500 227 228 #define PMA_SCRUBBER_SHARED_BUFFER_MAX_GUEST_PAGES_v1F_0C 500 229 230 /* 231 * Maximum number of SMs that can be read in one RPC call to get error states 232 */ 233 234 #define VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 80 235 236 #endif // __vgpu_rpc_nv_headers_h__ 237