1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 25 #ifndef _RPC_SDK_STRUCTURES_H_ 26 #define _RPC_SDK_STRUCTURES_H_ 27 28 #include <ctrl/ctrl83de.h> 29 #include <ctrl/ctrla080.h> 30 #include <ctrl/ctrlc36f.h> 31 #include <ctrl/ctrlc637.h> 32 #include <ctrl/ctrl0000/ctrl0000system.h> 33 #include <ctrl/ctrl0080/ctrl0080nvjpg.h> 34 #include <ctrl/ctrl0080/ctrl0080bsp.h> 35 #include <ctrl/ctrl0080/ctrl0080dma.h> 36 #include <ctrl/ctrl0080/ctrl0080fb.h> 37 #include <ctrl/ctrl0080/ctrl0080gr.h> 38 #include <ctrl/ctrl2080/ctrl2080ce.h> 39 #include <ctrl/ctrl2080/ctrl2080bus.h> 40 #include <ctrl/ctrl2080/ctrl2080fifo.h> 41 #include <ctrl/ctrl2080/ctrl2080gr.h> 42 #include <ctrl/ctrl2080/ctrl2080fb.h> 43 #include <ctrl/ctrl2080/ctrl2080internal.h> 44 #include <ctrl/ctrl83de/ctrl83dedebug.h> 45 #include <ctrl/ctrl0080/ctrl0080fifo.h> 46 #include <ctrl/ctrl2080/ctrl2080nvlink.h> 47 #include <ctrl/ctrl2080/ctrl2080fla.h> 48 #include <ctrl/ctrl2080/ctrl2080internal.h> 49 #include <ctrl/ctrl2080/ctrl2080mc.h> 50 #include <ctrl/ctrl2080/ctrl2080grmgr.h> 51 #include <ctrl/ctrl2080/ctrl2080ecc.h> 52 #include <ctrl/ctrl0090.h> 53 #include <ctrl/ctrl9096.h> 54 #include <ctrl/ctrlb0cc.h> 55 #include <ctrl/ctrla06f.h> 56 #include <ctrl/ctrl00f8.h> 57 #include <ctrl/ctrl90e6.h> 58 59 #include <class/cl2080.h> 60 #include <class/cl0073.h> 61 #include <class/clc670.h> 62 #include <class/clc673.h> 63 #include <class/clc67b.h> 64 #include <class/clc67d.h> 65 #include <class/clc67e.h> 66 #include "rpc_headers.h" 67 #include "nvctassert.h" 68 #include "nv_vgpu_types.h" 69 70 71 72 typedef struct vmiopd_SM_info { 73 NvU32 version; 74 NvU32 regBankCount; 75 NvU32 regBankRegCount; 76 NvU32 maxWarpsPerSM; 77 NvU32 maxThreadsPerWarp; 78 NvU32 geomGsObufEntries; 79 NvU32 geomXbufEntries; 80 NvU32 maxSPPerSM; 81 NvU32 rtCoreCount; 82 } VMIOPD_GRSMINFO; 83 84 // NV_SCAL_FAMILY_MAX_FBPS 16 85 #define MAX_FBPS 16 //Maximum number of FBPs 86 87 #define OBJ_MAX_HEADS_v03_00 4 88 #define OBJ_MAX_HEADS_v24_08 8 89 90 // NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES(256) / NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES(32) 91 #define MAX_ITERATIONS_DEVICE_INFO_TABLE 8 92 93 // NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES(512) / NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES(64) 94 #define MAX_ITERATIONS_DYNAMIC_BLACKLIST 8 95 96 #define NV0000_GPUACCT_RPC_PID_MAX_QUERY_COUNT 1000 97 98 #define NV2080_CTRL_CLK_ARCH_MAX_DOMAINS_v1E_0D 32 99 100 #define NV_RM_RPC_NO_MORE_DATA_TO_READ 0 101 #define NV_RM_RPC_MORE_RPC_DATA_TO_READ 1 102 103 //Maximum EXEC_PARTITIONS 104 #define NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05 8 105 106 //Maximum ECC Addresses 107 #define NV2080_CTRL_ECC_GET_LATEST_ECC_ADDRESSES_MAX_COUNT_v18_04 32 108 109 #define NV2080_CTRL_NVLINK_MAX_LINKS_v15_02 6 110 #define NV2080_CTRL_NVLINK_MAX_LINKS_v1A_18 12 111 #define NV2080_CTRL_NVLINK_MAX_LINKS_v23_04 24 112 113 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v15_02 8 114 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D 9 115 116 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02 32 117 #define VM_UUID_SIZE_v21_02 16 118 119 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v1A_1D 96 120 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00 120 121 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D 24 122 #define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D 96 123 #define NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D 8 124 125 #define NV0080_CTRL_GR_INFO_MAX_SIZE_1B_04 (0x0000002C) 126 #define NV0080_CTRL_GR_INFO_MAX_SIZE_1C_01 (0x00000030) 127 #define NV0080_CTRL_GR_INFO_MAX_SIZE_1E_02 (0x00000032) 128 #define NV0080_CTRL_GR_INFO_MAX_SIZE_21_01 (0x00000033) 129 #define NV0080_CTRL_GR_INFO_MAX_SIZE_22_02 (0x00000034) 130 #define NV0080_CTRL_GR_INFO_MAX_SIZE_23_00 (0x00000035) 131 #define NV0080_CTRL_GR_INFO_MAX_SIZE_24_02 (0x00000036) 132 #define NV0080_CTRL_GR_INFO_MAX_SIZE_24_03 (0x00000037) 133 #define NV0080_CTRL_GR_INFO_MAX_SIZE_24_07 (0x00000038) 134 #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8 135 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256 136 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240 137 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1B_05 8 138 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v1B_05 0x19 139 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07 0x1a 140 #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03 10 141 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03 12 142 #define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32 143 #define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 72 144 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04 6 145 #define NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 63 146 #define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50 147 #define NV2080_CTRL_MAX_PCES_v21_0A 32 148 #define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2 149 150 // Host USM type 151 #define NV_VGPU_CONFIG_USM_TYPE_DEFAULT 0x00000000 /* R-XVF */ 152 #define NV_VGPU_CONFIG_USM_TYPE_NVS 0x00000001 /* R-XVF */ 153 #define NV_VGPU_CONFIG_USM_TYPE_QUADRO 0x00000002 /* R-XVF */ 154 #define NV_VGPU_CONFIG_USM_TYPE_GEFORCE 0x00000003 /* R-XVF */ 155 #define NV_VGPU_CONFIG_USM_TYPE_COMPUTE 0x00000004 /* R-XVF */ 156 157 // Defined this intermediate RM-RPC structure for making RPC call from Guest as 158 // we have the restriction of passing max 4kb of data to plugin and the 159 // NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS is way more than that. 160 // This structure is similar to NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS 161 // RM control structure. 162 // Added passIndex member to identify from which index (in the full RM pid list 163 // on host)onwards the data needs to be read. Caller should initialize passIndex 164 // to NV_RM_RPC_MORE_RPC_DATA_TO_READ, and keep making RPC calls until the 165 // passIndex value is returned as NV_RM_RPC_NO_MORE_DATA_TO_READ by the RPC. 166 typedef struct 167 { 168 NvU32 gpuId; 169 NvU32 passIndex; 170 NvU32 pidTbl[NV0000_GPUACCT_RPC_PID_MAX_QUERY_COUNT]; 171 NvU32 pidCount; 172 } NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_RPC_EX; 173 174 typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG_v03_00[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES]; 175 176 typedef NvV32 NvRmctrlCmd; 177 178 struct pte_desc 179 { 180 NvU32 idr:2; 181 NvU32 reserved1:14; 182 NvU32 length:16; 183 union { 184 NvU64 pte; // PTE when IDR==0; PDE when IDR > 0 185 NvU64 pde; // PTE when IDR==0; PDE when IDR > 0 186 } pte_pde[] NV_ALIGN_BYTES(8); // PTE when IDR==0; PDE when IDR > 0 187 }; 188 189 typedef struct VGPU_BSP_CAPS 190 { 191 NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; 192 } VGPU_BSP_CAPS; 193 194 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v15_01 (0x00000014) 195 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1A_04 (0x00000014) 196 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1C_09 (0x00000016) 197 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v20_03 (0x00000018) 198 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06 (0x00000019) 199 200 #define NV2080_ENGINE_TYPE_LAST_v18_01 (0x0000002a) 201 #define NV2080_ENGINE_TYPE_LAST_v1C_09 (0x00000034) 202 203 #define NV2080_ENGINE_TYPE_LAST_v1A_00 (0x2a) 204 205 #define NV2080_ENGINE_TYPE_COPY_SIZE_v1A_0D (10) 206 #define NV2080_ENGINE_TYPE_COPY_SIZE_v22_00 (10) 207 #define NV2080_ENGINE_TYPE_COPY_SIZE_v24_09 (64) 208 209 #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1A_0F (0x00000033) 210 #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09 (0x00000034) 211 212 //Maximum GMMU_FMT_LEVELS 213 #define GMMU_FMT_MAX_LEVELS_v05_00 5 214 #define GMMU_FMT_MAX_LEVELS_v1A_12 6 215 216 //Maximum MMU FMT sub levels 217 #define MMU_FMT_MAX_SUB_LEVELS_v09_02 2 218 219 //Maximum number of supported TDP clients 220 #define NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F 5 221 222 //Maximum number of SMs whose error state can be read in single call 223 #define NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03 100 224 225 // Workaround for bug 200702083 (#15) 226 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1A_15 0x2F 227 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1A_24 0x33 228 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1E_01 0x35 229 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1F_0F 0x36 230 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A 0x37 231 232 #define NV2080_CTRL_PERF_MAX_LIMITS_v1C_0B 0x100 233 234 // Maximum guest address that can we queried in one RPC. 235 // Below number is calculated as per Max. Guest Adrresses and their 236 // state can be returned in a single 4K (RPC Page size) iteration 237 #define GET_PLCABLE_MAX_GUEST_ADDRESS_v1D_05 60 238 239 // 240 // Versioned define for 241 // NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES 242 // 243 #define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07 2 244 245 // Versioned define for 246 // NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 247 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08 13 248 249 #define MAX_NVDEC_ENGINES_V1A_07 5 250 #define MAX_NVDEC_ENGINES_V25_00 8 251 #define NV0080_CTRL_MSENC_CAPS_TBL_SIZE_V25_00 4 252 #define NV0080_CTRL_NVJPG_CAPS_TBL_SIZE_V18_0C 9 253 #define NV0080_CTRL_BSP_CAPS_TBL_SIZE_V09_10 8 254 #define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS_V25_01 0x40 255 #define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES_V25_05 256 256 257 #define NV0080_CTRL_GR_CAPS_TBL_SIZE_v25_0E 23 258 #define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E 5 259 #define RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E 13 260 #define NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07 4 261 262 #define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11 0x00000041 263 264 typedef struct _GPU_PARTITION_INFO 265 { 266 NvU32 swizzId; 267 NvU32 grEngCount; 268 NvU32 veidCount; 269 NvU32 ceCount; 270 NvU32 gpcCount; 271 NvU32 virtualGpcCount; 272 NvU32 gfxGpcCount; 273 NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 274 NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 275 NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 276 NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 277 NvU32 nvDecCount; 278 NvU32 nvEncCount; 279 NvU32 nvJpgCount; 280 NvU32 partitionFlag; 281 NvU32 smCount; 282 NvU32 nvOfaCount; 283 NvU64 memSize; 284 NvBool bValid; 285 NV2080_CTRL_GPU_PARTITION_SPAN span; 286 NvU64 validCTSIdMask; 287 } GPU_PARTITION_INFO; 288 289 typedef struct _GPU_EXEC_PARTITION_INFO 290 { 291 NvU32 execPartCount; 292 NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; 293 NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; 294 } GPU_EXEC_PARTITION_INFO; 295 296 typedef struct 297 { 298 NvBool bGpuSupportsFabricProbe; 299 } VGPU_P2P_CAPABILITY_PARAMS; 300 301 typedef struct _GPU_EXEC_SYSPIPE_INFO { 302 NvU32 execPartCount; 303 NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; 304 NvU32 syspipeId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; 305 } GPU_EXEC_SYSPIPE_INFO; 306 307 typedef struct _VGPU_STATIC_PROPERTIES 308 { 309 NvU32 encSessionStatsReportingState; 310 NvBool bProfilingTracingEnabled; 311 NvBool bDebuggingEnabled; 312 NvU32 channelCount; 313 NvBool bPblObjNotPresent; //Valid only in case of GA100 SRIOV Heavy 314 } VGPU_STATIC_PROPERTIES; 315 316 struct _vgpu_static_info 317 { 318 NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; 319 NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; 320 NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS fbLtcInfoForFbp[MAX_FBPS]; 321 NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS mcStaticIntrTable; 322 NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS grZcullInfo; 323 NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS fifoDeviceInfoTable[MAX_ITERATIONS_DEVICE_INFO_TABLE]; 324 NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS fbDynamicBlacklistedPages[MAX_ITERATIONS_DYNAMIC_BLACKLIST]; 325 NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS fifoLatencyBufferSize[NV2080_ENGINE_TYPE_LAST]; 326 NV2080_CTRL_CE_GET_CAPS_V2_PARAMS ceCaps[NV2080_ENGINE_TYPE_COPY_SIZE]; 327 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS nvlinkCaps; 328 NV2080_CTRL_BUS_GET_INFO_V2_PARAMS busGetInfoV2; 329 NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS grSmIssueRateModifier; 330 NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS pcieSupportedGpuAtomics; 331 NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS ceGetAllCaps; 332 NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS c2cInfo; 333 NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS vgxSystemInfo; 334 NVA080_CTRL_VGPU_GET_CONFIG_PARAMS vgpuConfig; 335 NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo; 336 NvU64 engineList; 337 NvU32 pcieGpuLinkCaps; 338 NvBool bFlaSupported; 339 NV2080_CTRL_FLA_GET_RANGE_PARAMS flaInfo; 340 NvBool bPerRunlistChannelRamEnabled; 341 NvU32 subProcessIsolation; 342 VGPU_STATIC_PROPERTIES vgpuStaticProperties; 343 NvU64 maxSupportedPageSize; 344 GPU_PARTITION_INFO gpuPartitionInfo; // Default (Admin created) EXEC-I PARTITION INFO 345 NvBool bC2CLinkUp; 346 NvBool bSelfHostedMode; 347 NvBool bLocalEgmEnabled; 348 NvU32 localEgmPeerId; 349 NvU32 ceFaultMethodBufferDepth; 350 NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 351 NvBool bPerSubCtxheaderSupported; 352 NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS grInfoParams; 353 NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS ctxBuffInfo; 354 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS ppcMaskParams; 355 NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS globalSmOrder; 356 NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS smIssueRateModifier; 357 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS floorsweepMaskParams; 358 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS fecsRecordSize; 359 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS fecsTraceDefines; 360 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS pdbTableParams; 361 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS ropInfoParams; 362 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS zcullInfoParams; 363 NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS ciProfiles; 364 NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS mcEngineNotificationIntrVectors; 365 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS eccStatus; 366 NvBool guestManagedHwAlloc; 367 NvU8 jpegCaps[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE]; 368 NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS nvencCaps; 369 VGPU_BSP_CAPS vgpuBspCaps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 370 NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS constructedFalconInfo; 371 GPU_EXEC_PARTITION_INFO execPartitionInfo; 372 NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo; 373 NvU64 fbTaxLength; 374 NvU64 fbLength; 375 NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams; 376 NvU32 grBufferSize[RPC_GR_BUFFER_TYPE_GRAPHICS_MAX]; 377 NvU32 fbioMask; 378 NvBool bSplitVasBetweenServerClientRm; 379 NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 380 NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 381 NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 382 NvBool poisonFuseEnabled; 383 NvBool bAtsSupported; 384 NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS deviceInfoTable; 385 NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS memsysStaticConfig; 386 VGPU_P2P_CAPABILITY_PARAMS p2pCaps; 387 NvU32 fbBusWidth; 388 NvU32 fbpMask; 389 NvU32 ltcMask; 390 NvU32 ltsCount; 391 NvU32 sizeL2Cache; 392 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS zbcTableSizes[NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT]; 393 NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS busGetPcieReqAtomicsCaps; 394 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS masterGetVfErrCntIntMsk; 395 }; 396 397 typedef struct _vgpu_static_info VGPU_STATIC_INFO, VGPU_STATIC_INFO2; 398 typedef struct _vgpu_static_info VGPU_STATIC_DATA; 399 400 typedef NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS VGPU_FB_GET_LTC_INFO_FOR_FBP[MAX_FBPS]; 401 typedef VGPU_BSP_CAPS VGPU_BSP_GET_CAPS[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 402 typedef NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS VGPU_FIFO_GET_DEVICE_INFO_TABLE[MAX_ITERATIONS_DEVICE_INFO_TABLE]; 403 typedef NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES[MAX_ITERATIONS_DYNAMIC_BLACKLIST]; 404 typedef NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS VGPU_GET_LATENCY_BUFFER_SIZE[NV2080_ENGINE_TYPE_LAST]; 405 typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS VGPU_CE_GET_CAPS_V2[NV2080_ENGINE_TYPE_COPY_SIZE]; 406 407 typedef struct GSP_FIRMWARE GSP_FIRMWARE; 408 409 ct_assert(NV2080_CTRL_GPU_ECC_UNIT_COUNT == NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06); 410 ct_assert(NV2080_ENGINE_TYPE_LAST == 0x40); 411 ct_assert(NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE == NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09); 412 ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERIES == NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00); 413 ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE == NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D); 414 ct_assert(NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES == NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D); 415 ct_assert(NV2080_CTRL_GRMGR_MAX_SMC_IDS == NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D); 416 ct_assert((NV0080_CTRL_GR_INFO_INDEX_MAX + 1) == NV0080_CTRL_GR_INFO_MAX_SIZE_24_07); 417 ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_ENGINES == NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04); 418 ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_SM == NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03); 419 ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_GPC == NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03); 420 ct_assert(NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT == 421 NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07); 422 ct_assert(NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT == NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03); 423 ct_assert(NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS == NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F); 424 ct_assert(NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL == NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03); 425 ct_assert(VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 < NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03); 426 ct_assert(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE == NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A); 427 ct_assert(NV2080_CTRL_GPU_MAX_SMC_IDS == 8); 428 ct_assert(NV2080_GPU_MAX_GID_LENGTH == 0x000000100); 429 ct_assert(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES == 16); 430 ct_assert(NV2080_GPU_MAX_NAME_STRING_LENGTH == 0x0000040); 431 ct_assert(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES == 256); 432 ct_assert(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX == NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09); 433 ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES == 256); 434 ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES == 32); 435 ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES == 16); 436 ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA == 2); 437 ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN == 16); 438 ct_assert(NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES == 64); 439 ct_assert(NV2080_CTRL_CE_CAPS_TBL_SIZE == NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A); 440 ct_assert(NV2080_ENGINE_TYPE_COPY_SIZE == NV2080_ENGINE_TYPE_COPY_SIZE_v24_09); 441 ct_assert(NV2080_ENGINE_TYPE_NVENC_SIZE <= 4); 442 ct_assert(NV2080_ENGINE_TYPE_NVDEC_SIZE == 8); 443 ct_assert(NV2080_ENGINE_TYPE_NVJPEG_SIZE == 8); 444 ct_assert(NV2080_ENGINE_TYPE_GR_SIZE == 8); 445 ct_assert(NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE == NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D); 446 ct_assert(NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS == NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02); 447 ct_assert(VM_UUID_SIZE == VM_UUID_SIZE_v21_02); 448 ct_assert(NV2080_CTRL_MAX_PCES == NV2080_CTRL_MAX_PCES_v21_0A); 449 ct_assert(NV0080_CTRL_MSENC_CAPS_TBL_SIZE_V25_00 == NV0080_CTRL_MSENC_CAPS_TBL_SIZE); 450 ct_assert(MAX_NVDEC_ENGINES_V1A_07 <= NV2080_CTRL_CMD_INTERNAL_MAX_BSPS); 451 ct_assert(MAX_NVDEC_ENGINES_V25_00 == NV2080_CTRL_CMD_INTERNAL_MAX_BSPS); 452 ct_assert(NV0080_CTRL_NVJPG_CAPS_TBL_SIZE_V18_0C == NV0080_CTRL_NVJPG_CAPS_TBL_SIZE); 453 ct_assert(NV0080_CTRL_BSP_CAPS_TBL_SIZE_V09_10 == NV0080_CTRL_BSP_CAPS_TBL_SIZE); 454 ct_assert(NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS_V25_01 == NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS); 455 ct_assert(NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES_V25_05 == NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES); 456 ct_assert(NV0080_CTRL_GR_CAPS_TBL_SIZE_v25_0E == NV0080_CTRL_GR_CAPS_TBL_SIZE); 457 ct_assert(NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E == NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL); 458 ct_assert(RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E == RPC_GR_BUFFER_TYPE_GRAPHICS_MAX); 459 ct_assert(NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07 == NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT); 460 ct_assert(NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11 == NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE); 461 462 #endif /*_RPC_SDK_STRUCTURES_H_*/ 463 464