1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 25 #ifndef _RPC_SDK_STRUCTURES_H_ 26 #define _RPC_SDK_STRUCTURES_H_ 27 28 #include <ctrl/ctrl83de.h> 29 #include <ctrl/ctrlc36f.h> 30 #include <ctrl/ctrlc637.h> 31 #include <ctrl/ctrl0000/ctrl0000system.h> 32 #include <ctrl/ctrl0080/ctrl0080nvjpg.h> 33 #include <ctrl/ctrl0080/ctrl0080bsp.h> 34 #include <ctrl/ctrl0080/ctrl0080dma.h> 35 #include <ctrl/ctrl0080/ctrl0080fb.h> 36 #include <ctrl/ctrl0080/ctrl0080gr.h> 37 #include <ctrl/ctrl2080/ctrl2080ce.h> 38 #include <ctrl/ctrl2080/ctrl2080bus.h> 39 #include <ctrl/ctrl2080/ctrl2080fifo.h> 40 #include <ctrl/ctrl2080/ctrl2080gr.h> 41 #include <ctrl/ctrl2080/ctrl2080fb.h> 42 #include <ctrl/ctrl83de/ctrl83dedebug.h> 43 #include <ctrl/ctrl0080/ctrl0080fifo.h> 44 #include <ctrl/ctrl2080/ctrl2080nvlink.h> 45 #include <ctrl/ctrl2080/ctrl2080fla.h> 46 #include <ctrl/ctrl2080/ctrl2080internal.h> 47 #include <ctrl/ctrl2080/ctrl2080mc.h> 48 #include <ctrl/ctrl2080/ctrl2080grmgr.h> 49 #include <ctrl/ctrl2080/ctrl2080ecc.h> 50 #include <ctrl/ctrl0090.h> 51 #include <ctrl/ctrl9096.h> 52 #include <ctrl/ctrlb0cc.h> 53 #include <ctrl/ctrla06f.h> 54 #include <ctrl/ctrl00f8.h> 55 56 #include <class/cl2080.h> 57 #include <class/cl0073.h> 58 #include <class/clc670.h> 59 #include <class/clc673.h> 60 #include <class/clc67b.h> 61 #include <class/clc67d.h> 62 #include <class/clc67e.h> 63 #include "rpc_headers.h" 64 #include "nvctassert.h" 65 #include "nv_vgpu_types.h" 66 67 68 69 typedef struct vmiopd_SM_info { 70 NvU32 version; 71 NvU32 regBankCount; 72 NvU32 regBankRegCount; 73 NvU32 maxWarpsPerSM; 74 NvU32 maxThreadsPerWarp; 75 NvU32 geomGsObufEntries; 76 NvU32 geomXbufEntries; 77 NvU32 maxSPPerSM; 78 NvU32 rtCoreCount; 79 } VMIOPD_GRSMINFO; 80 81 // NV_SCAL_FAMILY_MAX_FBPS 16 82 #define MAX_FBPS 16 //Maximum number of FBPs 83 84 #define OBJ_MAX_HEADS_v03_00 4 85 #define OBJ_MAX_HEADS_v24_08 8 86 87 88 #define MAX_NVDEC_ENGINES 5 // Maximum number of NVDEC engines 89 90 // NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES(256) / NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES(32) 91 #define MAX_ITERATIONS_DEVICE_INFO_TABLE 8 92 93 // NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES(512) / NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES(64) 94 #define MAX_ITERATIONS_DYNAMIC_BLACKLIST 8 95 96 #define NV0000_GPUACCT_RPC_PID_MAX_QUERY_COUNT 1000 97 98 #define NV2080_CTRL_CLK_ARCH_MAX_DOMAINS_v1E_0D 32 99 100 #define NV_RM_RPC_NO_MORE_DATA_TO_READ 0 101 #define NV_RM_RPC_MORE_RPC_DATA_TO_READ 1 102 103 //Maximum EXEC_PARTITIONS 104 #define NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05 8 105 106 //Maximum ECC Addresses 107 #define NV2080_CTRL_ECC_GET_LATEST_ECC_ADDRESSES_MAX_COUNT_v18_04 32 108 109 #define NV2080_CTRL_NVLINK_MAX_LINKS_v15_02 6 110 #define NV2080_CTRL_NVLINK_MAX_LINKS_v1A_18 12 111 #define NV2080_CTRL_NVLINK_MAX_LINKS_v23_04 24 112 113 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v15_02 8 114 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D 9 115 116 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02 32 117 #define VM_UUID_SIZE_v21_02 16 118 119 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v1A_1D 96 120 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00 120 121 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D 24 122 #define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D 96 123 #define NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D 8 124 125 #define NV0080_CTRL_GR_INFO_MAX_SIZE_1B_04 (0x0000002C) 126 #define NV0080_CTRL_GR_INFO_MAX_SIZE_1C_01 (0x00000030) 127 #define NV0080_CTRL_GR_INFO_MAX_SIZE_1E_02 (0x00000032) 128 #define NV0080_CTRL_GR_INFO_MAX_SIZE_21_01 (0x00000033) 129 #define NV0080_CTRL_GR_INFO_MAX_SIZE_22_02 (0x00000034) 130 #define NV0080_CTRL_GR_INFO_MAX_SIZE_23_00 (0x00000035) 131 #define NV0080_CTRL_GR_INFO_MAX_SIZE_24_02 (0x00000036) 132 #define NV0080_CTRL_GR_INFO_MAX_SIZE_24_03 (0x00000037) 133 #define NV0080_CTRL_GR_INFO_MAX_SIZE_24_07 (0x00000038) 134 #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8 135 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256 136 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240 137 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1B_05 8 138 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v1B_05 0x19 139 #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03 10 140 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03 12 141 #define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32 142 #define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 72 143 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04 6 144 #define NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 63 145 #define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50 146 #define NV2080_CTRL_MAX_PCES_v21_0A 32 147 #define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2 148 149 //NV2080_CTRL_PERF_PSTATES_INFO data union enums for r535 code 150 #define NV2080_CTRL_PERF_PSTATE_VERSION_INVALID_v23_02 0x00 151 #define NV2080_CTRL_PERF_PSTATE_VERSION_MODEL_10_v23_02 0xFE 152 #define NV2080_CTRL_PERF_PSTATE_VERSION_2X_v23_02 0x20 153 #define NV2080_CTRL_PERF_PSTATE_VERSION_3X_v23_02 0xFD 154 #define NV2080_CTRL_PERF_PSTATE_VERSION_30_v23_02 0x30 155 #define NV2080_CTRL_PERF_PSTATE_VERSION_35_v23_02 0x35 156 #define NV2080_CTRL_PERF_PSTATE_VERSION_40_v23_02 0x40 157 #define NV2080_CTRL_PERF_PSTATE_VERSION_PMU_INIT_1X_v23_02 0xFC 158 #define NV2080_CTRL_PERF_PSTATE_VERSION_70_v23_02 0x70 159 #define NV2080_CTRL_PERF_PSTATE_VERSION_DISABLED_v23_02 NV_U8_MAX 160 161 //NV2080_CTRL_PERF_PSTATES_INFO data union enums for chips_a 162 #define NV2080_CTRL_PERF_PSTATES_TYPE_BASE_v24_01 0x00U 163 #define NV2080_CTRL_PERF_PSTATES_TYPE_MODEL_10_v24_01 0x01U 164 #define NV2080_CTRL_PERF_PSTATES_TYPE_2X_v24_01 0x02U 165 #define NV2080_CTRL_PERF_PSTATES_TYPE_3X_v24_01 0x03U 166 #define NV2080_CTRL_PERF_PSTATES_TYPE_30_v24_01 0x04U 167 #define NV2080_CTRL_PERF_PSTATES_TYPE_35_v24_01 0x05U 168 #define NV2080_CTRL_PERF_PSTATES_TYPE_PMU_INIT_1X_v24_01 0x07U 169 #define NV2080_CTRL_PERF_PSTATES_TYPE_70_v24_01 0x08U 170 #define NV2080_CTRL_PERF_PSTATES_TYPE_50_v24_01 0x09U 171 #define NV2080_CTRL_PERF_PSTATES_TYPE_5X_v24_01 0x0AU 172 #define NV2080_CTRL_PERF_PSTATES_TYPE_INVALID_v24_01 NV2080_CTRL_BOARDOBJGRP_CLASS_TYPE_INVALID 173 174 // Defined this intermediate RM-RPC structure for making RPC call from Guest as 175 // we have the restriction of passing max 4kb of data to plugin and the 176 // NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS is way more than that. 177 // This structure is similar to NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS 178 // RM control structure. 179 // Added passIndex member to identify from which index (in the full RM pid list 180 // on host)onwards the data needs to be read. Caller should initialize passIndex 181 // to NV_RM_RPC_MORE_RPC_DATA_TO_READ, and keep making RPC calls until the 182 // passIndex value is returned as NV_RM_RPC_NO_MORE_DATA_TO_READ by the RPC. 183 typedef struct 184 { 185 NvU32 gpuId; 186 NvU32 passIndex; 187 NvU32 pidTbl[NV0000_GPUACCT_RPC_PID_MAX_QUERY_COUNT]; 188 NvU32 pidCount; 189 } NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_RPC_EX; 190 191 typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG_v03_00[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES]; 192 193 typedef NvV32 NvRmctrlCmd; 194 195 struct pte_desc 196 { 197 NvU32 idr:2; 198 NvU32 reserved1:14; 199 NvU32 length:16; 200 union { 201 NvU64 pte; // PTE when IDR==0; PDE when IDR > 0 202 NvU64 pde; // PTE when IDR==0; PDE when IDR > 0 203 } pte_pde[] NV_ALIGN_BYTES(8); // PTE when IDR==0; PDE when IDR > 0 204 }; 205 206 /* 207 * VGPU_CACHED_RMCTRL_LIST 208 * 209 * This macro contains the list of RmCtrls which return static values and can be cached in 210 * guest RM. 211 * 212 * To cache a RmCtrl, add it to VGPU_CACHED_RMCTRL_LIST in the format: 213 * VGPU_CACHED_RMCTRL_ENTRY(<RmCtrl Command>, <RmCtrl Parameter Type>) 214 */ 215 216 #define VGPU_CACHED_RMCTRL_LIST \ 217 VGPU_CACHED_RMCTRL_ENTRY(NV2080_CTRL_CMD_PERF_VPSTATES_GET_INFO, NV2080_CTRL_PERF_VPSTATES_INFO) 218 219 enum VGPU_CACHED_RMCTRL_INDICES 220 { 221 #define VGPU_CACHED_RMCTRL_ENTRY(ctrlCmd,type) \ 222 VGPU_CACHED_RMCTRL_IDX_##ctrlCmd, 223 224 VGPU_CACHED_RMCTRL_LIST 225 226 #undef VGPU_CACHED_RMCTRL_ENTRY 227 228 VGPU_CACHED_RMCTRL_IDX_COUNT, 229 }; 230 231 typedef struct vgpu_cached_rmctrl 232 { 233 void *ptr; 234 NvBool bCached; 235 NV_STATUS status; 236 }vgpu_cached_rmctrl; 237 238 typedef struct vgpu_cached_rmctrl_list 239 { 240 vgpu_cached_rmctrl vgpu_cached_rmctrls[VGPU_CACHED_RMCTRL_IDX_COUNT]; 241 } vgpu_cached_rmctrl_list; 242 243 typedef struct VGPU_BSP_CAPS 244 { 245 NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; 246 } VGPU_BSP_CAPS; 247 248 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v15_01 (0x00000014) 249 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1A_04 (0x00000014) 250 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1C_09 (0x00000016) 251 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v20_03 (0x00000018) 252 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06 (0x00000019) 253 254 #define NV2080_ENGINE_TYPE_LAST_v18_01 (0x0000002a) 255 #define NV2080_ENGINE_TYPE_LAST_v1C_09 (0x00000034) 256 257 #define NV2080_ENGINE_TYPE_LAST_v1A_00 (0x2a) 258 259 #define NV2080_ENGINE_TYPE_COPY_SIZE_v1A_0D (10) 260 #define NV2080_ENGINE_TYPE_COPY_SIZE_v22_00 (10) 261 #define NV2080_ENGINE_TYPE_COPY_SIZE_v24_09 (64) 262 263 #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1A_0F (0x00000033) 264 #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09 (0x00000034) 265 266 //Maximum GMMU_FMT_LEVELS 267 #define GMMU_FMT_MAX_LEVELS_v05_00 5 268 #define GMMU_FMT_MAX_LEVELS_v1A_12 6 269 270 //Maximum MMU FMT sub levels 271 #define MMU_FMT_MAX_SUB_LEVELS_v09_02 2 272 273 //Maximum number of supported TDP clients 274 #define NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F 5 275 276 //Maximum number of SMs whose error state can be read in single call 277 #define NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03 100 278 279 // Workaround for bug 200702083 (#15) 280 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1A_15 0x2F 281 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1A_24 0x33 282 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1E_01 0x35 283 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1F_0F 0x36 284 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A 0x37 285 286 #define NV2080_CTRL_PERF_MAX_LIMITS_v1C_0B 0x100 287 288 // Maximum guest address that can we queried in one RPC. 289 // Below number is calculated as per Max. Guest Adrresses and their 290 // state can be returned in a single 4K (RPC Page size) iteration 291 #define GET_PLCABLE_MAX_GUEST_ADDRESS_v1D_05 60 292 293 // 294 // Versioned define for 295 // NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES 296 // 297 #define NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07 2 298 299 // Versioned define for 300 // NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 301 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08 13 302 303 #endif /*_RPC_SDK_STRUCTURES_H_*/ 304 305