1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 //******************************************************************************
25 //
26 // Description:
27 // Collection of functions to handle RPC structurecopy
28 //
29 //******************************************************************************
30
31 #include "vgpu/rpc.h"
32 #include "g_rpcstructurecopy_private.h"
33 #include "vgpu/sdk-structures.h"
34
35 #define RPC_STRUCTURES
36 #define RPC_GENERIC_UNION
37 #include "g_rpc-structures.h"
38 #undef RPC_STRUCTURES
39 #undef RPC_GENERIC_UNION
40
deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS * fbLtcInfoForFbp,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)41 NV_STATUS deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS *fbLtcInfoForFbp, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
42 {
43
44 if (!offset)
45 {
46 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
47 }
48
49 *offset += sizeof(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03);
50
51 return NVOS_STATUS_SUCCESS;
52 }
53
deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D(VGPU_FB_GET_LTC_INFO_FOR_FBP * vgpuFbGetLtcInfoForFbp,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)54 NV_STATUS deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D(VGPU_FB_GET_LTC_INFO_FOR_FBP *vgpuFbGetLtcInfoForFbp, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
55 {
56
57 if (!offset)
58 {
59 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
60 }
61
62 // If vgpuFbGetLtcInfoForFbp and buffer are valid, then copy data and return the offset
63 if (vgpuFbGetLtcInfoForFbp && buffer)
64 {
65 VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D *vgpu_fb_get_ltc_info_for_fbp_v1A_0D = NULL;
66 NvU32 i;
67
68 if ((bufferSize < *offset) ||
69 (bufferSize < (*offset + sizeof(VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D))))
70 return NV_ERR_BUFFER_TOO_SMALL;
71
72 vgpu_fb_get_ltc_info_for_fbp_v1A_0D = (void*)(buffer + *offset);
73
74 for (i = 0; i < MAX_FBPS; i++)
75 {
76 (*vgpuFbGetLtcInfoForFbp)[i].fbpIndex = vgpu_fb_get_ltc_info_for_fbp_v1A_0D->fbLtcInfoForFbp[i].fbpIndex;
77 (*vgpuFbGetLtcInfoForFbp)[i].ltcMask = vgpu_fb_get_ltc_info_for_fbp_v1A_0D->fbLtcInfoForFbp[i].ltcMask;
78 (*vgpuFbGetLtcInfoForFbp)[i].ltcCount = vgpu_fb_get_ltc_info_for_fbp_v1A_0D->fbLtcInfoForFbp[i].ltcCount;
79 }
80 }
81
82 *offset += sizeof(VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D);
83
84 return NVOS_STATUS_SUCCESS;
85 }
86
deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS * mcEngineNotificationIntrVectors,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)87 NV_STATUS deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *mcEngineNotificationIntrVectors, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
88 {
89 if (!offset)
90 {
91 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
92 }
93
94 // If mcEngineNotificationIntrVectors and buffer are valid, then copy data and return the offset
95 if (mcEngineNotificationIntrVectors && buffer)
96 {
97 NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00 *mc_get_engine_notification_intr_vectors_v16_00 = NULL;
98 NvU32 i;
99
100 if ((bufferSize < *offset) ||
101 (bufferSize < (*offset + sizeof(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00))))
102 return NV_ERR_BUFFER_TOO_SMALL;
103
104 mc_get_engine_notification_intr_vectors_v16_00 = (void*)(buffer + *offset);
105
106 mcEngineNotificationIntrVectors->numEntries = mc_get_engine_notification_intr_vectors_v16_00->numEntries;
107
108 for (i = 0; i < mcEngineNotificationIntrVectors->numEntries; i++)
109 {
110 mcEngineNotificationIntrVectors->entries[i].nv2080EngineType = mc_get_engine_notification_intr_vectors_v16_00->entries[i].nv2080EngineType;
111 mcEngineNotificationIntrVectors->entries[i].notificationIntrVector = mc_get_engine_notification_intr_vectors_v16_00->entries[i].notificationIntrVector;
112 }
113
114 }
115
116 *offset += sizeof(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00);
117
118 return NVOS_STATUS_SUCCESS;
119 }
120
deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS * mcStaticIntrTable,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)121 NV_STATUS deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *mcStaticIntrTable, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
122 {
123 if (!offset)
124 {
125 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
126 }
127
128 // If mcStaticIntrs and buffer are valid, then copy data and return the offset
129 if (mcStaticIntrTable && buffer)
130 {
131 NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09 *mc_get_static_intr_table_v1E_09 = NULL;
132 NvU32 i;
133
134 if ((bufferSize < *offset) ||
135 (bufferSize < (*offset + sizeof(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09))))
136 return NV_ERR_BUFFER_TOO_SMALL;
137
138 mc_get_static_intr_table_v1E_09 = (void*)(buffer + *offset);
139
140 mcStaticIntrTable->numEntries = mc_get_static_intr_table_v1E_09->numEntries;
141
142 for (i = 0; i < mcStaticIntrTable->numEntries; i++)
143 {
144 mcStaticIntrTable->entries[i].nv2080IntrType = mc_get_static_intr_table_v1E_09->entries[i].nv2080IntrType;
145 mcStaticIntrTable->entries[i].pmcIntrMask = mc_get_static_intr_table_v1E_09->entries[i].pmcIntrMask;
146 mcStaticIntrTable->entries[i].intrVectorStall = mc_get_static_intr_table_v1E_09->entries[i].intrVectorStall;
147 mcStaticIntrTable->entries[i].intrVectorNonStall = mc_get_static_intr_table_v1E_09->entries[i].intrVectorNonStall;
148 }
149
150 }
151
152 *offset += sizeof(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09);
153
154 return NVOS_STATUS_SUCCESS;
155 }
156
deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07(VGPU_FIFO_GET_DEVICE_INFO_TABLE * fifoDeviceInfoTablePtr,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)157 NV_STATUS deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07(VGPU_FIFO_GET_DEVICE_INFO_TABLE *fifoDeviceInfoTablePtr, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
158 {
159 if (!offset)
160 {
161 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
162 }
163
164 // If fifoDeviceInfoTablePtr and buffer are valid, then copy data and return the offset
165 if (fifoDeviceInfoTablePtr && buffer)
166 {
167 NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *fifoDeviceInfoTable = *fifoDeviceInfoTablePtr;
168 VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07 *vgpu_fifo_get_device_info_table_v1A_07 = NULL;
169 NvU32 i, j;
170
171 if ((bufferSize < *offset) ||
172 (bufferSize < (*offset + sizeof(VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07))))
173 return NV_ERR_BUFFER_TOO_SMALL;
174
175 vgpu_fifo_get_device_info_table_v1A_07 = (void*)(buffer + *offset);
176
177 for (i = 0; i < MAX_ITERATIONS_DEVICE_INFO_TABLE; i++)
178 {
179 fifoDeviceInfoTable[i].baseIndex = vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].baseIndex;
180 fifoDeviceInfoTable[i].numEntries = vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].numEntries;
181 fifoDeviceInfoTable[i].bMore = vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].bMore;
182
183 for (j = 0; j < NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES; j++)
184 {
185 portMemCopy(&fifoDeviceInfoTable[i].entries[j].engineData,
186 sizeof(fifoDeviceInfoTable[i].entries[j].engineData),
187 &vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].engineData,
188 sizeof(fifoDeviceInfoTable[i].entries[j].engineData));
189 portMemCopy(&fifoDeviceInfoTable[i].entries[j].pbdmaIds,
190 sizeof(fifoDeviceInfoTable[i].entries[j].pbdmaIds),
191 &vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].pbdmaIds,
192 sizeof(fifoDeviceInfoTable[i].entries[j].pbdmaIds));
193 portMemCopy(&fifoDeviceInfoTable[i].entries[j].pbdmaFaultIds,
194 sizeof(fifoDeviceInfoTable[i].entries[j].pbdmaFaultIds),
195 &vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].pbdmaFaultIds,
196 sizeof(fifoDeviceInfoTable[i].entries[j].pbdmaFaultIds));
197 portMemCopy(&fifoDeviceInfoTable[i].entries[j].engineName,
198 sizeof(fifoDeviceInfoTable[i].entries[j].engineName),
199 &vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].engineName,
200 sizeof(fifoDeviceInfoTable[i].entries[j].engineName));
201 fifoDeviceInfoTable[i].entries[j].numPbdmas = vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].numPbdmas;
202 }
203 }
204 }
205
206 *offset += sizeof(VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07);
207
208 return NVOS_STATUS_SUCCESS;
209 }
210
deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES * fbDynamicBlacklistedPagesPtr,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)211 NV_STATUS deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES *fbDynamicBlacklistedPagesPtr, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
212 {
213 if (!offset)
214 {
215 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
216 }
217
218 // If fbDynamicBlacklistedPagesPtr and buffer are valid, then copy data and return the offset
219 if (fbDynamicBlacklistedPagesPtr && buffer)
220 {
221 NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS *fbDynamicBlacklistedPages = *fbDynamicBlacklistedPagesPtr;
222 VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07 *vgpu_fb_get_dynamic_blacklisted_pages_v1A_07 = NULL;
223 NvU32 i, j;
224
225 if ((bufferSize < *offset) ||
226 (bufferSize < (*offset + sizeof(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07))))
227 return NV_ERR_BUFFER_TOO_SMALL;
228
229 vgpu_fb_get_dynamic_blacklisted_pages_v1A_07 = (void*)(buffer + *offset);
230
231 for (i = 0; i < MAX_ITERATIONS_DYNAMIC_BLACKLIST; i++)
232 {
233 fbDynamicBlacklistedPages[i].baseIndex = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].baseIndex;
234 fbDynamicBlacklistedPages[i].validEntries = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].validEntries;
235 fbDynamicBlacklistedPages[i].bMore = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].bMore;
236
237 for (j = 0; j < NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES; j++)
238 {
239 fbDynamicBlacklistedPages[i].offlined[j].pageNumber = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].blackList[j].pageNumber;
240 fbDynamicBlacklistedPages[i].offlined[j].source = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].blackList[j].source;
241 }
242 }
243 }
244
245 *offset += sizeof(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07);
246
247 return NVOS_STATUS_SUCCESS;
248 }
249
deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS * busGetInfoV2,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)250 NV_STATUS deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *busGetInfoV2, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
251 {
252 if (!offset)
253 {
254 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
255 }
256
257 // If busGetInfoV2 and buffer are valid, then copy data and return the offset
258 if (busGetInfoV2 && buffer)
259 {
260 NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09 *bus_get_info_v2_v1C_09 = NULL;
261 NvU32 i = 0;
262
263 if ((bufferSize < *offset) ||
264 (bufferSize < (*offset + sizeof(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09))))
265 return NV_ERR_BUFFER_TOO_SMALL;
266
267 bus_get_info_v2_v1C_09 = (void*)(buffer + *offset);
268
269 busGetInfoV2->busInfoListSize = bus_get_info_v2_v1C_09->busInfoListSize;
270
271 if (bus_get_info_v2_v1C_09->busInfoListSize > NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09)
272 {
273 return NV_ERR_OUT_OF_RANGE;
274 }
275
276 for (i = 0; i < bus_get_info_v2_v1C_09->busInfoListSize; i++)
277 {
278 busGetInfoV2->busInfoList[i].index = bus_get_info_v2_v1C_09->busInfoList[i].index;
279 busGetInfoV2->busInfoList[i].data = bus_get_info_v2_v1C_09->busInfoList[i].data;
280 }
281 }
282
283 *offset += sizeof(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09);
284
285 return NVOS_STATUS_SUCCESS;
286 }
287
deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS * grSmIssueRateModifier,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)288 NV_STATUS deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *grSmIssueRateModifier, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
289 {
290 if (!offset)
291 {
292 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
293 }
294
295 // If pVSI and buffer are valid, then copy data and return the offset
296 if (grSmIssueRateModifier && buffer)
297 {
298 NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F *gr_get_sm_issue_rate_modifier_v1A_1F = NULL;
299
300 if ((bufferSize < *offset) ||
301 (bufferSize < (*offset + sizeof(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F))))
302 return NV_ERR_BUFFER_TOO_SMALL;
303
304 gr_get_sm_issue_rate_modifier_v1A_1F = (void*)(buffer + *offset);
305
306 grSmIssueRateModifier->grRouteInfo.flags = gr_get_sm_issue_rate_modifier_v1A_1F->grRouteInfo.flags;
307 grSmIssueRateModifier->grRouteInfo.route = gr_get_sm_issue_rate_modifier_v1A_1F->grRouteInfo.route;
308
309 grSmIssueRateModifier->imla0 = gr_get_sm_issue_rate_modifier_v1A_1F->imla0;
310 grSmIssueRateModifier->fmla16 = gr_get_sm_issue_rate_modifier_v1A_1F->fmla16;
311 grSmIssueRateModifier->dp = gr_get_sm_issue_rate_modifier_v1A_1F->dp;
312 grSmIssueRateModifier->fmla32 = gr_get_sm_issue_rate_modifier_v1A_1F->fmla32;
313 grSmIssueRateModifier->ffma = gr_get_sm_issue_rate_modifier_v1A_1F->ffma;
314 grSmIssueRateModifier->imla1 = gr_get_sm_issue_rate_modifier_v1A_1F->imla1;
315 grSmIssueRateModifier->imla2 = gr_get_sm_issue_rate_modifier_v1A_1F->imla2;
316 grSmIssueRateModifier->imla3 = gr_get_sm_issue_rate_modifier_v1A_1F->imla3;
317 grSmIssueRateModifier->imla4 = gr_get_sm_issue_rate_modifier_v1A_1F->imla4;
318 }
319
320 *offset += sizeof(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F);
321
322 return NVOS_STATUS_SUCCESS;
323 }
324
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS * grInfoParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)325 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS *grInfoParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
326 {
327 if (!offset)
328 {
329 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
330 }
331
332 if (grInfoParams && buffer)
333 {
334 NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07 *gr_info_v24_07 = NULL;
335 NvU32 i = 0, j = 0;
336
337 if ((bufferSize < *offset) ||
338 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07))))
339 return NV_ERR_BUFFER_TOO_SMALL;
340
341 gr_info_v24_07 = (void*)(buffer + *offset);
342
343 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
344 {
345 for (j = 0; j < NV0080_CTRL_GR_INFO_MAX_SIZE_24_07; j++)
346 {
347 grInfoParams->engineInfo[i].infoList[j].index = gr_info_v24_07->engineInfo[i].infoList[j].index;
348 grInfoParams->engineInfo[i].infoList[j].data = gr_info_v24_07->engineInfo[i].infoList[j].data;
349 }
350 }
351
352 }
353
354 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07);
355
356 return NVOS_STATUS_SUCCESS;
357 }
358
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS * smOrderParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)359 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS *smOrderParams, NvU8 *buffer,
360 NvU32 bufferSize, NvU32 *offset)
361 {
362 if (!offset)
363 {
364 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
365 }
366
367 if (smOrderParams && buffer)
368 {
369 NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01 *sm_order_v1F_01 = NULL;
370 NvU32 i = 0, j = 0;
371
372 if ((bufferSize < *offset) ||
373 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01))))
374 return NV_ERR_BUFFER_TOO_SMALL;
375
376 sm_order_v1F_01 = (void*)(buffer + *offset);
377
378 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
379 {
380 for (j = 0; j <NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03; j++)
381 {
382 smOrderParams->globalSmOrder[i].globalSmId[j].gpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].gpcId;
383 smOrderParams->globalSmOrder[i].globalSmId[j].localTpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].localTpcId;
384 smOrderParams->globalSmOrder[i].globalSmId[j].localSmId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].localSmId;
385 smOrderParams->globalSmOrder[i].globalSmId[j].globalTpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].globalTpcId;
386 smOrderParams->globalSmOrder[i].globalSmId[j].virtualGpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].virtualGpcId;
387 smOrderParams->globalSmOrder[i].globalSmId[j].migratableTpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].migratableTpcId;
388 }
389
390 smOrderParams->globalSmOrder[i].numSm = sm_order_v1F_01->globalSmOrder[i].numSm;
391 smOrderParams->globalSmOrder[i].numTpc = sm_order_v1F_01->globalSmOrder[i].numTpc;
392 }
393 }
394
395 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01);
396
397 return NVOS_STATUS_SUCCESS;
398 }
399
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS * ropInfoParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)400 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS *ropInfoParams, NvU8 *buffer,
401 NvU32 bufferSize, NvU32 *offset)
402 {
403 if (!offset)
404 {
405 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
406 }
407
408 if (ropInfoParams && buffer)
409 {
410 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05 *rop_info_v1B_05 = NULL;
411 NvU32 i = 0;
412
413 if ((bufferSize < *offset) ||
414 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05))))
415 return NV_ERR_BUFFER_TOO_SMALL;
416
417 rop_info_v1B_05 = (void*)(buffer + *offset);
418
419 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
420 {
421 ropInfoParams->engineRopInfo[i].ropUnitCount = rop_info_v1B_05->engineRopInfo[i].ropUnitCount;
422 ropInfoParams->engineRopInfo[i].ropOperationsFactor = rop_info_v1B_05->engineRopInfo[i].ropOperationsFactor;
423 ropInfoParams->engineRopInfo[i].ropOperationsCount = rop_info_v1B_05->engineRopInfo[i].ropOperationsCount;
424 }
425 }
426
427 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05);
428
429 return NVOS_STATUS_SUCCESS;
430 }
431
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS * ppcMaskParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)432 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS *ppcMaskParams, NvU8 *buffer,
433 NvU32 bufferSize, NvU32 *offset)
434 {
435 if (!offset)
436 {
437 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
438 }
439
440 if (ppcMaskParams && buffer)
441 {
442 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06 *ppc_mask_v1C_06 = NULL;
443 NvU32 i = 0, j = 0;
444
445 if ((bufferSize < *offset) ||
446 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06))))
447 return NV_ERR_BUFFER_TOO_SMALL;
448
449 ppc_mask_v1C_06 = (void*)(buffer + *offset);
450
451 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
452 {
453 for (j = 0; j < NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03; j++)
454 {
455 ppcMaskParams->enginePpcMasks[i].mask[j] = ppc_mask_v1C_06->enginePpcMasks[i].mask[j];
456 }
457 }
458 }
459
460 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06);
461
462 return NVOS_STATUS_SUCCESS;
463 }
464
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS * ctxBuffInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)465 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS* ctxBuffInfo, NvU8* buffer,
466 NvU32 bufferSize, NvU32* offset)
467 {
468 if (!offset)
469 {
470 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
471 }
472
473 if (ctxBuffInfo && buffer)
474 {
475 NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07* ctx_buff_info_v25_07 = NULL;
476 NvU32 i = 0, j = 0;
477
478 if ((bufferSize < *offset) ||
479 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07))))
480 return NV_ERR_BUFFER_TOO_SMALL;
481
482 ctx_buff_info_v25_07 = (void*)(buffer + *offset);
483
484 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
485 {
486 for (j = 0; j < NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07; j++)
487 {
488 ctxBuffInfo->engineContextBuffersInfo[i].engine[j].size = ctx_buff_info_v25_07->engineContextBuffersInfo[i].engine[j].size;
489 ctxBuffInfo->engineContextBuffersInfo[i].engine[j].alignment = ctx_buff_info_v25_07->engineContextBuffersInfo[i].engine[j].alignment;
490 }
491 }
492 }
493
494 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07);
495
496 return NVOS_STATUS_SUCCESS;
497 }
498
deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS * pParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)499 NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B
500 (
501 NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS* pParams,
502 NvU8 *buffer,
503 NvU32 bufferSize,
504 NvU32 *offset
505 )
506 {
507 if (offset == NULL)
508 {
509 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
510 }
511
512 if ((pParams != NULL) && (buffer != NULL))
513 {
514 NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B *pParams_v25_0B = NULL;
515
516 if ((bufferSize < *offset) ||
517 (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B))))
518 return NV_ERR_BUFFER_TOO_SMALL;
519
520 pParams_v25_0B = (void*)(buffer + *offset);
521
522 pParams->atomicsCaps = pParams_v25_0B->atomicsCaps;
523 }
524
525 *offset += sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B);
526
527 return NVOS_STATUS_SUCCESS;
528 }
529
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS * smIssueRateModifier,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)530 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *smIssueRateModifier,NvU8 *buffer,
531 NvU32 bufferSize, NvU32 *offset)
532 {
533 if (!offset)
534 {
535 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
536 }
537
538 if (smIssueRateModifier && buffer)
539 {
540 NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05 *rate_modifier_v1B_05 = NULL;
541 NvU32 i = 0;
542
543 if ((bufferSize < *offset) ||
544 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05))))
545 return NV_ERR_BUFFER_TOO_SMALL;
546
547 rate_modifier_v1B_05 = (void*)(buffer + *offset);
548
549 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
550 {
551 smIssueRateModifier->smIssueRateModifier[i].imla0 = rate_modifier_v1B_05->smIssueRateModifier[i].imla0;
552 smIssueRateModifier->smIssueRateModifier[i].imla1 = rate_modifier_v1B_05->smIssueRateModifier[i].imla1;
553 smIssueRateModifier->smIssueRateModifier[i].imla2 = rate_modifier_v1B_05->smIssueRateModifier[i].imla2;
554 smIssueRateModifier->smIssueRateModifier[i].imla3 = rate_modifier_v1B_05->smIssueRateModifier[i].imla3;
555 smIssueRateModifier->smIssueRateModifier[i].imla4 = rate_modifier_v1B_05->smIssueRateModifier[i].imla4;
556 smIssueRateModifier->smIssueRateModifier[i].fmla16 = rate_modifier_v1B_05->smIssueRateModifier[i].fmla16;
557 smIssueRateModifier->smIssueRateModifier[i].fmla32 = rate_modifier_v1B_05->smIssueRateModifier[i].fmla32;
558 smIssueRateModifier->smIssueRateModifier[i].ffma = rate_modifier_v1B_05->smIssueRateModifier[i].ffma;
559 smIssueRateModifier->smIssueRateModifier[i].dp = rate_modifier_v1B_05->smIssueRateModifier[i].dp;
560 }
561 }
562
563 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05);
564
565 return NVOS_STATUS_SUCCESS;
566 }
567
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS * floorsweepMaskParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)568 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS *floorsweepMaskParams, NvU8 *buffer,
569 NvU32 bufferSize, NvU32 *offset)
570 {
571 if (!offset)
572 {
573 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
574 }
575
576 if (floorsweepMaskParams && buffer)
577 {
578 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03 *floorsweep_mask_params_v1D_03 = NULL;
579 NvU32 i = 0, j = 0;
580
581 if ((bufferSize < *offset) ||
582 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03))))
583 return NV_ERR_BUFFER_TOO_SMALL;
584
585 floorsweep_mask_params_v1D_03 = (void*)(buffer + *offset);
586
587 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
588 {
589 for (j = 0; j < NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03; j++)
590 {
591 floorsweepMaskParams->floorsweepingMasks[i].tpcMask[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].tpcMask[j];
592 floorsweepMaskParams->floorsweepingMasks[i].tpcCount[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].tpcCount[j];
593 floorsweepMaskParams->floorsweepingMasks[i].numPesPerGpc[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].numPesPerGpc[j];
594 floorsweepMaskParams->floorsweepingMasks[i].mmuPerGpc[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].mmuPerGpc[j];
595 floorsweepMaskParams->floorsweepingMasks[i].zcullMask[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].zcullMask[j];
596 }
597
598 floorsweepMaskParams->floorsweepingMasks[i].gpcMask = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].gpcMask;
599 floorsweepMaskParams->floorsweepingMasks[i].physGpcMask = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].physGpcMask;
600
601 for (j = 0; j < NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03; j++)
602 {
603 floorsweepMaskParams->floorsweepingMasks[i].tpcToPesMap[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].tpcToPesMap[j];
604 }
605 }
606 }
607
608 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03);
609
610 return NVOS_STATUS_SUCCESS;
611
612 }
613
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS * zcullInfoParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)614 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS *zcullInfoParams, NvU8 *buffer,
615 NvU32 bufferSize, NvU32 *offset)
616 {
617 if (!offset)
618 {
619 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
620 }
621
622 if (zcullInfoParams && buffer)
623 {
624 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05 *zcull_info_v1B_05 = NULL;
625 NvU32 i = 0;
626
627 if ((bufferSize < *offset) ||
628 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05))))
629 return NV_ERR_BUFFER_TOO_SMALL;
630
631 zcull_info_v1B_05 = (void*)(buffer + *offset);
632
633 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
634 {
635 zcullInfoParams->engineZcullInfo[i].widthAlignPixels = zcull_info_v1B_05->engineZcullInfo[i].widthAlignPixels;
636 zcullInfoParams->engineZcullInfo[i].heightAlignPixels = zcull_info_v1B_05->engineZcullInfo[i].heightAlignPixels;
637 zcullInfoParams->engineZcullInfo[i].pixelSquaresByAliquots = zcull_info_v1B_05->engineZcullInfo[i].pixelSquaresByAliquots;
638 zcullInfoParams->engineZcullInfo[i].aliquotTotal = zcull_info_v1B_05->engineZcullInfo[i].aliquotTotal;
639 zcullInfoParams->engineZcullInfo[i].zcullRegionByteMultiplier = zcull_info_v1B_05->engineZcullInfo[i].zcullRegionByteMultiplier;
640 zcullInfoParams->engineZcullInfo[i].zcullRegionHeaderSize = zcull_info_v1B_05->engineZcullInfo[i].zcullRegionHeaderSize;
641 zcullInfoParams->engineZcullInfo[i].zcullSubregionHeaderSize = zcull_info_v1B_05->engineZcullInfo[i].zcullSubregionHeaderSize;
642 zcullInfoParams->engineZcullInfo[i].subregionCount = zcull_info_v1B_05->engineZcullInfo[i].subregionCount;
643 zcullInfoParams->engineZcullInfo[i].subregionWidthAlignPixels = zcull_info_v1B_05->engineZcullInfo[i].subregionWidthAlignPixels;
644 zcullInfoParams->engineZcullInfo[i].subregionHeightAlignPixels = zcull_info_v1B_05->engineZcullInfo[i].subregionHeightAlignPixels;
645 }
646 }
647
648 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05);
649
650 return NVOS_STATUS_SUCCESS;
651 }
652
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS * fecsRecordSize,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)653 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS *fecsRecordSize, NvU8 *buffer,
654 NvU32 bufferSize, NvU32 *offset)
655 {
656 if (!offset)
657 {
658 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
659 }
660
661 if (fecsRecordSize && buffer)
662 {
663 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05 *fecs_record_size_v1B_05 = NULL;
664 NvU32 i = 0;
665
666 if ((bufferSize < *offset) ||
667 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05))))
668 return NV_ERR_BUFFER_TOO_SMALL;
669
670 fecs_record_size_v1B_05 = (void*)(buffer + *offset);
671
672 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
673 {
674 fecsRecordSize->fecsRecordSize[i].fecsRecordSize = fecs_record_size_v1B_05->fecsRecordSize[i].fecsRecordSize;
675 }
676 }
677
678 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05);
679
680 return NVOS_STATUS_SUCCESS;
681 }
682
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS * fecsTraceDefines,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)683 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS *fecsTraceDefines, NvU8 *buffer,
684 NvU32 bufferSize, NvU32 *offset)
685 {
686 if (!offset)
687 {
688 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
689 }
690
691 if (fecsTraceDefines && buffer)
692 {
693 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04 *fecs_trace_defines_v1D_04 = NULL;
694 NvU32 i = 0;
695
696 if ((bufferSize < *offset) ||
697 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04))))
698 return NV_ERR_BUFFER_TOO_SMALL;
699
700 fecs_trace_defines_v1D_04 = (void*)(buffer + *offset);
701
702 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
703 {
704 fecsTraceDefines->fecsTraceDefines[i].fecsRecordSize = fecs_trace_defines_v1D_04->fecsTraceDefines[i].fecsRecordSize;
705 fecsTraceDefines->fecsTraceDefines[i].timestampHiTagMask = fecs_trace_defines_v1D_04->fecsTraceDefines[i].timestampHiTagMask;
706 fecsTraceDefines->fecsTraceDefines[i].timestampHiTagShift = fecs_trace_defines_v1D_04->fecsTraceDefines[i].timestampHiTagShift;
707 fecsTraceDefines->fecsTraceDefines[i].timestampVMask = fecs_trace_defines_v1D_04->fecsTraceDefines[i].timestampVMask;
708 fecsTraceDefines->fecsTraceDefines[i].numLowerBitsZeroShift = fecs_trace_defines_v1D_04->fecsTraceDefines[i].numLowerBitsZeroShift;
709 }
710 }
711
712 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04);
713
714 return NVOS_STATUS_SUCCESS;
715 }
716
deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS * grPdbPropertiesParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)717 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS *grPdbPropertiesParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
718 {
719 if (!offset)
720 {
721 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
722 }
723
724 if (grPdbPropertiesParams && buffer)
725 {
726 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02 *gr_pdb_properties_v1E_02 = NULL;
727 NvU32 i = 0;
728
729 if ((bufferSize < *offset) ||
730 (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02))))
731 return NV_ERR_BUFFER_TOO_SMALL;
732
733 gr_pdb_properties_v1E_02 = (void*)(buffer + *offset);
734
735 for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++)
736 {
737 grPdbPropertiesParams->pdbTable[i].bPerSubCtxheaderSupported = gr_pdb_properties_v1E_02->pdbTable[i].bPerSubCtxheaderSupported;
738 }
739
740 }
741
742 *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02);
743
744 return NVOS_STATUS_SUCCESS;
745 }
746
deserialize_VGPU_STATIC_DATA_v25_0E(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)747 NV_STATUS deserialize_VGPU_STATIC_DATA_v25_0E(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
748 {
749 if (!offset)
750 {
751 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
752 }
753
754 // If pVSI and buffer are valid, then copy data and return the offset
755 if (pVSI && buffer)
756 {
757 VGPU_STATIC_DATA_v25_0E *vgpu_static_data_v25_0E = NULL;
758 NvU32 i;
759
760 if ((bufferSize < *offset) ||
761 (bufferSize < (*offset + sizeof(VGPU_STATIC_DATA_v25_0E))))
762 return NV_ERR_BUFFER_TOO_SMALL;
763
764 vgpu_static_data_v25_0E = (void*)(buffer + *offset);
765
766 pVSI->fbTaxLength = vgpu_static_data_v25_0E->fbTaxLength;
767 pVSI->fbLength = vgpu_static_data_v25_0E->fbLength;
768 pVSI->fbBusWidth = vgpu_static_data_v25_0E->fbBusWidth;
769 pVSI->fbioMask = vgpu_static_data_v25_0E->fbioMask;
770 pVSI->fbpMask = vgpu_static_data_v25_0E->fbpMask;
771 pVSI->ltcMask = vgpu_static_data_v25_0E->ltcMask;
772 pVSI->ltsCount = vgpu_static_data_v25_0E->ltsCount;
773 pVSI->subProcessIsolation = vgpu_static_data_v25_0E->subProcessIsolation;
774 pVSI->engineList = vgpu_static_data_v25_0E->engineList;
775 pVSI->sizeL2Cache = vgpu_static_data_v25_0E->sizeL2Cache;
776 pVSI->poisonFuseEnabled = vgpu_static_data_v25_0E->poisonFuseEnabled;
777 pVSI->guestManagedHwAlloc = vgpu_static_data_v25_0E->guestManagedHwAlloc;
778
779 // gpuname
780 portMemCopy(pVSI->adapterName, sizeof(pVSI->adapterName),
781 vgpu_static_data_v25_0E->gpuName.adapterName, sizeof(pVSI->adapterName));
782 portMemCopy(pVSI->adapterName_Unicode, sizeof(pVSI->adapterName_Unicode),
783 vgpu_static_data_v25_0E->gpuName.adapterName_Unicode, sizeof(pVSI->adapterName_Unicode));
784 portMemCopy(pVSI->shortGpuNameString, sizeof(pVSI->shortGpuNameString),
785 vgpu_static_data_v25_0E->gpuName.shortGpuNameString, sizeof(pVSI->adapterName));
786
787 pVSI->bSplitVasBetweenServerClientRm = vgpu_static_data_v25_0E->bSplitVasBetweenServerClientRm;
788 pVSI->maxSupportedPageSize = vgpu_static_data_v25_0E->maxSupportedPageSize;
789 pVSI->bFlaSupported = vgpu_static_data_v25_0E->bFlaSupported;
790 pVSI->bPerRunlistChannelRamEnabled = vgpu_static_data_v25_0E->bPerRunlistChannelRamEnabled;
791 pVSI->bAtsSupported = vgpu_static_data_v25_0E->bAtsSupported;
792
793 pVSI->bPerSubCtxheaderSupported = vgpu_static_data_v25_0E->bPerSubCtxheaderSupported;
794 pVSI->bC2CLinkUp = vgpu_static_data_v25_0E->bC2CLinkUp;
795 pVSI->bLocalEgmEnabled = vgpu_static_data_v25_0E->bLocalEgmEnabled;
796 pVSI->localEgmPeerId = vgpu_static_data_v25_0E->localEgmPeerId;
797 pVSI->bSelfHostedMode = vgpu_static_data_v25_0E->bSelfHostedMode;
798
799 pVSI->ceFaultMethodBufferDepth = vgpu_static_data_v25_0E->ceFaultMethodBufferDepth;
800 pVSI->pcieGpuLinkCaps = vgpu_static_data_v25_0E->pcieGpuLinkCaps;
801
802 portMemCopy(pVSI->grCapsBits, sizeof(pVSI->grCapsBits),
803 vgpu_static_data_v25_0E->grCapsBits, sizeof(vgpu_static_data_v25_0E->grCapsBits));
804
805 for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E; i++)
806 {
807 pVSI->gfxpBufferSize[i] = vgpu_static_data_v25_0E->gfxpBufferSize[i];
808 pVSI->gfxpBufferAlignment[i] = vgpu_static_data_v25_0E->gfxpBufferAlignment[i];
809 }
810
811 for (i = 0; i < RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E; i++)
812 {
813 pVSI->grBufferSize[i] = vgpu_static_data_v25_0E->grBufferSize[i];
814 }
815
816 portMemCopy(pVSI->jpegCaps, sizeof(pVSI->jpegCaps),
817 vgpu_static_data_v25_0E->jpegCaps, sizeof(vgpu_static_data_v25_0E->jpegCaps));
818 }
819
820 *offset += sizeof(VGPU_STATIC_DATA_v25_0E);
821
822 return NVOS_STATUS_SUCCESS;
823 }
824
deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS * vgxSystemInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)825 NV_STATUS deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *vgxSystemInfo,
826 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
827 {
828 if (!offset)
829 {
830 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
831 }
832
833 // If vgxSystemInfo and buffer are valid, then copy data and return the offset
834 if (vgxSystemInfo && buffer)
835 {
836 NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00 *vgx_system_info_v03_00 = NULL;
837
838 if ((bufferSize < *offset) ||
839 (bufferSize < (*offset + sizeof(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00))))
840 return NV_ERR_BUFFER_TOO_SMALL;
841
842 vgx_system_info_v03_00 = (void*)(buffer + *offset);
843
844 portMemCopy(vgxSystemInfo->szHostDriverVersionBuffer,
845 sizeof(vgxSystemInfo->szHostDriverVersionBuffer),
846 vgx_system_info_v03_00->szHostDriverVersionBuffer,
847 sizeof(vgx_system_info_v03_00->szHostDriverVersionBuffer));
848 portMemCopy(vgxSystemInfo->szHostVersionBuffer,
849 sizeof(vgxSystemInfo->szHostVersionBuffer),
850 vgx_system_info_v03_00->szHostVersionBuffer,
851 sizeof(vgx_system_info_v03_00->szHostVersionBuffer));
852 portMemCopy(vgxSystemInfo->szHostTitleBuffer,
853 sizeof(vgxSystemInfo->szHostTitleBuffer),
854 vgx_system_info_v03_00->szHostTitleBuffer,
855 sizeof(vgx_system_info_v03_00->szHostTitleBuffer));
856
857 portMemCopy(vgxSystemInfo->szPluginTitleBuffer,
858 sizeof(vgxSystemInfo->szPluginTitleBuffer),
859 vgx_system_info_v03_00->szPluginTitleBuffer,
860 sizeof(vgx_system_info_v03_00->szPluginTitleBuffer));
861
862 portMemCopy(vgxSystemInfo->szHostUnameBuffer,
863 sizeof(vgxSystemInfo->szHostUnameBuffer),
864 vgx_system_info_v03_00->szHostUnameBuffer,
865 sizeof(vgx_system_info_v03_00->szHostUnameBuffer));
866
867 vgxSystemInfo->iHostChangelistNumber = vgx_system_info_v03_00->iHostChangelistNumber;
868 vgxSystemInfo->iPluginChangelistNumber = vgx_system_info_v03_00->iPluginChangelistNumber;
869 }
870
871 *offset += sizeof(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00);
872
873 return NVOS_STATUS_SUCCESS;
874 }
875
deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS * gidInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)876 NV_STATUS deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS *gidInfo,
877 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
878 {
879 if (!offset)
880 {
881 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
882 }
883
884 // If gidInfo and buffer are valid, then copy data and return the offset
885 if (gidInfo && buffer)
886 {
887 NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00 *gid_info_v03_00 = NULL;
888
889 if ((bufferSize < *offset) ||
890 (bufferSize < (*offset + sizeof(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00))))
891 return NV_ERR_BUFFER_TOO_SMALL;
892
893 gid_info_v03_00 = (void*)(buffer + *offset);
894
895 gidInfo->index = gid_info_v03_00->index;
896 gidInfo->flags = gid_info_v03_00->flags;
897 gidInfo->length = gid_info_v03_00->length;
898 portMemCopy(gidInfo->data, sizeof(gidInfo->data), gid_info_v03_00->data, sizeof(gid_info_v03_00->data));
899 }
900
901 *offset += sizeof(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00);
902
903 return NVOS_STATUS_SUCCESS;
904 }
905
deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v03_00(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS * skuInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)906 NV_STATUS deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v03_00(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *skuInfo,
907 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
908 {
909 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
910 }
911
deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS * skuInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)912 NV_STATUS deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *skuInfo,
913 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
914 {
915 if (!offset)
916 {
917 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
918 }
919
920 // If skuInfo and buffer are valid, then copy data and return the offset
921 if (skuInfo && buffer)
922 {
923 NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E *sku_info_v25_0E = NULL;
924
925 if ((bufferSize < *offset) ||
926 (bufferSize < (*offset + sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E))))
927 return NV_ERR_BUFFER_TOO_SMALL;
928
929 sku_info_v25_0E = (void*)(buffer + *offset);
930
931 skuInfo->BoardID = sku_info_v25_0E->BoardID;
932 skuInfo->skuConfigVersion = sku_info_v25_0E->skuConfigVersion;
933 portMemCopy(skuInfo->chipSKU, sizeof(skuInfo->chipSKU),
934 sku_info_v25_0E->chipSKU, sizeof(sku_info_v25_0E->chipSKU));
935 portMemCopy(skuInfo->chipSKUMod, sizeof(skuInfo->chipSKUMod),
936 sku_info_v25_0E->chipSKUMod, sizeof(sku_info_v25_0E->chipSKUMod));
937 portMemCopy(skuInfo->project, sizeof(skuInfo->project),
938 sku_info_v25_0E->project, sizeof(sku_info_v25_0E->project));
939 portMemCopy(skuInfo->projectSKU, sizeof(skuInfo->projectSKU),
940 sku_info_v25_0E->projectSKU, sizeof(sku_info_v25_0E->projectSKU));
941 portMemCopy(skuInfo->CDP, sizeof(skuInfo->CDP),
942 sku_info_v25_0E->CDP, sizeof(sku_info_v25_0E->CDP));
943 portMemCopy(skuInfo->projectSKUMod, sizeof(skuInfo->projectSKUMod),
944 sku_info_v25_0E->projectSKUMod, sizeof(sku_info_v25_0E->projectSKUMod));
945 skuInfo->businessCycle = sku_info_v25_0E->businessCycle;
946 }
947
948 *offset += sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E);
949
950 return NVOS_STATUS_SUCCESS;
951 }
952
deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS * fbRegionInfoParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)953 NV_STATUS deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *fbRegionInfoParams,
954 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
955 {
956 if (!offset)
957 {
958 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
959 }
960
961 // If fbRegionInfoParams and buffer are valid, then copy data and return the offset
962 if (fbRegionInfoParams && buffer)
963 {
964 NvU32 i;
965 NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00 *fbRegionInfoParams_v03_00 = NULL;
966
967 if ((bufferSize < *offset) ||
968 (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00))))
969 return NV_ERR_BUFFER_TOO_SMALL;
970
971 fbRegionInfoParams_v03_00 = (void*)(buffer + *offset);
972
973 fbRegionInfoParams->numFBRegions = fbRegionInfoParams_v03_00->numFBRegions;
974
975 for(i = 0; i < NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES; i++)
976 {
977 fbRegionInfoParams->fbRegion[i].base = fbRegionInfoParams_v03_00->fbRegion[i].base;
978 fbRegionInfoParams->fbRegion[i].limit = fbRegionInfoParams_v03_00->fbRegion[i].limit;
979 fbRegionInfoParams->fbRegion[i].reserved = fbRegionInfoParams_v03_00->fbRegion[i].reserved;
980 fbRegionInfoParams->fbRegion[i].performance = fbRegionInfoParams_v03_00->fbRegion[i].performance;
981 fbRegionInfoParams->fbRegion[i].supportCompressed = fbRegionInfoParams_v03_00->fbRegion[i].supportCompressed;
982 fbRegionInfoParams->fbRegion[i].supportISO = fbRegionInfoParams_v03_00->fbRegion[i].supportISO;
983 fbRegionInfoParams->fbRegion[i].bProtected = fbRegionInfoParams_v03_00->fbRegion[i].bProtected;
984 portMemCopy(&fbRegionInfoParams->fbRegion[i].blackList,
985 sizeof(fbRegionInfoParams->fbRegion[i].blackList),
986 &fbRegionInfoParams_v03_00->fbRegion[i].blackList,
987 sizeof(fbRegionInfoParams_v03_00->fbRegion[i].blackList));
988 }
989 }
990
991 *offset += sizeof(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00);
992
993 return NVOS_STATUS_SUCCESS;
994 }
995
deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS * ciProfiles,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)996 NV_STATUS deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *ciProfiles,
997 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
998 {
999 if (!offset)
1000 {
1001 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1002 }
1003
1004 // If ciProfiles and buffer are valid, then copy data and return the offset
1005 if (ciProfiles && buffer)
1006 {
1007 NvU32 i;
1008 NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04 *ciProfiles_v20_04 = NULL;
1009
1010 if ((bufferSize < *offset) ||
1011 (bufferSize < (*offset + sizeof(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04))))
1012 return NV_ERR_BUFFER_TOO_SMALL;
1013
1014 ciProfiles_v20_04 = (void*)(buffer + *offset);
1015
1016 NV_ASSERT(ciProfiles_v20_04->profileCount <= NV_ARRAY_ELEMENTS(ciProfiles->profiles));
1017
1018 ciProfiles->profileCount = ciProfiles_v20_04->profileCount;
1019 for (i = 0; i < ciProfiles->profileCount; i++)
1020 {
1021 ciProfiles->profiles[i].gfxGpcCount = ciProfiles_v20_04->profiles[i].gfxGpcCount;
1022 ciProfiles->profiles[i].computeSize = ciProfiles_v20_04->profiles[i].computeSize;
1023 ciProfiles->profiles[i].gpcCount = ciProfiles_v20_04->profiles[i].gpcCount;
1024 ciProfiles->profiles[i].veidCount = ciProfiles_v20_04->profiles[i].veidCount;
1025 ciProfiles->profiles[i].smCount = ciProfiles_v20_04->profiles[i].smCount;
1026 }
1027 }
1028
1029 *offset += sizeof(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04);
1030
1031 return NVOS_STATUS_SUCCESS;
1032 }
1033
deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v18_07(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS * execPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1034 NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v18_07(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *execPartitionInfo,
1035 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1036 {
1037 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1038 }
1039
deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v21_04(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS * execPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1040 NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v21_04(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *execPartitionInfo,
1041 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1042 {
1043 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1044 }
1045
deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v21_09(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS * execPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1046 NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v21_09(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *execPartitionInfo,
1047 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1048 {
1049 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1050 }
1051
deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS * execPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1052 NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *execPartitionInfo,
1053 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1054 {
1055 if (!offset)
1056 {
1057 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1058 }
1059
1060 // If execPartitionInfo and buffer are valid, then copy data and return the offset
1061 if (execPartitionInfo && buffer)
1062 {
1063 NvU32 i;
1064 NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05 *execPartitionInfo_v24_05 = NULL;
1065
1066 if ((bufferSize < *offset) ||
1067 (bufferSize < (*offset + sizeof(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05))))
1068 return NV_ERR_BUFFER_TOO_SMALL;
1069
1070 execPartitionInfo_v24_05 = (void*)(buffer + *offset);
1071
1072 execPartitionInfo->execPartCount = execPartitionInfo_v24_05->execPartCount;
1073
1074 for (i = 0; i < execPartitionInfo->execPartCount; i++)
1075 {
1076 NVC637_CTRL_EXEC_PARTITIONS_INFO *dst = &(execPartitionInfo->execPartInfo[i]);
1077
1078 execPartitionInfo->execPartId[i] = execPartitionInfo_v24_05->execPartId[i];
1079
1080 dst->gpcCount = execPartitionInfo_v24_05->execPartInfo[i].gpcCount;
1081 dst->gfxGpcCount = execPartitionInfo_v24_05->execPartInfo[i].gfxGpcCount;
1082 dst->veidCount = execPartitionInfo_v24_05->execPartInfo[i].veidCount;
1083 dst->ceCount = execPartitionInfo_v24_05->execPartInfo[i].ceCount;
1084 dst->nvEncCount = execPartitionInfo_v24_05->execPartInfo[i].nvEncCount;
1085 dst->nvDecCount = execPartitionInfo_v24_05->execPartInfo[i].nvDecCount;
1086 dst->nvJpgCount = execPartitionInfo_v24_05->execPartInfo[i].nvJpgCount;
1087 dst->ofaCount = execPartitionInfo_v24_05->execPartInfo[i].ofaCount;
1088 dst->sharedEngFlag = execPartitionInfo_v24_05->execPartInfo[i].sharedEngFlag;
1089 dst->smCount = execPartitionInfo_v24_05->execPartInfo[i].smCount;
1090 dst->spanStart = execPartitionInfo_v24_05->execPartInfo[i].spanStart;
1091 dst->computeSize = execPartitionInfo_v24_05->execPartInfo[i].computeSize;
1092 }
1093 }
1094
1095 *offset += sizeof(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05);
1096
1097 return NVOS_STATUS_SUCCESS;
1098 }
1099
deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS * zbcTableSizes,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1100 NV_STATUS deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *zbcTableSizes,
1101 NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1102 {
1103 if (!offset)
1104 {
1105 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1106 }
1107
1108 // If zbcTableSizes and buffer are valid, then copy data and return the offset
1109 if (zbcTableSizes && buffer)
1110 {
1111 NvU32 i;
1112 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07 *zbcTableSizes_v1A_07 = NULL;
1113
1114 if ((bufferSize < *offset) ||
1115 (bufferSize < (*offset + sizeof(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07))))
1116 return NV_ERR_BUFFER_TOO_SMALL;
1117
1118 zbcTableSizes_v1A_07 = (void*)(buffer + *offset);
1119
1120 for (i = 0; i < NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07; i++) {
1121 zbcTableSizes[i].indexStart = zbcTableSizes_v1A_07[i].indexStart;
1122 zbcTableSizes[i].indexEnd = zbcTableSizes_v1A_07[i].indexEnd;
1123 }
1124 }
1125
1126 *offset += sizeof(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07) * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07;
1127
1128 return NVOS_STATUS_SUCCESS;
1129 }
1130
deserialize_GPU_PARTITION_INFO_v12_01(GPU_PARTITION_INFO * gpuPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1131 NV_STATUS deserialize_GPU_PARTITION_INFO_v12_01(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1132 {
1133 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1134 }
1135
deserialize_GPU_PARTITION_INFO_v18_03(GPU_PARTITION_INFO * gpuPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1136 NV_STATUS deserialize_GPU_PARTITION_INFO_v18_03(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1137 {
1138 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1139 }
1140
deserialize_GPU_PARTITION_INFO_v20_01(GPU_PARTITION_INFO * gpuPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1141 NV_STATUS deserialize_GPU_PARTITION_INFO_v20_01(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1142 {
1143 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1144 }
1145
deserialize_GPU_PARTITION_INFO_v21_09(GPU_PARTITION_INFO * gpuPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1146 NV_STATUS deserialize_GPU_PARTITION_INFO_v21_09(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1147 {
1148 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1149 }
1150
deserialize_GPU_PARTITION_INFO_v24_05(GPU_PARTITION_INFO * gpuPartitionInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1151 NV_STATUS deserialize_GPU_PARTITION_INFO_v24_05(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1152 {
1153 if (!offset)
1154 {
1155 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1156 }
1157
1158 // If gpuPartitionInfo and buffer are valid, then copy data and return the offset
1159 if (gpuPartitionInfo && buffer)
1160 {
1161 NvU32 i;
1162 GPU_PARTITION_INFO_v24_05 *gpu_partition_info_v24_05 = NULL;
1163
1164 if ((bufferSize < *offset) ||
1165 (bufferSize < (*offset + sizeof(GPU_PARTITION_INFO_v24_05))))
1166 return NV_ERR_BUFFER_TOO_SMALL;
1167
1168 gpu_partition_info_v24_05 = (void*)(buffer + *offset);
1169
1170 // GPU PARTITION INFO
1171 gpuPartitionInfo->swizzId = gpu_partition_info_v24_05->swizzId;
1172 gpuPartitionInfo->grEngCount = gpu_partition_info_v24_05->grEngCount;
1173 gpuPartitionInfo->veidCount = gpu_partition_info_v24_05->veidCount;
1174 gpuPartitionInfo->ceCount = gpu_partition_info_v24_05->ceCount;
1175 gpuPartitionInfo->gpcCount = gpu_partition_info_v24_05->gpcCount;
1176 gpuPartitionInfo->virtualGpcCount = gpu_partition_info_v24_05->virtualGpcCount;
1177 gpuPartitionInfo->gfxGpcCount = gpu_partition_info_v24_05->gfxGpcCount;
1178 gpuPartitionInfo->nvDecCount = gpu_partition_info_v24_05->nvDecCount;
1179 gpuPartitionInfo->nvEncCount = gpu_partition_info_v24_05->nvEncCount;
1180 gpuPartitionInfo->nvJpgCount = gpu_partition_info_v24_05->nvJpgCount;
1181 gpuPartitionInfo->partitionFlag = gpu_partition_info_v24_05->partitionFlag;
1182 gpuPartitionInfo->smCount = gpu_partition_info_v24_05->smCount;
1183 gpuPartitionInfo->nvOfaCount = gpu_partition_info_v24_05->nvOfaCount;
1184 gpuPartitionInfo->memSize = gpu_partition_info_v24_05->memSize;
1185 gpuPartitionInfo->bValid = gpu_partition_info_v24_05->bValid;
1186 gpuPartitionInfo->span.lo = gpu_partition_info_v24_05->span.lo;
1187 gpuPartitionInfo->span.hi = gpu_partition_info_v24_05->span.hi;
1188 gpuPartitionInfo->validCTSIdMask = gpu_partition_info_v24_05->validCTSIdMask;
1189
1190 for (i = 0; i < gpuPartitionInfo->grEngCount; i++)
1191 {
1192 gpuPartitionInfo->gpcsPerGr[i] = gpu_partition_info_v24_05->gpcsPerGr[i];
1193 gpuPartitionInfo->veidsPerGr[i] = gpu_partition_info_v24_05->veidsPerGr[i];
1194 gpuPartitionInfo->virtualGpcsPerGr[i] = gpu_partition_info_v24_05->virtualGpcsPerGr[i];
1195 gpuPartitionInfo->gfxGpcPerGr[i] = gpu_partition_info_v24_05->gfxGpcPerGr[i];
1196 }
1197 }
1198 *offset += sizeof(GPU_PARTITION_INFO_v24_05);
1199
1200 return NVOS_STATUS_SUCCESS;
1201 }
1202
1203 // NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS deserialization is used starting with v24_06
deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v15_01(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS * eccStatusParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1204 NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v15_01(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1205 {
1206 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1207 }
1208
deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v1A_04(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS * eccStatusParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1209 NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v1A_04(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1210 {
1211 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1212 }
1213
deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v1C_09(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS * eccStatusParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1214 NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v1C_09(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1215 {
1216 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1217 }
1218
deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v20_03(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS * eccStatusParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1219 NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v20_03(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1220 {
1221 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1222 }
1223
deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS * eccStatusParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1224 NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1225 {
1226 if (!offset)
1227 {
1228 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1229 }
1230
1231 // If eccStatusParams and buffer are valid, then copy data and return the offset
1232 if (eccStatusParams && buffer)
1233 {
1234 NvU32 i;
1235 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06 *eccStatusParams_v24_06 = NULL;
1236
1237 if ((bufferSize < *offset) ||
1238 (bufferSize < (*offset + sizeof(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06))))
1239 return NV_ERR_BUFFER_TOO_SMALL;
1240
1241 eccStatusParams_v24_06 = (void*)(buffer + *offset);
1242
1243 eccStatusParams->bFatalPoisonError = eccStatusParams_v24_06->bFatalPoisonError;
1244
1245 for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06; i++) {
1246 eccStatusParams->units[i].enabled = eccStatusParams_v24_06->units[i].enabled;
1247 eccStatusParams->units[i].scrubComplete = eccStatusParams_v24_06->units[i].scrubComplete;
1248 eccStatusParams->units[i].supported = eccStatusParams_v24_06->units[i].supported;
1249 eccStatusParams->units[i].dbe.count = eccStatusParams_v24_06->units[i].dbe.count;
1250 eccStatusParams->units[i].dbeNonResettable.count = eccStatusParams_v24_06->units[i].dbeNonResettable.count;
1251 eccStatusParams->units[i].sbe.count = eccStatusParams_v24_06->units[i].sbe.count;
1252 eccStatusParams->units[i].sbeNonResettable.count = eccStatusParams_v24_06->units[i].sbeNonResettable.count;
1253 }
1254 }
1255 *offset += sizeof(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06);
1256
1257 return NVOS_STATUS_SUCCESS;
1258 }
1259
deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS * grZcullInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1260 NV_STATUS deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *grZcullInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1261 {
1262 if (!offset)
1263 {
1264 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1265 }
1266
1267 // If grZcullInfo and buffer are valid, then copy data and return the offset
1268 if (grZcullInfo && buffer)
1269 {
1270 NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01 *get_zcull_info_params_12_01 = NULL;
1271
1272 if ((bufferSize < *offset) ||
1273 (bufferSize < (*offset + sizeof(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01))))
1274 return NV_ERR_BUFFER_TOO_SMALL;
1275
1276 get_zcull_info_params_12_01 = (void*)(buffer + *offset);
1277
1278 grZcullInfo->widthAlignPixels = get_zcull_info_params_12_01->widthAlignPixels;
1279 grZcullInfo->heightAlignPixels = get_zcull_info_params_12_01->heightAlignPixels;
1280 grZcullInfo->pixelSquaresByAliquots = get_zcull_info_params_12_01->pixelSquaresByAliquots;
1281 grZcullInfo->aliquotTotal = get_zcull_info_params_12_01->aliquotTotal;
1282 grZcullInfo->zcullRegionByteMultiplier = get_zcull_info_params_12_01->zcullRegionByteMultiplier;
1283 grZcullInfo->zcullRegionHeaderSize = get_zcull_info_params_12_01->zcullRegionHeaderSize;
1284 grZcullInfo->zcullSubregionHeaderSize = get_zcull_info_params_12_01->zcullSubregionHeaderSize;
1285 grZcullInfo->subregionCount = get_zcull_info_params_12_01->subregionCount;
1286 grZcullInfo->subregionWidthAlignPixels = get_zcull_info_params_12_01->subregionWidthAlignPixels;
1287 grZcullInfo->subregionHeightAlignPixels = get_zcull_info_params_12_01->subregionHeightAlignPixels;
1288
1289 }
1290
1291 *offset += sizeof(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01);
1292
1293 return NVOS_STATUS_SUCCESS;
1294 }
1295
deserialize_VGPU_STATIC_PROPERTIES_v1B_01(VGPU_STATIC_PROPERTIES * vgpuStaticProperties,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1296 NV_STATUS deserialize_VGPU_STATIC_PROPERTIES_v1B_01(VGPU_STATIC_PROPERTIES *vgpuStaticProperties, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1297 {
1298 if (!offset)
1299 {
1300 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1301 }
1302
1303 // If vgpuStaticProperties and buffer are valid, then copy data and return the offset
1304 if (vgpuStaticProperties && buffer)
1305 {
1306 VGPU_STATIC_PROPERTIES_v1B_01 *vgpu_static_properties_v1B_01 = NULL;
1307
1308 if ((bufferSize < *offset) ||
1309 (bufferSize < (*offset + sizeof(VGPU_STATIC_PROPERTIES_v1B_01))))
1310 return NV_ERR_BUFFER_TOO_SMALL;
1311
1312 vgpu_static_properties_v1B_01 = (void*)(buffer + *offset);
1313
1314 // encSessionStatsReportingState
1315 vgpuStaticProperties->encSessionStatsReportingState = vgpu_static_properties_v1B_01->encSessionStatsReportingState;
1316 vgpuStaticProperties->bProfilingTracingEnabled = vgpu_static_properties_v1B_01->bProfilingTracingEnabled;
1317 vgpuStaticProperties->bDebuggingEnabled = vgpu_static_properties_v1B_01->bDebuggingEnabled;
1318 vgpuStaticProperties->channelCount = vgpu_static_properties_v1B_01->channelCount;
1319 vgpuStaticProperties->bPblObjNotPresent = vgpu_static_properties_v1B_01->bPblObjNotPresent;
1320 }
1321
1322 *offset += sizeof(VGPU_STATIC_PROPERTIES_v1B_01);
1323
1324 return NVOS_STATUS_SUCCESS;
1325 }
1326
deserialize_VGPU_BSP_GET_CAPS_v25_00(VGPU_BSP_GET_CAPS * vgpuBspCaps,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1327 NV_STATUS deserialize_VGPU_BSP_GET_CAPS_v25_00(VGPU_BSP_GET_CAPS *vgpuBspCaps, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1328 {
1329 if (!offset)
1330 {
1331 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1332 }
1333
1334 // If vgpuBspCaps and buffer are valid, then copy data and return the offset
1335 if (vgpuBspCaps && buffer)
1336 {
1337 VGPU_BSP_GET_CAPS_v25_00 *vgpu_bsp_get_caps_v25_00 = NULL;
1338 NvU32 i;
1339
1340 if ((bufferSize < *offset) ||
1341 (bufferSize < (*offset + sizeof(VGPU_BSP_GET_CAPS_v25_00))))
1342 return NV_ERR_BUFFER_TOO_SMALL;
1343
1344 vgpu_bsp_get_caps_v25_00 = (void*)(buffer + *offset);
1345
1346 for (i = 0; i < MAX_NVDEC_ENGINES_V25_00; i++)
1347 {
1348 portMemCopy(&(*vgpuBspCaps)[i].capsTbl, NV0080_CTRL_BSP_CAPS_TBL_SIZE,
1349 &vgpu_bsp_get_caps_v25_00->bspCaps[i].capsTblData, sizeof(vgpu_bsp_get_caps_v25_00->bspCaps[i].capsTblData));
1350 }
1351 }
1352
1353 *offset += sizeof(VGPU_BSP_GET_CAPS_v25_00);
1354 return NVOS_STATUS_SUCCESS;
1355 }
1356
deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09(VGPU_GET_LATENCY_BUFFER_SIZE * vgpu_get_latency_buffer_size,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1357 NV_STATUS deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09(VGPU_GET_LATENCY_BUFFER_SIZE *vgpu_get_latency_buffer_size, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1358 {
1359 if (!offset)
1360 {
1361 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1362 }
1363
1364 // If vgpu_get_latency_buffer_size and buffer are valid, then copy data and return the offset
1365 if (vgpu_get_latency_buffer_size && buffer)
1366 {
1367 VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09 *vgpu_get_latency_buffer_size_v1C_09 = NULL;
1368 NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS *fifoLatencyBufferSize = *vgpu_get_latency_buffer_size;
1369 NvU32 i;
1370
1371 if (bufferSize < (*offset + sizeof(VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09)))
1372 return NV_ERR_NO_MEMORY;
1373
1374 vgpu_get_latency_buffer_size_v1C_09 = (void*)(buffer + *offset);
1375
1376 for (i = 0; i < NV2080_ENGINE_TYPE_LAST_v1C_09; i++)
1377 {
1378 fifoLatencyBufferSize[i].engineID = vgpu_get_latency_buffer_size_v1C_09->fifoLatencyBufferSize[i].engineID;
1379 fifoLatencyBufferSize[i].gpEntries = vgpu_get_latency_buffer_size_v1C_09->fifoLatencyBufferSize[i].gpEntries;
1380 fifoLatencyBufferSize[i].pbEntries = vgpu_get_latency_buffer_size_v1C_09->fifoLatencyBufferSize[i].pbEntries;
1381 }
1382 }
1383
1384 // If vgpu_get_latency_buffer_size or buffer is NULL, then this will be used to determine the size of the
1385 // static info buffer corresponding to the negotiated version
1386 *offset += sizeof(VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09);
1387
1388 return NVOS_STATUS_SUCCESS;
1389 }
1390
deserialize_VGPU_CE_GET_CAPS_V2_v24_09(VGPU_CE_GET_CAPS_V2 * ceCapsPtr,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1391 NV_STATUS deserialize_VGPU_CE_GET_CAPS_V2_v24_09(VGPU_CE_GET_CAPS_V2 *ceCapsPtr, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1392 {
1393 if (!offset)
1394 {
1395 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1396 }
1397
1398 // If ceCapsPtr and buffer are valid, then copy data and return the offset
1399 if (ceCapsPtr && buffer)
1400 {
1401 NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *ceCaps = *ceCapsPtr;
1402 VGPU_CE_GET_CAPS_V2_v24_09 *vgpu_ce_get_caps_v2_v24_09 = NULL;
1403 NvU32 i;
1404
1405 if ((bufferSize < *offset) ||
1406 (bufferSize < (*offset + sizeof(VGPU_CE_GET_CAPS_V2_v24_09))))
1407 return NV_ERR_BUFFER_TOO_SMALL;
1408
1409 vgpu_ce_get_caps_v2_v24_09 = (void*)(buffer + *offset);
1410
1411 for (i = 0; i < NV2080_ENGINE_TYPE_COPY_SIZE_v24_09; i++) {
1412
1413 ceCaps[i].ceEngineType = vgpu_ce_get_caps_v2_v24_09->ceCaps[i].ceEngineType;
1414 portMemCopy(&ceCaps[i].capsTbl, NV2080_CTRL_CE_CAPS_TBL_SIZE,
1415 &vgpu_ce_get_caps_v2_v24_09->ceCaps[i].capsTbl, NV2080_CTRL_CE_CAPS_TBL_SIZE);
1416 }
1417 }
1418
1419 *offset += sizeof(VGPU_CE_GET_CAPS_V2_v24_09);
1420
1421 return NVOS_STATUS_SUCCESS;
1422 }
1423
deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS * nvlinkCaps,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1424 NV_STATUS deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *nvlinkCaps, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1425 {
1426 if (!offset)
1427 {
1428 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1429 }
1430
1431 // If nvlinkCaps and buffer are valid, then copy data and return the offset
1432 if (nvlinkCaps && buffer)
1433 {
1434 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02 *get_nvlink_caps_v15_02 = NULL;
1435
1436 if ((bufferSize < *offset) ||
1437 (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02))))
1438 return NV_ERR_BUFFER_TOO_SMALL;
1439
1440 get_nvlink_caps_v15_02 = (void*)(buffer + *offset);
1441
1442 nvlinkCaps->capsTbl = get_nvlink_caps_v15_02->capsTbl;
1443 nvlinkCaps->lowestNvlinkVersion = get_nvlink_caps_v15_02->lowestNvlinkVersion;
1444 nvlinkCaps->highestNvlinkVersion = get_nvlink_caps_v15_02->highestNvlinkVersion;
1445 nvlinkCaps->lowestNciVersion = get_nvlink_caps_v15_02->lowestNciVersion;
1446 nvlinkCaps->highestNciVersion = get_nvlink_caps_v15_02->highestNciVersion;
1447 nvlinkCaps->discoveredLinkMask = get_nvlink_caps_v15_02->discoveredLinkMask;
1448 nvlinkCaps->enabledLinkMask = get_nvlink_caps_v15_02->enabledLinkMask;
1449 }
1450
1451 *offset += sizeof(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02);
1452
1453 return NVOS_STATUS_SUCCESS;
1454 }
1455
deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18(NV2080_CTRL_FLA_GET_RANGE_PARAMS * range_params,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1456 NV_STATUS deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18(NV2080_CTRL_FLA_GET_RANGE_PARAMS *range_params, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1457 {
1458 if (!offset)
1459 {
1460 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1461 }
1462
1463 // If range_params and buffer are valid, then copy data and return the offset
1464 if (range_params && buffer)
1465 {
1466 NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18 *range_params_v1A_18 = NULL;
1467
1468 if ((bufferSize < *offset) ||
1469 (bufferSize < (*offset + sizeof(NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18))))
1470 return NV_ERR_BUFFER_TOO_SMALL;
1471
1472 range_params_v1A_18 = (void*)(buffer + *offset);
1473
1474 range_params->base = range_params_v1A_18->base;
1475 range_params->size = range_params_v1A_18->size;
1476
1477 }
1478
1479 *offset += sizeof(NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18);
1480
1481 return NVOS_STATUS_SUCCESS;
1482 }
1483
deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS * vgpuConfig,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1484 NV_STATUS deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *vgpuConfig, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1485 {
1486 if (!offset)
1487 {
1488 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1489 }
1490
1491 // If vgpuConfig and buffer are valid, then copy data and return the offset
1492 if (vgpuConfig && buffer)
1493 {
1494 NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C *vgpu_get_config_params_v21_0C = NULL;
1495
1496 if ((bufferSize < *offset) ||
1497 (bufferSize < (*offset + sizeof(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C))))
1498 return NV_ERR_BUFFER_TOO_SMALL;
1499
1500 vgpu_get_config_params_v21_0C = (void*)(buffer + *offset);
1501
1502 // vgpuConfig
1503 vgpuConfig->frameRateLimiter = vgpu_get_config_params_v21_0C->frameRateLimiter;
1504 vgpuConfig->swVSyncEnabled = vgpu_get_config_params_v21_0C->swVSyncEnabled;
1505 vgpuConfig->cudaEnabled = vgpu_get_config_params_v21_0C->cudaEnabled;
1506 vgpuConfig->pluginPteBlitEnabled = vgpu_get_config_params_v21_0C->pluginPteBlitEnabled;
1507 vgpuConfig->disableWddm1xPreemption = vgpu_get_config_params_v21_0C->disableWddm1xPreemption;
1508 vgpuConfig->debugBufferSize = vgpu_get_config_params_v21_0C->debugBufferSize;
1509 vgpuConfig->debugBuffer = vgpu_get_config_params_v21_0C->debugBuffer;
1510 vgpuConfig->guestFbOffset = vgpu_get_config_params_v21_0C->guestFbOffset;
1511 vgpuConfig->mappableCpuHostAperture = vgpu_get_config_params_v21_0C->mappableCpuHostAperture;
1512 vgpuConfig->linuxInterruptOptimization = vgpu_get_config_params_v21_0C->linuxInterruptOptimization;
1513 vgpuConfig->vgpuDeviceCapsBits = vgpu_get_config_params_v21_0C->vgpuDeviceCapsBits;
1514 vgpuConfig->maxPixels = vgpu_get_config_params_v21_0C->maxPixels;
1515 vgpuConfig->uvmEnabledFeatures = vgpu_get_config_params_v21_0C->uvmEnabledFeatures;
1516 vgpuConfig->enableKmdSysmemScratch = vgpu_get_config_params_v21_0C->enableKmdSysmemScratch;
1517 }
1518
1519 *offset += sizeof(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C);
1520
1521 return NVOS_STATUS_SUCCESS;
1522 }
1523
deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS * pcieSupportedGpuAtomics,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1524 NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *pcieSupportedGpuAtomics, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1525 {
1526 if (!offset)
1527 {
1528 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1529 }
1530
1531 // If pcieSupportedGpuAtomics and buffer are valid, then copy data and return the offset
1532 if (pcieSupportedGpuAtomics && buffer)
1533 {
1534 NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08 *pcie_supported_gpu_atomics_v1F_08 = NULL;
1535 NvU32 i;
1536
1537 if ((bufferSize < *offset) ||
1538 (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08))))
1539 return NV_ERR_BUFFER_TOO_SMALL;
1540
1541 pcie_supported_gpu_atomics_v1F_08 = (void*)(buffer + *offset);
1542
1543 NV_ASSERT_OR_RETURN(NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT <= NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08,
1544 NV_ERR_INSUFFICIENT_RESOURCES);
1545
1546 for (i = 0; i < NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08; i++) {
1547 pcieSupportedGpuAtomics->atomicOp[i].bSupported = pcie_supported_gpu_atomics_v1F_08->atomicOp[i].bSupported;
1548 pcieSupportedGpuAtomics->atomicOp[i].attributes = pcie_supported_gpu_atomics_v1F_08->atomicOp[i].attributes;
1549 }
1550 }
1551
1552 *offset += sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08);
1553
1554 return NVOS_STATUS_SUCCESS;
1555 }
1556
deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS * cegetAllCaps,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1557 NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *cegetAllCaps, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1558 {
1559 if (!offset)
1560 {
1561 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1562 }
1563
1564 // If cegetAllCaps and buffer are valid, then copy data and return the offset
1565 if (cegetAllCaps && buffer)
1566 {
1567 NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A *ce_get_all_caps_v21_0A = NULL;
1568 NvU32 i;
1569
1570 if ((bufferSize < *offset) ||
1571 (bufferSize < (*offset + sizeof(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A))))
1572 return NV_ERR_BUFFER_TOO_SMALL;
1573
1574 ce_get_all_caps_v21_0A = (void*)(buffer + *offset);
1575
1576 NV_ASSERT_OR_RETURN(NV2080_CTRL_MAX_PCES <= NV2080_CTRL_MAX_PCES_v21_0A,
1577 NV_ERR_INSUFFICIENT_RESOURCES);
1578
1579 NV_ASSERT_OR_RETURN(NV2080_CTRL_CE_CAPS_TBL_SIZE <= NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A,
1580 NV_ERR_INSUFFICIENT_RESOURCES);
1581
1582 cegetAllCaps->present = ce_get_all_caps_v21_0A->present;
1583
1584 for (i = 0; i < NV2080_CTRL_MAX_PCES_v21_0A; i++) {
1585 portMemCopy(cegetAllCaps->capsTbl[i], (sizeof(NvU8) * NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A),
1586 ce_get_all_caps_v21_0A->ceCaps[i].capsTbl, (sizeof(NvU8) * NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A));
1587 }
1588 }
1589
1590 *offset += sizeof(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A);
1591
1592 return NVOS_STATUS_SUCCESS;
1593 }
1594
deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS * c2cInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1595 NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *c2cInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1596 {
1597 if (!offset)
1598 {
1599 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1600 }
1601
1602 // If c2cInfo and buffer are valid, then copy data and return the offset
1603 if (c2cInfo && buffer)
1604 {
1605 NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 *c2c_info_v22_01 = NULL;
1606
1607 if ((bufferSize < *offset) ||
1608 (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01))))
1609 return NV_ERR_BUFFER_TOO_SMALL;
1610
1611 c2c_info_v22_01 = (void*)(buffer + *offset);
1612
1613 c2cInfo->bIsLinkUp = c2c_info_v22_01->bIsLinkUp;
1614 c2cInfo->nrLinks = c2c_info_v22_01->nrLinks;
1615 c2cInfo->linkMask = c2c_info_v22_01->linkMask;
1616 c2cInfo->perLinkBwMBps = c2c_info_v22_01->perLinkBwMBps;
1617 c2cInfo->remoteType = c2c_info_v22_01->remoteType;
1618 }
1619
1620 *offset += sizeof(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01);
1621
1622 return NVOS_STATUS_SUCCESS;
1623 }
1624
deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00(NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS * pParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1625 NV_STATUS deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00(
1626 NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize,
1627 NvU32 *offset)
1628 {
1629 NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00 *pParams_v25_00 = NULL;
1630
1631 if (offset == NULL)
1632 {
1633 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1634 }
1635
1636 if (pParams != NULL && buffer != NULL)
1637 {
1638 if ((bufferSize < *offset) ||
1639 (bufferSize < (*offset + sizeof(*pParams_v25_00))))
1640 return NV_ERR_BUFFER_TOO_SMALL;
1641
1642 pParams_v25_00 = (void*)(buffer + *offset);
1643 NV_ASSERT_OR_RETURN(NV0080_CTRL_MSENC_CAPS_TBL_SIZE_V25_00 <=
1644 NV0080_CTRL_MSENC_CAPS_TBL_SIZE,
1645 NV_ERR_INSUFFICIENT_RESOURCES);
1646
1647 pParams->instanceId = pParams_v25_00->instanceId;
1648 portMemCopy(pParams->capsTbl, sizeof(pParams->capsTbl),
1649 pParams_v25_00->capsTbl, sizeof(pParams_v25_00->capsTbl));
1650 }
1651
1652 *offset += sizeof(*pParams_v25_00);
1653 return NVOS_STATUS_SUCCESS;
1654 }
1655
deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01(NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS * pParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1656 NV_STATUS deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01(
1657 NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize,
1658 NvU32 *offset)
1659 {
1660 NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01 *pParams_v25_01 = NULL;
1661
1662 if (offset == NULL)
1663 {
1664 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1665 }
1666
1667 if (pParams != NULL && buffer != NULL)
1668 {
1669 NvU32 i;
1670 if ((bufferSize < *offset) ||
1671 (bufferSize < (*offset + sizeof(*pParams_v25_01))))
1672 return NV_ERR_BUFFER_TOO_SMALL;
1673
1674 pParams_v25_01 = (void*)(buffer + *offset);
1675
1676 pParams->numConstructedFalcons = pParams_v25_01->numConstructedFalcons;
1677 for (i = 0; i < NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS; i++) {
1678 NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO *dst = &(pParams->constructedFalconsTable[i]);
1679 NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01 *src = &(pParams_v25_01->constructedFalconsTable[i]);
1680
1681 dst->engDesc = src->engDesc;
1682 dst->ctxAttr = src->ctxAttr;
1683 dst->ctxBufferSize = src->ctxBufferSize;
1684 dst->addrSpaceList = src->addrSpaceList;
1685 dst->registerBase = src->registerBase;
1686 }
1687 }
1688
1689 *offset += sizeof(*pParams_v25_01);
1690 return NVOS_STATUS_SUCCESS;
1691 }
1692
deserialize_VGPU_P2P_CAPABILITY_PARAMS_v25_03(VGPU_P2P_CAPABILITY_PARAMS * pParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1693 NV_STATUS deserialize_VGPU_P2P_CAPABILITY_PARAMS_v25_03(
1694 VGPU_P2P_CAPABILITY_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize,
1695 NvU32 *offset)
1696 {
1697 VGPU_P2P_CAPABILITY_PARAMS_v25_03 *pParams_v = NULL;
1698
1699 if (offset == NULL)
1700 {
1701 return NV_ERR_INVALID_ARGUMENT;
1702 }
1703
1704 if (pParams != NULL && buffer != NULL)
1705 {
1706 if ((bufferSize < *offset) ||
1707 (bufferSize < (*offset + sizeof(*pParams_v))))
1708 return NV_ERR_BUFFER_TOO_SMALL;
1709
1710 pParams_v = (void*)(buffer + *offset);
1711
1712 pParams->bGpuSupportsFabricProbe = pParams_v->bGpuSupportsFabricProbe;
1713 }
1714
1715 *offset += sizeof(*pParams_v);
1716 return NV_OK;
1717 }
1718
deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05(NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS * pParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1719 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05(
1720 NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize,
1721 NvU32 *offset)
1722 {
1723 NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05 *pParams_v25_05 = NULL;
1724
1725 if (offset == NULL)
1726 {
1727 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1728 }
1729
1730 if (pParams != NULL && buffer != NULL)
1731 {
1732 NvU32 i;
1733 if ((bufferSize < *offset) ||
1734 (bufferSize < (*offset + sizeof(*pParams_v25_05))))
1735 return NV_ERR_BUFFER_TOO_SMALL;
1736
1737 pParams_v25_05 = (void*)(buffer + *offset);
1738
1739 pParams->numEntries = pParams_v25_05->numEntries;
1740 for (i = 0; i < NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES; i++) {
1741 NV2080_CTRL_INTERNAL_DEVICE_INFO *dst = &(pParams->deviceInfoTable[i]);
1742 NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05 *src = &(pParams_v25_05->deviceInfoTable[i]);
1743
1744 dst->faultId = src->faultId;
1745 dst->instanceId = src->instanceId;
1746 dst->typeEnum = src->typeEnum;
1747 dst->resetId = src->resetId;
1748 dst->devicePriBase = src->devicePriBase;
1749 dst->isEngine = src->isEngine;
1750 dst->rlEngId = src->rlEngId;
1751 dst->runlistPriBase = src->runlistPriBase;
1752 dst->groupId = src->groupId;
1753 }
1754 }
1755
1756 *offset += sizeof(*pParams_v25_05);
1757 return NVOS_STATUS_SUCCESS;
1758 }
1759
deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06(NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS * pParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1760 NV_STATUS deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06(
1761 NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize,
1762 NvU32 *offset)
1763 {
1764 NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06 *pParams_v25_06 = NULL;
1765
1766 if (offset == NULL)
1767 {
1768 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1769 }
1770
1771 if (pParams != NULL && buffer != NULL)
1772 {
1773 if ((bufferSize < *offset) ||
1774 (bufferSize < (*offset + sizeof(*pParams_v25_06))))
1775 return NV_ERR_BUFFER_TOO_SMALL;
1776
1777 pParams_v25_06 = (void*)(buffer + *offset);
1778
1779 pParams->bOneToOneComptagLineAllocation = pParams_v25_06->bOneToOneComptagLineAllocation;
1780 pParams->bUseOneToFourComptagLineAllocation = pParams_v25_06->bUseOneToFourComptagLineAllocation;
1781 pParams->bUseRawModeComptaglineAllocation = pParams_v25_06->bUseRawModeComptaglineAllocation;
1782 pParams->bDisableCompbitBacking = pParams_v25_06->bDisableCompbitBacking;
1783 pParams->bDisablePostL2Compression = pParams_v25_06->bDisablePostL2Compression;
1784 pParams->bEnabledEccFBPA = pParams_v25_06->bEnabledEccFBPA;
1785 pParams->bL2PreFill = pParams_v25_06->bL2PreFill;
1786 pParams->l2CacheSize = pParams_v25_06->l2CacheSize;
1787 pParams->bFbpaPresent = pParams_v25_06->bFbpaPresent;
1788 pParams->comprPageSize = pParams_v25_06->comprPageSize;
1789 pParams->comprPageShift = pParams_v25_06->comprPageShift;
1790 pParams->ramType = pParams_v25_06->ramType;
1791 pParams->ltcCount = pParams_v25_06->ltcCount;
1792 pParams->ltsPerLtcCount = pParams_v25_06->ltsPerLtcCount;
1793 }
1794
1795 *offset += sizeof(*pParams_v25_06);
1796 return NVOS_STATUS_SUCCESS;
1797 }
1798
deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS * pParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1799 NV_STATUS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1800 {
1801 if (!offset)
1802 {
1803 return NVOS_STATUS_ERROR_INVALID_ARGUMENT;
1804 }
1805 // If pParams and buffer are valid, then copy data and return the offset
1806 if (pParams && buffer)
1807 {
1808 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13 *pParams_v25_13 = NULL;
1809 if ((bufferSize < *offset) ||
1810 (bufferSize < (*offset + sizeof(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13))))
1811 return NV_ERR_BUFFER_TOO_SMALL;
1812 pParams_v25_13 = (void*)(buffer + *offset);
1813 pParams->eccMask = pParams_v25_13->eccMask;
1814 pParams->nvlinkMask = pParams_v25_13->nvlinkMask;
1815 }
1816 *offset += sizeof(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13);
1817 return NVOS_STATUS_SUCCESS;
1818 }
1819
1820 // Stub functions for earlier versions
1821
deserialize_VGPU_STATIC_INFO2_v18_07(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1822 NV_STATUS deserialize_VGPU_STATIC_INFO2_v18_07(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1823 {
1824 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1825 }
1826
deserialize_VGPU_STATIC_INFO2_v18_0C(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1827 NV_STATUS deserialize_VGPU_STATIC_INFO2_v18_0C(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1828 {
1829 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1830 }
1831
deserialize_VGPU_STATIC_INFO2_v18_0F(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1832 NV_STATUS deserialize_VGPU_STATIC_INFO2_v18_0F(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1833 {
1834 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1835 }
1836
deserialize_VGPU_STATIC_INFO2_v1A_02(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1837 NV_STATUS deserialize_VGPU_STATIC_INFO2_v1A_02(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1838 {
1839 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1840 }
1841
deserialize_VGPU_STATIC_INFO2_v1A_04(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1842 NV_STATUS deserialize_VGPU_STATIC_INFO2_v1A_04(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1843 {
1844 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1845 }
1846
deserialize_VGPU_STATIC_INFO2_v1A_07(VGPU_STATIC_INFO2 * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1847 NV_STATUS deserialize_VGPU_STATIC_INFO2_v1A_07(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1848 {
1849 return NVOS_STATUS_SUCCESS;
1850 }
1851
deserialize_VGPU_STATIC_INFO2_v1C_09(VGPU_STATIC_INFO2 * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1852 NV_STATUS deserialize_VGPU_STATIC_INFO2_v1C_09(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1853 {
1854 return NVOS_STATUS_SUCCESS;
1855 }
1856
deserialize_VGPU_STATIC_INFO2_v20_03(VGPU_STATIC_INFO2 * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1857 NV_STATUS deserialize_VGPU_STATIC_INFO2_v20_03(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1858 {
1859 return NVOS_STATUS_SUCCESS;
1860 }
1861
deserialize_VGPU_STATIC_INFO2_v21_04(VGPU_STATIC_INFO2 * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1862 NV_STATUS deserialize_VGPU_STATIC_INFO2_v21_04(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1863 {
1864 return NVOS_STATUS_SUCCESS;
1865 }
1866
deserialize_VGPU_STATIC_INFO2_v21_09(VGPU_STATIC_INFO2 * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1867 NV_STATUS deserialize_VGPU_STATIC_INFO2_v21_09(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1868 {
1869 return NVOS_STATUS_SUCCESS;
1870 }
1871
deserialize_VGPU_STATIC_INFO2_v24_05(VGPU_STATIC_INFO2 * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1872 NV_STATUS deserialize_VGPU_STATIC_INFO2_v24_05(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1873 {
1874 return NVOS_STATUS_SUCCESS;
1875 }
1876
deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v03_00(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS * grZcullInfo,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1877 NV_STATUS deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v03_00(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *grZcullInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1878 {
1879 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1880 }
1881
deserialize_VGPU_STATIC_INFO_v07_00(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1882 NV_STATUS deserialize_VGPU_STATIC_INFO_v07_00(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1883 {
1884 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1885 }
1886
deserialize_VGPU_STATIC_INFO_v09_04(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1887 NV_STATUS deserialize_VGPU_STATIC_INFO_v09_04(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1888 {
1889 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1890 }
1891
deserialize_VGPU_STATIC_INFO_v12_00(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1892 NV_STATUS deserialize_VGPU_STATIC_INFO_v12_00(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1893 {
1894 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1895 }
1896
deserialize_VGPU_STATIC_INFO_v12_01(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1897 NV_STATUS deserialize_VGPU_STATIC_INFO_v12_01(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1898 {
1899 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1900 }
1901
deserialize_VGPU_STATIC_INFO_v12_06(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1902 NV_STATUS deserialize_VGPU_STATIC_INFO_v12_06(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1903 {
1904 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1905 }
1906
deserialize_VGPU_STATIC_INFO_v12_0A(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1907 NV_STATUS deserialize_VGPU_STATIC_INFO_v12_0A(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1908 {
1909 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1910 }
1911
deserialize_VGPU_STATIC_INFO_v13_06(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1912 NV_STATUS deserialize_VGPU_STATIC_INFO_v13_06(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1913 {
1914 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1915 }
1916
deserialize_VGPU_STATIC_INFO_v16_02(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1917 NV_STATUS deserialize_VGPU_STATIC_INFO_v16_02(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1918 {
1919 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1920 }
1921
deserialize_VGPU_STATIC_INFO_v16_05(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1922 NV_STATUS deserialize_VGPU_STATIC_INFO_v16_05(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1923 {
1924 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1925 }
1926
deserialize_VGPU_STATIC_INFO_v16_07(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1927 NV_STATUS deserialize_VGPU_STATIC_INFO_v16_07(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1928 {
1929 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1930 }
1931
deserialize_VGPU_STATIC_INFO_v17_00(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1932 NV_STATUS deserialize_VGPU_STATIC_INFO_v17_00(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1933 {
1934 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1935 }
1936
deserialize_VGPU_STATIC_INFO_v17_01(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1937 NV_STATUS deserialize_VGPU_STATIC_INFO_v17_01(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1938 {
1939 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1940 }
1941
deserialize_VGPU_STATIC_INFO_v17_05(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1942 NV_STATUS deserialize_VGPU_STATIC_INFO_v17_05(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1943 {
1944 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1945 }
1946
deserialize_VGPU_STATIC_INFO_v18_03(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1947 NV_STATUS deserialize_VGPU_STATIC_INFO_v18_03(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1948 {
1949 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1950 }
1951
deserialize_VGPU_STATIC_INFO_v18_04(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1952 NV_STATUS deserialize_VGPU_STATIC_INFO_v18_04(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1953 {
1954 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1955 }
1956
deserialize_VGPU_STATIC_INFO_v18_0E(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1957 NV_STATUS deserialize_VGPU_STATIC_INFO_v18_0E(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1958 {
1959 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1960 }
1961
deserialize_VGPU_STATIC_INFO_v18_10(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1962 NV_STATUS deserialize_VGPU_STATIC_INFO_v18_10(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1963 {
1964 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1965 }
1966
deserialize_VGPU_STATIC_INFO_v18_11(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1967 NV_STATUS deserialize_VGPU_STATIC_INFO_v18_11(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1968 {
1969 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1970 }
1971
deserialize_VGPU_STATIC_INFO_v18_13(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1972 NV_STATUS deserialize_VGPU_STATIC_INFO_v18_13(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1973 {
1974 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1975 }
1976
deserialize_VGPU_STATIC_INFO_v18_16(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1977 NV_STATUS deserialize_VGPU_STATIC_INFO_v18_16(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1978 {
1979 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1980 }
1981
deserialize_VGPU_STATIC_INFO_v19_00(VGPU_STATIC_INFO * vgpu_static_info,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1982 NV_STATUS deserialize_VGPU_STATIC_INFO_v19_00(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1983 {
1984 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1985 }
1986
deserialize_VGPU_STATIC_INFO_v1A_00(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1987 NV_STATUS deserialize_VGPU_STATIC_INFO_v1A_00(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1988 {
1989 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1990 }
1991
deserialize_VGPU_STATIC_INFO_v1A_05(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1992 NV_STATUS deserialize_VGPU_STATIC_INFO_v1A_05(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1993 {
1994 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
1995 }
1996
deserialize_VGPU_STATIC_INFO_v1B_03(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)1997 NV_STATUS deserialize_VGPU_STATIC_INFO_v1B_03(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
1998 {
1999 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2000 }
2001
deserialize_VGPU_STATIC_INFO_v1D_01(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2002 NV_STATUS deserialize_VGPU_STATIC_INFO_v1D_01(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2003 {
2004 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2005 }
2006
deserialize_VGPU_STATIC_INFO_v1F_02(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2007 NV_STATUS deserialize_VGPU_STATIC_INFO_v1F_02(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2008 {
2009 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2010 }
2011
deserialize_VGPU_STATIC_INFO_v1F_09(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2012 NV_STATUS deserialize_VGPU_STATIC_INFO_v1F_09(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2013 {
2014 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2015 }
2016
deserialize_VGPU_STATIC_INFO_v20_01(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2017 NV_STATUS deserialize_VGPU_STATIC_INFO_v20_01(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2018 {
2019 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2020 }
2021
deserialize_VGPU_STATIC_INFO_v20_04(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2022 NV_STATUS deserialize_VGPU_STATIC_INFO_v20_04(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2023 {
2024 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2025 }
2026
deserialize_VGPU_STATIC_INFO_v21_09(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2027 NV_STATUS deserialize_VGPU_STATIC_INFO_v21_09(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2028 {
2029 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2030 }
2031
deserialize_VGPU_STATIC_INFO_v23_01(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2032 NV_STATUS deserialize_VGPU_STATIC_INFO_v23_01(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2033 {
2034 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2035 }
2036
deserialize_VGPU_STATIC_INFO_v24_05(VGPU_STATIC_INFO * pVSI,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2037 NV_STATUS deserialize_VGPU_STATIC_INFO_v24_05(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2038 {
2039 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2040 }
2041
deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS * pParams,NvU8 * buffer,NvU32 bufferSize,NvU32 * offset)2042 NV_STATUS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset)
2043 {
2044 return NVOS_STATUS_ERROR_NOT_SUPPORTED;
2045 }
2046