1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #include "gpu/gpu.h" 24 #include "gpu/gpu_child_class_defs.h" 25 #include "published/turing/tu102/dev_vm.h" 26 #include "published/turing/tu102/hwproject.h" 27 #include "jt.h" 28 29 /*! 30 * @brief Returns SR-IOV capabilities 31 * 32 * @param[in] pGpu OBJGPU pointer 33 * @param[out] pParams Pointer for get_sriov_caps params 34 * 35 * @returns NV_OK always 36 */ 37 NV_STATUS 38 gpuGetSriovCaps_TU102 39 ( 40 OBJGPU *pGpu, 41 NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams 42 ) 43 { 44 if (!gpuIsSriovEnabled(pGpu)) 45 { 46 pParams->bSriovEnabled = NV_FALSE; 47 return NV_OK; 48 } 49 50 pParams->bSriovEnabled = NV_TRUE; 51 pParams->totalVFs = pGpu->sriovState.totalVFs; 52 pParams->firstVfOffset = pGpu->sriovState.firstVFOffset; 53 pParams->FirstVFBar0Address = pGpu->sriovState.firstVFBarAddress[0]; 54 pParams->FirstVFBar1Address = pGpu->sriovState.firstVFBarAddress[1]; 55 pParams->FirstVFBar2Address = pGpu->sriovState.firstVFBarAddress[2]; 56 pParams->bar0Size = pGpu->sriovState.vfBarSize[0]; 57 pParams->bar1Size = pGpu->sriovState.vfBarSize[1]; 58 pParams->bar2Size = pGpu->sriovState.vfBarSize[2]; 59 pParams->b64bitBar0 = pGpu->sriovState.b64bitVFBar0; 60 pParams->b64bitBar1 = pGpu->sriovState.b64bitVFBar1; 61 pParams->b64bitBar2 = pGpu->sriovState.b64bitVFBar2; 62 pParams->bSriovHeavyEnabled = gpuIsWarBug200577889SriovHeavyEnabled(pGpu); 63 pParams->bEmulateVFBar0TlbInvalidationRegister = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE); 64 pParams->bClientRmAllocatedCtxBuffer = gpuIsClientRmAllocatedCtxBufferEnabled(pGpu); 65 pParams->bNonPowerOf2ChannelCountSupported = gpuIsNonPowerOf2ChannelCountSupported(pGpu); 66 67 return NV_OK; 68 } 69 70 /*! 71 * @brief determines whether this GPU mode needs to be initialized with an offset 72 * to access the registers defined in dev_vm.ref. 73 * 74 * @param[in] pGpu OBJGPU pointer 75 * 76 * @returns NvU32 - physical offset needed to access virtual registers in host 77 */ 78 NvU32 79 gpuGetVirtRegPhysOffset_TU102(OBJGPU *pGpu) 80 { 81 // No offset is needed, only in case of VF in SR-IOV 82 if (IS_VIRTUAL_WITH_SRIOV(pGpu)) 83 return 0; 84 else 85 return DRF_BASE(NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET); 86 } 87 88 /*! 89 * @brief Returns the physical address width for the given @ref NV_ADDRESS_SPACE 90 */ 91 NvU32 gpuGetPhysAddrWidth_TU102 92 ( 93 OBJGPU *pGpu, 94 NV_ADDRESS_SPACE addrSp 95 ) 96 { 97 // Currently this function supports only sysmem addresses 98 NV_ASSERT_OR_RETURN(ADDR_SYSMEM == addrSp, 0); 99 100 return NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS; 101 } 102 103 // 104 // List of GPU children that present for the chip. List entries contain$ 105 // {CLASS-ID, # of instances} pairs, e.g.: {CE, 2} is 2 instance of OBJCE. This$ 106 // list controls only engine presence. Order is defined by$ 107 // gpuGetChildrenOrder_HAL.$ 108 // 109 // IMPORTANT: This function is to be deleted. Engine removal should instead be$ 110 // handled by <eng>ConstructEngine returning NV_ERR_NOT_SUPPORTED. PLEASE DO NOT$ 111 // FORK THIS LIST!$ 112 // 113 // List entries contain {CLASS-ID, # of instances} pairs. 114 // 115 static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = 116 { 117 GPU_CHILD_PRESENT(OBJTMR, 1), 118 GPU_CHILD_PRESENT(KernelMIGManager, 1), 119 GPU_CHILD_PRESENT(KernelGraphicsManager, 1), 120 GPU_CHILD_PRESENT(KernelRc, 1), 121 GPU_CHILD_PRESENT(Intr, 1), 122 GPU_CHILD_PRESENT(NvDebugDump, 1), 123 GPU_CHILD_PRESENT(OBJGPUMON, 1), 124 GPU_CHILD_PRESENT(OBJSWENG, 1), 125 GPU_CHILD_PRESENT(OBJUVM, 1), 126 GPU_CHILD_PRESENT(KernelBif, 1), 127 GPU_CHILD_PRESENT(KernelBus, 1), 128 GPU_CHILD_PRESENT(KernelCE, 9), 129 GPU_CHILD_PRESENT(KernelDisplay, 1), 130 GPU_CHILD_PRESENT(VirtMemAllocator, 1), 131 GPU_CHILD_PRESENT(KernelMemorySystem, 1), 132 GPU_CHILD_PRESENT(MemoryManager, 1), 133 GPU_CHILD_PRESENT(KernelFifo, 1), 134 GPU_CHILD_PRESENT(KernelGmmu, 1), 135 GPU_CHILD_PRESENT(KernelGraphics, 1), 136 GPU_CHILD_PRESENT(KernelMc, 1), 137 GPU_CHILD_PRESENT(SwIntr, 1), 138 GPU_CHILD_PRESENT(KernelNvlink, 1), 139 GPU_CHILD_PRESENT(KernelPerf, 1), 140 GPU_CHILD_PRESENT(KernelPmu, 1), 141 GPU_CHILD_PRESENT(KernelSec2, 1), 142 GPU_CHILD_PRESENT(KernelGsp, 1), 143 }; 144 145 static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = 146 { 147 GPU_CHILD_PRESENT(OBJTMR, 1), 148 GPU_CHILD_PRESENT(KernelMIGManager, 1), 149 GPU_CHILD_PRESENT(KernelGraphicsManager, 1), 150 GPU_CHILD_PRESENT(KernelRc, 1), 151 GPU_CHILD_PRESENT(Intr, 1), 152 GPU_CHILD_PRESENT(NvDebugDump, 1), 153 GPU_CHILD_PRESENT(OBJGPUMON, 1), 154 GPU_CHILD_PRESENT(OBJSWENG, 1), 155 GPU_CHILD_PRESENT(OBJUVM, 1), 156 GPU_CHILD_PRESENT(KernelBif, 1), 157 GPU_CHILD_PRESENT(KernelBus, 1), 158 GPU_CHILD_PRESENT(KernelCE, 9), 159 GPU_CHILD_PRESENT(KernelDisplay, 1), 160 GPU_CHILD_PRESENT(VirtMemAllocator, 1), 161 GPU_CHILD_PRESENT(KernelMemorySystem, 1), 162 GPU_CHILD_PRESENT(MemoryManager, 1), 163 GPU_CHILD_PRESENT(KernelFifo, 1), 164 GPU_CHILD_PRESENT(KernelGmmu, 1), 165 GPU_CHILD_PRESENT(KernelGraphics, 1), 166 GPU_CHILD_PRESENT(KernelMc, 1), 167 GPU_CHILD_PRESENT(SwIntr, 1), 168 GPU_CHILD_PRESENT(KernelNvlink, 1), 169 GPU_CHILD_PRESENT(KernelPerf, 1), 170 GPU_CHILD_PRESENT(KernelPmu, 1), 171 GPU_CHILD_PRESENT(KernelSec2, 1), 172 GPU_CHILD_PRESENT(KernelGsp, 1), 173 }; 174 175 static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = 176 { 177 GPU_CHILD_PRESENT(OBJTMR, 1), 178 GPU_CHILD_PRESENT(KernelMIGManager, 1), 179 GPU_CHILD_PRESENT(KernelGraphicsManager, 1), 180 GPU_CHILD_PRESENT(KernelRc, 1), 181 GPU_CHILD_PRESENT(Intr, 1), 182 GPU_CHILD_PRESENT(NvDebugDump, 1), 183 GPU_CHILD_PRESENT(OBJGPUMON, 1), 184 GPU_CHILD_PRESENT(OBJSWENG, 1), 185 GPU_CHILD_PRESENT(OBJUVM, 1), 186 GPU_CHILD_PRESENT(KernelBif, 1), 187 GPU_CHILD_PRESENT(KernelBus, 1), 188 GPU_CHILD_PRESENT(KernelCE, 9), 189 GPU_CHILD_PRESENT(KernelDisplay, 1), 190 GPU_CHILD_PRESENT(VirtMemAllocator, 1), 191 GPU_CHILD_PRESENT(KernelMemorySystem, 1), 192 GPU_CHILD_PRESENT(MemoryManager, 1), 193 GPU_CHILD_PRESENT(KernelFifo, 1), 194 GPU_CHILD_PRESENT(KernelGmmu, 1), 195 GPU_CHILD_PRESENT(KernelGraphics, 1), 196 GPU_CHILD_PRESENT(KernelMc, 1), 197 GPU_CHILD_PRESENT(SwIntr, 1), 198 GPU_CHILD_PRESENT(KernelNvlink, 1), 199 GPU_CHILD_PRESENT(KernelPerf, 1), 200 GPU_CHILD_PRESENT(KernelPmu, 1), 201 GPU_CHILD_PRESENT(KernelSec2, 1), 202 GPU_CHILD_PRESENT(KernelGsp, 1), 203 }; 204 205 const GPUCHILDPRESENT * 206 gpuGetChildrenPresent_TU102(OBJGPU *pGpu, NvU32 *pNumEntries) 207 { 208 *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU102); 209 return gpuChildrenPresent_TU102; 210 } 211 212 const GPUCHILDPRESENT * 213 gpuGetChildrenPresent_TU104(OBJGPU *pGpu, NvU32 *pNumEntries) 214 { 215 *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU104); 216 return gpuChildrenPresent_TU104; 217 } 218 219 const GPUCHILDPRESENT * 220 gpuGetChildrenPresent_TU106(OBJGPU *pGpu, NvU32 *pNumEntries) 221 { 222 *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU106); 223 return gpuChildrenPresent_TU106; 224 } 225 226 /*! 227 * @brief Check if the DSM JT version is correct 228 * 229 * @param pGpu OBJGPU pointer 230 * 231 * @return NV_OK if DSM version matches otherwise NV_ERR_INVALID_PARAMETER 232 */ 233 NV_STATUS 234 gpuJtVersionSanityCheck_TU102 235 ( 236 OBJGPU *pGpu 237 ) 238 { 239 NV_STATUS status = NV_OK; 240 241 if (!IS_SILICON(pGpu) || NV_IS_MODS) 242 { 243 goto gpuJtVersionSanityCheck_TU102_EXIT; 244 } 245 246 if (FLD_TEST_DRF(_JT_FUNC, _CAPS, _JT_ENABLED, _TRUE, pGpu->acpiMethodData.jtMethodData.jtCaps)) 247 { 248 if (!(pGpu->acpiMethodData.jtMethodData.jtRevId == NV_JT_FUNC_CAPS_REVISION_ID_2_00)) 249 { 250 NV_PRINTF(LEVEL_ERROR, 251 "JT Version mismatch 0x%x\n", pGpu->acpiMethodData.jtMethodData.jtRevId); 252 DBG_BREAKPOINT(); 253 status = NV_ERR_INVALID_PARAMETER; 254 goto gpuJtVersionSanityCheck_TU102_EXIT; 255 } 256 } 257 258 gpuJtVersionSanityCheck_TU102_EXIT: 259 return status; 260 } 261