1 /*
2  * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES
3  * SPDX-License-Identifier: MIT
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 #include "gpu/gpu.h"
24 #include "gpu/gpu_child_class_defs.h"
25 #include "published/turing/tu102/dev_vm.h"
26 #include "published/turing/tu102/hwproject.h"
27 #include "jt.h"
28 
29 /*!
30  * @brief Returns SR-IOV capabilities
31  *
32  * @param[in]  pGpu           OBJGPU pointer
33  * @param[out] pParams        Pointer for get_sriov_caps params
34  *
35  * @returns NV_OK always
36  */
37 NV_STATUS
38 gpuGetSriovCaps_TU102
39 (
40     OBJGPU *pGpu,
41     NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams
42 )
43 {
44     if (!gpuIsSriovEnabled(pGpu))
45     {
46         pParams->bSriovEnabled = NV_FALSE;
47         return NV_OK;
48     }
49 
50     pParams->bSriovEnabled                         = NV_TRUE;
51     pParams->totalVFs                              = pGpu->sriovState.totalVFs;
52     pParams->firstVfOffset                         = pGpu->sriovState.firstVFOffset;
53     pParams->FirstVFBar0Address                    = pGpu->sriovState.firstVFBarAddress[0];
54     pParams->FirstVFBar1Address                    = pGpu->sriovState.firstVFBarAddress[1];
55     pParams->FirstVFBar2Address                    = pGpu->sriovState.firstVFBarAddress[2];
56     pParams->bar0Size                              = pGpu->sriovState.vfBarSize[0];
57     pParams->bar1Size                              = pGpu->sriovState.vfBarSize[1];
58     pParams->bar2Size                              = pGpu->sriovState.vfBarSize[2];
59     pParams->b64bitBar0                            = pGpu->sriovState.b64bitVFBar0;
60     pParams->b64bitBar1                            = pGpu->sriovState.b64bitVFBar1;
61     pParams->b64bitBar2                            = pGpu->sriovState.b64bitVFBar2;
62     pParams->bSriovHeavyEnabled                    = gpuIsWarBug200577889SriovHeavyEnabled(pGpu);
63     pParams->bEmulateVFBar0TlbInvalidationRegister = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE);
64     pParams->bClientRmAllocatedCtxBuffer           = gpuIsClientRmAllocatedCtxBufferEnabled(pGpu);
65 
66     return NV_OK;
67 }
68 
69 /*!
70  * @brief determines whether this GPU mode needs to be initialized with an offset
71  *        to access the registers defined in dev_vm.ref.
72  *
73  * @param[in]  pGpu          OBJGPU pointer
74  *
75  * @returns NvU32 - physical offset needed to access virtual registers in host
76  */
77 NvU32
78 gpuGetVirtRegPhysOffset_TU102(OBJGPU *pGpu)
79 {
80     // No offset is needed, only in case of VF in SR-IOV
81     if (IS_VIRTUAL_WITH_SRIOV(pGpu))
82         return 0;
83     else
84         return DRF_BASE(NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET);
85 }
86 
87 /*!
88  * @brief Returns the physical address width for the given @ref NV_ADDRESS_SPACE
89  */
90 NvU32 gpuGetPhysAddrWidth_TU102
91 (
92     OBJGPU          *pGpu,
93     NV_ADDRESS_SPACE addrSp
94 )
95 {
96     // Currently this function supports only sysmem addresses
97     NV_ASSERT_OR_RETURN(ADDR_SYSMEM == addrSp, 0);
98 
99     return NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS;
100 }
101 
102 //
103 // List of GPU children that present for the chip. List entries contain$
104 // {CLASS-ID, # of instances} pairs, e.g.: {CE, 2} is 2 instance of OBJCE. This$
105 // list controls only engine presence. Order is defined by$
106 // gpuGetChildrenOrder_HAL.$
107 //
108 // IMPORTANT: This function is to be deleted. Engine removal should instead be$
109 // handled by <eng>ConstructEngine returning NV_ERR_NOT_SUPPORTED. PLEASE DO NOT$
110 // FORK THIS LIST!$
111 //
112 // List entries contain {CLASS-ID, # of instances} pairs.
113 //
114 static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] =
115 {
116     GPU_CHILD_PRESENT(OBJTMR, 1),
117     GPU_CHILD_PRESENT(KernelMIGManager, 1),
118     GPU_CHILD_PRESENT(KernelGraphicsManager, 1),
119     GPU_CHILD_PRESENT(KernelRc, 1),
120     GPU_CHILD_PRESENT(Intr, 1),
121     GPU_CHILD_PRESENT(NvDebugDump, 1),
122     GPU_CHILD_PRESENT(OBJGPUMON, 1),
123     GPU_CHILD_PRESENT(OBJSWENG, 1),
124     GPU_CHILD_PRESENT(OBJUVM, 1),
125     GPU_CHILD_PRESENT(KernelBif, 1),
126     GPU_CHILD_PRESENT(KernelBus, 1),
127     GPU_CHILD_PRESENT(KernelCE, 9),
128     GPU_CHILD_PRESENT(KernelDisplay, 1),
129     GPU_CHILD_PRESENT(VirtMemAllocator, 1),
130     GPU_CHILD_PRESENT(KernelMemorySystem, 1),
131     GPU_CHILD_PRESENT(MemoryManager, 1),
132     GPU_CHILD_PRESENT(KernelFifo, 1),
133     GPU_CHILD_PRESENT(KernelGmmu, 1),
134     GPU_CHILD_PRESENT(KernelGraphics, 1),
135     GPU_CHILD_PRESENT(KernelMc, 1),
136     GPU_CHILD_PRESENT(SwIntr, 1),
137     GPU_CHILD_PRESENT(KernelNvlink, 1),
138     GPU_CHILD_PRESENT(KernelPerf, 1),
139     GPU_CHILD_PRESENT(KernelPmu, 1),
140     GPU_CHILD_PRESENT(KernelSec2, 1),
141     GPU_CHILD_PRESENT(KernelGsp, 1),
142 };
143 
144 static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] =
145 {
146     GPU_CHILD_PRESENT(OBJTMR, 1),
147     GPU_CHILD_PRESENT(KernelMIGManager, 1),
148     GPU_CHILD_PRESENT(KernelGraphicsManager, 1),
149     GPU_CHILD_PRESENT(KernelRc, 1),
150     GPU_CHILD_PRESENT(Intr, 1),
151     GPU_CHILD_PRESENT(NvDebugDump, 1),
152     GPU_CHILD_PRESENT(OBJGPUMON, 1),
153     GPU_CHILD_PRESENT(OBJSWENG, 1),
154     GPU_CHILD_PRESENT(OBJUVM, 1),
155     GPU_CHILD_PRESENT(KernelBif, 1),
156     GPU_CHILD_PRESENT(KernelBus, 1),
157     GPU_CHILD_PRESENT(KernelCE, 9),
158     GPU_CHILD_PRESENT(KernelDisplay, 1),
159     GPU_CHILD_PRESENT(VirtMemAllocator, 1),
160     GPU_CHILD_PRESENT(KernelMemorySystem, 1),
161     GPU_CHILD_PRESENT(MemoryManager, 1),
162     GPU_CHILD_PRESENT(KernelFifo, 1),
163     GPU_CHILD_PRESENT(KernelGmmu, 1),
164     GPU_CHILD_PRESENT(KernelGraphics, 1),
165     GPU_CHILD_PRESENT(KernelMc, 1),
166     GPU_CHILD_PRESENT(SwIntr, 1),
167     GPU_CHILD_PRESENT(KernelNvlink, 1),
168     GPU_CHILD_PRESENT(KernelPerf, 1),
169     GPU_CHILD_PRESENT(KernelPmu, 1),
170     GPU_CHILD_PRESENT(KernelSec2, 1),
171     GPU_CHILD_PRESENT(KernelGsp, 1),
172 };
173 
174 static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] =
175 {
176     GPU_CHILD_PRESENT(OBJTMR, 1),
177     GPU_CHILD_PRESENT(KernelMIGManager, 1),
178     GPU_CHILD_PRESENT(KernelGraphicsManager, 1),
179     GPU_CHILD_PRESENT(KernelRc, 1),
180     GPU_CHILD_PRESENT(Intr, 1),
181     GPU_CHILD_PRESENT(NvDebugDump, 1),
182     GPU_CHILD_PRESENT(OBJGPUMON, 1),
183     GPU_CHILD_PRESENT(OBJSWENG, 1),
184     GPU_CHILD_PRESENT(OBJUVM, 1),
185     GPU_CHILD_PRESENT(KernelBif, 1),
186     GPU_CHILD_PRESENT(KernelBus, 1),
187     GPU_CHILD_PRESENT(KernelCE, 9),
188     GPU_CHILD_PRESENT(KernelDisplay, 1),
189     GPU_CHILD_PRESENT(VirtMemAllocator, 1),
190     GPU_CHILD_PRESENT(KernelMemorySystem, 1),
191     GPU_CHILD_PRESENT(MemoryManager, 1),
192     GPU_CHILD_PRESENT(KernelFifo, 1),
193     GPU_CHILD_PRESENT(KernelGmmu, 1),
194     GPU_CHILD_PRESENT(KernelGraphics, 1),
195     GPU_CHILD_PRESENT(KernelMc, 1),
196     GPU_CHILD_PRESENT(SwIntr, 1),
197     GPU_CHILD_PRESENT(KernelNvlink, 1),
198     GPU_CHILD_PRESENT(KernelPerf, 1),
199     GPU_CHILD_PRESENT(KernelPmu, 1),
200     GPU_CHILD_PRESENT(KernelSec2, 1),
201     GPU_CHILD_PRESENT(KernelGsp, 1),
202 };
203 
204 const GPUCHILDPRESENT *
205 gpuGetChildrenPresent_TU102(OBJGPU *pGpu, NvU32 *pNumEntries)
206 {
207     *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU102);
208     return gpuChildrenPresent_TU102;
209 }
210 
211 const GPUCHILDPRESENT *
212 gpuGetChildrenPresent_TU104(OBJGPU *pGpu, NvU32 *pNumEntries)
213 {
214     *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU104);
215     return gpuChildrenPresent_TU104;
216 }
217 
218 const GPUCHILDPRESENT *
219 gpuGetChildrenPresent_TU106(OBJGPU *pGpu, NvU32 *pNumEntries)
220 {
221     *pNumEntries = NV_ARRAY_ELEMENTS(gpuChildrenPresent_TU106);
222     return gpuChildrenPresent_TU106;
223 }
224 
225 /*!
226  * @brief Check if the DSM JT version is correct
227  *
228  * @param  pGpu    OBJGPU pointer
229  *
230  * @return NV_OK if DSM version matches otherwise NV_ERR_INVALID_PARAMETER
231  */
232 NV_STATUS
233 gpuJtVersionSanityCheck_TU102
234 (
235     OBJGPU *pGpu
236 )
237 {
238     NV_STATUS status = NV_OK;
239 
240     if (!IS_SILICON(pGpu) || NV_IS_MODS)
241     {
242         goto gpuJtVersionSanityCheck_TU102_EXIT;
243     }
244 
245     if (FLD_TEST_DRF(_JT_FUNC, _CAPS, _JT_ENABLED, _TRUE, pGpu->acpiMethodData.jtMethodData.jtCaps))
246     {
247         if (!(pGpu->acpiMethodData.jtMethodData.jtRevId == NV_JT_FUNC_CAPS_REVISION_ID_2_00))
248         {
249             NV_PRINTF(LEVEL_ERROR,
250                       "JT Version mismatch 0x%x\n", pGpu->acpiMethodData.jtMethodData.jtRevId);
251             DBG_BREAKPOINT();
252             status = NV_ERR_INVALID_PARAMETER;
253             goto gpuJtVersionSanityCheck_TU102_EXIT;
254         }
255     }
256 
257 gpuJtVersionSanityCheck_TU102_EXIT:
258     return status;
259 }
260