1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24
25 /* ------------------------ Includes ---------------------------------------- */
26 #include "gpu/bif/kernel_bif.h"
27 #include "published/ampere/ga102/dev_nv_pcfg_xve_regmap.h"
28
29 // XVE register map for PCIe config space
30 static const NvU32 xveRegMapValid[] = NV_PCFG_XVE_REGISTER_VALID_MAP;
31 static const NvU32 xveRegMapWrite[] = NV_PCFG_XVE_REGISTER_WR_MAP;
32
33 /* ------------------------ Public Functions -------------------------------- */
34
35 /*!
36 * This function setups the xve register map pointers
37 *
38 * @param[in] pGpu GPU object pointer
39 * @param[in] pKernelBif Pointer to KernelBif object
40 * @param[in] func PCIe function number
41 *
42 * @return 'NV_OK' if successful, an RM error code otherwise.
43 */
44 NV_STATUS
kbifInitXveRegMap_GA102(OBJGPU * pGpu,KernelBif * pKernelBif,NvU8 func)45 kbifInitXveRegMap_GA102
46 (
47 OBJGPU *pGpu,
48 KernelBif *pKernelBif,
49 NvU8 func
50 )
51 {
52 extern NvU32 kbifInitXveRegMap_GM107(OBJGPU *pGpu, KernelBif *pKernelBif, NvU8 func);
53 NV_STATUS status = NV_OK;
54 NvU32 controlSize = 0;
55
56 if (func == 0)
57 {
58 pKernelBif->xveRegmapRef[0].nFunc = 0;
59 pKernelBif->xveRegmapRef[0].xveRegMapValid = xveRegMapValid;
60 pKernelBif->xveRegmapRef[0].xveRegMapWrite = xveRegMapWrite;
61 pKernelBif->xveRegmapRef[0].numXveRegMapValid = sizeof(xveRegMapValid)/sizeof(xveRegMapValid[0]);
62 pKernelBif->xveRegmapRef[0].numXveRegMapWrite = sizeof(xveRegMapWrite)/sizeof(xveRegMapWrite[0]);
63 pKernelBif->xveRegmapRef[0].bufBootConfigSpace = pKernelBif->cacheData.gpuBootConfigSpace;
64 // Each MSIX table entry is 4 NvU32s
65 controlSize = kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif);
66 if (pKernelBif->xveRegmapRef[0].bufMsixTable == NULL)
67 pKernelBif->xveRegmapRef[0].bufMsixTable = portMemAllocNonPaged(controlSize * 4 * sizeof(NvU32));
68 NV_ASSERT_OR_RETURN(pKernelBif->xveRegmapRef[0].bufMsixTable != NULL, NV_ERR_NO_MEMORY);
69 }
70 else if (func == 1)
71 {
72 // Init regmap for Fn1 using older HAL
73 status = kbifInitXveRegMap_GM107(pGpu, pKernelBif, 1);
74 }
75 else
76 {
77 NV_PRINTF(LEVEL_ERROR, "Invalid argument, func: %d.\n", func);
78 NV_ASSERT(0);
79 status = NV_ERR_INVALID_ARGUMENT;
80 }
81
82 return status;
83 }
84